From af3fae0ed7497c0a8e1ec63acdda637b7c0df8b4 Mon Sep 17 00:00:00 2001 From: 1fHu Date: Sun, 8 Mar 2026 19:29:14 -0400 Subject: [PATCH 1/2] docs(dn)-Simon Hu-03/08/2026 --- src/design_notebooks/2026spring/yh4970.md | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/design_notebooks/2026spring/yh4970.md b/src/design_notebooks/2026spring/yh4970.md index 829dfd75..8abcfc9b 100644 --- a/src/design_notebooks/2026spring/yh4970.md +++ b/src/design_notebooks/2026spring/yh4970.md @@ -1,5 +1,12 @@ # Simon Hu - Design Notebook (Spring 2026) +## Week 6 +### Comments: +Read the paper Design and Constructionof RTL Toolchains at NYU + +Summary of the paper: +This paper describes the design of an open-source RTL verification toolchain developed by the NYU Processor Design Team to replace traditional ad-hoc workflows that rely on commercial EDA tools. The system integrates modern software development tools—CMake for orchestration, Verilator for RTL simulation, vcpkg for dependency management, and Catch2 for testing—to create a portable and automated workflow that students can run on their own machines. The goal is to provide a robust, reproducible, and software-style development environment for hardware design and verification, supporting testing, waveform generation, and continuous integration. + ## Week 5 ### Comments: Read the paper NYU Processor Design Team SoC CPU Core From 3b3f36b2ef1c6e66f7d572e9a7845841eaee91b3 Mon Sep 17 00:00:00 2001 From: 1fHu Date: Sun, 15 Mar 2026 23:29:16 -0400 Subject: [PATCH 2/2] docs(dn)-Simon Hu-03/15/2026 --- src/design_notebooks/2026spring/yh4970.md | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/design_notebooks/2026spring/yh4970.md b/src/design_notebooks/2026spring/yh4970.md index 8abcfc9b..952a9b50 100644 --- a/src/design_notebooks/2026spring/yh4970.md +++ b/src/design_notebooks/2026spring/yh4970.md @@ -1,5 +1,17 @@ # Simon Hu - Design Notebook (Spring 2026) +## Week 7 +### Comments: +In lab 3 exercise 3, the reset and several output is revised, so I need to do correponding changes +in the cpp testing file. After the revision, I verified the testbench and all tests passed. +### Work done: +- revised the lab 3 and verified the testbench on exercise 3. +- terminal respond: +simonlinux@DESKTOP-8L3L3I6:/mnt/e/NYU/processerVIP/onboarding-lab-3/build$ ./exercise3 +Randomness seeded to: 703770779 +=============================================================================== +All tests passed (101 assertions in 1 test case) + ## Week 6 ### Comments: Read the paper Design and Constructionof RTL Toolchains at NYU