diff --git a/src/design_notebooks/2026spring/bln7876.md b/src/design_notebooks/2026spring/bln7876.md
index d2145750..99ee0a08 100644
--- a/src/design_notebooks/2026spring/bln7876.md
+++ b/src/design_notebooks/2026spring/bln7876.md
@@ -30,8 +30,19 @@
 * February 18th: I attended the second team meeting on Zoom due to delaying MTA trains.
 
 ## Week of February 23rd
+### RiSC-16 Onboarding Project
 * February 23rd: [Tim](https://github.com/NYU-Processor-Design/nyu-processor-design.github.io/blob/main/src/design_notebooks/2026spring/tc3956.md) and I finished the module of Assignment 4 of the onboarding project, collaborating using Live Share extension on Virtual Studio Code.
   * We implemented the ALU testbench. We also wondered whether a dedicated folder should be created for testbenches.
   * Another module (Sixth RiSC-16 Module:
 Control Module) of the onboarding project was included in the assignment slides, ofwhich not much information was shared. We henceforth decided not to accomplish it for now.
-  * We were able to meet at the intended time.
\ No newline at end of file
+  * We were able to meet at the intended time.
+
+## Week of March 2nd
+### RiSC-16 Onboarding Project
+* March 2nd: [Tim](https://github.com/NYU-Processor-Design/nyu-processor-design.github.io/blob/main/src/design_notebooks/2026spring/tc3956.md) and I started Assignment 5 of the onboarding project. However, we could not finish due to upcoming midterms so decided to proceed in the following week.
+### Team Meeting
+* March 4th: I attended the third team meeting in-person and chose to be working with [Noah](https://nyu-processor-design.github.io/design_notebooks/2026spring/nm4207.html) and [Ghala](https://nyu-processor-design.github.io/design_notebooks/2026spring/gb2789.html) in the Core team.
+
+## Week of March 9th
+### RiSC-16 Onboarding Project
+* March 11th: [Tim](https://github.com/NYU-Processor-Design/nyu-processor-design.github.io/blob/main/src/design_notebooks/2026spring/tc3956.md) and I started Assignment 5 of the onboarding project. We successfully compiled and ran our RiSC-16 processor with the provided testbench and confirmed all outputs were corrects.
\ No newline at end of file