Skip to content

Commit dec6d10

Browse files
eclipsesweclipsesw
authored
Merge pull request #15 from Rbb666/5.1.0
修复创建芯片工程时排除不必要文件的问题
2 parents 9b4ee12 + 2276309 commit dec6d10

196 files changed

Lines changed: 35277 additions & 6 deletions

File tree

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

‎bsp/stm32/libraries/HAL_Drivers/Kconfig‎

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,62 @@
1+
if BSP_USING_USBD
2+
config BSP_USBD_TYPE_FS
3+
bool
4+
# "USB Full Speed (FS) Core"
5+
config BSP_USBD_TYPE_HS
6+
bool
7+
# "USB High Speed (HS) Core"
8+
9+
config BSP_USBD_SPEED_HS
10+
bool
11+
# "USB High Speed (HS) Mode"
12+
config BSP_USBD_SPEED_HSINFS
13+
bool
14+
# "USB High Speed (HS) Core in FS mode"
15+
16+
config BSP_USBD_PHY_EMBEDDED
17+
bool
18+
# "Using Embedded phy interface"
19+
config BSP_USBD_PHY_UTMI
20+
bool
21+
# "UTMI: USB 2.0 Transceiver Macrocell Interace"
22+
config BSP_USBD_PHY_ULPI
23+
bool
24+
# "ULPI: UTMI+ Low Pin Interface"
25+
endif
26+
27+
config BSP_USING_CRC
28+
bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)"
29+
select RT_USING_HWCRYPTO
30+
select RT_HWCRYPTO_USING_CRC
31+
# "Crypto device frame dose not support above 8-bits granularity"
32+
# "Reserve progress, running well, about 32-bits granularity, such as stm32f1, stm32f4"
33+
depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F0 || SOC_SERIES_STM32F7 || SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1)
34+
default n
35+
36+
config BSP_USING_RNG
37+
bool "Enable RNG (Random Number Generator)"
38+
select RT_USING_HWCRYPTO
39+
select RT_HWCRYPTO_USING_RNG
40+
depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F4 || SOC_SERIES_STM32F7 || \
41+
SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1)
42+
default n
43+
44+
config BSP_USING_HASH
45+
bool "Enable HASH (Hash House Harriers)"
46+
select RT_USING_HWCRYPTO
47+
select RT_HWCRYPTO_USING_HASH
48+
depends on (SOC_SERIES_STM32MP1)
49+
default n
50+
51+
config BSP_USING_CRYP
52+
bool "Enable CRYP (Encrypt And Decrypt Data)"
53+
select RT_USING_HWCRYPTO
54+
select RT_HWCRYPTO_USING_CRYP
55+
depends on (SOC_SERIES_STM32MP1)
56+
default n
57+
58+
config BSP_USING_UDID
59+
bool "Enable UDID (Unique Device Identifier)"
60+
select RT_USING_HWCRYPTO
61+
default n
62+

‎bsp/stm32/libraries/HAL_Drivers/config/f0/adc_config.h‎

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,46 @@
1+
/*
2+
* Copyright (c) 2006-2023, RT-Thread Development Team
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2018-12-24 zylx first version
9+
*/
10+
11+
#ifndef __ADC_CONFIG_H__
12+
#define __ADC_CONFIG_H__
13+
14+
#include <rtthread.h>
15+
16+
#ifdef __cplusplus
17+
extern "C" {
18+
#endif
19+
20+
#ifdef BSP_USING_ADC1
21+
#ifndef ADC1_CONFIG
22+
#define ADC1_CONFIG \
23+
{ \
24+
.Instance = ADC1, \
25+
.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1, \
26+
.Init.Resolution = ADC_RESOLUTION_12B, \
27+
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
28+
.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD, \
29+
.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
30+
.Init.LowPowerAutoWait = DISABLE, \
31+
.Init.LowPowerAutoPowerOff = DISABLE, \
32+
.Init.ContinuousConvMode = DISABLE, \
33+
.Init.DiscontinuousConvMode = ENABLE, \
34+
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
35+
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
36+
.Init.DMAContinuousRequests = ENABLE, \
37+
.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
38+
}
39+
#endif /* ADC1_CONFIG */
40+
#endif /* BSP_USING_ADC1 */
41+
42+
#ifdef __cplusplus
43+
}
44+
#endif
45+
46+
#endif /* __ADC_CONFIG_H__ */

‎bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h‎

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
1+
/*
2+
* Copyright (c) 2006-2023, RT-Thread Development Team
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2018-01-05 zylx first version
9+
* 2019-01-08 SummerGift clean up the code
10+
*/
11+
12+
#ifndef __DMA_CONFIG_H__
13+
#define __DMA_CONFIG_H__
14+
15+
#include <rtthread.h>
16+
17+
#ifdef __cplusplus
18+
extern "C" {
19+
#endif
20+
21+
/* DMA1 channel1 */
22+
23+
/* DMA1 channel2-3 DMA2 channel1-2 */
24+
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
25+
#define UART1_DMA_RX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
26+
#define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN
27+
#define UART1_RX_DMA_INSTANCE DMA1_Channel3
28+
#define UART1_RX_DMA_IRQ DMA1_Ch2_3_DMA2_Ch1_2_IRQn
29+
#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
30+
#define SPI1_DMA_RX_TX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
31+
#define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN
32+
#define SPI1_RX_DMA_INSTANCE DMA1_Channel2
33+
#define SPI1_RX_DMA_IRQ DMA1_Ch2_3_DMA2_Ch1_2_IRQn
34+
#endif
35+
36+
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
37+
#define SPI1_DMA_RX_TX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
38+
#define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN
39+
#define SPI1_TX_DMA_INSTANCE DMA1_Channel3
40+
#define SPI1_TX_DMA_IRQ DMA1_Ch2_3_DMA2_Ch1_2_IRQn
41+
#endif
42+
/* DMA1 channel2-3 DMA2 channel1-2 */
43+
44+
/* DMA1 channel4-7 DMA2 channel3-5 */
45+
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
46+
#define UART2_DMA_RX_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
47+
#define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN
48+
#define UART2_RX_DMA_INSTANCE DMA1_Channel5
49+
#define UART2_RX_DMA_IRQ DMA1_Ch4_7_DMA2_Ch3_5_IRQn
50+
#endif
51+
/* DMA1 channel4-7 DMA2 channel3-5 */
52+
53+
#ifdef __cplusplus
54+
}
55+
#endif
56+
57+
#endif /* __DMA_CONFIG_H__ */

‎bsp/stm32/libraries/HAL_Drivers/config/f0/pwm_config.h‎

Lines changed: 196 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,196 @@
1+
/*
2+
* Copyright (c) 2006-2023, RT-Thread Development Team
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2018-12-24 zylx first version
9+
* 2023-04-08 Wangyuqiang complete PWM defination
10+
*/
11+
12+
#ifndef __PWM_CONFIG_H__
13+
#define __PWM_CONFIG_H__
14+
15+
#include <rtthread.h>
16+
17+
#ifdef __cplusplus
18+
extern "C" {
19+
#endif
20+
21+
#ifdef BSP_USING_PWM1
22+
#define PWM1_CONFIG \
23+
{ \
24+
.tim_handle.Instance = TIM1, \
25+
.name = "pwm1", \
26+
.channel = RT_NULL \
27+
}
28+
#endif /* BSP_USING_PWM1 */
29+
30+
#ifdef BSP_USING_PWM2
31+
#define PWM2_CONFIG \
32+
{ \
33+
.tim_handle.Instance = TIM2, \
34+
.name = "pwm2", \
35+
.channel = RT_NULL \
36+
}
37+
#endif /* BSP_USING_PWM2 */
38+
39+
#ifdef BSP_USING_PWM3
40+
#define PWM3_CONFIG \
41+
{ \
42+
.tim_handle.Instance = TIM3, \
43+
.name = "pwm3", \
44+
.channel = RT_NULL \
45+
}
46+
#endif /* BSP_USING_PWM3 */
47+
48+
#ifdef BSP_USING_PWM4
49+
#define PWM4_CONFIG \
50+
{ \
51+
.tim_handle.Instance = TIM4, \
52+
.name = "pwm4", \
53+
.channel = RT_NULL \
54+
}
55+
#endif /* BSP_USING_PWM4 */
56+
57+
#ifdef BSP_USING_PWM5
58+
#define PWM5_CONFIG \
59+
{ \
60+
.tim_handle.Instance = TIM5, \
61+
.name = "pwm5", \
62+
.channel = RT_NULL \
63+
}
64+
#endif /* BSP_USING_PWM5 */
65+
66+
#ifdef BSP_USING_PWM6
67+
#define PWM6_CONFIG \
68+
{ \
69+
.tim_handle.Instance = TIM6, \
70+
.name = "pwm6", \
71+
.channel = RT_NULL \
72+
}
73+
#endif /* BSP_USING_PWM6 */
74+
75+
#ifdef BSP_USING_PWM7
76+
#define PWM7_CONFIG \
77+
{ \
78+
.tim_handle.Instance = TIM7, \
79+
.name = "pwm7", \
80+
.channel = RT_NULL \
81+
}
82+
#endif /* BSP_USING_PWM7 */
83+
84+
#ifdef BSP_USING_PWM8
85+
#define PWM8_CONFIG \
86+
{ \
87+
.tim_handle.Instance = TIM8, \
88+
.name = "pwm8", \
89+
.channel = RT_NULL \
90+
}
91+
#endif /* BSP_USING_PWM8 */
92+
93+
#ifdef BSP_USING_PWM9
94+
#define PWM9_CONFIG \
95+
{ \
96+
.tim_handle.Instance = TIM9, \
97+
.name = "pwm9", \
98+
.channel = RT_NULL \
99+
}
100+
#endif /* BSP_USING_PWM9 */
101+
102+
#ifdef BSP_USING_PWM10
103+
#define PWM10_CONFIG \
104+
{ \
105+
.tim_handle.Instance = TIM10, \
106+
.name = "pwm10", \
107+
.channel = RT_NULL \
108+
}
109+
#endif /* BSP_USING_PWM10 */
110+
111+
#ifdef BSP_USING_PWM11
112+
#define PWM11_CONFIG \
113+
{ \
114+
.tim_handle.Instance = TIM11, \
115+
.name = "pwm11", \
116+
.channel = RT_NULL \
117+
}
118+
#endif /* BSP_USING_PWM11 */
119+
120+
#ifdef BSP_USING_PWM12
121+
#define PWM12_CONFIG \
122+
{ \
123+
.tim_handle.Instance = TIM12, \
124+
.name = "pwm12", \
125+
.channel = RT_NULL \
126+
}
127+
#endif /* BSP_USING_PWM12 */
128+
129+
#ifdef BSP_USING_PWM13
130+
#define PWM13_CONFIG \
131+
{ \
132+
.tim_handle.Instance = TIM13, \
133+
.name = "pwm13", \
134+
.channel = RT_NULL \
135+
}
136+
#endif /* BSP_USING_PWM13 */
137+
138+
#ifdef BSP_USING_PWM14
139+
#define PWM14_CONFIG \
140+
{ \
141+
.tim_handle.Instance = TIM14, \
142+
.name = "pwm14", \
143+
.channel = RT_NULL \
144+
}
145+
#endif /* BSP_USING_PWM14 */
146+
147+
#ifdef BSP_USING_PWM15
148+
#define PWM15_CONFIG \
149+
{ \
150+
.tim_handle.Instance = TIM15, \
151+
.name = "pwm15", \
152+
.channel = RT_NULL \
153+
}
154+
#endif /* BSP_USING_PWM15 */
155+
156+
#ifdef BSP_USING_PWM16
157+
#define PWM16_CONFIG \
158+
{ \
159+
.tim_handle.Instance = TIM16, \
160+
.name = "pwm16", \
161+
.channel = RT_NULL \
162+
}
163+
#endif /* BSP_USING_PWM16 */
164+
165+
#ifdef BSP_USING_PWM17
166+
#define PWM17_CONFIG \
167+
{ \
168+
.tim_handle.Instance = TIM17, \
169+
.name = "pwm17", \
170+
.channel = RT_NULL \
171+
}
172+
#endif /* BSP_USING_PWM17 */
173+
174+
#ifdef BSP_USING_PWM18
175+
#define PWM18_CONFIG \
176+
{ \
177+
.tim_handle.Instance = TIM18, \
178+
.name = "pwm18", \
179+
.channel = RT_NULL \
180+
}
181+
#endif /* BSP_USING_PWM18 */
182+
183+
#ifdef BSP_USING_PWM19
184+
#define PWM19_CONFIG \
185+
{ \
186+
.tim_handle.Instance = TIM19, \
187+
.name = "pwm19", \
188+
.channel = RT_NULL \
189+
}
190+
#endif /* BSP_USING_PWM19 */
191+
192+
#ifdef __cplusplus
193+
}
194+
#endif
195+
196+
#endif /* __PWM_CONFIG_H__ */

0 commit comments

Comments
 (0)