diff --git a/.github/workflows/ci_results_comment.yml b/.github/workflows/ci_results_comment.yml index 01dd46efe52..607de534b94 100644 --- a/.github/workflows/ci_results_comment.yml +++ b/.github/workflows/ci_results_comment.yml @@ -9,17 +9,17 @@ name: CI Results Comment -# on: -# workflow_run: -# workflows: -# - "RT-Thread BSP Static Build Check" -# - "Static code analysis" -# - "Check File Format and License" -# - "utest_auto_run" -# - "ToolsCI" -# - "pkgs_test" -# types: -# - completed +on: + workflow_run: + workflows: + - "RT-Thread BSP Static Build Check" + - "Static code analysis" + - "Check File Format and License" + - "utest_auto_run" + - "ToolsCI" + - "pkgs_test" + types: + - completed permissions: pull-requests: write diff --git a/.github/workflows/post_ci_status.yml b/.github/workflows/post_ci_status.yml index 1f24592c800..39b93875800 100644 --- a/.github/workflows/post_ci_status.yml +++ b/.github/workflows/post_ci_status.yml @@ -9,21 +9,21 @@ name: Post CI Status Comment -# on: -# workflow_call: -# inputs: -# workflow_name: -# description: 'Name of the workflow' -# required: true -# type: string -# workflow_status: -# description: 'Status of the workflow (success/failure)' -# required: true -# type: string -# pr_number: -# description: 'Pull request number' -# required: true -# type: number +on: + workflow_call: + inputs: + workflow_name: + description: 'Name of the workflow' + required: true + type: string + workflow_status: + description: 'Status of the workflow (success/failure)' + required: true + type: string + pr_number: + description: 'Pull request number' + required: true + type: number permissions: pull-requests: write diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config index af50c62b1e4..c1c6211680e 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config @@ -238,10 +238,11 @@ CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -# CONFIG_RT_SERIAL_USING_DMA is not set -CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set +CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y +CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_CLOCK_TIME is not set @@ -269,7 +270,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_LCD is not set # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set # CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set # CONFIG_RT_USING_VIRTIO is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_CHERRYUSB is not set @@ -584,6 +588,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # tools packages # # CONFIG_PKG_USING_VECTOR is not set +# CONFIG_PKG_USING_SORCH is not set +# CONFIG_PKG_USING_DICT is not set # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set @@ -730,6 +736,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_HEARTBEAT is not set # CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set # CONFIG_PKG_USING_CHERRYECAT is not set +# CONFIG_PKG_USING_EVENT_LOOP is not set +# CONFIG_PKG_USING_THREAD_MANAGER is not set # end of system packages # @@ -878,9 +886,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # # NUVOTON Drivers # -# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set # CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set -# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set # end of NUVOTON Drivers # @@ -1086,6 +1092,7 @@ CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" # CONFIG_PKG_USING_ISOTP_C is not set # CONFIG_PKG_USING_IKUNLED is not set # CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_IRUART is not set # CONFIG_PKG_USING_ST7305 is not set # CONFIG_PKG_USING_TM1668 is not set # CONFIG_PKG_USING_SPI_TOOLS is not set @@ -1441,15 +1448,18 @@ CONFIG_SOC_MIMXRT1189CVM8C_CM33=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_DMA=y -# CONFIG_BSP_USING_GPIO is not set +CONFIG_BSP_USING_GPIO=y # CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_USB is not set # CONFIG_BSP_USING_SDIO is not set CONFIG_BSP_USING_LPUART=y CONFIG_BSP_USING_LPUART1=y -# CONFIG_BSP_LPUART1_RX_USING_DMA is not set -# CONFIG_BSP_LPUART1_TX_USING_DMA is not set -# CONFIG_BSP_USING_LPUART3 is not set +CONFIG_BSP_LPUART1_RX_USING_DMA=y +CONFIG_BSP_LPUART1_RX_DMA_CHANNEL=0 +CONFIG_BSP_LPUART1_TX_USING_DMA=y +CONFIG_BSP_LPUART1_TX_DMA_CHANNEL=1 +# CONFIG_BSP_USING_LPUART10 is not set +# CONFIG_BSP_USING_LPUART12 is not set # CONFIG_BSP_USING_CAN is not set # CONFIG_BSP_USING_FLEXSPI is not set # end of On-chip Peripheral Drivers diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/main.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/main.c index db33aa290d8..3d1a0910769 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/main.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/main.c @@ -12,14 +12,21 @@ #include #include #include -#include + +#define LED_PIN GET_PIN(4, 27) int main(void) { rt_kprintf("MIMXRT1180_CM33 Hello_World\r\n"); + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); while (1) { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); rt_thread_mdelay(500); } } + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig index 12d8078d8c2..8266b6e9faf 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig @@ -99,34 +99,62 @@ menu "On-chip Peripheral Drivers" int "Set LPUART1 TX DMA channel (0-32)" default 1 - config BSP_USING_LPUART3 - bool "Enable LPUART3" - default n - - config BSP_LPUART3_RX_USING_DMA - bool "Enable LPUART3 RX DMA" - depends on BSP_USING_LPUART3 - select BSP_USING_DMA - select RT_SERIAL_USING_DMA - default n - - config BSP_LPUART3_RX_DMA_CHANNEL - depends on BSP_LPUART3_RX_USING_DMA - int "Set LPUART3 RX DMA channel (0-32)" - default 0 - - config BSP_LPUART3_TX_USING_DMA - bool "Enable LPUART3 TX DMA" - depends on BSP_USING_LPUART3 - select BSP_USING_DMA - select RT_SERIAL_USING_DMA - default n - - config BSP_LPUART3_TX_DMA_CHANNEL - depends on BSP_LPUART3_TX_USING_DMA - int "Set LPUART3 TX DMA channel (0-32)" - default 1 - endif + config BSP_USING_LPUART10 + bool "Enable LPUART10" + default n + + config BSP_LPUART10_RX_USING_DMA + bool "Enable LPUART10 RX DMA" + depends on BSP_USING_LPUART10 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART10_RX_DMA_CHANNEL + depends on BSP_LPUART10_RX_USING_DMA + int "Set LPUART10 RX DMA channel (0-32)" + default 0 + + config BSP_LPUART10_TX_USING_DMA + bool "Enable LPUART10 TX DMA" + depends on BSP_USING_LPUART10 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART10_TX_DMA_CHANNEL + depends on BSP_LPUART10_TX_USING_DMA + int "Set LPUART10 TX DMA channel (0-32)" + default 1 + + config BSP_USING_LPUART12 + bool "Enable LPUART12" + default n + + config BSP_LPUART12_RX_USING_DMA + bool "Enable LPUART12 RX DMA" + depends on BSP_USING_LPUART12 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART12_RX_DMA_CHANNEL + depends on BSP_LPUART12_RX_USING_DMA + int "Set LPUART12 RX DMA channel (0-32)" + default 2 + + config BSP_LPUART12_TX_USING_DMA + bool "Enable LPUART12 TX DMA" + depends on BSP_USING_LPUART12 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART12_TX_DMA_CHANNEL + depends on BSP_LPUART12_TX_USING_DMA + int "Set LPUART12 TX DMA channel (0-32)" + default 3 + endif menuconfig BSP_USING_CAN bool "Enable CAN" diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c index 9ef62aca0ed..e95691074c4 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c @@ -57,37 +57,44 @@ void BOARD_InitPins(void) { CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ -// /* GPIO configuration on GPIO_AD_27 (pin M16) */ -// rgpio_pin_config_t gpio4_pinM16_config = { -// .pinDirection = kRGPIO_DigitalOutput, -// .outputLogic = 1U, -// }; -// /* Initialize GPIO functionality on GPIO_AD_27 (pin M16) */ -// RGPIO_PinInit(RGPIO4, 27U, &gpio4_pinM16_config); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_08_LPUART1_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_09_LPUART1_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_08_LPUART1_TX, + 0x02U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_09_LPUART1_RX, + 0x02U); + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_32_LPUART10_TX, + 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_33_LPUART10_RX, + 0U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_32_LPUART10_TX, + 0x02U); + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_33_LPUART10_RX, + 0x02U); -// IOMUXC_SetPinMux( -// IOMUXC_GPIO_AD_27_GPIO4_IO27, /* GPIO_AD_27 is configured as GPIO4_IO27 */ -// 0U); IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_GPIO_AON_19_LPUART12_TX, + 0U); IOMUXC_SetPinMux( - IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_GPIO_AON_20_LPUART12_RX, + 0U); IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 PAD functional properties : */ - 0x02U); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: high driver - Pull / Keep Select Field: Pull Disable, Highz - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled */ + IOMUXC_GPIO_AON_19_LPUART12_TX, + 0x02U); IOMUXC_SetPinConfig( - IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 PAD functional properties : */ - 0x02U); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: high driver - Pull / Keep Select Field: Pull Disable, Highz - Pull Up / Down Config. Field: Weak pull down - Open Drain Field: Disabled */ + IOMUXC_GPIO_AON_20_LPUART12_RX, + 0x02U); } void BOARD_InitLeds(void) { diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c index 2557a72bc40..ca489b8e703 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c @@ -1267,6 +1267,10 @@ void rt_hw_board_init() rt_components_board_init(); #endif +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + #ifdef RT_USING_CONSOLE rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif @@ -1276,8 +1280,6 @@ void rt_hw_board_init() rt_kprintf("Heap: 0x%08x - 0x%08x (Size: %d bytes)\n", HEAP_BEGIN, HEAP_END, (uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN); - - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif } diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.scf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.scf index 9ee6de8571d..9368c687206 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.scf +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.scf @@ -78,7 +78,7 @@ #if defined(__heap_size__) #define heap_size __heap_size__ #else - #define heap_size 0x04000 + #define heap_size 0x20000 #endif /* Target specific definition, code & data allocation */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/project.uvoptx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/project.uvoptx new file mode 100644 index 00000000000..2d4e331b3ae --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/project.uvoptx @@ -0,0 +1,1204 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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+ 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + thread.c + 1 + ..\..\..\..\..\..\src\thread.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + timer.c + 1 + ..\..\..\..\..\..\src\timer.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + Libc + + + syscall_mem.c + 1 + ..\..\..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + syscalls.c + 1 + ..\..\..\..\..\..\components\libc\compilers\armlibc\syscalls.c + + + cctype.c + 1 + ..\..\..\..\..\..\components\libc\compilers\common\cctype.c + + + cstdlib.c + 1 + ..\..\..\..\..\..\components\libc\compilers\common\cstdlib.c + + + cstring.c + 1 + ..\..\..\..\..\..\components\libc\compilers\common\cstring.c + + + ctime.c + 1 + ..\..\..\..\..\..\components\libc\compilers\common\ctime.c + + + cunistd.c + 1 + ..\..\..\..\..\..\components\libc\compilers\common\cunistd.c + + + cwchar.c + 1 + ..\..\..\..\..\..\components\libc\compilers\common\cwchar.c + + + kerrno.c + 1 + ..\..\..\..\..\..\src\klibc\kerrno.c + + + kstdio.c + 1 + ..\..\..\..\..\..\src\klibc\kstdio.c + + + kstring.c + 1 + ..\..\..\..\..\..\src\klibc\kstring.c + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + rt_vsscanf.c + 1 + ..\..\..\..\..\..\src\klibc\rt_vsscanf.c + + + + + Libraries + + + fsl_common.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_common.c + + + fsl_common_arm.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_common_arm.c + + + fsl_dcdc.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_dcdc.c + + + fsl_pmu.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_pmu.c + + + fsl_clock.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_clock.c + + + fsl_ele_base_api.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_ele_base_api.c + + + fsl_s3mu.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_s3mu.c + + + fsl_trdc.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_trdc.c + + + fsl_gpc.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_gpc.c + + + fsl_memory.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_memory.c + + + fsl_soc_src.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_soc_src.c + + + fsl_rgpio.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_rgpio.c + + + fsl_lpuart.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_lpuart.c + + + fsl_edma.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_edma.c + + + fsl_edma_soc.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_edma_soc.c + + + fsl_lpuart_edma.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_lpuart_edma.c + + + system_MIMXRT1189_cm33.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\system_MIMXRT1189_cm33.c + + + fsl_cache.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\cm33\fsl_cache.c + + + startup_MIMXRT1189_cm33.s + 2 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\arm\startup_MIMXRT1189_cm33.s + + + + + xip + + + evkmimxrt1180_flexspi_nor_config.c + 1 + xip\evkmimxrt1180_flexspi_nor_config.c + + + fsl_flexspi_nor_boot.c + 1 + xip\fsl_flexspi_nor_boot.c + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h index c0b50be6fce..c9375ca62a8 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h @@ -147,8 +147,9 @@ #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_BUF_STRATEGY_OVERWRITE +#define RT_SERIAL_USING_DMA #define RT_USING_PIN /* end of Device Drivers */ @@ -419,8 +420,13 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_DMA +#define BSP_USING_GPIO #define BSP_USING_LPUART #define BSP_USING_LPUART1 +#define BSP_LPUART1_RX_USING_DMA +#define BSP_LPUART1_RX_DMA_CHANNEL 0 +#define BSP_LPUART1_TX_USING_DMA +#define BSP_LPUART1_TX_DMA_CHANNEL 1 /* end of On-chip Peripheral Drivers */ /* Onboard Peripheral Drivers */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx index cef821f2bc6..f7a2729ccd2 100644 --- a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx @@ -1061,9 +1061,9 @@ - dev_serial.c + dev_serial_v2.c 1 - ..\..\..\..\..\components\drivers\serial\dev_serial.c + ..\..\..\..\..\components\drivers\serial\dev_serial_v2.c 2 @@ -2161,6 +2161,21 @@ 1 packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_lpuart.c + + fsl_lpuart_edma.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_lpuart_edma.c + + + fsl_edma.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_edma.c + + + fsl_edma_soc.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_edma_soc.c + fsl_dcdc.c 1 diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.c index 018785b945c..8e93d07bdd4 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_gpio.c @@ -7,6 +7,7 @@ * Date Author Notes * 2018-4-30 misonyo the first version. * 2022-6-22 solar Implement api docking of rt_pin_get. + * 2026-6-9 shannon support IMXRT1180 series. */ #include @@ -15,13 +16,21 @@ #include #include "drv_gpio.h" #include "board.h" +#ifdef SOC_IMXRT1180_SERIES +#include "fsl_rgpio.h" +#else #include "fsl_gpio.h" +#endif #include "fsl_iomuxc.h" #define LOG_TAG "drv.gpio" #include +#ifdef SOC_IMXRT1180_SERIES +#define IMX_PIN_NUM(port, no) (((((port) & 0x7u) << 5) | ((no) & 0x1Fu))) +#else #define IMX_PIN_NUM(port, no) (((((port) & 0x5u) << 5) | ((no) & 0x1Fu))) +#endif #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!" @@ -29,8 +38,10 @@ #define __IMXRT_HDR_DEFAULT {-1, 0, RT_NULL, RT_NULL} -#ifdef SOC_IMXRT1170_SERIES +#if defined(SOC_IMXRT1170_SERIES) #define PIN_INVALID_CHECK(PORT_INDEX, PIN_NUM) (PORT_INDEX > 7) || ((mask_tab[PORT_INDEX].valid_mask & (1 << PIN_NUM)) == 0) +#elif defined(SOC_IMXRT1180_SERIES) +#define PIN_INVALID_CHECK(PORT_INDEX, PIN_NUM) (PORT_INDEX > 5) || ((mask_tab[PORT_INDEX].valid_mask & (1 << PIN_NUM)) == 0) #else #define PIN_INVALID_CHECK(PORT_INDEX, PIN_NUM) (PORT_INDEX > 4) || ((mask_tab[PORT_INDEX].valid_mask & (1 << PIN_NUM)) == 0) #endif @@ -44,6 +55,9 @@ #elif defined(SOC_IMXRT1170_SERIES) #define MUX_BASE 0x400E8010 #define CONFIG_BASE 0x400E8254 +#elif defined(SOC_IMXRT1180_SERIES) +#define MUX_BASE (IOMUXC_BASE + 0x10u) +#define CONFIG_BASE (IOMUXC_BASE + 0x258u) #else /* 1050 & 1060 & 1064 series*/ #define MUX_BASE 0x401f8014 #define CONFIG_BASE 0x401f8204 @@ -56,13 +70,28 @@ #define GPIO13_MUX_BASE 0x40C94000 #define GPIO13_CONFIG_BASE 0x40C94040 +#if defined(SOC_IMXRT1180_SERIES) +#define AON_MUX_BASE (IOMUXC_AON_BASE) +#define AON_CONFIG_BASE (IOMUXC_AON_BASE + 0x74u) +#endif + struct pin_mask { +#if defined(SOC_IMXRT1180_SERIES) + RGPIO_Type *gpio; +#else GPIO_Type *gpio; +#endif rt_int32_t valid_mask; }; +#if defined(SOC_IMXRT1170_SERIES) const struct pin_mask mask_tab[7] = +#elif defined(SOC_IMXRT1180_SERIES) +const struct pin_mask mask_tab[6] = +#else +const struct pin_mask mask_tab[5] = +#endif { #if defined(SOC_IMXRT1015_SERIES) {GPIO1, 0xfc00ffff}, /* GPIO1,16~25 not supported */ @@ -84,6 +113,13 @@ const struct pin_mask mask_tab[7] = {GPIO5, 0x0001ffff}, {GPIO6, 0x0000ffff}, {GPIO13, 0x00001fff}, +#elif defined(SOC_IMXRT1180_SERIES) + {RGPIO1, 0x0fffffff}, /* GPIO1, pins 28~31 not supported */ + {RGPIO2, 0xffffffff}, /* GPIO2 */ + {RGPIO3, 0x7fffffff}, /* GPIO3, pin 31 not supported */ + {RGPIO4, 0xffffffff}, /* GPIO4 */ + {RGPIO5, 0x007fffff}, /* GPIO5, pins 23~31 not supported */ + {RGPIO6, 0x0fffffff}, /* GPIO6, pins 28~31 not supported */ #else /* 1050 & 1060 & 1064 series*/ {GPIO1, 0xffffffff}, /* GPIO1 */ {GPIO2, 0xffffffff}, /* GPIO2 */ @@ -110,6 +146,25 @@ const rt_int32_t reg_offset[] = 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, 128,129, 130,131,132,133,134,135,136,137,138,139,140,141,142,143,144, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, +#elif defined(SOC_IMXRT1180_SERIES) + /* GPIO1 (AON domain) */ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, -1, -1, -1, -1, + /* GPIO2 (main domain) */ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + /* GPIO3 (main domain) */ + 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, -1, + /* GPIO4 (main domain) */ + 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, + 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, + /* GPIO5 (main domain) */ + 95, 96, 97, 98, 99,100,101,102,103,104,105,106,107,108,109,110, + 111,112,113,114,115,116,117, -1, -1, -1, -1, -1, -1, -1, -1, -1, + /* GPIO6 (main domain) */ + 118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133, + 134,135,136,137,138,139,140,141,142,143,144,145, -1, -1, -1, -1, #else /* 1050 & 1060 & 1064 series*/ 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,103,104,105, @@ -119,8 +174,22 @@ const rt_int32_t reg_offset[] = }; -static const IRQn_Type irq_tab[13] = +static const IRQn_Type irq_tab[] = { +#if defined(SOC_IMXRT1180_SERIES) + GPIO1_0_IRQn, + GPIO1_1_IRQn, + GPIO2_0_IRQn, + GPIO2_1_IRQn, + GPIO3_0_IRQn, + GPIO3_1_IRQn, + GPIO4_IRQn, + GPIO4_IRQn, + GPIO5_IRQn, + GPIO5_IRQn, + GPIO6_IRQn, + GPIO6_IRQn, +#else GPIO1_Combined_0_15_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_0_15_IRQn, @@ -138,10 +207,67 @@ static const IRQn_Type irq_tab[13] = GPIO6_Combined_16_31_IRQn, GPIO13_Combined_0_31_IRQn #endif +#endif }; static struct rt_pin_irq_hdr hdr_tab[] = { +#if defined(SOC_IMXRT1180_SERIES) + /* GPIO1 */ + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + /* GPIO2 */ + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + /* GPIO3 */ + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + /* GPIO4 */ + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + /* GPIO5 */ + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + /* GPIO6 */ + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, + __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, +#else /* GPIO1 */ __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, @@ -375,8 +501,32 @@ static struct rt_pin_irq_hdr hdr_tab[] = __IMXRT_HDR_DEFAULT, __IMXRT_HDR_DEFAULT, #endif +#endif }; +#if defined(SOC_IMXRT1180_SERIES) +static void imxrt_isr(rt_int16_t index_offset, rt_int8_t pin_start, RGPIO_Type *base) +{ + rt_int32_t isr_status, index; + rt_int8_t i, pin_end; + + pin_end = pin_start + 15; + isr_status = RGPIO_GetPinsInterruptFlags(base, 0); + + for (i = pin_start; i <= pin_end ; i++) + { + if (isr_status & (1 << i)) + { + RGPIO_ClearPinsInterruptFlags(base, 0, (1 << i)); + index = index_offset + i; + if (hdr_tab[index].hdr != RT_NULL) + { + hdr_tab[index].hdr(hdr_tab[index].args); + } + } + } +} +#else static void imxrt_isr(rt_int16_t index_offset, rt_int8_t pin_start, GPIO_Type *base) { rt_int32_t isr_status, index; @@ -398,7 +548,73 @@ static void imxrt_isr(rt_int16_t index_offset, rt_int8_t pin_start, GPIO_Type *b } } } +#endif +#if defined(SOC_IMXRT1180_SERIES) +/* GPIO1 index offset is 0 */ +void GPIO1_0_IRQHandler(void) +{ + rt_interrupt_enter(); + imxrt_isr(0, 0, RGPIO1); + rt_interrupt_leave(); +} +void GPIO1_1_IRQHandler(void) +{ + rt_interrupt_enter(); + imxrt_isr(0, 16, RGPIO1); + rt_interrupt_leave(); +} +/* GPIO2 index offset is 32 */ +void GPIO2_0_IRQHandler(void) +{ + rt_interrupt_enter(); + imxrt_isr(32, 0, RGPIO2); + rt_interrupt_leave(); +} +void GPIO2_1_IRQHandler(void) +{ + rt_interrupt_enter(); + imxrt_isr(32, 16, RGPIO2); + rt_interrupt_leave(); +} +/* GPIO3 index offset is 64 */ +void GPIO3_0_IRQHandler(void) +{ + rt_interrupt_enter(); + imxrt_isr(64, 0, RGPIO3); + rt_interrupt_leave(); +} +void GPIO3_1_IRQHandler(void) +{ + rt_interrupt_enter(); + imxrt_isr(64, 16, RGPIO3); + rt_interrupt_leave(); +} +/* GPIO4 index offset is 96 */ +void GPIO4_IRQHandler(void) +{ + rt_interrupt_enter(); + imxrt_isr(96, 0, RGPIO4); + imxrt_isr(96, 16, RGPIO4); + rt_interrupt_leave(); +} +/* GPIO5 index offset is 128 */ +void GPIO5_IRQHandler(void) +{ + rt_interrupt_enter(); + imxrt_isr(128, 0, RGPIO5); + imxrt_isr(128, 16, RGPIO5); + rt_interrupt_leave(); +} +/* GPIO6 index offset is 160 */ +void GPIO6_IRQHandler(void) +{ + rt_interrupt_enter(); + imxrt_isr(160, 0, RGPIO6); + imxrt_isr(160, 16, RGPIO6); + rt_interrupt_leave(); +} +#else /* GPIO1 index offset is 0 */ void GPIO1_Combined_0_15_IRQHandler(void) { @@ -519,12 +735,18 @@ void GPIO13_Combined_0_31_IRQHandler(void) rt_interrupt_leave(); } #endif +#endif static void imxrt_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) { - gpio_pin_config_t gpio; rt_int8_t port, pin_num; -#ifndef SOC_IMXRT1170_SERIES +#if defined(SOC_IMXRT1180_SERIES) + rgpio_pin_config_t gpio; + rt_uint32_t config_value = 0; +#elif defined(SOC_IMXRT1170_SERIES) + gpio_pin_config_t gpio; +#else + gpio_pin_config_t gpio; rt_uint32_t config_value = 0; #endif @@ -537,6 +759,53 @@ static void imxrt_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) return; } +#if defined(SOC_IMXRT1180_SERIES) + gpio.outputLogic = 0; + gpio.pinDirection = kRGPIO_DigitalOutput; + + switch (mode) + { + case PIN_MODE_OUTPUT: + gpio.pinDirection = kRGPIO_DigitalOutput; + config_value = 0x02U; /* DSE=1 (high driver), ODE=0 (push-pull) */ + break; + case PIN_MODE_INPUT: + gpio.pinDirection = kRGPIO_DigitalInput; + config_value = 0x00U; /* no pull, input buffer on */ + break; + case PIN_MODE_INPUT_PULLDOWN: + gpio.pinDirection = kRGPIO_DigitalInput; + config_value = 0x04U; /* PUE=1, PUS=0 (weak pull down) */ + break; + case PIN_MODE_INPUT_PULLUP: + gpio.pinDirection = kRGPIO_DigitalInput; + config_value = 0x0CU; /* PUE=1, PUS=1 (weak pull up) */ + break; + case PIN_MODE_OUTPUT_OD: + gpio.pinDirection = kRGPIO_DigitalOutput; + config_value = 0x12U; /* ODE=1 (open drain), DSE=1 */ + break; + } + + CLOCK_EnableClock(kCLOCK_Iomuxc1); + + if (mask_tab[port].gpio == RGPIO1) + { + /* AON domain GPIO1 */ + CLOCK_EnableClock(kCLOCK_Iomuxc2); + IOMUXC_SetPinMux(AON_MUX_BASE + pin_num * 4, 0x0U, 0, 0, AON_CONFIG_BASE + pin_num * 4, 1); + IOMUXC_SetPinConfig(AON_MUX_BASE + pin_num * 4, 0x0U, 0, 0, AON_CONFIG_BASE + pin_num * 4, config_value); + } + else + { + /* Main domain GPIO2-6 */ + IOMUXC_SetPinMux(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, 1); + IOMUXC_SetPinConfig(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, config_value); + } + + RGPIO_PinInit(mask_tab[port].gpio, pin_num, &gpio); + +#else /* other SOC series */ gpio.outputLogic = 0; gpio.interruptMode = kGPIO_NoIntmode; @@ -620,6 +889,7 @@ static void imxrt_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) #endif GPIO_PinInit(mask_tab[port].gpio, pin_num, &gpio); +#endif } static rt_ssize_t imxrt_pin_read(rt_device_t dev, rt_base_t pin) @@ -637,7 +907,11 @@ static rt_ssize_t imxrt_pin_read(rt_device_t dev, rt_base_t pin) return -RT_EINVAL; } +#if defined(SOC_IMXRT1180_SERIES) + return RGPIO_PinRead(mask_tab[port].gpio, pin_num); +#else return GPIO_PinReadPadStatus(mask_tab[port].gpio, pin_num); +#endif } static void imxrt_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) @@ -653,7 +927,11 @@ static void imxrt_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) return; } +#if defined(SOC_IMXRT1180_SERIES) + RGPIO_PinWrite(mask_tab[port].gpio, pin_num, value); +#else GPIO_PinWrite(mask_tab[port].gpio, pin_num, value); +#endif } static rt_err_t imxrt_pin_attach_irq(struct rt_device *device, rt_base_t pin, @@ -721,7 +999,6 @@ static rt_err_t imxrt_pin_detach_irq(struct rt_device *device, rt_base_t pin) static rt_err_t imxrt_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled) { - gpio_interrupt_mode_t int_mode; rt_int8_t port, pin_num, irq_index; port = pin >> 5; @@ -739,6 +1016,63 @@ static rt_err_t imxrt_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt return -RT_ENOSYS; } +#if defined(SOC_IMXRT1180_SERIES) + if (enabled == PIN_IRQ_ENABLE) + { + rgpio_interrupt_config_t int_mode; + + switch (hdr_tab[pin].mode) + { + case PIN_IRQ_MODE_RISING: + int_mode = kRGPIO_InterruptRisingEdge; + break; + case PIN_IRQ_MODE_FALLING: + int_mode = kRGPIO_InterruptFallingEdge; + break; + case PIN_IRQ_MODE_RISING_FALLING: + int_mode = kRGPIO_InterruptEitherEdge; + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + int_mode = kRGPIO_InterruptLogicOne; + break; + case PIN_IRQ_MODE_LOW_LEVEL: + int_mode = kRGPIO_InterruptLogicZero; + break; + default: + int_mode = kRGPIO_InterruptRisingEdge; + break; + } + irq_index = (port << 1) + (pin_num >> 4); + RGPIO_SetPinInterruptConfig(mask_tab[port].gpio, pin_num, 0, int_mode); + if (pin_num < 16) + { + mask_tab[port].gpio->GICLR = (1U << pin_num); + } + else + { + mask_tab[port].gpio->GICHR = (1U << (pin_num - 16)); + } + NVIC_SetPriority(irq_tab[irq_index], NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0)); + EnableIRQ(irq_tab[irq_index]); + } + else if (enabled == PIN_IRQ_DISABLE) + { + if (pin_num < 16) + { + mask_tab[port].gpio->GICLR = (1U << (pin_num + 16)); + } + else + { + mask_tab[port].gpio->GICHR = (1U << pin_num); + } + } + else + { + return -RT_EINVAL; + } +#else + gpio_interrupt_mode_t int_mode; + if (enabled == PIN_IRQ_ENABLE) { switch (hdr_tab[pin].mode) @@ -776,6 +1110,7 @@ static rt_err_t imxrt_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt { return -RT_EINVAL; } +#endif return RT_EOK; } @@ -798,7 +1133,11 @@ static rt_base_t imxrt_pin_get(const char *name) return -RT_EINVAL; } +#if defined(SOC_IMXRT1180_SERIES) + if ((name[1] >= '1') && (name[1] <= '6')) +#else if ((name[1] >= '1') && (name[1] <= '5')) +#endif { hw_port_num = (int)(name[1] - '1'); } diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c index 2ad546fb45e..5168fad3afa 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c @@ -8,6 +8,7 @@ * 2017-10-10 Tanek the first version * 2019-5-10 misonyo add DMA TX and RX function * 2026-4-29 Ran add RT1180 support + * 2026-6-4 shannon add LPUART10/12, Serial V2, DMA (V2) */ #include #ifdef BSP_USING_LPUART @@ -55,6 +56,12 @@ enum #ifdef BSP_USING_LPUART8 LPUART8_INDEX, #endif +#ifdef BSP_USING_LPUART10 + LPUART10_INDEX, +#endif +#ifdef BSP_USING_LPUART12 + LPUART12_INDEX, +#endif }; #if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) @@ -64,6 +71,7 @@ struct dma_rx_config dma_request_source_t request; rt_uint8_t channel; rt_uint32_t last_index; + EDMA_Type *edma_base; }; struct dma_tx_config @@ -72,6 +80,7 @@ struct dma_tx_config lpuart_edma_handle_t uart_edma; dma_request_source_t request; rt_uint8_t channel; + EDMA_Type *edma_base; }; #endif @@ -187,258 +196,244 @@ static struct imxrt_uart uarts[] = .dma_flag = 0, }, #endif +#ifdef BSP_USING_LPUART10 + { + .name = "uart10", + .uart_base = LPUART10, + .irqn = LPUART10_IRQn, +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) + .dma_rx = RT_NULL, + .dma_tx = RT_NULL, +#endif + .dma_flag = 0, + }, +#endif +#ifdef BSP_USING_LPUART12 + { + .name = "uart12", + .uart_base = LPUART12, + .irqn = LPUART12_IRQn, +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) + .dma_rx = RT_NULL, + .dma_tx = RT_NULL, +#endif + .dma_flag = 0, + }, +#endif }; static void uart_get_dma_config(void) { +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) +#ifdef SOC_IMXRT1180_SERIES #ifdef BSP_LPUART1_RX_USING_DMA - static struct dma_rx_config uart1_dma_rx = {.request = kDmaRequestMuxLPUART1Rx, .channel = BSP_LPUART1_RX_DMA_CHANNEL, .last_index = 0}; + static struct dma_rx_config uart1_dma_rx = + {.request = kDma3RequestMuxLPUART1Rx, .channel = BSP_LPUART1_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA3}; uarts[LPUART1_INDEX].dma_rx = &uart1_dma_rx; uarts[LPUART1_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif #ifdef BSP_LPUART1_TX_USING_DMA - static struct dma_tx_config uart1_dma_tx = {.request = kDmaRequestMuxLPUART1Tx, .channel = BSP_LPUART1_TX_DMA_CHANNEL}; + static struct dma_tx_config uart1_dma_tx = + {.request = kDma3RequestMuxLPUART1Tx, .channel = BSP_LPUART1_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA3}; uarts[LPUART1_INDEX].dma_tx = &uart1_dma_tx; uarts[LPUART1_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif - -#ifdef BSP_LPUART2_RX_USING_DMA - static struct dma_rx_config uart2_dma_rx = {.request = kDmaRequestMuxLPUART2Rx, .channel = BSP_LPUART2_RX_DMA_CHANNEL, .last_index = 0}; - uarts[LPUART2_INDEX].dma_rx = &uart2_dma_rx; - uarts[LPUART2_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; -#endif -#ifdef BSP_LPUART2_TX_USING_DMA - static struct dma_tx_config uart2_dma_tx = {.request = kDmaRequestMuxLPUART2Tx, .channel = BSP_LPUART2_TX_DMA_CHANNEL}; - uarts[LPUART2_INDEX].dma_tx = &uart2_dma_tx; - uarts[LPUART2_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif -#ifdef BSP_LPUART3_RX_USING_DMA - static struct dma_rx_config uart3_dma_rx = {.request = kDmaRequestMuxLPUART3Rx, .channel = BSP_LPUART3_RX_DMA_CHANNEL, .last_index = 0}; - uarts[LPUART3_INDEX].dma_rx = &uart3_dma_rx; - uarts[LPUART3_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#ifdef BSP_LPUART10_RX_USING_DMA + static struct dma_rx_config uart10_dma_rx = + {.request = kDma4RequestMuxLPUART10Rx, .channel = BSP_LPUART10_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA4}; + uarts[LPUART10_INDEX].dma_rx = &uart10_dma_rx; + uarts[LPUART10_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif -#ifdef BSP_LPUART3_TX_USING_DMA - static struct dma_tx_config uart3_dma_tx = {.request = kDmaRequestMuxLPUART3Tx, .channel = BSP_LPUART3_TX_DMA_CHANNEL}; - uarts[LPUART3_INDEX].dma_tx = &uart3_dma_tx; - uarts[LPUART3_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; +#ifdef BSP_LPUART10_TX_USING_DMA + static struct dma_tx_config uart10_dma_tx = + {.request = kDma4RequestMuxLPUART10Tx, .channel = BSP_LPUART10_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA4}; + uarts[LPUART10_INDEX].dma_tx = &uart10_dma_tx; + uarts[LPUART10_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif -#ifdef BSP_LPUART4_RX_USING_DMA - static struct dma_rx_config uart4_dma_rx = {.request = kDmaRequestMuxLPUART4Rx, .channel = BSP_LPUART4_RX_DMA_CHANNEL, .last_index = 0}; - uarts[LPUART4_INDEX].dma_rx = &uart4_dma_rx; - uarts[LPUART4_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#ifdef BSP_LPUART12_RX_USING_DMA + static struct dma_rx_config uart12_dma_rx = + {.request = kDma3RequestMuxLPUART12Rx, .channel = BSP_LPUART12_RX_DMA_CHANNEL, .last_index = 0, .edma_base = (EDMA_Type *)DMA3}; + uarts[LPUART12_INDEX].dma_rx = &uart12_dma_rx; + uarts[LPUART12_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; #endif -#ifdef BSP_LPUART4_TX_USING_DMA - static struct dma_tx_config uart4_dma_tx = {.request = kDmaRequestMuxLPUART4Tx, .channel = BSP_LPUART4_TX_DMA_CHANNEL}; - uarts[LPUART4_INDEX].dma_tx = &uart4_dma_tx; - uarts[LPUART4_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; -#endif - -#ifdef BSP_LPUART5_RX_USING_DMA - static struct dma_rx_config uart5_dma_rx = {.request = kDmaRequestMuxLPUART5Rx, .channel = BSP_LPUART5_RX_DMA_CHANNEL, .last_index = 0}; - uarts[LPUART5_INDEX].dma_rx = &uart5_dma_rx; - uarts[LPUART5_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; +#ifdef BSP_LPUART12_TX_USING_DMA + static struct dma_tx_config uart12_dma_tx = + {.request = kDma3RequestMuxLPUART12Tx, .channel = BSP_LPUART12_TX_DMA_CHANNEL, .edma_base = (EDMA_Type *)DMA3}; + uarts[LPUART12_INDEX].dma_tx = &uart12_dma_tx; + uarts[LPUART12_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif -#ifdef BSP_LPUART5_TX_USING_DMA - static struct dma_tx_config uart5_dma_tx = {.request = kDmaRequestMuxLPUART5Tx, .channel = BSP_LPUART5_TX_DMA_CHANNEL}; - uarts[LPUART5_INDEX].dma_tx = &uart5_dma_tx; - uarts[LPUART5_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; -#endif - -#ifdef BSP_LPUART6_RX_USING_DMA - static struct dma_rx_config uart6_dma_rx = {.request = kDmaRequestMuxLPUART6Rx, .channel = BSP_LPUART6_RX_DMA_CHANNEL, .last_index = 0}; - uarts[LPUART6_INDEX].dma_rx = &uart6_dma_rx; - uarts[LPUART6_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; -#endif -#ifdef BSP_LPUART6_TX_USING_DMA - static struct dma_tx_config uart6_dma_tx = {.request = kDmaRequestMuxLPUART6Tx, .channel = BSP_LPUART6_TX_DMA_CHANNEL}; - uarts[LPUART6_INDEX].dma_tx = &uart6_dma_tx; - uarts[LPUART6_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; -#endif - -#ifdef BSP_LPUART7_RX_USING_DMA - static struct dma_rx_config uart7_dma_rx = {.request = kDmaRequestMuxLPUART7Rx, .channel = BSP_LPUART7_RX_DMA_CHANNEL, .last_index = 0}; - uarts[LPUART7_INDEX].dma_rx = &uart7_dma_rx; - uarts[LPUART7_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; -#endif -#ifdef BSP_LPUART7_TX_USING_DMA - static struct dma_tx_config uart7_dma_tx = {.request = kDmaRequestMuxLPUART7Tx, .channel = BSP_LPUART7_TX_DMA_CHANNEL}; - uarts[LPUART7_INDEX].dma_tx = &uart7_dma_tx; - uarts[LPUART7_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; -#endif - -#ifdef BSP_LPUART8_RX_USING_DMA - static struct dma_rx_config uart8_dma_rx = {.request = kDmaRequestMuxLPUART8Rx, .channel = BSP_LPUART8_RX_DMA_CHANNEL, .last_index = 0}; - uarts[LPUART8_INDEX].dma_rx = &uart8_dma_rx; - uarts[LPUART8_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_RX; -#endif -#ifdef BSP_LPUART8_TX_USING_DMA - static struct dma_tx_config uart8_dma_tx = {.request = kDmaRequestMuxLPUART8Tx, .channel = BSP_LPUART8_TX_DMA_CHANNEL}; - uarts[LPUART8_INDEX].dma_tx = &uart8_dma_tx; - uarts[LPUART8_INDEX].dma_flag |= RT_DEVICE_FLAG_DMA_TX; #endif } static void uart_isr(struct imxrt_uart *uart); #if defined(BSP_USING_LPUART1) - void LPUART1_IRQHandler(void) { rt_interrupt_enter(); - uart_isr(&uarts[LPUART1_INDEX]); - rt_interrupt_leave(); } - -#endif /* BSP_USING_LPUART1 */ +#endif #if defined(BSP_USING_LPUART2) -struct rt_serial_device serial2; - void LPUART2_IRQHandler(void) { rt_interrupt_enter(); - uart_isr(&uarts[LPUART2_INDEX]); - rt_interrupt_leave(); } - -#endif /* BSP_USING_LPUART2 */ +#endif #if defined(BSP_USING_LPUART3) -struct rt_serial_device serial3; - void LPUART3_IRQHandler(void) { rt_interrupt_enter(); - uart_isr(&uarts[LPUART3_INDEX]); - rt_interrupt_leave(); } - -#endif /* BSP_USING_LPUART3 */ +#endif #if defined(BSP_USING_LPUART4) - void LPUART4_IRQHandler(void) { rt_interrupt_enter(); - uart_isr(&uarts[LPUART4_INDEX]); - rt_interrupt_leave(); } - -#endif /* BSP_USING_LPUART4 */ +#endif #if defined(BSP_USING_LPUART5) -struct rt_serial_device serial5; - void LPUART5_IRQHandler(void) { rt_interrupt_enter(); - uart_isr(&uarts[LPUART5_INDEX]); - rt_interrupt_leave(); } - -#endif /* BSP_USING_LPUART5 */ +#endif #if defined(BSP_USING_LPUART6) -struct rt_serial_device serial6; - void LPUART6_IRQHandler(void) { rt_interrupt_enter(); - uart_isr(&uarts[LPUART6_INDEX]); - rt_interrupt_leave(); } - -#endif /* BSP_USING_LPUART6 */ +#endif #if defined(BSP_USING_LPUART7) -struct rt_serial_device serial7; - void LPUART7_IRQHandler(void) { rt_interrupt_enter(); - uart_isr(&uarts[LPUART7_INDEX]); - rt_interrupt_leave(); } - -#endif /* BSP_USING_LPUART7 */ +#endif #if defined(BSP_USING_LPUART8) -struct rt_serial_device serial8; - void LPUART8_IRQHandler(void) { rt_interrupt_enter(); - uart_isr(&uarts[LPUART8_INDEX]); + rt_interrupt_leave(); +} +#endif +#if defined(BSP_USING_LPUART10) +void LPUART10_IRQHandler(void) +{ + rt_interrupt_enter(); + uart_isr(&uarts[LPUART10_INDEX]); rt_interrupt_leave(); } +#endif -#endif /* BSP_USING_LPUART8 */ +#if defined(BSP_USING_LPUART12) +void LPUART12_IRQHandler(void) +{ + rt_interrupt_enter(); + uart_isr(&uarts[LPUART12_INDEX]); + rt_interrupt_leave(); +} +#endif static void uart_isr(struct imxrt_uart *uart) { RT_ASSERT(uart != RT_NULL); -#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) - rt_size_t total_index, recv_len; - rt_base_t level; -#endif - /* kLPUART_RxDataRegFullFlag can only cleared or set by hardware */ if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxDataRegFullFlag) { +#ifdef RT_USING_SERIAL_V2 + uint8_t ch = LPUART_ReadByte(uart->uart_base); + rt_hw_serial_control_isr(&uart->serial, RT_HW_SERIAL_CTRL_PUTC, &ch); + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_IND); +#else rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_IND); +#endif } if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxOverrunFlag) { - /* Clear overrun flag, otherwise the RX does not work. */ LPUART_ClearStatusFlags(uart->uart_base, kLPUART_RxOverrunFlag); } + if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag) + { + LPUART_DisableInterrupts(uart->uart_base, kLPUART_TxDataRegEmptyInterruptEnable); + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DONE); + } + #if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) if ((LPUART_GetStatusFlags(uart->uart_base) & kLPUART_IdleLineFlag) && (uart->dma_rx != RT_NULL)) { LPUART_ClearStatusFlags(uart->uart_base, kLPUART_IdleLineFlag); +#ifdef RT_USING_SERIAL_V2 + rt_size_t recv_len; + rt_base_t level; level = rt_hw_interrupt_disable(); + { + edma_handle_t *edma_h = &uart->dma_rx->edma; + rt_size_t total_index = EDMA_TCD_CITER(&edma_h->tcdBase[edma_h->channel], EDMA_TCD_TYPE(edma_h->base)) & 0x7FFFU; + total_index = uart->serial.config.dma_ping_bufsz - total_index; + if (total_index > uart->dma_rx->last_index) + recv_len = total_index - uart->dma_rx->last_index; + else if (total_index < uart->dma_rx->last_index) + recv_len = total_index + (uart->serial.config.dma_ping_bufsz - uart->dma_rx->last_index); + else + recv_len = 0; + uart->dma_rx->last_index = total_index; + } + rt_hw_interrupt_enable(level); - total_index = uart->serial.config.bufsz - EDMA_GetRemainingMajorLoopCount(DMA0, uart->dma_rx->channel); - if (total_index > uart->dma_rx->last_index) + if (recv_len > 0) { - recv_len = total_index - uart->dma_rx->last_index; + if (recv_len > uart->serial.config.dma_ping_bufsz) + recv_len = uart->serial.config.dma_ping_bufsz; + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); } +#else + rt_size_t total_index, recv_len; + rt_base_t level; + level = rt_hw_interrupt_disable(); + total_index = uart->serial.config.bufsz - EDMA_GetRemainingMajorLoopCount(uart->dma_rx->edma_base, uart->dma_rx->channel); + if (total_index > uart->dma_rx->last_index) + recv_len = total_index - uart->dma_rx->last_index; else - { recv_len = total_index + (uart->serial.config.bufsz - uart->dma_rx->last_index); - } - if ((recv_len > 0) && (recv_len < uart->serial.config.bufsz)) { uart->dma_rx->last_index = total_index; rt_hw_interrupt_enable(level); - rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); } else { rt_hw_interrupt_enable(level); } +#endif } #endif } @@ -446,7 +441,7 @@ static void uart_isr(struct imxrt_uart *uart) #if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) void edma_rx_callback(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds) { - rt_size_t total_index, recv_len; + rt_size_t recv_len = 0; rt_base_t level; struct imxrt_uart *uart = (struct imxrt_uart *)userData; RT_ASSERT(uart != RT_NULL); @@ -454,36 +449,46 @@ void edma_rx_callback(struct _edma_handle *handle, void *userData, bool transfer if (transferDone) { level = rt_hw_interrupt_disable(); - - if ((EDMA_GetChannelStatusFlags(DMA0, uart->dma_rx->channel) & kEDMA_DoneFlag) != 0U) + if ((EDMA_GetChannelStatusFlags(uart->dma_rx->edma_base, uart->dma_rx->channel) & kEDMA_DoneFlag) != 0U) { - /* clear full interrupt */ - EDMA_ClearChannelStatusFlags(DMA0, uart->dma_rx->channel,kEDMA_DoneFlag); - + EDMA_ClearChannelStatusFlags(uart->dma_rx->edma_base, uart->dma_rx->channel, kEDMA_DoneFlag); +#ifdef RT_USING_SERIAL_V2 + recv_len = uart->serial.config.dma_ping_bufsz - uart->dma_rx->last_index; +#else recv_len = uart->serial.config.bufsz - uart->dma_rx->last_index; +#endif uart->dma_rx->last_index = 0; } else { - /* clear half interrupt */ - EDMA_ClearChannelStatusFlags(DMA0, uart->dma_rx->channel,kEDMA_InterruptFlag); - - total_index = uart->serial.config.bufsz - EDMA_GetRemainingMajorLoopCount(DMA0, uart->dma_rx->channel); + EDMA_ClearChannelStatusFlags(uart->dma_rx->edma_base, uart->dma_rx->channel, kEDMA_InterruptFlag); +#ifdef RT_USING_SERIAL_V2 + rt_size_t total_index = EDMA_TCD_CITER(&handle->tcdBase[handle->channel], EDMA_TCD_TYPE(handle->base)) & 0x7FFFU; + total_index = uart->serial.config.dma_ping_bufsz - total_index; +#else + rt_size_t total_index = uart->serial.config.bufsz - EDMA_GetRemainingMajorLoopCount(uart->dma_rx->edma_base, uart->dma_rx->channel); +#endif if (total_index > uart->dma_rx->last_index) - { recv_len = total_index - uart->dma_rx->last_index; - } else - { +#ifdef RT_USING_SERIAL_V2 + recv_len = total_index + (uart->serial.config.dma_ping_bufsz - uart->dma_rx->last_index); +#else recv_len = total_index + (uart->serial.config.bufsz - uart->dma_rx->last_index); - } +#endif uart->dma_rx->last_index = total_index; } - rt_hw_interrupt_enable(level); if (recv_len) { +#ifdef RT_USING_SERIAL_V2 + if (recv_len > uart->serial.config.dma_ping_bufsz) + recv_len = uart->serial.config.dma_ping_bufsz; +#else + if (recv_len >= uart->serial.config.bufsz) + recv_len = uart->serial.config.bufsz - 1; +#endif rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); } } @@ -499,27 +504,54 @@ void edma_tx_callback(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DMADONE); } } - static void imxrt_dma_rx_config(struct imxrt_uart *uart) - { - RT_ASSERT(uart != RT_NULL); - - edma_transfer_config_t xferConfig; - struct rt_serial_rx_fifo *rx_fifo; - - #ifndef SOC_IMXRT1180_SERIES - DMAMUX_SetSource(DMAMUX, uart->dma_rx->channel, uart->dma_rx->request); - DMAMUX_EnableChannel(DMAMUX, uart->dma_rx->channel); - #else - /* RT1180 uses EDMA4, configure DMA request source differently */ - EDMA_SetChannelMux(DMA0, uart->dma_rx->channel, uart->dma_rx->request); - #endif - - EDMA_CreateHandle(&uart->dma_rx->edma, DMA0, uart->dma_rx->channel); - EDMA_SetCallback(&uart->dma_rx->edma, edma_rx_callback, uart); - - rx_fifo = (struct rt_serial_rx_fifo *)uart->serial.serial_rx; - - EDMA_PrepareTransfer(&xferConfig, + +#ifdef SOC_IMXRT1180_SERIES +static void imxrt_edma_mux_setup(EDMA_Type *base, rt_uint8_t channel, dma_request_source_t request) +{ + EDMA_SetChannelMux(base, channel, request); +} +#else +static void imxrt_edma_mux_setup(EDMA_Type *base, rt_uint8_t channel, dma_request_source_t request) +{ + (void)base; + DMAMUX_SetSource(DMAMUX, channel, request); + DMAMUX_EnableChannel(DMAMUX, channel); +} +#endif + +static void imxrt_dma_rx_config(struct imxrt_uart *uart) +{ + RT_ASSERT(uart != RT_NULL); + edma_transfer_config_t xferConfig; + EDMA_Type *base = uart->dma_rx->edma_base; + + imxrt_edma_mux_setup(base, uart->dma_rx->channel, uart->dma_rx->request); + + EDMA_CreateHandle(&uart->dma_rx->edma, base, uart->dma_rx->channel); + EDMA_SetCallback(&uart->dma_rx->edma, edma_rx_callback, uart); + +#ifdef RT_USING_SERIAL_V2 + rt_uint8_t *ping_buf; + rt_hw_serial_control_isr(&uart->serial, RT_HW_SERIAL_CTRL_GET_DMA_PING_BUF, (void *)&ping_buf); + + EDMA_PrepareTransfer(&xferConfig, + (void *)LPUART_GetDataRegisterAddress(uart->uart_base), + sizeof(uint8_t), + ping_buf, + sizeof(uint8_t), + sizeof(uint8_t), + uart->serial.config.dma_ping_bufsz, + kEDMA_PeripheralToMemory); + + EDMA_SubmitTransfer(&uart->dma_rx->edma, &xferConfig); + EDMA_EnableChannelInterrupts(base, uart->dma_rx->channel, kEDMA_MajorInterruptEnable | kEDMA_HalfInterruptEnable); + EDMA_EnableAutoStopRequest(base, uart->dma_rx->channel, false); + EDMA_TCD_DLAST_SGA(&uart->dma_rx->edma.tcdBase[uart->dma_rx->edma.channel], EDMA_TCD_TYPE(uart->dma_rx->edma.base)) = -(int32_t)uart->serial.config.dma_ping_bufsz; +#else + struct rt_serial_rx_fifo *rx_fifo; + rx_fifo = (struct rt_serial_rx_fifo *)uart->serial.serial_rx; + + EDMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(uart->uart_base), sizeof(uint8_t), rx_fifo->buffer, @@ -528,123 +560,103 @@ void edma_tx_callback(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t uart->serial.config.bufsz, kEDMA_PeripheralToMemory); - EDMA_SubmitTransfer(&uart->dma_rx->edma, &xferConfig); - EDMA_EnableChannelInterrupts(DMA0, uart->dma_rx->channel, kEDMA_MajorInterruptEnable | kEDMA_HalfInterruptEnable); - EDMA_EnableAutoStopRequest(DMA0, uart->dma_rx->channel, false); - /* complement to adjust final destination address */ - uart->dma_rx->edma.base->TCD[uart->dma_rx->channel].DLAST_SGA = -(uart->serial.config.bufsz); - EDMA_StartTransfer(&uart->dma_rx->edma); - LPUART_EnableRxDMA(uart->uart_base, true); - - LPUART_EnableInterrupts(uart->uart_base, kLPUART_IdleLineInterruptEnable); - NVIC_SetPriority(uart->irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0)); - EnableIRQ(uart->irqn); - - LOG_D("%s dma rx config done\n", uart->name); - } - - static void imxrt_dma_tx_config(struct imxrt_uart *uart) - { - RT_ASSERT(uart != RT_NULL); - - #ifndef SOC_IMXRT1180_SERIES - DMAMUX_SetSource(DMAMUX, uart->dma_tx->channel, uart->dma_tx->request); - DMAMUX_EnableChannel(DMAMUX, uart->dma_tx->channel); - #else - /* RT1180 uses EDMA4, configure DMA request source differently */ - EDMA_SetChannelMux(DMA0, uart->dma_tx->channel, uart->dma_tx->request); - #endif - - EDMA_CreateHandle(&uart->dma_tx->edma, DMA0, uart->dma_tx->channel); - - LPUART_TransferCreateHandleEDMA(uart->uart_base, - &uart->dma_tx->uart_edma, - edma_tx_callback, - uart, - &uart->dma_tx->edma, - RT_NULL); - - LOG_D("%s dma tx config done\n", uart->name); - } -#endif - uint32_t GetUartSrcFreq(LPUART_Type *uart_base) - { - uint32_t freq; - #if defined(SOC_IMXRT1170_SERIES) - uint32_t base = (uint32_t) uart_base; - switch (base) - { - case LPUART1_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1); - break; - case LPUART12_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart12); - break; - default: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart2); - break; - } - #elif defined(SOC_IMXRT1180_SERIES) - /* RT1180 uses different clock root architecture */ - uint32_t base = (uint32_t) uart_base; - switch (base) - { - case LPUART1_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102); - break; - case LPUART2_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102); - break; - case LPUART3_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0304); - break; - case LPUART4_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0304); - break; - case LPUART5_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0506); - break; - case LPUART6_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0506); - break; - case LPUART7_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0708); - break; - case LPUART8_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0708); - break; - case LPUART9_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0910); - break; - case LPUART10_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0910); - break; - case LPUART11_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1112); - break; - case LPUART12_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1112); - break; - - default: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102); - break; - } - #else - /* To make it simple, we assume default PLL and divider settings, and the only variable - from application is use PLL3 source or OSC source */ - if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ - { - freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); - } - else - { - freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); - } - #endif - return freq; - - } + EDMA_SubmitTransfer(&uart->dma_rx->edma, &xferConfig); + EDMA_EnableChannelInterrupts(base, uart->dma_rx->channel, kEDMA_MajorInterruptEnable | kEDMA_HalfInterruptEnable); + EDMA_EnableAutoStopRequest(base, uart->dma_rx->channel, false); + EDMA_TCD_DLAST_SGA(&uart->dma_rx->edma.tcdBase[uart->dma_rx->channel], EDMA_TCD_TYPE(uart->dma_rx->edma.base)) = -(int32_t)uart->serial.config.bufsz; +#endif + EDMA_StartTransfer(&uart->dma_rx->edma); + LPUART_EnableRxDMA(uart->uart_base, true); + + LPUART_EnableInterrupts(uart->uart_base, kLPUART_IdleLineInterruptEnable); + NVIC_SetPriority(uart->irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0)); + EnableIRQ(uart->irqn); + + LOG_D("%s dma rx config done\n", uart->name); +} + +static void imxrt_dma_tx_config(struct imxrt_uart *uart) +{ + RT_ASSERT(uart != RT_NULL); + EDMA_Type *base = uart->dma_tx->edma_base; + + imxrt_edma_mux_setup(base, uart->dma_tx->channel, uart->dma_tx->request); + + EDMA_CreateHandle(&uart->dma_tx->edma, base, uart->dma_tx->channel); + + LPUART_TransferCreateHandleEDMA(uart->uart_base, + &uart->dma_tx->uart_edma, + edma_tx_callback, + uart, + &uart->dma_tx->edma, + RT_NULL); + + LOG_D("%s dma tx config done\n", uart->name); +} +#endif + +uint32_t GetUartSrcFreq(LPUART_Type *uart_base) +{ + uint32_t freq; +#if defined(SOC_IMXRT1170_SERIES) + uint32_t base = (uint32_t) uart_base; + switch (base) + { + case LPUART1_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1); + break; + case LPUART12_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart12); + break; + default: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart2); + break; + } +#elif defined(SOC_IMXRT1180_SERIES) + uint32_t base = (uint32_t) uart_base; + switch (base) + { + case LPUART1_BASE: + case LPUART2_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102); + break; + case LPUART3_BASE: + case LPUART4_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0304); + break; + case LPUART5_BASE: + case LPUART6_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0506); + break; + case LPUART7_BASE: + case LPUART8_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0708); + break; + case LPUART9_BASE: + case LPUART10_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0910); + break; + case LPUART11_BASE: + case LPUART12_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1112); + break; + default: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102); + break; + } +#else + if (CLOCK_GetMux(kCLOCK_UartMux) == 0) + { + freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } + else + { + freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } +#endif + return freq; +} + static rt_err_t imxrt_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { struct imxrt_uart *uart; @@ -663,7 +675,6 @@ static rt_err_t imxrt_configure(struct rt_serial_device *serial, struct serial_c case DATA_BITS_7: config.dataBitsCount = kLPUART_SevenDataBits; break; - default: config.dataBitsCount = kLPUART_EightDataBits; break; @@ -707,10 +718,6 @@ static rt_err_t imxrt_control(struct rt_serial_device *serial, int cmd, void *ar RT_ASSERT(serial != RT_NULL); uart = rt_container_of(serial, struct imxrt_uart, serial); -#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) - rt_ubase_t ctrl_arg = (rt_ubase_t)arg; -#endif - switch (cmd) { case RT_DEVICE_CTRL_CLR_INT: @@ -723,18 +730,47 @@ static rt_err_t imxrt_control(struct rt_serial_device *serial, int cmd, void *ar EnableIRQ(uart->irqn); break; -#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) case RT_DEVICE_CTRL_CONFIG: + { + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; +#if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) if (RT_DEVICE_FLAG_DMA_RX == ctrl_arg) { imxrt_dma_rx_config(uart); + break; } - else if (RT_DEVICE_FLAG_DMA_TX == ctrl_arg) + if (RT_DEVICE_FLAG_DMA_TX == ctrl_arg) { imxrt_dma_tx_config(uart); + break; } +#endif + +#ifdef RT_USING_SERIAL_V2 + if (RT_DEVICE_FLAG_RX_BLOCKING == ctrl_arg || RT_DEVICE_FLAG_RX_NON_BLOCKING == ctrl_arg) + { + LPUART_EnableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable); + NVIC_SetPriority(uart->irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0)); + EnableIRQ(uart->irqn); + break; + } + if (RT_DEVICE_FLAG_TX_BLOCKING == ctrl_arg || RT_DEVICE_FLAG_TX_NON_BLOCKING == ctrl_arg) + { + LPUART_EnableInterrupts(uart->uart_base, kLPUART_TxDataRegEmptyInterruptEnable); + NVIC_SetPriority(uart->irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0)); + EnableIRQ(uart->irqn); + break; + } +#endif break; + } + +#ifdef RT_USING_SERIAL_V2 + case RT_DEVICE_CHECK_OPTMODE: + if (uart->dma_flag & RT_DEVICE_FLAG_DMA_TX) + return RT_SERIAL_TX_BLOCKING_NO_BUFFER; + return RT_SERIAL_TX_BLOCKING_BUFFER; #endif } @@ -772,7 +808,45 @@ static int imxrt_getc(struct rt_serial_device *serial) } #if defined(RT_SERIAL_USING_DMA) && defined(BSP_USING_DMA) -rt_size_t dma_tx_xfer(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) + +#ifdef RT_USING_SERIAL_V2 +static rt_ssize_t imxrt_transmit(struct rt_serial_device *serial, + rt_uint8_t *buf, rt_size_t size, rt_uint32_t tx_flag) +{ + struct imxrt_uart *uart; + + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct imxrt_uart, serial); + + if (uart->dma_flag & RT_DEVICE_FLAG_DMA_TX) + { + lpuart_transfer_t xfer; + RT_ASSERT(buf != RT_NULL); + xfer.data = buf; + xfer.dataSize = size; + if (LPUART_SendEDMA(uart->uart_base, &uart->dma_tx->uart_edma, &xfer) == kStatus_Success) + return (rt_ssize_t)size; + return -RT_EIO; + } + + if (size == 0) + { + LPUART_EnableInterrupts(uart->uart_base, kLPUART_TxDataRegEmptyInterruptEnable); + return 0; + } + + { + rt_uint8_t *ptr = buf; + while (size--) + { + LPUART_WriteByte(uart->uart_base, *ptr++); + while (!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag)); + } + return (rt_ssize_t)(ptr - buf); + } +} +#else +static rt_ssize_t dma_tx_xfer(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) { struct imxrt_uart *uart; lpuart_transfer_t xfer; @@ -788,9 +862,7 @@ rt_size_t dma_tx_xfer(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_ xfer.data = buf; xfer.dataSize = size; if (LPUART_SendEDMA(uart->uart_base, &uart->dma_tx->uart_edma, &xfer) == kStatus_Success) - { xfer_size = size; - } } } @@ -798,8 +870,17 @@ rt_size_t dma_tx_xfer(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_ } #endif +#endif + static const struct rt_uart_ops imxrt_uart_ops = { +#ifdef RT_USING_SERIAL_V2 + imxrt_configure, + imxrt_control, + imxrt_putc, + imxrt_getc, + imxrt_transmit, +#else imxrt_configure, imxrt_control, imxrt_putc, @@ -809,16 +890,21 @@ static const struct rt_uart_ops imxrt_uart_ops = #else RT_NULL #endif +#endif }; int rt_hw_uart_init(void) { int i; - rt_uint32_t flag; rt_err_t ret = RT_EOK; - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; +#ifdef RT_USING_SERIAL_V2 + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; +#else + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_uint32_t flag; flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX; +#endif uart_get_dma_config(); @@ -827,7 +913,13 @@ int rt_hw_uart_init(void) uarts[i].serial.ops = &imxrt_uart_ops; uarts[i].serial.config = config; - ret = rt_hw_serial_register(&uarts[i].serial, uarts[i].name, flag | uarts[i].dma_flag, NULL); +#ifdef RT_USING_SERIAL_V2 + ret = rt_hw_serial_register(&uarts[i].serial, uarts[i].name, + RT_DEVICE_FLAG_RDWR, NULL); +#else + ret = rt_hw_serial_register(&uarts[i].serial, uarts[i].name, + flag | uarts[i].dma_flag, NULL); +#endif } return ret; diff --git a/components/drivers/include/drivers/dev_serial_v2.h b/components/drivers/include/drivers/dev_serial_v2.h index b987bc45434..765dea3a30b 100644 --- a/components/drivers/include/drivers/dev_serial_v2.h +++ b/components/drivers/include/drivers/dev_serial_v2.h @@ -216,8 +216,12 @@ #define RT_SERIAL_ERR_FRAMING 0x02 #define RT_SERIAL_ERR_PARITY 0x03 +#ifndef RT_SERIAL_RX_MINBUFSZ #define RT_SERIAL_RX_MINBUFSZ 64 +#endif +#ifndef RT_SERIAL_TX_MINBUFSZ #define RT_SERIAL_TX_MINBUFSZ 64 +#endif #define RT_SERIAL_TX_BLOCKING_BUFFER 1 #define RT_SERIAL_TX_BLOCKING_NO_BUFFER 0 diff --git a/components/drivers/serial/Kconfig b/components/drivers/serial/Kconfig index 95b375c3e6a..411b6e9e04c 100644 --- a/components/drivers/serial/Kconfig +++ b/components/drivers/serial/Kconfig @@ -7,6 +7,7 @@ menuconfig RT_USING_SERIAL if RT_USING_SERIAL choice RT_USING_SERIAL_VERSION prompt "Choice Serial version" + default RT_USING_SERIAL_V2 if SOC_MIMXRT1189CVM8C_CM33 default RT_USING_SERIAL_V1 config RT_USING_SERIAL_V1 bool "RT_USING_SERIAL_V1" diff --git a/components/drivers/serial/dev_serial.c b/components/drivers/serial/dev_serial.c index 45bf97c3289..991fae6e878 100644 --- a/components/drivers/serial/dev_serial.c +++ b/components/drivers/serial/dev_serial.c @@ -33,6 +33,7 @@ #include #include #include +#ifndef RT_USING_SERIAL_V2 #define DBG_TAG "UART" #define DBG_LVL DBG_INFO @@ -1495,6 +1496,7 @@ void rt_hw_serial_isr(struct rt_serial_device *serial, int event) struct rt_serial_tx_fifo* tx_fifo; tx_fifo = (struct rt_serial_tx_fifo*)serial->serial_tx; + if (tx_fifo == RT_NULL) break; rt_completion_done(&(tx_fifo->completion)); break; } @@ -1507,6 +1509,7 @@ void rt_hw_serial_isr(struct rt_serial_device *serial, int event) struct rt_serial_tx_dma *tx_dma; tx_dma = (struct rt_serial_tx_dma*) serial->serial_tx; + if (tx_dma == RT_NULL) break; rt_data_queue_pop(&(tx_dma->data_queue), &last_data_ptr, &data_size, 0); if (rt_data_queue_peek(&(tx_dma->data_queue), &data_ptr, &data_size) == RT_EOK) @@ -1567,3 +1570,4 @@ void rt_hw_serial_isr(struct rt_serial_device *serial, int event) #endif /* RT_SERIAL_USING_DMA */ } } +#endif /* RT_USING_SERIAL_V2 */ \ No newline at end of file