From 247a1bcec607ed77a7846fb12dcd6a9c98d730b8 Mon Sep 17 00:00:00 2001 From: rbb666 Date: Thu, 18 Jun 2026 13:36:04 +0800 Subject: [PATCH 1/3] [bsp/rockchip]Add CI compilation checks for RK3500 BSP. --- .github/ALL_BSP_COMPILE.json | 8 ++++++++ .github/workflows/bsp_buildings.yml | 13 ++++++++++++- .../rk3500/.ci/attachconfig/ci.attachconfig.yml | 14 ++++++++++++++ 3 files changed, 34 insertions(+), 1 deletion(-) create mode 100644 bsp/rockchip/rk3500/.ci/attachconfig/ci.attachconfig.yml diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index ff70275c9e7..9d97520f6c5 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -398,6 +398,14 @@ "zynqmp-a53-dfzu2eg" ] }, + { + "RTT_BSP": "aarch64-bsp-smart", + "RTT_TOOL_CHAIN": "sourcery-aarch64", + "RTT_SMART_TOOL_CHAIN": "aarch64-linux-musleabi", + "SUB_RTT_BSP": [ + "rockchip/rk3500" + ] + }, { "RTT_BSP": "riscv-none", "RTT_TOOL_CHAIN": "sourcery-riscv-none-embed", diff --git a/.github/workflows/bsp_buildings.yml b/.github/workflows/bsp_buildings.yml index d3b4968c1ee..312ee717451 100644 --- a/.github/workflows/bsp_buildings.yml +++ b/.github/workflows/bsp_buildings.yml @@ -144,7 +144,7 @@ jobs: echo "RTT_EXEC_PATH=/opt/LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64/bin" >> $GITHUB_ENV - name: Install AArch64 ToolChains - if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-aarch64' && success() }} + if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-aarch64' && matrix.legs.RTT_SMART_TOOL_CHAIN != 'aarch64-linux-musleabi' && success() }} shell: bash run: | wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.6/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf.tar.xz @@ -153,6 +153,17 @@ jobs: echo "RTT_EXEC_PATH=/opt/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf/bin" >> $GITHUB_ENV sudo apt-get -qq install device-tree-compiler + - name: Install AArch64 RT-Smart ToolChains + if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-aarch64' && matrix.legs.RTT_SMART_TOOL_CHAIN == 'aarch64-linux-musleabi' && success() }} + shell: bash + run: | + wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/aarch64-linux-musleabi_for_x86_64-pc-linux-gnu_stable.tar.bz2 + sudo tar xjf aarch64-linux-musleabi_for_x86_64-pc-linux-gnu_stable.tar.bz2 -C /opt + /opt/aarch64-linux-musleabi_for_x86_64-pc-linux-gnu/bin/aarch64-linux-musleabi-gcc --version + echo "RTT_EXEC_PATH=/opt/aarch64-linux-musleabi_for_x86_64-pc-linux-gnu/bin" >> $GITHUB_ENV + echo "RTT_CC_PREFIX=aarch64-linux-musleabi-" >> $GITHUB_ENV + sudo apt-get -qq install device-tree-compiler + - name: Install Mips ToolChains if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-mips' && success() }} shell: bash diff --git a/bsp/rockchip/rk3500/.ci/attachconfig/ci.attachconfig.yml b/bsp/rockchip/rk3500/.ci/attachconfig/ci.attachconfig.yml new file mode 100644 index 00000000000..27c707f3db8 --- /dev/null +++ b/bsp/rockchip/rk3500/.ci/attachconfig/ci.attachconfig.yml @@ -0,0 +1,14 @@ +scons.args: &scons + scons_arg: + - '--strict' + +devices.spi: + <<: *scons + kconfig: + - CONFIG_RT_USING_SPI=y + - CONFIG_RT_USING_QSPI=y + - CONFIG_RT_USING_DMA=y + - CONFIG_RT_USING_PIN=y + - CONFIG_RT_USING_PINCTRL=y + - CONFIG_RT_SPI_ROCKCHIP=y + - CONFIG_RT_SPI_ROCKCHIP_SFC=y From 78f23f72e3dc291156f94d7ff09a444093f4caaf Mon Sep 17 00:00:00 2001 From: rbb666 Date: Thu, 18 Jun 2026 16:44:37 +0800 Subject: [PATCH 2/3] Adding to the macro definition that was mistakenly deleted in #11477 --- components/drivers/dma/dma-pl330.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/components/drivers/dma/dma-pl330.c b/components/drivers/dma/dma-pl330.c index b0f4bbaa100..8fa207a94d9 100644 --- a/components/drivers/dma/dma-pl330.c +++ b/components/drivers/dma/dma-pl330.c @@ -212,6 +212,27 @@ /** @brief Microcode instruction: write memory barrier */ #define PL330_CMD_DMAWMB 0x13 +/** @brief Microcode instruction sizes */ +#define PL330_SIZE_DMAADDH 3 +#define PL330_SIZE_DMAEND 1 +#define PL330_SIZE_DMAFLUSHP 2 +#define PL330_SIZE_DMALD 1 +#define PL330_SIZE_DMALDP 2 +#define PL330_SIZE_DMALP 2 +#define PL330_SIZE_DMALPEND 2 +#define PL330_SIZE_DMAKILL 1 +#define PL330_SIZE_DMAMOV 6 +#define PL330_SIZE_DMANOP 1 +#define PL330_SIZE_DMARMB 1 +#define PL330_SIZE_DMASEV 2 +#define PL330_SIZE_DMAST 1 +#define PL330_SIZE_DMASTP 2 +#define PL330_SIZE_DMASTZ 1 +#define PL330_SIZE_DMAWFE 2 +#define PL330_SIZE_DMAWFP 2 +#define PL330_SIZE_DMAWMB 1 +#define PL330_SIZE_DMAGO 6 + /** @brief DMAMOV to Source Address Register */ #define PL330_DIR_SAR 0 /** @brief DMAMOV to Channel Control Register */ From db0419de65c8365819546e6cf6cd2095269fe1f6 Mon Sep 17 00:00:00 2001 From: rbb666 Date: Thu, 18 Jun 2026 17:14:49 +0800 Subject: [PATCH 3/3] [bsp/rockchip] Fix RK3528 PLL parent names initialization --- bsp/rockchip/dm/clk/clk-rk3528.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/bsp/rockchip/dm/clk/clk-rk3528.c b/bsp/rockchip/dm/clk/clk-rk3528.c index c77e74d3602..8dd0e8cd3aa 100755 --- a/bsp/rockchip/dm/clk/clk-rk3528.c +++ b/bsp/rockchip/dm/clk/clk-rk3528.c @@ -200,19 +200,19 @@ PNAMES(clk_32k_p) = { "xin_osc0_div", "clk_pvtm_32k" }; #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) static struct rockchip_pll_clk_cell rk3528_pll_apll = - PLL_RAW(pll_type_rk3328, PLL_APLL, "apll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(0), RK3528_MODE_CON, + PLL_RAW(pll_type_rk3328, PLL_APLL, "apll", &mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(0), RK3528_MODE_CON, 0, 0, RK3528_GRF_SOC_STATUS0, 0, rk3528_pll_rates); static struct rockchip_pll_clk_cell rk3528_pll_cpll = - PLL_RAW(pll_type_rk3328, PLL_CPLL, "cpll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(8), RK3528_MODE_CON, + PLL_RAW(pll_type_rk3328, PLL_CPLL, "cpll", &mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(8), RK3528_MODE_CON, 2, 0, RK3528_GRF_SOC_STATUS0, 0, rk3528_pll_rates); static struct rockchip_pll_clk_cell rk3528_pll_gpll = - PLL_RAW(pll_type_rk3328, PLL_GPLL, "gpll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(24), RK3528_MODE_CON, + PLL_RAW(pll_type_rk3328, PLL_GPLL, "gpll", &mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(24), RK3528_MODE_CON, 4, 0, RK3528_GRF_SOC_STATUS0, 0, rk3528_pll_rates); static struct rockchip_pll_clk_cell rk3528_pll_ppll = - PLL_RAW(pll_type_rk3328, PLL_PPLL, "ppll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PCIE_PLL_CON(32), RK3528_MODE_CON, + PLL_RAW(pll_type_rk3328, PLL_PPLL, "ppll", &mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PCIE_PLL_CON(32), RK3528_MODE_CON, 6, 0, RK3528_GRF_SOC_STATUS0, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates); static struct rockchip_pll_clk_cell rk3528_pll_dpll = - PLL_RAW(pll_type_rk3328, PLL_DPLL, "dpll", mux_pll_p, 1, RT_CLK_F_IGNORE_UNUSED, RK3528_DDRPHY_PLL_CON(16), RK3528_DDRPHY_MODE_CON, + PLL_RAW(pll_type_rk3328, PLL_DPLL, "dpll", &mux_pll_p, 1, RT_CLK_F_IGNORE_UNUSED, RK3528_DDRPHY_PLL_CON(16), RK3528_DDRPHY_MODE_CON, 0, 0, RK3528_GRF_SOC_STATUS0, 0, rk3528_pll_rates); static struct rockchip_clk_cell rk3528_uart0_fracmux =