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Description
Describe the Issue
If I call abc with no extra arguments in a Yosys script, then the setup slack is worsened (as shown in report_checks)
Environment
I encountered this using Yosys version Yosys 0.58+74 (git sha1 272aa9cde, clang++ 18.1.8 -fPIC -O3)
I don't know what ABC version is bundled with that version of Yosys.
Reproduction Steps
- Create
synth.tcl(notice the extraabcbeforedfflibmap):
yosys -import
read_verilog -sv OpenROAD-flow-scripts/flow/designs/src/riscv32i/*.v
hierarchy -check -top riscv
synth -flatten
abc
dfflibmap -liberty $env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
abc -liberty $env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
write_verilog -noexpr riscv32i.v
- Run the following commands:
git clone https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts.git
yosys synth.tcl
(Cloning OpenROAD-flow-scripts is only to get the riscv32i design)
- Then, run the following commands (enter OpenROAD first):
openroad
read_lib $env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
read_lef $env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef
read_lef $env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef
read_verilog riscv32i.v
link_design riscv
read_sdc OpenROAD-flow-scripts/flow/designs/sky130hd/riscv32i/constraint.sdc
report_checks
- Observe that the setup slack is about -8
- Remove the lone
abccall fromsynth.tcl - Repeat steps 2 and 3 (no need to clone ORFS again)
- Observe that the setup slack is about -4. This is higher than the slack from step 4.
Expected Behavior
Unless I'm mistaken, abc shouldn't affect timing results.
Actual Behavior
The screenshot to the left is when the extra abc is added. The screenshot to the right is without the extra abc. The setup slack worsens when the additional abc is called, and improves when abc is not called.

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