From f636599796199fc569a56611ca36a584606902a4 Mon Sep 17 00:00:00 2001 From: joeywang4 Date: Mon, 1 Jun 2020 20:30:18 +0800 Subject: [PATCH] Fix verilog file parsing error When the parser encounters a gate name, it will not skip this name but throws an error of `expected opening parenthesis`. For example, the following verilog file will cause this error: module top(x1, x2, z); input x1, x2; output z; and aaa(z, x1, x2); endmodule I fixed this bug by simply calling the `Ver_ParseGetName` function to skip the gate name. --- src/base/ver/verCore.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/base/ver/verCore.c b/src/base/ver/verCore.c index 183b1dedfd..2031f5ac03 100644 --- a/src/base/ver/verCore.c +++ b/src/base/ver/verCore.c @@ -1340,6 +1340,7 @@ int Ver_ParseGateStandard( Ver_Man_t * pMan, Abc_Ntk_t * pNtk, Ver_GateType_t Ga Ver_StreamMove( p ); // this is gate name - throw it away + Ver_ParseGetName( pMan ); if ( Ver_StreamPopChar(p) != '(' ) { sprintf( pMan->sError, "Cannot parse a standard gate (expected opening parenthesis)." ); @@ -1436,6 +1437,7 @@ int Ver_ParseFlopStandard( Ver_Man_t * pMan, Abc_Ntk_t * pNtk ) return 0; // this is gate name - throw it away + Ver_ParseGetName( pMan ); if ( Ver_StreamPopChar(p) != '(' ) { sprintf( pMan->sError, "Cannot parse a standard gate (expected opening parenthesis)." ); @@ -1573,6 +1575,7 @@ int Ver_ParseGate( Ver_Man_t * pMan, Abc_Ntk_t * pNtk, Mio_Gate_t * pGate ) if ( pWord == NULL ) return 0; // this is gate name - throw it away + Ver_ParseGetName( pMan ); if ( Ver_StreamPopChar(p) != '(' ) { sprintf( pMan->sError, "Cannot parse gate %s (expected opening parenthesis).", Mio_GateReadName(pGate) );