diff --git a/_sources/index.rst.txt b/_sources/index.rst.txt index 5e98c40d..64c0cb17 100644 --- a/_sources/index.rst.txt +++ b/_sources/index.rst.txt @@ -1,9 +1,9 @@ -.. CHIPSEC 2.0.3 documentation file, created by +.. CHIPSEC 2.0.4 documentation file, created by sphinx-quickstart on Wed Mar 25 13:24:44 2015. You can adapt this file completely to your liking, but it should at least contain the root `toctree` directive. -CHIPSEC 2.0.3 +CHIPSEC 2.0.4 ============= CHIPSEC is a framework for analyzing platform level security of diff --git a/_sources/modules/chipsec.cfg.parsers.ip.generic.rst.txt b/_sources/modules/chipsec.cfg.parsers.ip.generic.rst.txt new file mode 100644 index 00000000..4fc6ae63 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.ip.generic.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.ip.generic module +===================================== + +.. automodule:: chipsec.cfg.parsers.ip.generic + + + diff --git a/_sources/modules/chipsec.cfg.parsers.ip.io.rst.txt b/_sources/modules/chipsec.cfg.parsers.ip.io.rst.txt new file mode 100644 index 00000000..141ad2c0 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.ip.io.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.ip.io module +================================ + +.. automodule:: chipsec.cfg.parsers.ip.io + + + diff --git a/_sources/modules/chipsec.cfg.parsers.ip.iobar.rst.txt b/_sources/modules/chipsec.cfg.parsers.ip.iobar.rst.txt new file mode 100644 index 00000000..fe2e8856 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.ip.iobar.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.ip.iobar module +=================================== + +.. automodule:: chipsec.cfg.parsers.ip.iobar + + + diff --git a/_sources/modules/chipsec.cfg.parsers.ip.memory.rst.txt b/_sources/modules/chipsec.cfg.parsers.ip.memory.rst.txt new file mode 100644 index 00000000..93bb7f84 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.ip.memory.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.ip.memory module +==================================== + +.. automodule:: chipsec.cfg.parsers.ip.memory + + + diff --git a/_sources/modules/chipsec.cfg.parsers.ip.mm_msgbus.rst.txt b/_sources/modules/chipsec.cfg.parsers.ip.mm_msgbus.rst.txt new file mode 100644 index 00000000..bf76e8e0 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.ip.mm_msgbus.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.ip.mm\_msgbus module +======================================== + +.. automodule:: chipsec.cfg.parsers.ip.mm_msgbus + + + diff --git a/_sources/modules/chipsec.cfg.parsers.ip.mmio_bar.rst.txt b/_sources/modules/chipsec.cfg.parsers.ip.mmio_bar.rst.txt new file mode 100644 index 00000000..b388d5c4 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.ip.mmio_bar.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.ip.mmio\_bar module +======================================= + +.. automodule:: chipsec.cfg.parsers.ip.mmio_bar + + + diff --git a/_sources/modules/chipsec.cfg.parsers.ip.msgbus.rst.txt b/_sources/modules/chipsec.cfg.parsers.ip.msgbus.rst.txt new file mode 100644 index 00000000..757d5cf9 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.ip.msgbus.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.ip.msgbus module +==================================== + +.. automodule:: chipsec.cfg.parsers.ip.msgbus + + + diff --git a/_sources/modules/chipsec.cfg.parsers.ip.msr.rst.txt b/_sources/modules/chipsec.cfg.parsers.ip.msr.rst.txt new file mode 100644 index 00000000..269509f8 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.ip.msr.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.ip.msr module +================================= + +.. automodule:: chipsec.cfg.parsers.ip.msr + + + diff --git a/_sources/modules/chipsec.cfg.parsers.ip.pci_device.rst.txt b/_sources/modules/chipsec.cfg.parsers.ip.pci_device.rst.txt new file mode 100644 index 00000000..c260bb07 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.ip.pci_device.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.ip.pci\_device module +========================================= + +.. automodule:: chipsec.cfg.parsers.ip.pci_device + + + diff --git a/_sources/modules/chipsec.cfg.parsers.ip.platform.rst.txt b/_sources/modules/chipsec.cfg.parsers.ip.platform.rst.txt new file mode 100644 index 00000000..bb68d411 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.ip.platform.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.ip.platform module +====================================== + +.. automodule:: chipsec.cfg.parsers.ip.platform + + + diff --git a/_sources/modules/chipsec.cfg.parsers.ip.rst.txt b/_sources/modules/chipsec.cfg.parsers.ip.rst.txt new file mode 100644 index 00000000..ad78cd66 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.ip.rst.txt @@ -0,0 +1,21 @@ +chipsec.cfg.parsers.ip package +============================== + +.. toctree:: + :maxdepth: 10 + + chipsec.cfg.parsers.ip.generic + chipsec.cfg.parsers.ip.io + chipsec.cfg.parsers.ip.iobar + chipsec.cfg.parsers.ip.memory + chipsec.cfg.parsers.ip.mm_msgbus + chipsec.cfg.parsers.ip.mmio_bar + chipsec.cfg.parsers.ip.msgbus + chipsec.cfg.parsers.ip.msr + chipsec.cfg.parsers.ip.pci_device + chipsec.cfg.parsers.ip.platform + +.. automodule:: chipsec.cfg.parsers.ip + + + diff --git a/_sources/modules/chipsec.cfg.parsers.registers.controls.rst.txt b/_sources/modules/chipsec.cfg.parsers.registers.controls.rst.txt new file mode 100644 index 00000000..1ae4f4e0 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.registers.controls.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.registers.controls module +============================================= + +.. automodule:: chipsec.cfg.parsers.registers.controls + + + diff --git a/_sources/modules/chipsec.cfg.parsers.registers.io.rst.txt b/_sources/modules/chipsec.cfg.parsers.registers.io.rst.txt new file mode 100644 index 00000000..4b0bb602 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.registers.io.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.registers.io module +======================================= + +.. automodule:: chipsec.cfg.parsers.registers.io + + + diff --git a/_sources/modules/chipsec.cfg.parsers.registers.iobar.rst.txt b/_sources/modules/chipsec.cfg.parsers.registers.iobar.rst.txt new file mode 100644 index 00000000..39ce86bb --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.registers.iobar.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.registers.iobar module +========================================== + +.. automodule:: chipsec.cfg.parsers.registers.iobar + + + diff --git a/_sources/modules/chipsec.cfg.parsers.registers.locks.rst.txt b/_sources/modules/chipsec.cfg.parsers.registers.locks.rst.txt new file mode 100644 index 00000000..12785dce --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.registers.locks.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.registers.locks module +========================================== + +.. automodule:: chipsec.cfg.parsers.registers.locks + + + diff --git a/_sources/modules/chipsec.cfg.parsers.registers.memory.rst.txt b/_sources/modules/chipsec.cfg.parsers.registers.memory.rst.txt new file mode 100644 index 00000000..c9a8860c --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.registers.memory.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.registers.memory module +=========================================== + +.. automodule:: chipsec.cfg.parsers.registers.memory + + + diff --git a/_sources/modules/chipsec.cfg.parsers.registers.mm_msgbus.rst.txt b/_sources/modules/chipsec.cfg.parsers.registers.mm_msgbus.rst.txt new file mode 100644 index 00000000..9c62939b --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.registers.mm_msgbus.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.registers.mm\_msgbus module +=============================================== + +.. automodule:: chipsec.cfg.parsers.registers.mm_msgbus + + + diff --git a/_sources/modules/chipsec.cfg.parsers.registers.mmcfg.rst.txt b/_sources/modules/chipsec.cfg.parsers.registers.mmcfg.rst.txt new file mode 100644 index 00000000..8aa30e36 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.registers.mmcfg.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.registers.mmcfg module +========================================== + +.. automodule:: chipsec.cfg.parsers.registers.mmcfg + + + diff --git a/_sources/modules/chipsec.cfg.parsers.registers.mmio.rst.txt b/_sources/modules/chipsec.cfg.parsers.registers.mmio.rst.txt new file mode 100644 index 00000000..e8bdcea2 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.registers.mmio.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.registers.mmio module +========================================= + +.. automodule:: chipsec.cfg.parsers.registers.mmio + + + diff --git a/_sources/modules/chipsec.cfg.parsers.registers.msgbus.rst.txt b/_sources/modules/chipsec.cfg.parsers.registers.msgbus.rst.txt new file mode 100644 index 00000000..47bf84ad --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.registers.msgbus.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.registers.msgbus module +=========================================== + +.. automodule:: chipsec.cfg.parsers.registers.msgbus + + + diff --git a/_sources/modules/chipsec.cfg.parsers.registers.msr.rst.txt b/_sources/modules/chipsec.cfg.parsers.registers.msr.rst.txt new file mode 100644 index 00000000..8e3537ab --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.registers.msr.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.registers.msr module +======================================== + +.. automodule:: chipsec.cfg.parsers.registers.msr + + + diff --git a/_sources/modules/chipsec.cfg.parsers.registers.pci.rst.txt b/_sources/modules/chipsec.cfg.parsers.registers.pci.rst.txt new file mode 100644 index 00000000..db2068a7 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.registers.pci.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.registers.pci module +======================================== + +.. automodule:: chipsec.cfg.parsers.registers.pci + + + diff --git a/_sources/modules/chipsec.cfg.parsers.registers.rst.txt b/_sources/modules/chipsec.cfg.parsers.registers.rst.txt new file mode 100644 index 00000000..fae24336 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.registers.rst.txt @@ -0,0 +1,23 @@ +chipsec.cfg.parsers.registers package +===================================== + +.. toctree:: + :maxdepth: 10 + + chipsec.cfg.parsers.registers.controls + chipsec.cfg.parsers.registers.io + chipsec.cfg.parsers.registers.iobar + chipsec.cfg.parsers.registers.locks + chipsec.cfg.parsers.registers.memory + chipsec.cfg.parsers.registers.mm_msgbus + chipsec.cfg.parsers.registers.mmcfg + chipsec.cfg.parsers.registers.mmio + chipsec.cfg.parsers.registers.msgbus + chipsec.cfg.parsers.registers.msr + chipsec.cfg.parsers.registers.pci + chipsec.cfg.parsers.registers.simple + +.. automodule:: chipsec.cfg.parsers.registers + + + diff --git a/_sources/modules/chipsec.cfg.parsers.registers.simple.rst.txt b/_sources/modules/chipsec.cfg.parsers.registers.simple.rst.txt new file mode 100644 index 00000000..e3e1a758 --- /dev/null +++ b/_sources/modules/chipsec.cfg.parsers.registers.simple.rst.txt @@ -0,0 +1,7 @@ +chipsec.cfg.parsers.registers.simple module +=========================================== + +.. automodule:: chipsec.cfg.parsers.registers.simple + + + diff --git a/_sources/modules/chipsec.hal.amd.cpu.rst.txt b/_sources/modules/chipsec.hal.amd.cpu.rst.txt new file mode 100644 index 00000000..20d2415a --- /dev/null +++ b/_sources/modules/chipsec.hal.amd.cpu.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.amd.cpu module +========================== + +.. automodule:: chipsec.hal.amd.cpu + + + diff --git a/_sources/modules/chipsec.hal.amd.psp.rst.txt b/_sources/modules/chipsec.hal.amd.psp.rst.txt new file mode 100644 index 00000000..cf661abc --- /dev/null +++ b/_sources/modules/chipsec.hal.amd.psp.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.amd.psp module +========================== + +.. automodule:: chipsec.hal.amd.psp + + + diff --git a/_sources/modules/chipsec.hal.amd.rst.txt b/_sources/modules/chipsec.hal.amd.rst.txt new file mode 100644 index 00000000..dd4b4d77 --- /dev/null +++ b/_sources/modules/chipsec.hal.amd.rst.txt @@ -0,0 +1,13 @@ +chipsec.hal.amd package +======================= + +.. toctree:: + :maxdepth: 10 + + chipsec.hal.amd.cpu + chipsec.hal.amd.psp + +.. automodule:: chipsec.hal.amd + + + diff --git a/_sources/modules/chipsec.hal.common.acpi.rst.txt b/_sources/modules/chipsec.hal.common.acpi.rst.txt new file mode 100644 index 00000000..302d9146 --- /dev/null +++ b/_sources/modules/chipsec.hal.common.acpi.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.acpi module +============================== + +.. automodule:: chipsec.hal.common.acpi + + + diff --git a/_sources/modules/chipsec.hal.common.cmos.rst.txt b/_sources/modules/chipsec.hal.common.cmos.rst.txt new file mode 100644 index 00000000..956aea3e --- /dev/null +++ b/_sources/modules/chipsec.hal.common.cmos.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.cmos module +============================== + +.. automodule:: chipsec.hal.common.cmos + + + diff --git a/_sources/modules/chipsec.hal.common.cpuid.rst.txt b/_sources/modules/chipsec.hal.common.cpuid.rst.txt new file mode 100644 index 00000000..614fb2a7 --- /dev/null +++ b/_sources/modules/chipsec.hal.common.cpuid.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.cpuid module +=============================== + +.. automodule:: chipsec.hal.common.cpuid + + + diff --git a/_sources/modules/chipsec.hal.common.ec.rst.txt b/_sources/modules/chipsec.hal.common.ec.rst.txt new file mode 100644 index 00000000..dd9cffad --- /dev/null +++ b/_sources/modules/chipsec.hal.common.ec.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.ec module +============================ + +.. automodule:: chipsec.hal.common.ec + + + diff --git a/_sources/modules/chipsec.hal.common.interrupts.rst.txt b/_sources/modules/chipsec.hal.common.interrupts.rst.txt new file mode 100644 index 00000000..3d3d7a2c --- /dev/null +++ b/_sources/modules/chipsec.hal.common.interrupts.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.interrupts module +==================================== + +.. automodule:: chipsec.hal.common.interrupts + + + diff --git a/_sources/modules/chipsec.hal.common.io.rst.txt b/_sources/modules/chipsec.hal.common.io.rst.txt new file mode 100644 index 00000000..42bd95f0 --- /dev/null +++ b/_sources/modules/chipsec.hal.common.io.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.io module +============================ + +.. automodule:: chipsec.hal.common.io + + + diff --git a/_sources/modules/chipsec.hal.common.iobar.rst.txt b/_sources/modules/chipsec.hal.common.iobar.rst.txt new file mode 100644 index 00000000..b3de57c3 --- /dev/null +++ b/_sources/modules/chipsec.hal.common.iobar.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.iobar module +=============================== + +.. automodule:: chipsec.hal.common.iobar + + + diff --git a/_sources/modules/chipsec.hal.common.iommu.rst.txt b/_sources/modules/chipsec.hal.common.iommu.rst.txt new file mode 100644 index 00000000..715a0c5c --- /dev/null +++ b/_sources/modules/chipsec.hal.common.iommu.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.iommu module +=============================== + +.. automodule:: chipsec.hal.common.iommu + + + diff --git a/_sources/modules/chipsec.hal.common.locks.rst.txt b/_sources/modules/chipsec.hal.common.locks.rst.txt new file mode 100644 index 00000000..4f81a90c --- /dev/null +++ b/_sources/modules/chipsec.hal.common.locks.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.locks module +=============================== + +.. automodule:: chipsec.hal.common.locks + + + diff --git a/_sources/modules/chipsec.hal.common.memrange.rst.txt b/_sources/modules/chipsec.hal.common.memrange.rst.txt new file mode 100644 index 00000000..ba7d5d41 --- /dev/null +++ b/_sources/modules/chipsec.hal.common.memrange.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.memrange module +================================== + +.. automodule:: chipsec.hal.common.memrange + + + diff --git a/_sources/modules/chipsec.hal.common.mmio.rst.txt b/_sources/modules/chipsec.hal.common.mmio.rst.txt new file mode 100644 index 00000000..361c39b2 --- /dev/null +++ b/_sources/modules/chipsec.hal.common.mmio.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.mmio module +============================== + +.. automodule:: chipsec.hal.common.mmio + + + diff --git a/_sources/modules/chipsec.hal.common.msr.rst.txt b/_sources/modules/chipsec.hal.common.msr.rst.txt new file mode 100644 index 00000000..22487c4c --- /dev/null +++ b/_sources/modules/chipsec.hal.common.msr.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.msr module +============================= + +.. automodule:: chipsec.hal.common.msr + + + diff --git a/_sources/modules/chipsec.hal.common.pci.rst.txt b/_sources/modules/chipsec.hal.common.pci.rst.txt new file mode 100644 index 00000000..89d79a01 --- /dev/null +++ b/_sources/modules/chipsec.hal.common.pci.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.pci module +============================= + +.. automodule:: chipsec.hal.common.pci + + + diff --git a/_sources/modules/chipsec.hal.common.physmem.rst.txt b/_sources/modules/chipsec.hal.common.physmem.rst.txt new file mode 100644 index 00000000..0de72a84 --- /dev/null +++ b/_sources/modules/chipsec.hal.common.physmem.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.physmem module +================================= + +.. automodule:: chipsec.hal.common.physmem + + + diff --git a/_sources/modules/chipsec.hal.common.rst.txt b/_sources/modules/chipsec.hal.common.rst.txt new file mode 100644 index 00000000..9be63121 --- /dev/null +++ b/_sources/modules/chipsec.hal.common.rst.txt @@ -0,0 +1,32 @@ +chipsec.hal.common package +========================== + +.. toctree:: + :maxdepth: 10 + + chipsec.hal.common.acpi + chipsec.hal.common.cmos + chipsec.hal.common.cpuid + chipsec.hal.common.ec + chipsec.hal.common.interrupts + chipsec.hal.common.io + chipsec.hal.common.iobar + chipsec.hal.common.iommu + chipsec.hal.common.locks + chipsec.hal.common.memrange + chipsec.hal.common.mmio + chipsec.hal.common.msr + chipsec.hal.common.pci + chipsec.hal.common.physmem + chipsec.hal.common.smbios + chipsec.hal.common.smbus + chipsec.hal.common.spd + chipsec.hal.common.tpm + chipsec.hal.common.uefi + chipsec.hal.common.virtmem + chipsec.hal.common.vmm + +.. automodule:: chipsec.hal.common + + + diff --git a/_sources/modules/chipsec.hal.common.smbios.rst.txt b/_sources/modules/chipsec.hal.common.smbios.rst.txt new file mode 100644 index 00000000..dd104179 --- /dev/null +++ b/_sources/modules/chipsec.hal.common.smbios.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.smbios module +================================ + +.. automodule:: chipsec.hal.common.smbios + + + diff --git a/_sources/modules/chipsec.hal.common.smbus.rst.txt b/_sources/modules/chipsec.hal.common.smbus.rst.txt new file mode 100644 index 00000000..7d8f0329 --- /dev/null +++ b/_sources/modules/chipsec.hal.common.smbus.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.smbus module +=============================== + +.. automodule:: chipsec.hal.common.smbus + + + diff --git a/_sources/modules/chipsec.hal.common.spd.rst.txt b/_sources/modules/chipsec.hal.common.spd.rst.txt new file mode 100644 index 00000000..04c116cc --- /dev/null +++ b/_sources/modules/chipsec.hal.common.spd.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.spd module +============================= + +.. automodule:: chipsec.hal.common.spd + + + diff --git a/_sources/modules/chipsec.hal.common.tpm.rst.txt b/_sources/modules/chipsec.hal.common.tpm.rst.txt new file mode 100644 index 00000000..f4217088 --- /dev/null +++ b/_sources/modules/chipsec.hal.common.tpm.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.tpm module +============================= + +.. automodule:: chipsec.hal.common.tpm + + + diff --git a/_sources/modules/chipsec.hal.common.uefi.rst.txt b/_sources/modules/chipsec.hal.common.uefi.rst.txt new file mode 100644 index 00000000..62ec12c5 --- /dev/null +++ b/_sources/modules/chipsec.hal.common.uefi.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.uefi module +============================== + +.. automodule:: chipsec.hal.common.uefi + + + diff --git a/_sources/modules/chipsec.hal.common.virtmem.rst.txt b/_sources/modules/chipsec.hal.common.virtmem.rst.txt new file mode 100644 index 00000000..ca59bfb0 --- /dev/null +++ b/_sources/modules/chipsec.hal.common.virtmem.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.virtmem module +================================= + +.. automodule:: chipsec.hal.common.virtmem + + + diff --git a/_sources/modules/chipsec.hal.common.vmm.rst.txt b/_sources/modules/chipsec.hal.common.vmm.rst.txt new file mode 100644 index 00000000..bafe60c4 --- /dev/null +++ b/_sources/modules/chipsec.hal.common.vmm.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.common.vmm module +============================= + +.. automodule:: chipsec.hal.common.vmm + + + diff --git a/_sources/modules/chipsec.hal.intel.cpu.rst.txt b/_sources/modules/chipsec.hal.intel.cpu.rst.txt new file mode 100644 index 00000000..2c41d531 --- /dev/null +++ b/_sources/modules/chipsec.hal.intel.cpu.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.intel.cpu module +============================ + +.. automodule:: chipsec.hal.intel.cpu + + + diff --git a/_sources/modules/chipsec.hal.intel.igd.rst.txt b/_sources/modules/chipsec.hal.intel.igd.rst.txt new file mode 100644 index 00000000..3fb76db7 --- /dev/null +++ b/_sources/modules/chipsec.hal.intel.igd.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.intel.igd module +============================ + +.. automodule:: chipsec.hal.intel.igd + + + diff --git a/_sources/modules/chipsec.hal.intel.mm_msgbus.rst.txt b/_sources/modules/chipsec.hal.intel.mm_msgbus.rst.txt new file mode 100644 index 00000000..4a1c23c2 --- /dev/null +++ b/_sources/modules/chipsec.hal.intel.mm_msgbus.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.intel.mm\_msgbus module +=================================== + +.. automodule:: chipsec.hal.intel.mm_msgbus + + + diff --git a/_sources/modules/chipsec.hal.intel.mmcfg.rst.txt b/_sources/modules/chipsec.hal.intel.mmcfg.rst.txt new file mode 100644 index 00000000..2930be71 --- /dev/null +++ b/_sources/modules/chipsec.hal.intel.mmcfg.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.intel.mmcfg module +============================== + +.. automodule:: chipsec.hal.intel.mmcfg + + + diff --git a/_sources/modules/chipsec.hal.intel.msgbus.rst.txt b/_sources/modules/chipsec.hal.intel.msgbus.rst.txt new file mode 100644 index 00000000..8d888eeb --- /dev/null +++ b/_sources/modules/chipsec.hal.intel.msgbus.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.intel.msgbus module +=============================== + +.. automodule:: chipsec.hal.intel.msgbus + + + diff --git a/_sources/modules/chipsec.hal.intel.rst.txt b/_sources/modules/chipsec.hal.intel.rst.txt new file mode 100644 index 00000000..2130e277 --- /dev/null +++ b/_sources/modules/chipsec.hal.intel.rst.txt @@ -0,0 +1,19 @@ +chipsec.hal.intel package +========================= + +.. toctree:: + :maxdepth: 10 + + chipsec.hal.intel.cpu + chipsec.hal.intel.igd + chipsec.hal.intel.mm_msgbus + chipsec.hal.intel.mmcfg + chipsec.hal.intel.msgbus + chipsec.hal.intel.spi + chipsec.hal.intel.spi_descriptor + chipsec.hal.intel.ucode + +.. automodule:: chipsec.hal.intel + + + diff --git a/_sources/modules/chipsec.hal.intel.spi.rst.txt b/_sources/modules/chipsec.hal.intel.spi.rst.txt new file mode 100644 index 00000000..b61c42e2 --- /dev/null +++ b/_sources/modules/chipsec.hal.intel.spi.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.intel.spi module +============================ + +.. automodule:: chipsec.hal.intel.spi + + + diff --git a/_sources/modules/chipsec.hal.intel.spi_descriptor.rst.txt b/_sources/modules/chipsec.hal.intel.spi_descriptor.rst.txt new file mode 100644 index 00000000..78b5085b --- /dev/null +++ b/_sources/modules/chipsec.hal.intel.spi_descriptor.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.intel.spi\_descriptor module +======================================== + +.. automodule:: chipsec.hal.intel.spi_descriptor + + + diff --git a/_sources/modules/chipsec.hal.intel.ucode.rst.txt b/_sources/modules/chipsec.hal.intel.ucode.rst.txt new file mode 100644 index 00000000..6ac446f9 --- /dev/null +++ b/_sources/modules/chipsec.hal.intel.ucode.rst.txt @@ -0,0 +1,7 @@ +chipsec.hal.intel.ucode module +============================== + +.. automodule:: chipsec.hal.intel.ucode + + + diff --git a/_sources/modules/chipsec.hal.rst.txt b/_sources/modules/chipsec.hal.rst.txt index 361bad40..79c0d1ee 100644 --- a/_sources/modules/chipsec.hal.rst.txt +++ b/_sources/modules/chipsec.hal.rst.txt @@ -1,6 +1,13 @@ chipsec.hal package =================== +.. toctree:: + :maxdepth: 10 + + chipsec.hal.amd + chipsec.hal.common + chipsec.hal.intel + .. toctree:: :maxdepth: 10 diff --git a/_sources/modules/chipsec.helper.record.recordhelper.rst.txt b/_sources/modules/chipsec.helper.record.recordhelper.rst.txt new file mode 100644 index 00000000..be53b727 --- /dev/null +++ b/_sources/modules/chipsec.helper.record.recordhelper.rst.txt @@ -0,0 +1,7 @@ +chipsec.helper.record.recordhelper module +========================================= + +.. automodule:: chipsec.helper.record.recordhelper + + + diff --git a/_sources/modules/chipsec.helper.record.rst.txt b/_sources/modules/chipsec.helper.record.rst.txt new file mode 100644 index 00000000..7b556b14 --- /dev/null +++ b/_sources/modules/chipsec.helper.record.rst.txt @@ -0,0 +1,12 @@ +chipsec.helper.record package +============================= + +.. toctree:: + :maxdepth: 10 + + chipsec.helper.record.recordhelper + +.. automodule:: chipsec.helper.record + + + diff --git a/_sources/modules/chipsec.helper.replay.replayhelper.rst.txt b/_sources/modules/chipsec.helper.replay.replayhelper.rst.txt new file mode 100644 index 00000000..b67f659e --- /dev/null +++ b/_sources/modules/chipsec.helper.replay.replayhelper.rst.txt @@ -0,0 +1,7 @@ +chipsec.helper.replay.replayhelper module +========================================= + +.. automodule:: chipsec.helper.replay.replayhelper + + + diff --git a/_sources/modules/chipsec.helper.replay.rst.txt b/_sources/modules/chipsec.helper.replay.rst.txt new file mode 100644 index 00000000..2ebdb723 --- /dev/null +++ b/_sources/modules/chipsec.helper.replay.rst.txt @@ -0,0 +1,12 @@ +chipsec.helper.replay package +============================= + +.. toctree:: + :maxdepth: 10 + + chipsec.helper.replay.replayhelper + +.. automodule:: chipsec.helper.replay + + + diff --git a/_sources/modules/chipsec.helper.rst.txt b/_sources/modules/chipsec.helper.rst.txt index e91bd8c5..93feebf2 100644 --- a/_sources/modules/chipsec.helper.rst.txt +++ b/_sources/modules/chipsec.helper.rst.txt @@ -8,6 +8,8 @@ chipsec.helper package chipsec.helper.efi chipsec.helper.linux chipsec.helper.linuxnative + chipsec.helper.record + chipsec.helper.replay chipsec.helper.windows .. toctree:: diff --git a/_sources/modules/chipsec.library.intel.rst.txt b/_sources/modules/chipsec.library.intel.rst.txt new file mode 100644 index 00000000..785a209e --- /dev/null +++ b/_sources/modules/chipsec.library.intel.rst.txt @@ -0,0 +1,14 @@ +chipsec.library.intel package +============================= + +.. toctree:: + :maxdepth: 10 + + chipsec.library.intel.spi + chipsec.library.intel.spi_descriptor_cfgs + chipsec.library.intel.vmm_common + +.. automodule:: chipsec.library.intel + + + diff --git a/_sources/modules/chipsec.library.intel.spi.rst.txt b/_sources/modules/chipsec.library.intel.spi.rst.txt new file mode 100644 index 00000000..bcad4a79 --- /dev/null +++ b/_sources/modules/chipsec.library.intel.spi.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.intel.spi module +================================ + +.. automodule:: chipsec.library.intel.spi + + + diff --git a/_sources/modules/chipsec.library.intel.spi_descriptor_cfgs.rst.txt b/_sources/modules/chipsec.library.intel.spi_descriptor_cfgs.rst.txt new file mode 100644 index 00000000..151464a9 --- /dev/null +++ b/_sources/modules/chipsec.library.intel.spi_descriptor_cfgs.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.intel.spi\_descriptor\_cfgs module +================================================== + +.. automodule:: chipsec.library.intel.spi_descriptor_cfgs + + + diff --git a/_sources/modules/chipsec.library.intel.vmm_common.rst.txt b/_sources/modules/chipsec.library.intel.vmm_common.rst.txt new file mode 100644 index 00000000..1f72599d --- /dev/null +++ b/_sources/modules/chipsec.library.intel.vmm_common.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.intel.vmm\_common module +======================================== + +.. automodule:: chipsec.library.intel.vmm_common + + + diff --git a/_sources/modules/chipsec.library.registers.baseregister.rst.txt b/_sources/modules/chipsec.library.registers.baseregister.rst.txt new file mode 100644 index 00000000..6d7d67bd --- /dev/null +++ b/_sources/modules/chipsec.library.registers.baseregister.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.registers.baseregister module +============================================= + +.. automodule:: chipsec.library.registers.baseregister + + + diff --git a/_sources/modules/chipsec.library.registers.io.rst.txt b/_sources/modules/chipsec.library.registers.io.rst.txt new file mode 100644 index 00000000..1dbc0a53 --- /dev/null +++ b/_sources/modules/chipsec.library.registers.io.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.registers.io module +=================================== + +.. automodule:: chipsec.library.registers.io + + + diff --git a/_sources/modules/chipsec.library.registers.iobar.rst.txt b/_sources/modules/chipsec.library.registers.iobar.rst.txt new file mode 100644 index 00000000..a349266b --- /dev/null +++ b/_sources/modules/chipsec.library.registers.iobar.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.registers.iobar module +====================================== + +.. automodule:: chipsec.library.registers.iobar + + + diff --git a/_sources/modules/chipsec.library.registers.memory.rst.txt b/_sources/modules/chipsec.library.registers.memory.rst.txt new file mode 100644 index 00000000..36dc7a37 --- /dev/null +++ b/_sources/modules/chipsec.library.registers.memory.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.registers.memory module +======================================= + +.. automodule:: chipsec.library.registers.memory + + + diff --git a/_sources/modules/chipsec.library.registers.mm_msgbus.rst.txt b/_sources/modules/chipsec.library.registers.mm_msgbus.rst.txt new file mode 100644 index 00000000..71b6754d --- /dev/null +++ b/_sources/modules/chipsec.library.registers.mm_msgbus.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.registers.mm\_msgbus module +=========================================== + +.. automodule:: chipsec.library.registers.mm_msgbus + + + diff --git a/_sources/modules/chipsec.library.registers.mmcfg.rst.txt b/_sources/modules/chipsec.library.registers.mmcfg.rst.txt new file mode 100644 index 00000000..1a3d9e47 --- /dev/null +++ b/_sources/modules/chipsec.library.registers.mmcfg.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.registers.mmcfg module +====================================== + +.. automodule:: chipsec.library.registers.mmcfg + + + diff --git a/_sources/modules/chipsec.library.registers.mmio.rst.txt b/_sources/modules/chipsec.library.registers.mmio.rst.txt new file mode 100644 index 00000000..2c36a17f --- /dev/null +++ b/_sources/modules/chipsec.library.registers.mmio.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.registers.mmio module +===================================== + +.. automodule:: chipsec.library.registers.mmio + + + diff --git a/_sources/modules/chipsec.library.registers.msgbus.rst.txt b/_sources/modules/chipsec.library.registers.msgbus.rst.txt new file mode 100644 index 00000000..0d1f8fba --- /dev/null +++ b/_sources/modules/chipsec.library.registers.msgbus.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.registers.msgbus module +======================================= + +.. automodule:: chipsec.library.registers.msgbus + + + diff --git a/_sources/modules/chipsec.library.registers.msr.rst.txt b/_sources/modules/chipsec.library.registers.msr.rst.txt new file mode 100644 index 00000000..f7833b1f --- /dev/null +++ b/_sources/modules/chipsec.library.registers.msr.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.registers.msr module +==================================== + +.. automodule:: chipsec.library.registers.msr + + + diff --git a/_sources/modules/chipsec.library.registers.pcicfg.rst.txt b/_sources/modules/chipsec.library.registers.pcicfg.rst.txt new file mode 100644 index 00000000..e6cc59f4 --- /dev/null +++ b/_sources/modules/chipsec.library.registers.pcicfg.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.registers.pcicfg module +======================================= + +.. automodule:: chipsec.library.registers.pcicfg + + + diff --git a/_sources/modules/chipsec.library.registers.rst.txt b/_sources/modules/chipsec.library.registers.rst.txt new file mode 100644 index 00000000..89bdf31f --- /dev/null +++ b/_sources/modules/chipsec.library.registers.rst.txt @@ -0,0 +1,21 @@ +chipsec.library.registers package +================================= + +.. toctree:: + :maxdepth: 10 + + chipsec.library.registers.baseregister + chipsec.library.registers.io + chipsec.library.registers.iobar + chipsec.library.registers.memory + chipsec.library.registers.mm_msgbus + chipsec.library.registers.mmcfg + chipsec.library.registers.mmio + chipsec.library.registers.msgbus + chipsec.library.registers.msr + chipsec.library.registers.pcicfg + +.. automodule:: chipsec.library.registers + + + diff --git a/_sources/modules/chipsec.library.uefi.common.rst.txt b/_sources/modules/chipsec.library.uefi.common.rst.txt new file mode 100644 index 00000000..d065d61a --- /dev/null +++ b/_sources/modules/chipsec.library.uefi.common.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.uefi.common module +================================== + +.. automodule:: chipsec.library.uefi.common + + + diff --git a/_sources/modules/chipsec.library.uefi.compression.rst.txt b/_sources/modules/chipsec.library.uefi.compression.rst.txt new file mode 100644 index 00000000..776fbb1f --- /dev/null +++ b/_sources/modules/chipsec.library.uefi.compression.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.uefi.compression module +======================================= + +.. automodule:: chipsec.library.uefi.compression + + + diff --git a/_sources/modules/chipsec.library.uefi.fv.rst.txt b/_sources/modules/chipsec.library.uefi.fv.rst.txt new file mode 100644 index 00000000..ba6cc890 --- /dev/null +++ b/_sources/modules/chipsec.library.uefi.fv.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.uefi.fv module +============================== + +.. automodule:: chipsec.library.uefi.fv + + + diff --git a/_sources/modules/chipsec.library.uefi.platform.rst.txt b/_sources/modules/chipsec.library.uefi.platform.rst.txt new file mode 100644 index 00000000..613c8233 --- /dev/null +++ b/_sources/modules/chipsec.library.uefi.platform.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.uefi.platform module +==================================== + +.. automodule:: chipsec.library.uefi.platform + + + diff --git a/_sources/modules/chipsec.library.uefi.rst.txt b/_sources/modules/chipsec.library.uefi.rst.txt new file mode 100644 index 00000000..50a721e1 --- /dev/null +++ b/_sources/modules/chipsec.library.uefi.rst.txt @@ -0,0 +1,20 @@ +chipsec.library.uefi package +============================ + +.. toctree:: + :maxdepth: 10 + + chipsec.library.uefi.common + chipsec.library.uefi.compression + chipsec.library.uefi.fv + chipsec.library.uefi.platform + chipsec.library.uefi.search + chipsec.library.uefi.sleep_states + chipsec.library.uefi.spi + chipsec.library.uefi.variables + chipsec.library.uefi.varstore + +.. automodule:: chipsec.library.uefi + + + diff --git a/_sources/modules/chipsec.library.uefi.search.rst.txt b/_sources/modules/chipsec.library.uefi.search.rst.txt new file mode 100644 index 00000000..d1b1c452 --- /dev/null +++ b/_sources/modules/chipsec.library.uefi.search.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.uefi.search module +================================== + +.. automodule:: chipsec.library.uefi.search + + + diff --git a/_sources/modules/chipsec.library.uefi.sleep_states.rst.txt b/_sources/modules/chipsec.library.uefi.sleep_states.rst.txt new file mode 100644 index 00000000..790e655e --- /dev/null +++ b/_sources/modules/chipsec.library.uefi.sleep_states.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.uefi.sleep\_states module +========================================= + +.. automodule:: chipsec.library.uefi.sleep_states + + + diff --git a/_sources/modules/chipsec.library.uefi.spi.rst.txt b/_sources/modules/chipsec.library.uefi.spi.rst.txt new file mode 100644 index 00000000..7399f92a --- /dev/null +++ b/_sources/modules/chipsec.library.uefi.spi.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.uefi.spi module +=============================== + +.. automodule:: chipsec.library.uefi.spi + + + diff --git a/_sources/modules/chipsec.library.uefi.variables.rst.txt b/_sources/modules/chipsec.library.uefi.variables.rst.txt new file mode 100644 index 00000000..b9a31288 --- /dev/null +++ b/_sources/modules/chipsec.library.uefi.variables.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.uefi.variables module +===================================== + +.. automodule:: chipsec.library.uefi.variables + + + diff --git a/_sources/modules/chipsec.library.uefi.varstore.rst.txt b/_sources/modules/chipsec.library.uefi.varstore.rst.txt new file mode 100644 index 00000000..ba39e39a --- /dev/null +++ b/_sources/modules/chipsec.library.uefi.varstore.rst.txt @@ -0,0 +1,7 @@ +chipsec.library.uefi.varstore module +==================================== + +.. automodule:: chipsec.library.uefi.varstore + + + diff --git a/contribution/code-style-python.html b/contribution/code-style-python.html index d20a152b..915dcd9d 100644 --- a/contribution/code-style-python.html +++ b/contribution/code-style-python.html @@ -617,7 +617,7 @@

Navigation

diff --git a/contribution/sphinx.html b/contribution/sphinx.html index 05b49cb5..9dfa42a0 100644 --- a/contribution/sphinx.html +++ b/contribution/sphinx.html @@ -157,7 +157,7 @@

Navigation

diff --git a/development/Architecture-Overview.html b/development/Architecture-Overview.html index 4b7b38a2..5f86bb6a 100644 --- a/development/Architecture-Overview.html +++ b/development/Architecture-Overview.html @@ -163,6 +163,46 @@

HAL (Hardware Abstraction Layer) diff --git a/development/Configuration-Files.html b/development/Configuration-Files.html index 872cc853..9eac7d98 100644 --- a/development/Configuration-Files.html +++ b/development/Configuration-Files.html @@ -206,7 +206,7 @@

Navigation

diff --git a/development/Developing.html b/development/Developing.html index b38e6573..b937403f 100644 --- a/development/Developing.html +++ b/development/Developing.html @@ -193,7 +193,7 @@

Navigation

diff --git a/development/OS-Helpers-and-Drivers.html b/development/OS-Helpers-and-Drivers.html index e47b6794..686ffa65 100644 --- a/development/OS-Helpers-and-Drivers.html +++ b/development/OS-Helpers-and-Drivers.html @@ -81,6 +81,8 @@

Helper componentschipsec.helper.efi package
  • chipsec.helper.linux package
  • chipsec.helper.linuxnative package
    • +
  • chipsec.helper.record package
    • +
  • chipsec.helper.replay package
  • chipsec.helper.windows package
  • chipsec.helper.basehelper module
  • chipsec.helper.nonehelper module
    • @@ -190,7 +192,7 @@

    Navigation

    diff --git a/development/Platform-Detection.html b/development/Platform-Detection.html index ce868e20..6d121af7 100644 --- a/development/Platform-Detection.html +++ b/development/Platform-Detection.html @@ -164,7 +164,7 @@

    Navigation

    diff --git a/development/Sample-Module-Code.html b/development/Sample-Module-Code.html index 6343cd06..406f9aa5 100644 --- a/development/Sample-Module-Code.html +++ b/development/Sample-Module-Code.html @@ -173,7 +173,7 @@

    Navigation

    diff --git a/development/Sample-Util-Command.html b/development/Sample-Util-Command.html index 59363299..d065bfa4 100644 --- a/development/Sample-Util-Command.html +++ b/development/Sample-Util-Command.html @@ -176,7 +176,7 @@

    Navigation

    diff --git a/development/Vulnerabilities-and-CHIPSEC-Modules.html b/development/Vulnerabilities-and-CHIPSEC-Modules.html index 1056fb16..599a968d 100644 --- a/development/Vulnerabilities-and-CHIPSEC-Modules.html +++ b/development/Vulnerabilities-and-CHIPSEC-Modules.html @@ -653,7 +653,7 @@

    Navigation

    diff --git a/genindex.html b/genindex.html index 0b8a21d9..3b5651dd 100644 --- a/genindex.html +++ b/genindex.html @@ -65,48 +65,447 @@

    C

    +
  • + chipsec.cfg.parsers.ip + +
    • +
  • + chipsec.cfg.parsers.ip.generic + +
    • +
  • + chipsec.cfg.parsers.ip.io + +
    • +
  • + chipsec.cfg.parsers.ip.iobar + +
    • +
  • + chipsec.cfg.parsers.ip.memory + +
    • +
  • + chipsec.cfg.parsers.ip.mm_msgbus + +
    • +
  • + chipsec.cfg.parsers.ip.mmio_bar + +
    • +
  • + chipsec.cfg.parsers.ip.msgbus + +
    • +
  • + chipsec.cfg.parsers.ip.msr + +
    • +
  • + chipsec.cfg.parsers.ip.pci_device + +
    • +
  • + chipsec.cfg.parsers.ip.platform + +
  • chipsec.cfg.parsers.locks
    • +
  • + chipsec.cfg.parsers.registers + +
    • +
  • + chipsec.cfg.parsers.registers.controls + +
    • +
  • + chipsec.cfg.parsers.registers.io + +
    • +
  • + chipsec.cfg.parsers.registers.iobar + +
    • +
  • + chipsec.cfg.parsers.registers.locks + +
    • +
  • + chipsec.cfg.parsers.registers.memory + +
    • +
  • + chipsec.cfg.parsers.registers.mm_msgbus + +
    • +
  • + chipsec.cfg.parsers.registers.mmcfg + +
    • +
  • + chipsec.cfg.parsers.registers.mmio + +
    • +
  • + chipsec.cfg.parsers.registers.msgbus + +
    • +
  • + chipsec.cfg.parsers.registers.msr + +
    • +
  • + chipsec.cfg.parsers.registers.pci + +
    • +
  • + chipsec.cfg.parsers.registers.simple + +
    • +
  • + chipsec.fuzzing + +
    • +
  • + chipsec.fuzzing.primitives + +
    • +
  • + chipsec.hal + +
    • +
  • + chipsec.hal.amd + +
    • +
  • + chipsec.hal.amd.cpu + +
    • +
  • + chipsec.hal.amd.psp + +
    • +
  • + chipsec.hal.common + +
    • +
  • + chipsec.hal.common.acpi + +
    • +
  • + chipsec.hal.common.cmos + +
    • +
  • + chipsec.hal.common.cpuid + +
    • +
  • + chipsec.hal.common.ec + +
    • +
  • + chipsec.hal.common.interrupts + +
    • +
  • + chipsec.hal.common.io + +
    • +
  • + chipsec.hal.common.iobar + +
    • +
  • + chipsec.hal.common.iommu + +
    • +
  • + chipsec.hal.common.locks + +
    • +
  • + chipsec.hal.common.memrange + +
    • +
  • + chipsec.hal.common.mmio + +
    • +
  • + chipsec.hal.common.msr + +
    • +
  • + chipsec.hal.common.pci + +
    • +
  • + chipsec.hal.common.physmem + +
    • +
  • + chipsec.hal.common.smbios + +
    • +
  • + chipsec.hal.common.smbus + +
    • +
  • + chipsec.hal.common.spd + +
    • +
  • + chipsec.hal.common.tpm + +
    • +
  • + chipsec.hal.common.uefi + +
    • +
  • + chipsec.hal.common.virtmem + +
    • +
  • + chipsec.hal.common.vmm + +
    • +
  • + chipsec.hal.hal_base + +
    • +
  • + chipsec.hal.hals + +
    • +
  • + chipsec.hal.intel + +
  • - chipsec.fuzzing + chipsec.hal.intel.cpu
  • - chipsec.fuzzing.primitives + chipsec.hal.intel.igd
  • - chipsec.hal + chipsec.hal.intel.mm_msgbus
  • - chipsec.hal.hal_base + chipsec.hal.intel.mmcfg
  • - chipsec.hal.hals + chipsec.hal.intel.msgbus
    • +
  • + chipsec.hal.intel.spi + +
    • +
  • + chipsec.hal.intel.ucode + +
  • @@ -205,6 +604,34 @@

    C

    • +
  • + chipsec.helper.record + +
    • +
  • + chipsec.helper.record.recordhelper + +
    • +
  • + chipsec.helper.replay + +
    • +
  • + chipsec.helper.replay.replayhelper + +
  • @@ -247,6 +674,34 @@

    C

    • +
  • + chipsec.library.intel + +
    • +
  • + chipsec.library.intel.spi + +
    • +
  • + chipsec.library.intel.spi_descriptor_cfgs + +
    • +
  • + chipsec.library.intel.vmm_common + +
  • @@ -268,6 +723,83 @@

    C

    • +
  • + chipsec.library.registers + +
    • +
  • + chipsec.library.registers.baseregister + +
    • +
  • + chipsec.library.registers.io + +
    • +
  • + chipsec.library.registers.iobar + +
    • +
  • + chipsec.library.registers.memory + +
    • +
  • + chipsec.library.registers.mm_msgbus + +
    • +
  • + chipsec.library.registers.mmcfg + +
    • +
  • + chipsec.library.registers.mmio + +
    • +
  • + chipsec.library.registers.msgbus + +
    • +
  • + chipsec.library.registers.msr + +
    • +
  • + chipsec.library.registers.pcicfg + +
  • @@ -289,6 +821,78 @@

    C

    • +
  • + chipsec.library.uefi + +
    • +
  • + chipsec.library.uefi.common + +
    • +
  • + chipsec.library.uefi.compression + +
    • + + - - diff --git a/index.html b/index.html index 4d8c7dd7..72e75f0d 100644 --- a/index.html +++ b/index.html @@ -5,7 +5,7 @@ - CHIPSEC 2.0.3 — CHIPSEC documentation + CHIPSEC 2.0.4 — CHIPSEC documentation @@ -31,7 +31,7 @@

    Navigation

    next |
  • CHIPSEC documentation »
    • -
  • CHIPSEC 2.0.3
    • +
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    • @@ -40,8 +40,8 @@

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    -
    -

    CHIPSEC 2.0.3¶

    +
    +

    CHIPSEC 2.0.4¶

    CHIPSEC is a framework for analyzing platform level security of hardware, devices, system firmware, low-level protection mechanisms, and the configuration of various platform components.

    @@ -229,11 +229,11 @@

    Navigation

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    • -
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    • +
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    diff --git a/modules/chipsec.cfg.parsers.core_parser_helper.html b/modules/chipsec.cfg.parsers.core_parser_helper.html index 5dea72e8..d3cbc3b7 100644 --- a/modules/chipsec.cfg.parsers.core_parser_helper.html +++ b/modules/chipsec.cfg.parsers.core_parser_helper.html @@ -125,7 +125,7 @@

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    diff --git a/modules/chipsec.cfg.parsers.iommu_parser.html b/modules/chipsec.cfg.parsers.iommu_parser.html index 4decf14c..c218ddc7 100644 --- a/modules/chipsec.cfg.parsers.iommu_parser.html +++ b/modules/chipsec.cfg.parsers.iommu_parser.html @@ -124,7 +124,7 @@

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    diff --git a/modules/chipsec.cfg.parsers.ip.generic.html b/modules/chipsec.cfg.parsers.ip.generic.html new file mode 100644 index 00000000..232db0cf --- /dev/null +++ b/modules/chipsec.cfg.parsers.ip.generic.html @@ -0,0 +1,133 @@ + + + + + + + + chipsec.cfg.parsers.ip.generic module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.ip.generic module¶

    +

    Generic IP Configuration Helper

    +

    This module provides generic configuration management functionality for IP-based parsers. +It serves as the base class for all IP-specific configuration helpers, offering common +functionality like configuration validation, manipulation, and utility methods.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.ip.html b/modules/chipsec.cfg.parsers.ip.html new file mode 100644 index 00000000..ce3e311b --- /dev/null +++ b/modules/chipsec.cfg.parsers.ip.html @@ -0,0 +1,143 @@ + + + + + + + + chipsec.cfg.parsers.ip package — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.ip package¶

    +
    + +
    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.ip.io.html b/modules/chipsec.cfg.parsers.ip.io.html new file mode 100644 index 00000000..df62b8fd --- /dev/null +++ b/modules/chipsec.cfg.parsers.ip.io.html @@ -0,0 +1,132 @@ + + + + + + + + chipsec.cfg.parsers.ip.io module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.ip.io module¶

    +

    I/O Port IP Configuration Helper

    +

    Provides I/O port-specific configuration management functionality for +I/O port-based IP parsers.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.ip.iobar.html b/modules/chipsec.cfg.parsers.ip.iobar.html new file mode 100644 index 00000000..574b0a54 --- /dev/null +++ b/modules/chipsec.cfg.parsers.ip.iobar.html @@ -0,0 +1,132 @@ + + + + + + + + chipsec.cfg.parsers.ip.iobar module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.ip.iobar module¶

    +

    I/O BAR IP Configuration Helper

    +

    Provides I/O BAR-specific configuration management functionality for +I/O base address registers.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.ip.memory.html b/modules/chipsec.cfg.parsers.ip.memory.html new file mode 100644 index 00000000..b5fbb612 --- /dev/null +++ b/modules/chipsec.cfg.parsers.ip.memory.html @@ -0,0 +1,132 @@ + + + + + + + + chipsec.cfg.parsers.ip.memory module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.ip.memory module¶

    +

    Memory IP Configuration Helper

    +

    Provides memory-specific configuration management functionality for +memory-mapped regions.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.ip.mm_msgbus.html b/modules/chipsec.cfg.parsers.ip.mm_msgbus.html new file mode 100644 index 00000000..05422627 --- /dev/null +++ b/modules/chipsec.cfg.parsers.ip.mm_msgbus.html @@ -0,0 +1,132 @@ + + + + + + + + chipsec.cfg.parsers.ip.mm_msgbus module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.ip.mm_msgbus module¶

    +

    MM_MSGBUS (Memory-Mapped Message Bus) configuration parser.

    +

    This module provides MM_MSGBUSConfig class for parsing and managing memory-mapped message bus configurations +in the CHIPSEC framework. Memory-mapped message buses provide MMIO-based communication interfaces.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.ip.mmio_bar.html b/modules/chipsec.cfg.parsers.ip.mmio_bar.html new file mode 100644 index 00000000..5c3a40c9 --- /dev/null +++ b/modules/chipsec.cfg.parsers.ip.mmio_bar.html @@ -0,0 +1,132 @@ + + + + + + + + chipsec.cfg.parsers.ip.mmio_bar module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.ip.mmio_bar module¶

    +

    MMIO BAR IP Configuration Helper

    +

    Provides MMIO BAR-specific configuration management functionality for +memory-mapped I/O base address registers.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.ip.msgbus.html b/modules/chipsec.cfg.parsers.ip.msgbus.html new file mode 100644 index 00000000..c450b6d9 --- /dev/null +++ b/modules/chipsec.cfg.parsers.ip.msgbus.html @@ -0,0 +1,132 @@ + + + + + + + + chipsec.cfg.parsers.ip.msgbus module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.ip.msgbus module¶

    +

    MSGBUS (Message Bus) configuration parser.

    +

    This module provides MSGBUSConfig class for parsing and managing message bus configurations in the CHIPSEC framework. +Message buses provide communication interfaces between different platform components.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.ip.msr.html b/modules/chipsec.cfg.parsers.ip.msr.html new file mode 100644 index 00000000..bcce8e88 --- /dev/null +++ b/modules/chipsec.cfg.parsers.ip.msr.html @@ -0,0 +1,132 @@ + + + + + + + + chipsec.cfg.parsers.ip.msr module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.ip.msr module¶

    +

    MSR (Model Specific Register) configuration parser.

    +

    This module provides MSRConfig class for parsing and managing MSR configurations in the CHIPSEC framework. +MSRs are CPU-specific registers that provide access to processor features and debugging capabilities.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.ip.pci_device.html b/modules/chipsec.cfg.parsers.ip.pci_device.html new file mode 100644 index 00000000..445858fd --- /dev/null +++ b/modules/chipsec.cfg.parsers.ip.pci_device.html @@ -0,0 +1,132 @@ + + + + + + + + chipsec.cfg.parsers.ip.pci_device module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.ip.pci_device module¶

    +

    PCI Device IP Configuration Helper

    +

    Provides PCI device-specific configuration management functionality for +PCI-based IP parsers.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.ip.platform.html b/modules/chipsec.cfg.parsers.ip.platform.html new file mode 100644 index 00000000..04a1c769 --- /dev/null +++ b/modules/chipsec.cfg.parsers.ip.platform.html @@ -0,0 +1,133 @@ + + + + + + + + chipsec.cfg.parsers.ip.platform module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.ip.platform module¶

    +

    Platform configuration parser and hierarchy management.

    +

    This module provides classes for managing platform configurations in a hierarchical structure: +Platform -> Vendor -> IP -> Bar -> Register. It supports pattern matching, scoping, +and register access across the configuration hierarchy.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.locks.html b/modules/chipsec.cfg.parsers.locks.html index 062fb0ba..7212bbf0 100644 --- a/modules/chipsec.cfg.parsers.locks.html +++ b/modules/chipsec.cfg.parsers.locks.html @@ -125,7 +125,7 @@

    Navigation

    diff --git a/modules/chipsec.cfg.parsers.registers.controls.html b/modules/chipsec.cfg.parsers.registers.controls.html new file mode 100644 index 00000000..d76079c1 --- /dev/null +++ b/modules/chipsec.cfg.parsers.registers.controls.html @@ -0,0 +1,132 @@ + + + + + + + + chipsec.cfg.parsers.registers.controls module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.registers.controls module¶

    +

    Control Register Helper configuration parser and accessor.

    +

    This module provides CONTROLHelper class for parsing and accessing control register fields +in the CHIPSEC framework. Control helpers provide access to specific fields within registers.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.registers.html b/modules/chipsec.cfg.parsers.registers.html new file mode 100644 index 00000000..cfcf8797 --- /dev/null +++ b/modules/chipsec.cfg.parsers.registers.html @@ -0,0 +1,145 @@ + + + + + + + + chipsec.cfg.parsers.registers package — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.registers package¶

    +
    + +
    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.registers.io.html b/modules/chipsec.cfg.parsers.registers.io.html new file mode 100644 index 00000000..c4df7e09 --- /dev/null +++ b/modules/chipsec.cfg.parsers.registers.io.html @@ -0,0 +1,132 @@ + + + + + + + + chipsec.cfg.parsers.registers.io module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.registers.io module¶

    +

    I/O Register configuration parser and accessor.

    +

    This module provides IORegisters class for parsing and accessing I/O port-based registers +in the CHIPSEC framework. I/O registers are accessed through CPU I/O port instructions.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.registers.iobar.html b/modules/chipsec.cfg.parsers.registers.iobar.html new file mode 100644 index 00000000..51a345d9 --- /dev/null +++ b/modules/chipsec.cfg.parsers.registers.iobar.html @@ -0,0 +1,132 @@ + + + + + + + + chipsec.cfg.parsers.registers.iobar module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.registers.iobar module¶

    +

    I/O BAR Register configuration parser and accessor.

    +

    This module provides IOBARRegisters class for parsing and accessing I/O Base Address Register (BAR) registers +in the CHIPSEC framework. I/O BAR registers provide access to device registers through I/O port spaces.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.registers.locks.html b/modules/chipsec.cfg.parsers.registers.locks.html new file mode 100644 index 00000000..de872ad7 --- /dev/null +++ b/modules/chipsec.cfg.parsers.registers.locks.html @@ -0,0 +1,132 @@ + + + + + + + + chipsec.cfg.parsers.registers.locks module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.registers.locks module¶

    +

    Lock Register Helper configuration parser and accessor.

    +

    This module provides LOCKSHelper class for parsing and managing lock register configurations +in the CHIPSEC framework. Lock helpers provide access to lock bits and dependency management.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.registers.memory.html b/modules/chipsec.cfg.parsers.registers.memory.html new file mode 100644 index 00000000..6f673524 --- /dev/null +++ b/modules/chipsec.cfg.parsers.registers.memory.html @@ -0,0 +1,132 @@ + + + + + + + + chipsec.cfg.parsers.registers.memory module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.registers.memory module¶

    +

    Memory Register configuration parser and accessor.

    +

    This module provides MEMORYRegisters class for parsing and accessing memory-mapped registers +in the CHIPSEC framework. Memory registers can be accessed through DRAM or MMIO methods.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.registers.mm_msgbus.html b/modules/chipsec.cfg.parsers.registers.mm_msgbus.html new file mode 100644 index 00000000..d7d532a9 --- /dev/null +++ b/modules/chipsec.cfg.parsers.registers.mm_msgbus.html @@ -0,0 +1,133 @@ + + + + + + + + chipsec.cfg.parsers.registers.mm_msgbus module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.registers.mm_msgbus module¶

    +

    MM_MSGBUS Register configuration parser and accessor.

    +

    This module provides MM_MSGBUSRegisters class for parsing and accessing memory-mapped message bus registers +in the CHIPSEC framework. MM_MSGBUS registers provide access to various hardware interfaces through +memory-mapped message bus protocols.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.registers.mmcfg.html b/modules/chipsec.cfg.parsers.registers.mmcfg.html new file mode 100644 index 00000000..83deeca8 --- /dev/null +++ b/modules/chipsec.cfg.parsers.registers.mmcfg.html @@ -0,0 +1,133 @@ + + + + + + + + chipsec.cfg.parsers.registers.mmcfg module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.registers.mmcfg module¶

    +

    MMCFG Register configuration parser and accessor.

    +

    This module provides MMCFGRegisters class for parsing and accessing memory-mapped configuration +space registers in the CHIPSEC framework. MMCFG registers provide access to PCI configuration +space through memory-mapped I/O.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.registers.mmio.html b/modules/chipsec.cfg.parsers.registers.mmio.html new file mode 100644 index 00000000..2c804e5f --- /dev/null +++ b/modules/chipsec.cfg.parsers.registers.mmio.html @@ -0,0 +1,133 @@ + + + + + + + + chipsec.cfg.parsers.registers.mmio module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.registers.mmio module¶

    +

    MMIO Register configuration parser and accessor.

    +

    This module provides MMIORegisters class for parsing and accessing Memory-Mapped I/O registers +in the CHIPSEC framework. MMIO registers provide access to hardware interfaces through +memory-mapped address spaces.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.registers.msgbus.html b/modules/chipsec.cfg.parsers.registers.msgbus.html new file mode 100644 index 00000000..40b6ec72 --- /dev/null +++ b/modules/chipsec.cfg.parsers.registers.msgbus.html @@ -0,0 +1,133 @@ + + + + + + + + chipsec.cfg.parsers.registers.msgbus module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.registers.msgbus module¶

    +

    MSGBUS Register configuration parser and accessor.

    +

    This module provides MSGBUSRegisters class for parsing and accessing message bus registers +in the CHIPSEC framework. Message bus registers provide access to various hardware interfaces +through Intel’s Message Bus protocol.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.registers.msr.html b/modules/chipsec.cfg.parsers.registers.msr.html new file mode 100644 index 00000000..ae36d9f4 --- /dev/null +++ b/modules/chipsec.cfg.parsers.registers.msr.html @@ -0,0 +1,133 @@ + + + + + + + + chipsec.cfg.parsers.registers.msr module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.registers.msr module¶

    +

    MSR Register configuration parser and accessor.

    +

    This module provides MSRRegisters class for parsing and accessing Model Specific Registers (MSRs) +in the CHIPSEC framework. MSR registers provide access to processor-specific configuration and +control settings.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.registers.pci.html b/modules/chipsec.cfg.parsers.registers.pci.html new file mode 100644 index 00000000..ed7e53dd --- /dev/null +++ b/modules/chipsec.cfg.parsers.registers.pci.html @@ -0,0 +1,131 @@ + + + + + + + + chipsec.cfg.parsers.registers.pci module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.registers.pci module¶

    +

    PCI Register Configuration Helper

    +

    Provides PCI configuration space register-specific functionality.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.cfg.parsers.registers.simple.html b/modules/chipsec.cfg.parsers.registers.simple.html new file mode 100644 index 00000000..bede4e2f --- /dev/null +++ b/modules/chipsec.cfg.parsers.registers.simple.html @@ -0,0 +1,133 @@ + + + + + + + + chipsec.cfg.parsers.registers.simple module — CHIPSEC documentation + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.cfg.parsers.registers.simple module¶

    +

    Simple in-memory register.

    +

    Provides a register object backed solely by an in-memory value. Useful for +decoding raw values (e.g. fields read from a flash descriptor or a buffer) +into named bitfields without any hardware access.

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.fuzzing.html b/modules/chipsec.fuzzing.html index 28fd5b5e..b5efbe7c 100644 --- a/modules/chipsec.fuzzing.html +++ b/modules/chipsec.fuzzing.html @@ -153,7 +153,7 @@

    Navigation

    diff --git a/modules/chipsec.fuzzing.primitives.html b/modules/chipsec.fuzzing.primitives.html index 0065c115..31bfeeb6 100644 --- a/modules/chipsec.fuzzing.primitives.html +++ b/modules/chipsec.fuzzing.primitives.html @@ -150,7 +150,7 @@

    Navigation

    diff --git a/modules/chipsec.hal.amd.cpu.html b/modules/chipsec.hal.amd.cpu.html new file mode 100644 index 00000000..45e2345a --- /dev/null +++ b/modules/chipsec.hal.amd.cpu.html @@ -0,0 +1,160 @@ + + + + + + + + chipsec.hal.amd.cpu module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.amd.cpu module¶

    +

    CPU related functionality

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.amd.html b/modules/chipsec.hal.amd.html new file mode 100644 index 00000000..1985119f --- /dev/null +++ b/modules/chipsec.hal.amd.html @@ -0,0 +1,163 @@ + + + + + + + + chipsec.hal.amd package — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.amd package¶

    +
    + +
    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.amd.psp.html b/modules/chipsec.hal.amd.psp.html new file mode 100644 index 00000000..9f9a850a --- /dev/null +++ b/modules/chipsec.hal.amd.psp.html @@ -0,0 +1,159 @@ + + + + + + + + chipsec.hal.amd.psp module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.amd.psp module¶

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.acpi.html b/modules/chipsec.hal.common.acpi.html new file mode 100644 index 00000000..006cb145 --- /dev/null +++ b/modules/chipsec.hal.common.acpi.html @@ -0,0 +1,160 @@ + + + + + + + + chipsec.hal.common.acpi module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.acpi module¶

    +

    HAL component providing access to and decoding of ACPI tables

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.cmos.html b/modules/chipsec.hal.common.cmos.html new file mode 100644 index 00000000..8af03bbb --- /dev/null +++ b/modules/chipsec.hal.common.cmos.html @@ -0,0 +1,172 @@ + + + + + + + + chipsec.hal.common.cmos module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.cmos module¶

    +

    CMOS memory specific functions (dump, read/write)

    +
    +
    usage:
    >>> cmos.dump_low()
+>>> cmos.dump_high()
+>>> cmos.dump()
+>>> cmos.read_cmos_low( offset )
+>>> cmos.write_cmos_low( offset, value )
+>>> cmos.read_cmos_high( offset )
+>>> cmos.write_cmos_high( offset, value )
+
    +
    +
    +
    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.cpuid.html b/modules/chipsec.hal.common.cpuid.html new file mode 100644 index 00000000..0a75d171 --- /dev/null +++ b/modules/chipsec.hal.common.cpuid.html @@ -0,0 +1,166 @@ + + + + + + + + chipsec.hal.common.cpuid module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.cpuid module¶

    +

    CPUID information

    +
    +
    usage:
    >>> cpuid(0)
+
    +
    +
    +
    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.ec.html b/modules/chipsec.hal.common.ec.html new file mode 100644 index 00000000..3553f776 --- /dev/null +++ b/modules/chipsec.hal.common.ec.html @@ -0,0 +1,172 @@ + + + + + + + + chipsec.hal.common.ec module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.ec module¶

    +

    Access to Embedded Controller (EC)

    +

    Usage:

    +
    >>> write_command( command )
+>>> write_data( data )
+>>> read_data()
+>>> read_memory( offset )
+>>> write_memory( offset, data )
+>>> read_memory_extended( word_offset )
+>>> write_memory_extended( word_offset, data )
+>>> read_range( start_offset, size )
+>>> write_range( start_offset, buffer )
+
    +
    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.html b/modules/chipsec.hal.common.html new file mode 100644 index 00000000..0ea9d805 --- /dev/null +++ b/modules/chipsec.hal.common.html @@ -0,0 +1,182 @@ + + + + + + + + chipsec.hal.common package — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common package¶

    +
    + +
    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.interrupts.html b/modules/chipsec.hal.common.interrupts.html new file mode 100644 index 00000000..8b6e7065 --- /dev/null +++ b/modules/chipsec.hal.common.interrupts.html @@ -0,0 +1,168 @@ + + + + + + + + chipsec.hal.common.interrupts module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.interrupts module¶

    +

    Functionality encapsulating interrupt generation +CPU Interrupts specific functions (SMI, NMI)

    +
    +
    usage:
    >>> send_SMI_APMC( 0xDE )
+>>> send_NMI()
+
    +
    +
    +
    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.io.html b/modules/chipsec.hal.common.io.html new file mode 100644 index 00000000..ff932c9f --- /dev/null +++ b/modules/chipsec.hal.common.io.html @@ -0,0 +1,175 @@ + + + + + + + + chipsec.hal.common.io module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.io module¶

    +

    Access to Port I/O

    +
    +
    usage:
    >>> read(0x61, 1)
+>>> read_port_byte(0x61)
+>>> read_port_word(0x61)
+>>> read_port_dword(0x61)
+>>> read_range(0x71, 0x4, 1)
+>>> dump_range(0x71, 0x4, 1)
+>>> write(0x71, 0, 1)
+>>> write_port_byte(0x61, 0xAA)
+>>> write_port_word(0x61, 0xAAAA)
+>>> write_port_dword(0x61, 0xAAAAAAAA)
+
    +
    +
    +
    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.iobar.html b/modules/chipsec.hal.common.iobar.html new file mode 100644 index 00000000..13f4839d --- /dev/null +++ b/modules/chipsec.hal.common.iobar.html @@ -0,0 +1,169 @@ + + + + + + + + chipsec.hal.common.iobar module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.iobar module¶

    +

    I/O BAR access (dump, read/write)

    +
    +
    usage:
    >>> get_IO_BAR_base_address( bar_name )
+>>> read_IO_BAR_reg( bar_name, offset, size )
+>>> write_IO_BAR_reg( bar_name, offset, size, value )
+>>> dump_IO_BAR( bar_name )
+
    +
    +
    +
    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.iommu.html b/modules/chipsec.hal.common.iommu.html new file mode 100644 index 00000000..51394472 --- /dev/null +++ b/modules/chipsec.hal.common.iommu.html @@ -0,0 +1,160 @@ + + + + + + + + chipsec.hal.common.iommu module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.iommu module¶

    +

    Access to IOMMU engines - uses DMAR table for dynamic VT-d engine discovery

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.locks.html b/modules/chipsec.hal.common.locks.html new file mode 100644 index 00000000..b15245d3 --- /dev/null +++ b/modules/chipsec.hal.common.locks.html @@ -0,0 +1,159 @@ + + + + + + + + chipsec.hal.common.locks module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.locks module¶

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.memrange.html b/modules/chipsec.hal.common.memrange.html new file mode 100644 index 00000000..522a403d --- /dev/null +++ b/modules/chipsec.hal.common.memrange.html @@ -0,0 +1,169 @@ + + + + + + + + chipsec.hal.common.memrange module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.memrange module¶

    +

    Access to physical memory

    +
    +
    usage:
    >>> read_physical_mem( 0xf0000, 0x100 )
+>>> write_physical_mem( 0xf0000, 0x100, buffer )
+>>> write_physical_mem_dowrd( 0xf0000, 0xdeadbeef )
+>>> read_physical_mem_dowrd( 0xfed40000 )
+
    +
    +
    +
    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.mmio.html b/modules/chipsec.hal.common.mmio.html new file mode 100644 index 00000000..46809997 --- /dev/null +++ b/modules/chipsec.hal.common.mmio.html @@ -0,0 +1,179 @@ + + + + + + + + chipsec.hal.common.mmio module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.mmio module¶

    +

    Access to MMIO (Memory Mapped IO) BARs and Memory-Mapped PCI Configuration Space (MMCFG)

    +
    +
    usage:
    >>> read_MMIO_reg(bar_base, 0x0, 4)
+>>> write_MMIO_reg(bar_base, 0x0, 0xFFFFFFFF, 4)
+>>> read_MMIO(bar_base, 0x1000)
+>>> dump_MMIO(bar_base, 0x1000)
+
    +
    +

    Access MMIO by BAR name:

    +
    >>> read_MMIO_BAR_reg('MCHBAR', 0x0, 4)
+>>> write_MMIO_BAR_reg('MCHBAR', 0x0, 0xFFFFFFFF, 4)
+>>> get_MMIO_BAR_base_address('8086.HOSTCTL.MCHBAR')
+>>> is_MMIO_BAR_enabled('8086.HOSTCTL.MCHBAR')
+>>> is_MMIO_BAR_programmed('8086.HOSTCTL.MCHBAR')
+>>> dump_MMIO_BAR('8086.HOSTCTL.MCHBAR')
+>>> list_MMIO_BARs()
+
    +
    +
    +
    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.msr.html b/modules/chipsec.hal.common.msr.html new file mode 100644 index 00000000..d965fe64 --- /dev/null +++ b/modules/chipsec.hal.common.msr.html @@ -0,0 +1,175 @@ + + + + + + + + chipsec.hal.common.msr module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.msr module¶

    +

    Access to CPU resources (for each CPU thread): Model Specific Registers (MSR), IDT/GDT

    +
    +
    usage:
    >>> read( 0x8B )
+>>> write( 0x79, 0x12345678 )
+>>> get_cpu_thread_count()
+>>> get_IDTR( 0 )
+>>> get_GDTR( 0 )
+>>> dump_Descriptor_Table( 0, DESCRIPTOR_TABLE_CODE_IDTR )
+>>> IDT( 0 )
+>>> GDT( 0 )
+>>> IDT_all()
+>>> GDT_all()
+
    +
    +
    +
    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.pci.html b/modules/chipsec.hal.common.pci.html new file mode 100644 index 00000000..76741088 --- /dev/null +++ b/modules/chipsec.hal.common.pci.html @@ -0,0 +1,177 @@ + + + + + + + + chipsec.hal.common.pci module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.pci module¶

    +

    Access to of PCI/PCIe device hierarchy +- enumerating PCI/PCIe devices +- read/write access to PCI configuration headers/registers +- enumerating PCI expansion (option) ROMs +- identifying PCI/PCIe devices MMIO and I/O ranges (BARs)

    +
    +
    usage:
    >>> self.cs.hals.pci.read_byte( 0, 0, 0, 0x88 )
+>>> self.cs.hals.pci.write_byte( 0, 0, 0, 0x88, 0x1A )
+>>> self.cs.hals.pci.enumerate_devices()
+>>> self.cs.hals.pci.enumerate_xroms()
+>>> self.cs.hals.pci.find_XROM( 2, 0, 0, True, True, 0xFED00000 )
+>>> self.cs.hals.pci.get_device_bars( 2, 0, 0 )
+>>> self.cs.hals.pci.get_DIDVID( 2, 0, 0 )
+>>> self.cs.hals.pci.is_enabled( 2, 0, 0 )
+
    +
    +
    +
    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.physmem.html b/modules/chipsec.hal.common.physmem.html new file mode 100644 index 00000000..a370f7ec --- /dev/null +++ b/modules/chipsec.hal.common.physmem.html @@ -0,0 +1,169 @@ + + + + + + + + chipsec.hal.common.physmem module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.physmem module¶

    +

    Access to physical memory

    +
    +
    usage:
    >>> read_physical_mem( 0xf0000, 0x100 )
+>>> write_physical_mem( 0xf0000, 0x100, buffer )
+>>> write_physical_mem_dowrd( 0xf0000, 0xdeadbeef )
+>>> read_physical_mem_dowrd( 0xfed40000 )
+
    +
    +
    +
    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.smbios.html b/modules/chipsec.hal.common.smbios.html new file mode 100644 index 00000000..5aeededc --- /dev/null +++ b/modules/chipsec.hal.common.smbios.html @@ -0,0 +1,160 @@ + + + + + + + + chipsec.hal.common.smbios module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.smbios module¶

    +

    HAL component providing access to and decoding of SMBIOS structures

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.smbus.html b/modules/chipsec.hal.common.smbus.html new file mode 100644 index 00000000..7abf049d --- /dev/null +++ b/modules/chipsec.hal.common.smbus.html @@ -0,0 +1,160 @@ + + + + + + + + chipsec.hal.common.smbus module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.smbus module¶

    +

    Access to SMBus Controller

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.spd.html b/modules/chipsec.hal.common.spd.html new file mode 100644 index 00000000..af1b7f8f --- /dev/null +++ b/modules/chipsec.hal.common.spd.html @@ -0,0 +1,169 @@ + + + + + + + + chipsec.hal.common.spd module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.spd module¶

    +

    Access to Memory (DRAM) Serial Presence Detect (SPD) EEPROM

    +

    References:

    +

    http://www.jedec.org/sites/default/files/docs/4_01_02R19.pdf +http://www.jedec.org/sites/default/files/docs/4_01_02_10R17.pdf +http://www.jedec.org/sites/default/files/docs/4_01_02_11R24.pdf +http://www.jedec.org/sites/default/files/docs/4_01_02_12R23A.pdf +https://www.simmtester.com/News/PublicationArticle/184 +https://www.simmtester.com/News/PublicationArticle/153 +https://www.simmtester.com/News/PublicationArticle/101 +http://en.wikipedia.org/wiki/Serial_presence_detect

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.tpm.html b/modules/chipsec.hal.common.tpm.html new file mode 100644 index 00000000..bffc90af --- /dev/null +++ b/modules/chipsec.hal.common.tpm.html @@ -0,0 +1,161 @@ + + + + + + + + chipsec.hal.common.tpm module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.tpm module¶

    +

    Trusted Platform Module (TPM) HAL component

    +

    https://trustedcomputinggroup.org

    +
    + + +
    +
    +
    +
    + +
    +
    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.uefi.html b/modules/chipsec.hal.common.uefi.html new file mode 100644 index 00000000..3e84560f --- /dev/null +++ b/modules/chipsec.hal.common.uefi.html @@ -0,0 +1,160 @@ + + + + + + + + chipsec.hal.common.uefi module — CHIPSEC documentation + + + + + + + + + + + + + + + +
    +
    +
    +
    + +
    +

    chipsec.hal.common.uefi module¶

    +

    Main UEFI component using platform specific and common UEFI functionality

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    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.virtmem.html b/modules/chipsec.hal.common.virtmem.html new file mode 100644 index 00000000..18d1be3e --- /dev/null +++ b/modules/chipsec.hal.common.virtmem.html @@ -0,0 +1,169 @@ + + + + + + + + chipsec.hal.common.virtmem module — CHIPSEC documentation + + + + + + + + + + + + + + + +
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    chipsec.hal.common.virtmem module¶

    +

    Access to virtual memory

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    usage:
    >>> read_virtual_mem( 0xf0000, 0x100 )
+>>> write_virtual_mem( 0xf0000, 0x100, buffer )
+>>> write_virtual_mem_dowrd( 0xf0000, 0xdeadbeef )
+>>> read_virtual_mem_dowrd( 0xfed40000 )
+
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    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.common.vmm.html b/modules/chipsec.hal.common.vmm.html new file mode 100644 index 00000000..e04ee77c --- /dev/null +++ b/modules/chipsec.hal.common.vmm.html @@ -0,0 +1,164 @@ + + + + + + + + chipsec.hal.common.vmm module — CHIPSEC documentation + + + + + + + + + + + + + + + +
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    chipsec.hal.common.vmm module¶

    +

    VMM specific functionality +1. Hypervisor hypercall interfaces +2. Second-level Address Translation (SLAT) +3. VirtIO devices +4. …

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    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.hal_base.html b/modules/chipsec.hal.hal_base.html index d13d36fe..9c2e2165 100644 --- a/modules/chipsec.hal.hal_base.html +++ b/modules/chipsec.hal.hal_base.html @@ -17,7 +17,7 @@ - + diff --git a/modules/chipsec.hal.html b/modules/chipsec.hal.html index 7e8e9a90..ae6f4164 100644 --- a/modules/chipsec.hal.html +++ b/modules/chipsec.hal.html @@ -16,7 +16,7 @@ - + diff --git a/modules/chipsec.hal.intel.cpu.html b/modules/chipsec.hal.intel.cpu.html new file mode 100644 index 00000000..99318804 --- /dev/null +++ b/modules/chipsec.hal.intel.cpu.html @@ -0,0 +1,160 @@ + + + + + + + + chipsec.hal.intel.cpu module — CHIPSEC documentation + + + + + + + + + + + + + + + +
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    chipsec.hal.intel.cpu module¶

    +

    CPU related functionality

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    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.intel.html b/modules/chipsec.hal.intel.html new file mode 100644 index 00000000..264b4343 --- /dev/null +++ b/modules/chipsec.hal.intel.html @@ -0,0 +1,169 @@ + + + + + + + + chipsec.hal.intel package — CHIPSEC documentation + + + + + + + + + + + + + + + +
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    chipsec.hal.intel package¶

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    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.intel.igd.html b/modules/chipsec.hal.intel.igd.html new file mode 100644 index 00000000..31875cbb --- /dev/null +++ b/modules/chipsec.hal.intel.igd.html @@ -0,0 +1,166 @@ + + + + + + + + chipsec.hal.intel.igd module — CHIPSEC documentation + + + + + + + + + + + + + + + +
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    chipsec.hal.intel.igd module¶

    +

    Working with Intel processor Integrated Graphics Device (IGD)

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    usage:
    >>> gfx_aperture_dma_read(0x80000000, 0x100)
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    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.intel.mm_msgbus.html b/modules/chipsec.hal.intel.mm_msgbus.html new file mode 100644 index 00000000..8ad11fc1 --- /dev/null +++ b/modules/chipsec.hal.intel.mm_msgbus.html @@ -0,0 +1,173 @@ + + + + + + + + chipsec.hal.intel.mm_msgbus module — CHIPSEC documentation + + + + + + + + + + + + + + + +
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    chipsec.hal.intel.mm_msgbus module¶

    +

    Access to message bus (IOSF sideband) interface registers on Intel SoCs

    +

    References:

    + +
    +
    usage:
    >>> get_sbreg_base_address( )
+>>> read( port, register )
+>>> write( port, register, data )
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    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.intel.mmcfg.html b/modules/chipsec.hal.intel.mmcfg.html new file mode 100644 index 00000000..e508a366 --- /dev/null +++ b/modules/chipsec.hal.intel.mmcfg.html @@ -0,0 +1,169 @@ + + + + + + + + chipsec.hal.intel.mmcfg module — CHIPSEC documentation + + + + + + + + + + + + + + + +
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    chipsec.hal.intel.mmcfg module¶

    +

    Access to MMIO (Memory Mapped IO) BARs and Memory-Mapped PCI Configuration Space (MMCFG)

    +
    +
    usage:

    Access Memory Mapped Config Space:

    +
    >>> get_MMCFG_base_address(cs)
+>>> read_mmcfg_reg(cs, 0, 0, 0, 0x10, 4)
+>>> read_mmcfg_reg(cs, 0, 0, 0, 0x10, 4, 0xFFFFFFFF)
+
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    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.intel.msgbus.html b/modules/chipsec.hal.intel.msgbus.html new file mode 100644 index 00000000..3ebbb715 --- /dev/null +++ b/modules/chipsec.hal.intel.msgbus.html @@ -0,0 +1,175 @@ + + + + + + + + chipsec.hal.intel.msgbus module — CHIPSEC documentation + + + + + + + + + + + + + + + +
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    chipsec.hal.intel.msgbus module¶

    +

    Access to message bus (IOSF sideband) interface registers on Intel SoCs

    +

    References:

    + +
    +
    usage:
    >>> msgbus_reg_read( port, register )
+>>> msgbus_reg_write( port, register, data )
+>>> msgbus_read_message( port, register, opcode )
+>>> msgbus_write_message( port, register, opcode, data )
+>>> msgbus_send_message( port, register, opcode, data )
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    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.intel.spi.html b/modules/chipsec.hal.intel.spi.html new file mode 100644 index 00000000..26601127 --- /dev/null +++ b/modules/chipsec.hal.intel.spi.html @@ -0,0 +1,181 @@ + + + + + + + + chipsec.hal.intel.spi module — CHIPSEC documentation + + + + + + + + + + + + + + + +
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    chipsec.hal.intel.spi module¶

    +

    Access to SPI Flash parts

    +
    +
    usage:
    >>> read_spi( spi_fla, length )
+>>> write_spi( spi_fla, buf )
+>>> erase_spi_block( spi_fla )
+>>> get_SPI_JEDEC_ID()
+>>> get_SPI_JEDEC_ID_decoded()
+
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    +
    +

    Note

    +

    !! IMPORTANT: +Size of the data chunk used in SPI read cycle (in bytes) +default = maximum 64 bytes (remainder is read in 4 byte chunks)

    +

    If you want to change logic to read SPI Flash in 4 byte chunks: +SPI_READ_WRITE_MAX_DBC = 4

    +

    @TBD: SPI write cycles operate on 4 byte chunks (not optimized yet)

    +

    Approximate performance (on 2-core SMT Intel Core i5-4300U (Haswell) CPU 1.9GHz): +SPI read: ~7 sec per 1MB (with DBC=64)

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    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.intel.spi_descriptor.html b/modules/chipsec.hal.intel.spi_descriptor.html new file mode 100644 index 00000000..ec36fdc3 --- /dev/null +++ b/modules/chipsec.hal.intel.spi_descriptor.html @@ -0,0 +1,159 @@ + + + + + + + + chipsec.hal.intel.spi_descriptor module — CHIPSEC documentation + + + + + + + + + + + + + + + +
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    chipsec.hal.intel.spi_descriptor module¶

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    + + + + \ No newline at end of file diff --git a/modules/chipsec.hal.intel.ucode.html b/modules/chipsec.hal.intel.ucode.html new file mode 100644 index 00000000..4e34d878 --- /dev/null +++ b/modules/chipsec.hal.intel.ucode.html @@ -0,0 +1,169 @@ + + + + + + + + chipsec.hal.intel.ucode module — CHIPSEC documentation + + + + + + + + + + + + + + + +
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    chipsec.hal.intel.ucode module¶

    +

    Microcode update specific functionality (for each CPU thread)

    +
    +
    usage:
    >>> ucode_update_id( 0 )
+>>> load_ucode_update( 0, ucode_buf )
+>>> update_ucode_all_cpus( 'ucode.pdb' )
+>>> dump_ucode_update_header( 'ucode.pdb' )
+
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    + + + + \ No newline at end of file diff --git a/modules/chipsec.helper.basehelper.html b/modules/chipsec.helper.basehelper.html index 228cf538..05452954 100644 --- a/modules/chipsec.helper.basehelper.html +++ b/modules/chipsec.helper.basehelper.html @@ -150,7 +150,7 @@

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    chipsec.helper packagechipsec.helper.linuxnative.linuxnativehelper module +
  • chipsec.helper.record package +
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  • chipsec.helper.replay package +
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