RISC-V64 qemu_virt example support RVV Extension;

Author: goodnorning

ports/risc-v64/gnu/example_build/qemu_virt/csr.h

@@ -21,6 +21,7 @@
 #define MSTATUS_MIE 		(1L << 3)    // machine-mode interrupt enable.
 #define MSTATUS_MPIE		(1L << 7)
 #define MSTATUS_FS		(1L << 13)
+#define MSTATUS_VS    (1L << 9)
 
 // Machine-mode Interrupt Enable
 #define MIE_MTIE		(1L << 7)  

ports/risc-v64/gnu/example_build/qemu_virt/demo_threadx.c

@@ -4,8 +4,13 @@
 
 #include "tx_api.h"
 #include "uart.h"
+#if defined(__riscv_vector)
+#define DEMO_STACK_SIZE         (1024 + 16448)      /* 16448 for RVV Extension */
+#define DEMO_BYTE_POOL_SIZE     (9180 + 148032)     /* 148032 for RVV Extension */
+#else
 #define DEMO_STACK_SIZE         1024
 #define DEMO_BYTE_POOL_SIZE     9180
+#endif
 #define DEMO_BLOCK_POOL_SIZE    100
 #define DEMO_QUEUE_SIZE         100
 

ports/risc-v64/gnu/example_build/qemu_virt/entry.s

@@ -41,7 +41,7 @@ _start:
 	li x30, 0
 	li x31, 0
 	la t0, _sysstack_start
-	li t1, 0x1000
+	li t1, 0x5000
 	add sp, t0, t1
 	la  t0, _bss_start
 	la  t1, _bss_end

ports/risc-v64/gnu/example_build/qemu_virt/link.lds

@@ -41,7 +41,7 @@ SECTIONS
   .stack : {
     . = ALIGN(4096);
     _sysstack_start = .;
-    . += 0x1000;
+    . += 0x5000;
     _sysstack_end = .;
   }
 

ports/risc-v64/gnu/example_build/qemu_virt/tx_initialize_low_level.S

@@ -70,6 +70,13 @@
 #else
 	addi sp, sp, -256                 // Allocate space for all registers - without floating point enabled (32*8)
 #endif
+#if defined(__riscv_vector)
+    /* Allocate space for vector registers */
+    csrr    t4, vlenb
+    slli    t4, t4, 5
+    addi    t4, t4, 5*8
+    sub     sp, sp, t4
+#endif
 
 	sd   x1, 224(sp)                  // Store RA (28*8 = 224, because call will override ra [ra is a callee register in riscv])
 
@@ -153,6 +160,10 @@ _tx_initialize_low_level:
     li      t0, MSTATUS_FS
     csrrs   zero, mstatus, t0			           // set MSTATUS_FS bit to open f/d isa in riscv
     fscsr   x0
+#endif
+#ifdef __riscv_vector
+    li      t0, MSTATUS_VS
+    csrrs   zero, mstatus, t0			           // set MSTATUS_VS bit to open vector isa in riscv
 #endif
     addi    sp, sp, -8
     sd	    ra, 0(sp)