Prerequisites
Please make sure to check off these prerequisites before submitting a bug report.
Quick summary
C/C++ driver for HLS4ML designs with AXI streaming interface.
Details
Hi all. I have a simple MNIST design for which I have the HLS code generated by HLS4ML using the Vitis backend. I manually ported the generated HLS code into Vitis_HLS (2021) for C synthesis and used Vivado (2021) to create the system. My interfaces are AXI streaming. When writing the C/C++ driver to exercise the IP, the execution hangs while waiting for DMA data in the Device -> DMA direction. I know the HLS code is correct and the block design is also correct as I have tested the block design with a similar HLS IP that reads and writes to memory using DMA and that works. Is there a sample C/C++ driver that I can compare against to check if I am doing something wrong? I have not tried the python driver as I am not deploying my model on a pynq board.
Steps to Reproduce
Add what needs to be done to reproduce the bug. Add commented code examples and make sure to include the original model files / code, and the commit hash you are working on.
- Clone the hls4ml repository
- Checkout the master branch, with commit hash: [...]
- Run conversion [...] on model file with code [...]
- [Further steps ...]
Expected behavior
Expect the memory to be updated by device.
Actual behavior
Describe what actually happens instead.
Optional
Possible fix
If you already know where the issue stems from, or you have a hint please let us know.
Additional context
Add any other context about the problem here.
Prerequisites
Please make sure to check off these prerequisites before submitting a bug report.
Quick summary
C/C++ driver for HLS4ML designs with AXI streaming interface.
Details
Hi all. I have a simple MNIST design for which I have the HLS code generated by HLS4ML using the Vitis backend. I manually ported the generated HLS code into Vitis_HLS (2021) for C synthesis and used Vivado (2021) to create the system. My interfaces are AXI streaming. When writing the C/C++ driver to exercise the IP, the execution hangs while waiting for DMA data in the Device -> DMA direction. I know the HLS code is correct and the block design is also correct as I have tested the block design with a similar HLS IP that reads and writes to memory using DMA and that works. Is there a sample C/C++ driver that I can compare against to check if I am doing something wrong? I have not tried the python driver as I am not deploying my model on a pynq board.
Steps to Reproduce
Add what needs to be done to reproduce the bug. Add commented code examples and make sure to include the original model files / code, and the commit hash you are working on.
Expected behavior
Expect the memory to be updated by device.
Actual behavior
Describe what actually happens instead.
Optional
Possible fix
If you already know where the issue stems from, or you have a hint please let us know.
Additional context
Add any other context about the problem here.