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Verilog support
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‎README.md‎

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@@ -87,6 +87,7 @@ Other languages are supported via extensions:
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[TCL](src/lang-tcl.js);
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[LaTeX](src/lang-tex.js);
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[Visual Basic](src/lang-vb.js);
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[Verilog](src/lang-verilog.js);
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[VHDL](src/lang-vhdl.js);
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[Wiki](src/lang-wiki.js);
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[XQ](src/lang-xq.js);

‎src/lang-verilog.js‎

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/**
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* @license
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* Copyright (C) 2020 wmin0@hotmail.com
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @fileoverview
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* Registers a language handler for Verilog.
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*
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* Based on the lexical grammar and keywords at
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* https://www.verilog.com/VerilogBNF.html#REF170
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*
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* @author wmin0@hotmail.com
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*/
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PR['registerLangHandler'](
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PR['createSimpleLexer'](
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[
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[PR['PR_PLAIN'], /^[\t\n\r \xA0]+/, null, '\t\n\r \xA0'],
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[PR['PR_PUNCTUATION'], /^[.!%&()*+,\-;<=>?\[\\\]^{|}:@#]+/, null, '.!%&()*+,-;<=>?[\\]^{|}:@#']
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],
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[
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[PR['PR_KEYWORD'], /^(?:\$hold|\$period|\$recovery|\$setup|\$setuphold\$skew|\$width|always|assign|begin|case|casex|casez|default|defparam|disable|else|end|endcase|endfunction|endmodule|endprimitive|endspecify|endtable|endtask|for|force|forever|fork|function|if|initial|join|macromodule|module|negedge|parameter|posedge|primitive|release|repeat|specify|specparam|table|task|wait|while)(?=[^\w-]|$)/i],
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[PR['PR_TYPE'], /^(?:and|buf|bufif0|bufif1|cmos|event|inout|input|integer|nand|nmos|nor|not|notif0|notif1|or|output|pmos|pulldown|pullup|rcmos|real|reg|rnmos|rpmos|rtran|rtranif0|rtranif1|scalared|supply0|supply1|time|tran|tranif0|tranif1|tri|tri0|tri1|triand|trior|trireg|vectored|wand|wire|wor|xnor|xor)(?=[^\w-]|$)/i],
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[PR['PR_TAG'], /^(?:highz0|highz1|large|medium|pull0|pull1|small|strong0|strong1|supply0|supply1|weak0|weak1)(?=[^\w-]|$)/i],
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// number
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[PR['PR_LITERAL'], /^(?:[0-9][0-9_]*(?:\.[0-9_]+)?(?:e[0-9_]+)?)|(?:(?:[0-9][0-9_]*)?'[bodh][0-9a-fA-FxXzZ?]+)/i],
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// edge
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[PR['PR_LITERAL'], /^(?:01|0x|10|1x|x0|x1)(?=[^\w-]|$)/i],
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// string
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[PR['PR_STRING'], /^"([^"\\]|\\[\s\S])*"/],
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// double slash comments
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[PR['PR_COMMENT'], /^\/\/.*/],
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// slash star comments and documentation
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[PR['PR_COMMENT'], /^\/\*[\s\S]*?(?:\*\/|$)/]
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]),
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['verilog', 'v']);

‎tests/prettify_test_2.html‎

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'lang-r.js',
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'lang-tcl.js',
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'lang-tex.js',
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'lang-verilog.js',
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'lang-xq.js'
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];
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var styles = [
@@ -1201,5 +1202,76 @@ <h1>Kotlin</h1>
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fun Boolean?.getOrThrow(): Boolean = this ?: throw Exception()
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</pre>
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<h1>Verilog</h1>
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<pre class="prettyprint lang-verilog" id="verilog">
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/*
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* Multiline
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* comment
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*/
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a = "123"
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nor ( small )
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nor (highz1, strong0)
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//-----------------------------------------------------
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// Design Name : cam
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// File Name : cam.v
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// Function : CAM
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module cam (
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clk , // Cam clock
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cam_enable , // Cam enable
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cam_data_in , // Cam data to match
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cam_hit_out , // Cam match has happened
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cam_addr_out // Cam output address
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);
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parameter ADDR_WIDTH = 8;
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parameter DEPTH = 1 &lt;&lt; ADDR_WIDTH;
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//------------Input Ports--------------
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input clk;
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input cam_enable;
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input [DEPTH-1:0] cam_data_in;
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//----------Output Ports--------------
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output cam_hit_out;
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output [ADDR_WIDTH-1:0] cam_addr_out;
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//------------Internal Variables--------
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reg [ADDR_WIDTH-1:0] cam_addr_out;
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reg cam_hit_out;
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reg [ADDR_WIDTH-1:0] cam_addr_combo;
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reg cam_hit_combo;
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reg found_match;
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integer i;
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//-------------Code Starts Here-------
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always @(cam_data_in) begin
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cam_addr_combo = {ADDR_WIDTH{1'b0}};
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found_match = 1'b0;
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cam_hit_combo = 1'b0;
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for (i=0; i&lt;DEPTH; i=i+1) begin
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if (cam_data_in[i] && !found_match) begin
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found_match = 1'b1;
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cam_hit_combo = 1'b1;
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cam_addr_combo = i;
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end else begin
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found_match = found_match;
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cam_hit_combo = cam_hit_combo;
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cam_addr_combo = cam_addr_combo;
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end
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end
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end
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// Register the outputs
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always @(posedge clk) begin
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if (cam_enable) begin
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cam_hit_out &lt;= cam_hit_combo;
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cam_addr_out &lt;= cam_addr_combo;
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end else begin
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cam_hit_out &lt;= 1'b0;
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cam_addr_out &lt;= {ADDR_WIDTH{1'b0}};
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end
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end
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endmodule
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</pre>
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</body>
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</html>

‎tests/prettify_test_2.js‎

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'\n' +
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'`END`KWDfun`END`PLN `END`TYPBoolean`END`PUN?.`END`PLNgetOrThrow`END`PUN():`END`PLN `END`TYPBoolean`END`PLN `END`PUN=`END`PLN `END`KWDthis`END`PLN `END`PUN?:`END`PLN `END`KWDthrow`END`PLN `END`TYPException`END`PUN()`END'
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),
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verilog: (
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'`COM/*\n' +
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' * Multiline\n' +
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' * comment\n' +
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' */`END`PLN\n' +
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'a `END`PUN=`END`PLN `END`STR"123"`END`PLN\n' +
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'`END<span class="typ">nor`END`PLN `END`PUN(`END`PLN `END`TAGsmall`END`PLN `END`PUN)`END`PLN\n' +
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'`END<span class="typ">nor`END`PLN `END`PUN(`END`TAGhighz1`END`PUN,`END`PLN `END`TAGstrong0`END`PUN)`END`PLN\n' +
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'`END`COM//-----------------------------------------------------`END`PLN\n' +
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'`END`COM// Design Name : cam`END`PLN\n' +
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'`END`COM// File Name : cam.v`END`PLN\n' +
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'`END`COM// Function : CAM`END`PLN\n' +
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'`END`COM// Coder : Deepak Kumar Tala`END`PLN\n' +
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'`END`COM//-----------------------------------------------------`END`PLN\n' +
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'`END`KWDmodule`END`PLN cam `END`PUN(`END`PLN\n' +
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'clk `END`PUN,`END`PLN `END`COM// Cam clock`END`PLN\n' +
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'cam_enable `END`PUN,`END`PLN `END`COM// Cam enable`END`PLN\n' +
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'cam_data_in `END`PUN,`END`PLN `END`COM// Cam data to match`END`PLN\n' +
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'cam_hit_out `END`PUN,`END`PLN `END`COM// Cam match has happened`END`PLN\n' +
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'cam_addr_out `END`COM// Cam output address`END`PLN\n' +
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'`END`PUN);`END`PLN\n' +
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'\n' +
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'`END`KWDparameter`END`PLN ADDR_WIDTH `END`PUN=`END`PLN `END`LIT8`END`PUN;`END`PLN\n' +
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'`END`KWDparameter`END`PLN DEPTH `END`PUN=`END`PLN `END`LIT1`END`PLN `END`PUN&lt;&lt;`END`PLN ADDR_WIDTH`END`PUN;`END`PLN\n' +
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'`END`COM//------------Input Ports--------------`END`PLN\n' +
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'`END`TYPinput`END`PLN clk`END`PUN;`END`PLN\n' +
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'`END`TYPinput`END`PLN cam_enable`END`PUN;`END`PLN\n' +
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'`END`TYPinput`END`PLN `END`PUN[`END`PLNDEPTH`END`PUN-`END`LIT1`END`PUN:`END`LIT0`END`PUN]`END`PLN cam_data_in`END`PUN;`END`PLN\n' +
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'`END`COM//----------Output Ports--------------`END`PLN\n' +
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'`END`TYPoutput`END`PLN cam_hit_out`END`PUN;`END`PLN\n' +
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'`END`TYPoutput`END`PLN `END`PUN[`END`PLNADDR_WIDTH`END`PUN-`END`LIT1`END`PUN:`END`LIT0`END`PUN]`END`PLN cam_addr_out`END`PUN;`END`PLN\n' +
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'`END`COM//------------Internal Variables--------`END`PLN\n' +
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'`END`TYPreg`END`PLN `END`PUN[`END`PLNADDR_WIDTH`END`PUN-`END`LIT1`END`PUN:`END`LIT0`END`PUN]`END`PLN cam_addr_out`END`PUN;`END`PLN\n' +
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'`END`TYPreg`END`PLN cam_hit_out`END`PUN;`END`PLN\n' +
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'`END`TYPreg`END`PLN `END`PUN[`END`PLNADDR_WIDTH`END`PUN-`END`LIT1`END`PUN:`END`LIT0`END`PUN]`END`PLN cam_addr_combo`END`PUN;`END`PLN\n' +
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'`END`TYPreg`END`PLN cam_hit_combo`END`PUN;`END`PLN\n' +
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'`END`TYPreg`END`PLN found_match`END`PUN;`END`PLN\n' +
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'`END`TYPinteger`END`PLN i`END`PUN;`END`PLN\n' +
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'`END`COM//-------------Code Starts Here-------`END`PLN\n' +
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'`END`KWDalways`END`PLN `END`PUN@(`END`PLNcam_data_in`END`PUN)`END`PLN `END`KWDbegin`END`PLN\n' +
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' cam_addr_combo `END`PUN=`END`PLN `END`PUN{`END`PLNADDR_WIDTH`END`PUN{`END`LIT1\'b0`END`PUN}};`END`PLN\n' +
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' found_match `END`PUN=`END`PLN `END`LIT1\'b0`END`PUN;`END`PLN\n' +
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' cam_hit_combo `END`PUN=`END`PLN `END`LIT1\'b0`END`PUN;`END`PLN\n' +
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' `END`KWDfor`END`PLN `END`PUN(`END`PLNi`END`PUN=`END`LIT0`END`PUN;`END`PLN i`END`PUN&lt;`END`PLNDEPTH`END`PUN;`END`PLN i`END`PUN=`END`PLNi`END`PUN+`END`LIT1`END`PUN)`END`PLN `END`KWDbegin`END`PLN\n' +
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' `END`KWDif`END`PLN `END`PUN(`END`PLNcam_data_in`END`PUN[`END`PLNi`END`PUN]`END`PLN `END`PUN&amp;&amp;`END`PLN `END`PUN!`END`PLNfound_match`END`PUN)`END`PLN `END`KWDbegin`END`PLN\n' +
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' found_match `END`PUN=`END`PLN `END`LIT1\'b1`END`PUN;`END`PLN\n' +
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' cam_hit_combo `END`PUN=`END`PLN `END`LIT1\'b1`END`PUN;`END`PLN\n' +
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' cam_addr_combo `END`PUN=`END`PLN i`END`PUN;`END`PLN\n' +
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' `END`KWDend`END`PLN `END`KWDelse`END`PLN `END`KWDbegin`END`PLN\n' +
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' found_match `END`PUN=`END`PLN found_match`END`PUN;`END`PLN\n' +
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' cam_hit_combo `END`PUN=`END`PLN cam_hit_combo`END`PUN;`END`PLN\n' +
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' cam_addr_combo `END`PUN=`END`PLN cam_addr_combo`END`PUN;`END`PLN\n' +
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' `END`KWDend`END`PLN\n' +
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' `END`KWDend`END`PLN\n' +
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'`END`KWDend`END`PLN\n' +
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'\n' +
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'`END`COM// Register the outputs`END`PLN\n' +
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'`END`KWDalways`END`PLN `END`PUN@(`END`KWDposedge`END`PLN clk`END`PUN)`END`PLN `END`KWDbegin`END`PLN\n' +
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' `END`KWDif`END`PLN `END`PUN(`END`PLNcam_enable`END`PUN)`END`PLN `END`KWDbegin`END`PLN\n' +
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' cam_hit_out `END`PUN&lt;=`END`PLN cam_hit_combo`END`PUN;`END`PLN\n' +
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' cam_addr_out `END`PUN&lt;=`END`PLN cam_addr_combo`END`PUN;`END`PLN\n' +
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' `END`KWDend`END`PLN `END`KWDelse`END`PLN `END`KWDbegin`END`PLN\n' +
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' cam_hit_out `END`PUN&lt;=`END`PLN `END`LIT1\'b0`END`PUN;`END`PLN\n' +
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' cam_addr_out `END`PUN&lt;=`END`PLN `END`PUN{`END`PLNADDR_WIDTH`END`PUN{`END`LIT1\'b0`END`PUN}};`END`PLN\n' +
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' `END`KWDend`END`PLN\n' +
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'`END`KWDend`END`PLN\n' +
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'\n' +
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'`END`KWDendmodule`END'
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),
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llvm: (
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'`COM; Declare the string constant as a global constant.`END`PLN\n' +
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'@.str `END`PUN=`END`PLN `END`KWDprivate`END`PLN `END`KWDunnamed_addr`END`PLN `END`KWDconstant`END`PLN `END`PUN[`END`LIT13`END`PLN `END`KWDx`END`PLN `END`KWDi8`END`PUN]`END`PLN `END`KWDc`END`STR"hello world\\0A\\00"`END`PLN\n' +

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