diff --git "a/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\344\270\200.docx" "b/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\344\270\200.docx" new file mode 100644 index 00000000..7a044183 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\344\270\200.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:699fd48dc7a2b5085bbb37cfd0e81e384934509941b74ce87d41e762ea3692ca +size 17935 diff --git "a/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\344\270\211.docx" "b/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\344\270\211.docx" new file mode 100644 index 00000000..993da926 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\344\270\211.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3329b9ae03f4e8f9937a93e8cd95bd5849846039e63624ac92b48e76673be144 +size 21273 diff --git "a/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\344\272\214.docx" "b/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\344\272\214.docx" new file mode 100644 index 00000000..3461befe --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\344\272\214.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f218d07bcb6d52607d5a07d25d4bccb353d467331d5c5d67980237da57e9baa1 +size 29236 diff --git "a/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\344\272\224.docx" "b/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\344\272\224.docx" new file mode 100644 index 00000000..58dc51f2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\344\272\224.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:212a550b7923bcaad81817af3e487ef5a8d00a8ecbea87f189972e1dad577da0 +size 99361 diff --git "a/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\345\205\255.docx" "b/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\345\205\255.docx" new file mode 100644 index 00000000..f0325afa --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\345\205\255.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:4ed4ee9c0cc8d79dcabe3673def0e5a592462d6996d0624ba58fa9118652509a +size 27736 diff --git "a/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\345\233\233.docx" "b/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\345\233\233.docx" new file mode 100644 index 00000000..a07398ee --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DataStructure/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\344\275\234\344\270\232\345\233\233.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ff5cf298481032ef8ff66057e7b7b99ecb1ea43755b5b6ce1be35962770882bf +size 446808 diff --git "a/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/2425\346\231\272\350\203\275\346\234\237\344\270\255.pdf" "b/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/2425\346\231\272\350\203\275\346\234\237\344\270\255.pdf" new file mode 100644 index 00000000..30a2ddd1 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/2425\346\231\272\350\203\275\346\234\237\344\270\255.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/lmh24\346\234\237\344\270\255b\345\215\267.png" "b/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/lmh24\346\234\237\344\270\255b\345\215\267.png" new file mode 100644 index 00000000..0895cad1 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/lmh24\346\234\237\344\270\255b\345\215\267.png" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/lmh24\346\234\237\344\270\255\346\240\267\344\276\213.docx" "b/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/lmh24\346\234\237\344\270\255\346\240\267\344\276\213.docx" new file mode 100644 index 00000000..d4625002 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/lmh24\346\234\237\344\270\255\346\240\267\344\276\213.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:d871872531937f938ebe64557c6678be4e2a2e4a839c74252a3fc67ea0a49dc6 +size 27345 diff --git "a/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/\346\225\260\346\215\256\347\273\223\346\236\204\350\277\221\345\271\264\346\234\237\344\270\255 \344\270\223\344\270\232\346\234\252\347\237\245.docx" "b/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/\346\225\260\346\215\256\347\273\223\346\236\204\350\277\221\345\271\264\346\234\237\344\270\255 \344\270\223\344\270\232\346\234\252\347\237\245.docx" new file mode 100644 index 00000000..0fff2aab --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/\346\225\260\346\215\256\347\273\223\346\236\204\350\277\221\345\271\264\346\234\237\344\270\255 \344\270\223\344\270\232\346\234\252\347\237\245.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c52e1438076dfbc5eb27d25522649346637714e2f4c14512c90120b0b4de9e81 +size 627202 diff --git "a/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/\346\231\272\350\203\275\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255\346\250\241\346\213\237\345\215\2671.pdf" "b/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/\346\231\272\350\203\275\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255\346\250\241\346\213\237\345\215\2671.pdf" new file mode 100644 index 00000000..d750c125 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/\346\231\272\350\203\275\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255\346\250\241\346\213\237\345\215\2671.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/\346\231\272\350\203\275\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255\346\250\241\346\213\237\345\215\2671_keyonly.pdf" "b/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/\346\231\272\350\203\275\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255\346\250\241\346\213\237\345\215\2671_keyonly.pdf" new file mode 100644 index 00000000..1218c88e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255/\346\231\272\350\203\275\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\344\270\255\346\250\241\346\213\237\345\215\2671_keyonly.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\346\234\253/24\347\272\247\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\346\234\253\350\200\203.md" "b/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\346\234\253/24\347\272\247\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\346\234\253\350\200\203.md" new file mode 100644 index 00000000..c7381117 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\346\234\253/24\347\272\247\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\346\234\253\350\200\203.md" @@ -0,0 +1,37 @@ +### 24级数据结构期末考 + ++ 无绪论或者对概念的简答题,比如顺序表和链表的区别、数据结构和抽象数据结构的区别这一类 ++ 考察范围简单的为书本上的一些概念,中等的为作业题(就是word上的)和15-16卷(2023半原卷),我觉得比较偏难的或者有印象的列在下面 ++ 没考线索化、括号匹配和表达式求值、求任何的ASL、哈希表有关$\alpha$的ASL公式、WPL、串、特殊数组、广义表、dij、Floyd、Kruskal,但不表示之后不会考 + +#### 选择题 + +* 时间复杂度跟什么有关,跟注释肯定没关系 +* 给出总数,问二叉判定树的深度(还是最多查找次数,忘了,也是15-16原题) + +* 问两个链表的合并的最小时间复杂度,选项O(1), O(max(m,n)), O(min(m+n))), O(m+n) +* 循环链表判断队列满的条件 +* 写出以首个元素为pivot,一趟快速排序后的结果 +* 二叉链表的左指针指向什么,选项第一颗、最后一棵子树、兄弟树 +* 给出深度和结点数,问完全二叉树有几个叶子节点(15-16原题) +* 要取出5000个数据中最小的50个数据用哪个最快,选项快速、归并、插入、堆 +* 线性探测再散列,问哈希地址在哪 +* 哈夫曼树的性质,是一道值最小的两个为兄弟节点、共有2n+1个结点、不一定完全二叉树的作业题 +* 15-16入栈再入队的序列题 +* (忘了是啥)除了DFS还可以拓扑排序(作业题原题) +* 给出邻接表(书上的邻接表示意图),问关键路径 +* 插入到AVl树后,BF=-2,1的两次旋转,问根节点和新插入结点的双亲 + +#### 简答题 + +* 给出一个序列,要求画出依次插入后的小根堆 + +* 画出依赖序列的拓扑结构图,就是有一道有S1~12,有数据结构、软件工程导论、毕业设计的那道题 +* 描述链式基数排序的过程,并回答将题目的序列经过一趟排序的结果 +* 给出网图和起始顶点,利用Prim写出每步的顶点和权,并画出最小生成树 + +#### 设计题 + +* 给出含头节点的链表,设计将按绝对值递增的含正负整数的序列排序的算法,并分析时间复杂度 +* 统计叶子节点 +* 非递归dfs遍历 \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\346\234\253/\350\266\205\345\244\23224\347\272\247\346\234\237\346\234\253\350\200\203\345\216\237\351\242\230.doc" "b/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\346\234\253/\350\266\205\345\244\23224\347\272\247\346\234\237\346\234\253\350\200\203\345\216\237\351\242\230.doc" new file mode 100644 index 00000000..8e912ebb Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DataStructure/\346\225\260\346\215\256\347\273\223\346\236\204\346\234\237\346\234\253/\350\266\205\345\244\23224\347\272\247\346\234\237\346\234\253\350\200\203\345\216\237\351\242\230.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2541\346\254\241\344\275\234\344\270\232.pptx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2541\346\254\241\344\275\234\344\270\232.pptx" new file mode 100644 index 00000000..226e70b5 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2541\346\254\241\344\275\234\344\270\232.pptx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:5a9d83408bae1b52760766a440df73e3eeaf2f8823a0fd9fabe9831dd1edc26c +size 95034 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2542\346\254\241\344\275\234\344\270\232.pptx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2542\346\254\241\344\275\234\344\270\232.pptx" new file mode 100644 index 00000000..8dc28706 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2542\346\254\241\344\275\234\344\270\232.pptx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6fa23b70ab1e69612546a63ddfaf370e05d521efebf1ddc390af39132dfba240 +size 499997 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2543\346\254\241\344\275\234\344\270\232.pptx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2543\346\254\241\344\275\234\344\270\232.pptx" new file mode 100644 index 00000000..1e0b8f18 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2543\346\254\241\344\275\234\344\270\232.pptx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:eaf4a323c5d5aae73d5a45697312d9cc1b52846b8cad39b2b0523904e01d6fbf +size 1732866 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2544\346\254\241\344\275\234\344\270\232.pptx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2544\346\254\241\344\275\234\344\270\232.pptx" new file mode 100644 index 00000000..a0d6d4d5 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2544\346\254\241\344\275\234\344\270\232.pptx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8c19a4d4a30f37f18241be6b0704c23cd82cafd15d4e0c4a4cea26a7fecf2f09 +size 1076661 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2545\346\254\241\344\275\234\344\270\232.pptx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2545\346\254\241\344\275\234\344\270\232.pptx" new file mode 100644 index 00000000..940c15f5 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2545\346\254\241\344\275\234\344\270\232.pptx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f47455ce1bf396cf69efacfcfb55e4070773bc34ff1cc6b5d4d61674593a6293 +size 1652637 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2546\346\254\241\344\275\234\344\270\232.pptx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2546\346\254\241\344\275\234\344\270\232.pptx" new file mode 100644 index 00000000..2833ba87 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2546\346\254\241\344\275\234\344\270\232.pptx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:e3aee9951fdeec4433dad5305b60a081f2bb452e93f31a94996abd2eadad7ab3 +size 2588622 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2547\346\254\241\344\275\234\344\270\232.pptx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2547\346\254\241\344\275\234\344\270\232.pptx" new file mode 100644 index 00000000..c630df92 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2547\346\254\241\344\275\234\344\270\232.pptx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:01888d5df246d6d7c91245495ca6aaee8b886619ff02d695192438539063759c +size 1638133 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2548\346\254\241\344\275\234\344\270\232.pptx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2548\346\254\241\344\275\234\344\270\232.pptx" new file mode 100644 index 00000000..5eddb448 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\344\275\234\344\270\232/\344\275\234\344\270\232\345\217\202\350\200\203/\347\254\2548\346\254\241\344\275\234\344\270\232.pptx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9415155719de0f104dcabe5bf43655ca3d6e40fb70fd362c5e0cee6c3772c2c1 +size 400931 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\347\254\2541\346\254\241\345\256\236\351\252\214\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224.zip" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\347\254\2541\346\254\241\345\256\236\351\252\214\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224.zip" new file mode 100644 index 00000000..9e56b869 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\347\254\2541\346\254\241\345\256\236\351\252\214\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224.zip" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9219aed33a23468e25e62404e1ce6c9c22c85600e276a6d90ad8e5673ad21c11 +size 25647 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\347\254\2544\346\254\241\345\256\236\351\252\214\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.zip" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\347\254\2544\346\254\241\345\256\236\351\252\214\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.zip" new file mode 100644 index 00000000..31c53837 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\347\254\2544\346\254\241\345\256\236\351\252\214\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.zip" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:cab7dc59d83283ca496db2d81dc7fff75067861f2c527c5bf9288ff484ce9093 +size 1606328 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\347\254\2545\346\254\241\345\256\236\351\252\214\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.zip" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\347\254\2545\346\254\241\345\256\236\351\252\214\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.zip" new file mode 100644 index 00000000..f253cd56 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\347\254\2545\346\254\241\345\256\236\351\252\214\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.zip" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6b6f95066cbe33aaad7871e55703874cce69fc9a61b74a9aa430690ae908ec5b +size 3492410 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\347\254\2546\346\254\241\345\256\236\351\252\214\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.zip" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\347\254\2546\346\254\241\345\256\236\351\252\214\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.zip" new file mode 100644 index 00000000..121b67a8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\347\254\2546\346\254\241\345\256\236\351\252\214\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.zip" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1831b69b5f43a98161a6c375f61bdcb8092de7d78a9ca8a7d4150d8508bdd075 +size 1385191 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\347\254\2547\346\254\241\345\256\236\351\252\214\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.zip" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\347\254\2547\346\254\241\345\256\236\351\252\214\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.zip" new file mode 100644 index 00000000..d56669b5 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\347\254\2547\346\254\241\345\256\236\351\252\214\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.zip" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:90697073bdd8e2d78392edd0c57475f330712f113fbd8815c6e997b6dec34634 +size 2113443 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\357\274\210\345\256\236\351\252\214\344\270\200\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210.pdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\357\274\210\345\256\236\351\252\214\344\270\200\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210.pdf" new file mode 100644 index 00000000..7e6b5280 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\357\274\210\345\256\236\351\252\214\344\270\200\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\357\274\210\345\256\236\351\252\214\344\270\203\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.pdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\357\274\210\345\256\236\351\252\214\344\270\203\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.pdf" new file mode 100644 index 00000000..4d2db259 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\357\274\210\345\256\236\351\252\214\344\270\203\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\357\274\210\345\256\236\351\252\214\344\270\211\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.pdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\357\274\210\345\256\236\351\252\214\344\270\211\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.pdf" new file mode 100644 index 00000000..1eaf909b Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\357\274\210\345\256\236\351\252\214\344\270\211\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\357\274\210\345\256\236\351\252\214\344\272\224\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.pdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\357\274\210\345\256\236\351\252\214\344\272\224\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.pdf" new file mode 100644 index 00000000..859ed002 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\357\274\210\345\256\236\351\252\214\344\272\224\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\357\274\210\345\256\236\351\252\214\345\205\255\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.pdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\357\274\210\345\256\236\351\252\214\345\205\255\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.pdf" new file mode 100644 index 00000000..b99ae3aa Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\357\274\210\345\256\236\351\252\214\345\205\255\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211\357\274\210\347\255\224\346\241\210\357\274\211.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\346\225\260\345\255\227\351\200\273\350\276\221\357\274\210\346\234\237\344\270\255\350\200\203\350\257\225\347\255\224\346\241\210\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211.pdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\346\225\260\345\255\227\351\200\273\350\276\221\357\274\210\346\234\237\344\270\255\350\200\203\350\257\225\347\255\224\346\241\210\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211.pdf" new file mode 100644 index 00000000..562951cf Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\346\225\260\345\255\227\351\200\273\350\276\221\357\274\210\346\234\237\344\270\255\350\200\203\350\257\225\347\255\224\346\241\210\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\346\225\260\345\255\227\351\200\273\350\276\221\357\274\210\347\254\2545\347\253\240\344\271\240\351\242\230\347\255\224\346\241\210\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211.pdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\346\225\260\345\255\227\351\200\273\350\276\221\357\274\210\347\254\2545\347\253\240\344\271\240\351\242\230\347\255\224\346\241\210\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211.pdf" new file mode 100644 index 00000000..fa4d3769 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\346\225\260\345\255\227\351\200\273\350\276\221\357\274\210\347\254\2545\347\253\240\344\271\240\351\242\230\347\255\224\346\241\210\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\346\225\260\345\255\227\351\200\273\350\276\221\357\274\210\347\254\2547\347\253\240\344\271\240\351\242\230\347\255\224\346\241\210\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211.pdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\346\225\260\345\255\227\351\200\273\350\276\221\357\274\210\347\254\2547\347\253\240\344\271\240\351\242\230\347\255\224\346\241\210\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211.pdf" new file mode 100644 index 00000000..3aec9c7f Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\346\225\260\345\255\227\351\200\273\350\276\221\357\274\210\347\254\2547\347\253\240\344\271\240\351\242\230\347\255\224\346\241\210\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\346\225\260\345\255\227\351\200\273\350\276\221\357\274\210\347\254\2548\347\253\240\344\271\240\351\242\230\347\255\224\346\241\210\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211.pdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\346\225\260\345\255\227\351\200\273\350\276\221\357\274\210\347\254\2548\347\253\240\344\271\240\351\242\230\347\255\224\346\241\210\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211.pdf" new file mode 100644 index 00000000..ec1a127e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\346\225\260\345\255\227\351\200\273\350\276\221\357\274\210\347\254\2548\347\253\240\344\271\240\351\242\230\347\255\224\346\241\210\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\347\254\2542\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260.circ" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\347\254\2542\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260.circ" new file mode 100644 index 00000000..c20a6a5a --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\347\254\2542\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260.circ" @@ -0,0 +1,12262 @@ + + +This file is intended to be loaded by Logisim http://logisim.altervista.org + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + addr/data: 8 8 +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\347\254\254\344\270\211\347\253\240\344\271\240\351\242\230\347\232\204\344\273\277\347\234\237\347\273\223\346\236\234.circ" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\347\254\254\344\270\211\347\253\240\344\271\240\351\242\230\347\232\204\344\273\277\347\234\237\347\273\223\346\236\234.circ" new file mode 100644 index 00000000..6cfa8367 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\347\254\254\344\270\211\347\253\240\344\271\240\351\242\230\347\232\204\344\273\277\347\234\237\347\273\223\346\236\234.circ" @@ -0,0 +1,1325 @@ + + +This file is intended to be loaded by Logisim http://logisim.altervista.org + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + addr/data: 8 8 +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\351\242\230\350\247\243/arch\346\225\260\345\255\227\351\200\273\350\276\2211-7\347\253\240\350\257\276\345\220\216\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\351\242\230\350\247\243/arch\346\225\260\345\255\227\351\200\273\350\276\2211-7\347\253\240\350\257\276\345\220\216\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..0444ef10 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\351\242\230\350\247\243/arch\346\225\260\345\255\227\351\200\273\350\276\2211-7\347\253\240\350\257\276\345\220\216\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\351\242\230\350\247\243/\346\225\260\345\255\227\351\200\273\350\276\221\350\257\276\345\220\216\344\271\240\351\242\230\347\255\224\346\241\210(\345\215\216\344\270\255\347\247\221\346\212\200\345\244\247\345\255\246\345\207\272\347\211\210\347\244\276,\346\254\247\351\230\263\346\230\237\346\230\216\344\270\273\347\274\226)(1).ppt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\351\242\230\350\247\243/\346\225\260\345\255\227\351\200\273\350\276\221\350\257\276\345\220\216\344\271\240\351\242\230\347\255\224\346\241\210(\345\215\216\344\270\255\347\247\221\346\212\200\345\244\247\345\255\246\345\207\272\347\211\210\347\244\276,\346\254\247\351\230\263\346\230\237\346\230\216\344\270\273\347\274\226)(1).ppt" new file mode 100644 index 00000000..12c15959 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\351\242\230\350\247\243/\346\225\260\345\255\227\351\200\273\350\276\221\350\257\276\345\220\216\344\271\240\351\242\230\347\255\224\346\241\210(\345\215\216\344\270\255\347\247\221\346\212\200\345\244\247\345\255\246\345\207\272\347\211\210\347\244\276,\346\254\247\351\230\263\346\230\237\346\230\216\344\270\273\347\274\226)(1).ppt" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\351\242\230\350\247\243/\346\225\260\345\255\227\351\200\273\350\276\221\357\274\210\346\200\273\345\244\215\344\271\240\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211.pdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\351\242\230\350\247\243/\346\225\260\345\255\227\351\200\273\350\276\221\357\274\210\346\200\273\345\244\215\344\271\240\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211.pdf" new file mode 100644 index 00000000..79335bee Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\217\202\350\200\203\347\255\224\346\241\210/\351\242\230\350\247\243/\346\225\260\345\255\227\351\200\273\350\276\221\357\274\210\346\200\273\345\244\215\344\271\240\357\274\211\357\274\2102025\345\271\264\344\270\213\345\215\212\345\271\264\357\274\211.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\200/\347\254\2541\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\200/\347\254\2541\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" new file mode 100644 index 00000000..a7990a45 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\200/\347\254\2541\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:155c6d64d62d447c01845724537eace39c38632136fd12870bfe4340f829cdbb +size 1278935 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\200/\347\254\2541\346\254\241\345\256\236\351\252\214\350\256\276\350\256\241\346\226\207\344\273\266.circ" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\200/\347\254\2541\346\254\241\345\256\236\351\252\214\350\256\276\350\256\241\346\226\207\344\273\266.circ" new file mode 100644 index 00000000..00792480 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\200/\347\254\2541\346\254\241\345\256\236\351\252\214\350\256\276\350\256\241\346\226\207\344\273\266.circ" @@ -0,0 +1,4718 @@ + + +This file is intended to be loaded by Logisim http://logisim.altervista.org + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + addr/data: 8 8 +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/EGO1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/EGO1.xdc" new file mode 100644 index 00000000..18c97a11 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/EGO1.xdc" @@ -0,0 +1,253 @@ +//----------------------------------------------系统时钟和复位------------------------------------ +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports sys_clk_in] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports sys_rst_n] + + +//-----------------------------------------------5个按键--------------------------------------------- +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports btn_4] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_0_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_2_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_3_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_4_IBUF] + + +//---------------------------------------------拨码开关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + +//------------------------------------------拨码开关(DIP开关)sw8~sw15--------------------- +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[0]}] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[1]}] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[2]}] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[3]}] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports {dip_pin[4]}] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[5]}] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[6]}] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[7]}] + + +//---------------------------------------------LED0~LED15---------------------------------------- +set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN G3 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {led_pin[8]}] +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {led_pin[9]}] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led_pin[10]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led_pin[11]}] +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {led_pin[12]}] +set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports {led_pin[13]}] +set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports {led_pin[14]}] +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {led_pin[15]}] + + +//-----------------------------------8个数码管位选信号----------------------------------------------- +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[0]}] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[1]}] +set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[2]}] +set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[3]}] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[4]}] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[5]}] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[6]}] +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[7]}] + +//--------------------------------------------数码管段选信号--------------------------------------------- +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[0]}] +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[1]}] +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[2]}] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[3]}] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[4]}] +set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[5]}] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[6]}] +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[7]}] + +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[0]}] +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[1]}] +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[2]}] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[3]}] +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[4]}] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[5]}] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[6]}] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[7]}] + + +//--------------------------------------VGA行同步场同步信号----------------------------------------------- +set_property -dict {PACKAGE_PIN D7 IOSTANDARD LVCMOS33} [get_ports vga_hs_pin] +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports vga_vs_pin] + + +//--------------------------------------VGA红绿蓝信号------------------------------------------------------ +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[0]}] +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[1]}] +set_property -dict {PACKAGE_PIN C5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[2]}] +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[3]}] +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[4]}] +set_property -dict {PACKAGE_PIN A6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[5]}] +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[6]}] +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[7]}] +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[8]}] +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[9]}] +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[10]}] +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[11]}] + + +//----------------------------------------------串口-------------------------------------------------- +set_property -dict {PACKAGE_PIN N5 IOSTANDARD LVCMOS33} [get_ports PC_Uart_rxd] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports PC_Uart_txd] + + +//---------------------------------------------------PS2接口------------------------------------- +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports ps2_clk] +set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports ps2_data] + + +//------------------------------------------------IIC接口--------------------------------------------- +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports pw_iic_scl_io] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports pw_iic_sda_io] + + +//---------------------------------------------------蓝牙--------------------------------------------- +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports BT_Uart_rxd] +set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports BT_Uart_txd] + +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[0]}] +set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[1]}] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[2]}] +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[3]}] +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[4]}] + +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports bt_mcu_int_i] + + + +//-----------------------------------------------------音频接口--------------------------------------- +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports audio_pwm_o] +set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports audio_sd_o ] + + + +//--------------------------------------------------------XADC模数转换----------------------------------- +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_n] +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_p] +set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_n] +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_p] + + +//--------------------------------------------------------DAC数模转换--------------------------- +set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports dac_ile] +set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports dac_cs_n] +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports dac_wr1_n] +set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports dac_wr2_n] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports dac_xfer_n] + +set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS33} [get_ports {dac_data[0]}] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33} [get_ports {dac_data[1]}] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports {dac_data[2]}] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports {dac_data[3]}] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {dac_data[4]}] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {dac_data[5]}] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports {dac_data[6]}] +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports {dac_data[7]}] + + + +//-------------------------------------------------SDRAM芯片接口------------------------------------- +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[18]}] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[17]}] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[16]}] +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[15]}] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {sram_addr[14]}] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[13]}] +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[12]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[11]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[10]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[9]}] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[8]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[7]}] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[6]}] +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[5]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[4]}] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[3]}] +set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[2]}] +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[1]}] +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[0]}] + +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports sram_ce_n] +set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports sram_lb_n] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports sram_oe_n] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports sram_ub_n] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports sram_we_n] + +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {sram_data[15]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {sram_data[14]}] +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {sram_data[13]}] +set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS33} [get_ports {sram_data[12]}] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {sram_data[11]}] +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {sram_data[10]}] +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {sram_data[9]}] +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {sram_data[8]}] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {sram_data[7]}] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {sram_data[6]}] +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {sram_data[5]}] +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {sram_data[4]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {sram_data[3]}] +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {sram_data[2]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {sram_data[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {sram_data[0]}] + + + + +//--------------------------------------32个pmod接口(扩展接口)------------------------------- +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {exp_io[0]}] +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports {exp_io[1]}] +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports {exp_io[2]}] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS33} [get_ports {exp_io[3]}] +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {exp_io[4]}] +set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports {exp_io[5]}] +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports {exp_io[6]}] +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {exp_io[7]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {exp_io[8]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {exp_io[9]}] +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports {exp_io[10]}] +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {exp_io[11]}] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {exp_io[12]}] +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {exp_io[13]}] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {exp_io[14]}] +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {exp_io[15]}] + +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {exp_io[16]}] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {exp_io[17]}] +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports {exp_io[18]}] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {exp_io[19]}] +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports {exp_io[20]}] +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports {exp_io[21]}] +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports {exp_io[22]}] +set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {exp_io[23]}] +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {exp_io[24]}] +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {exp_io[25]}] +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {exp_io[26]}] +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports {exp_io[27]}] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {exp_io[28]}] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {exp_io[29]}] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {exp_io[30]}] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {exp_io[31]}] + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..07d2ced0 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,4 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:31:00:00 +eof:2674977240 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..de67d9ce --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:3 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..bc0640dd --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,30 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.hw/clock_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.hw/clock_EGO1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.hw/clock_EGO1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.srcs/sources_1/new/clock_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.srcs/sources_1/new/clock_EGO1.v" new file mode 100644 index 00000000..32dbdaf2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.srcs/sources_1/new/clock_EGO1.v" @@ -0,0 +1,209 @@ +`timescale 1ns / 1ps + +// ģ1ɨ +module number( + input clk, + input rst, + input [31:0] data, // HH-MM-SS + output reg[7:0] seg_data, // ѡ (a,b,c,d,e,f,g,dp) + output reg[7:0] seg_cs // λѡ (AN7-AN0) + ); + + reg clk_scan; + integer clk_cnt; + reg [2:0] scan_idx; // 0-7 ɨ + reg [3:0] hex_in; // ǰҪʾ4λ + + // ɨʱ (Լ1kHz) + always @(posedge clk or negedge rst) begin + if(!rst) begin + clk_scan <= 0; + clk_cnt <= 0; + end else begin + if(clk_cnt >= 50_000) begin // 100MHz / 50000 * 2 = 1kHz + clk_cnt <= 0; + clk_scan <= ~clk_scan; + end else begin + clk_cnt <= clk_cnt + 1; + end + end + end + + // ɨλѡ߼ + always @(posedge clk_scan or negedge rst) begin + if(!rst) + scan_idx <= 0; + else + scan_idx <= scan_idx + 1; + end + + // λѡ (EGO1 ͨλѡҲǵ͵ƽЧɶķ) + always @(*) begin + case(scan_idx) + 3'd0: begin seg_cs = 8'b1111_1110; hex_in = data[3:0]; end // λ + 3'd1: begin seg_cs = 8'b1111_1101; hex_in = data[7:4]; end // ʮλ + 3'd2: begin seg_cs = 8'b1111_1011; hex_in = data[11:8]; end // - + 3'd3: begin seg_cs = 8'b1111_0111; hex_in = data[15:12]; end // ָλ + 3'd4: begin seg_cs = 8'b1110_1111; hex_in = data[19:16]; end // ʮλ + 3'd5: begin seg_cs = 8'b1101_1111; hex_in = data[23:20]; end // - + 3'd6: begin seg_cs = 8'b1011_1111; hex_in = data[27:24]; end // ʱλ + 3'd7: begin seg_cs = 8'b0111_1111; hex_in = data[31:28]; end // ʱʮλ + default: begin seg_cs = 8'b1111_1111; hex_in = 4'hF; end + endcase + end + + // + always @(*) begin + case(hex_in) + 4'h0: seg_data = 8'hC0; // 0 (1100 0000) + 4'h1: seg_data = 8'hF9; // 1 + 4'h2: seg_data = 8'hA4; // 2 + 4'h3: seg_data = 8'hB0; // 3 + 4'h4: seg_data = 8'h99; // 4 + 4'h5: seg_data = 8'h92; // 5 + 4'h6: seg_data = 8'h82; // 6 + 4'h7: seg_data = 8'hF8; // 7 + 4'h8: seg_data = 8'h80; // 8 + 4'h9: seg_data = 8'h90; // 9 + 4'hf: seg_data = 8'hBF; // - (Dash, 1011 1111) + default: seg_data = 8'hFF; // ȫ + endcase + end + +endmodule + +// ģ2 +module btn_debounce( + input clk, + input rst_n, + input btn_in, + output reg btn_posedge // µ˲һ + ); + reg [19:0] cnt; + reg btn_prev; + reg btn_curr; + + always @(posedge clk or negedge rst_n) begin + if(!rst_n) begin + cnt <= 0; + btn_curr <= 0; + btn_prev <= 0; + btn_posedge <= 0; + end else begin + btn_prev <= btn_curr; // һ״̬ + + // 򵥵߼ + if(cnt < 20'd999_999) begin // 10ms + if(btn_in == 1'b1) cnt <= cnt + 1; + else cnt <= 0; + end + else begin + btn_curr <= 1'b1; // ȷϰ + cnt <= 0; // ȴɿ򻯴 + end + + // ɿ + if(btn_in == 0) begin + cnt <= 0; + btn_curr <= 0; + end + + // + btn_posedge <= (~btn_prev) & btn_curr; + end + end +endmodule + +// ģ3ʱ߼ +module E_CLOCK( + input sys_clk_in, + input sys_rst_n, + input [4:0] btn, // 5 (S4, S3, S2, S1, S0) + output [7:0] seg_data_pin, // ܶ + output [7:0] seg_cs_pin // λ + ); + + integer timer_cnt; + reg [5:0] seconds; + reg [5:0] minutes; + reg [5:0] hours; + reg [31:0] display_data; + + // ź + wire btn4_pulse, btn3_pulse, btn2_pulse, btn1_pulse; // S0ֱͨλҲ + + // ʵģ + btn_debounce u_btn4 (.clk(sys_clk_in), .rst_n(sys_rst_n), .btn_in(btn[4]), .btn_posedge(btn4_pulse)); // S4: Сʱ+ + btn_debounce u_btn3 (.clk(sys_clk_in), .rst_n(sys_rst_n), .btn_in(btn[3]), .btn_posedge(btn3_pulse)); // S3: + + btn_debounce u_btn2 (.clk(sys_clk_in), .rst_n(sys_rst_n), .btn_in(btn[2]), .btn_posedge(btn2_pulse)); // S2: + + // ʱ߼ + always @(posedge sys_clk_in or negedge sys_rst_n) begin + if(!sys_rst_n) begin + timer_cnt <= 0; + seconds <= 0; + minutes <= 0; + hours <= 0; + end + else begin + // --- S4: Сʱ --- + if(btn4_pulse) begin + if(hours >= 23) hours <= 0; + else hours <= hours + 1; + end + + // --- S3: --- + else if(btn3_pulse) begin + if(minutes >= 59) minutes <= 0; + else minutes <= minutes + 1; + end + + // --- S2: --- + else if(btn2_pulse) begin + seconds <= 0; + timer_cnt <= 0; // + end + + // --- ʱ --- + else if(timer_cnt >= 100_000_000 - 1) begin + timer_cnt <= 0; + if(seconds >= 59) begin + seconds <= 0; + if(minutes >= 59) begin + minutes <= 0; + if(hours >= 23) hours <= 0; + else hours <= hours + 1; + end + else minutes <= minutes + 1; + end + else seconds <= seconds + 1; + end + else begin + timer_cnt <= timer_cnt + 1; + end + end + end + + // ʾ + // ʽ: HH-MM-SSм F + always @(*) begin + display_data[31:28] = hours / 10; + display_data[27:24] = hours % 10; + display_data[23:20] = 4'hf; // ʾ - + display_data[19:16] = minutes / 10; + display_data[15:12] = minutes % 10; + display_data[11:8] = 4'hf; // ʾ - + display_data[7:4] = seconds / 10; + display_data[3:0] = seconds % 10; + end + + // ʵʾģ + number U1( + .clk(sys_clk_in), + .rst(sys_rst_n), + .data(display_data), + .seg_data(seg_data_pin), + .seg_cs(seg_cs_pin) + ); + +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.xpr" new file mode 100644 index 00000000..e6c0e4d6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/clock_EGO1/clock_EGO1.xpr" @@ -0,0 +1,185 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/\347\254\2547\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/\347\254\2547\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" new file mode 100644 index 00000000..6482ea1d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/\347\254\2547\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:e4413e02a8780d4007b954053d2f2a42ee67d317fa990c9da41199d8dff83b02 +size 2066651 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/\347\254\2547\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260\357\274\210\347\254\2542\351\203\250\345\210\206\357\274\211.circ" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/\347\254\2547\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260\357\274\210\347\254\2542\351\203\250\345\210\206\357\274\211.circ" new file mode 100644 index 00000000..10c596a4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\203/\347\254\2547\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260\357\274\210\347\254\2542\351\203\250\345\210\206\357\274\211.circ" @@ -0,0 +1,2249 @@ + + + This file is intended to be loaded by Logisim http://logisim.altervista.org + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + addr/data: 8 8 +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/EGO1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/EGO1.xdc" new file mode 100644 index 00000000..6ae3adfe --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/EGO1.xdc" @@ -0,0 +1,250 @@ +//----------------------------------------------系统时钟和复位------------------------------------ +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports sys_clk_in] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports sys_rst_n] + + +//-----------------------------------------------5个按键--------------------------------------------- +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports btn_4] + + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] + + +//---------------------------------------------拨码开关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + +//------------------------------------------拨码开关(DIP开关)sw8~sw15--------------------- +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[0]}] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[1]}] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[2]}] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[3]}] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports {dip_pin[4]}] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[5]}] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[6]}] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[7]}] + + +//---------------------------------------------LED0~LED15---------------------------------------- +set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN G3 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {led_pin[8]}] +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {led_pin[9]}] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led_pin[10]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led_pin[11]}] +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {led_pin[12]}] +set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports {led_pin[13]}] +set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports {led_pin[14]}] +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {led_pin[15]}] + + +//-----------------------------------8个数码管位选信号----------------------------------------------- +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[0]}] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[1]}] +set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[2]}] +set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[3]}] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[4]}] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[5]}] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[6]}] +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[7]}] + +//--------------------------------------------数码管段选信号--------------------------------------------- +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[0]}] +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[1]}] +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[2]}] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[3]}] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[4]}] +set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[5]}] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[6]}] +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[7]}] + +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[0]}] +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[1]}] +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[2]}] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[3]}] +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[4]}] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[5]}] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[6]}] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[7]}] + + +//--------------------------------------VGA行同步场同步信号----------------------------------------------- +set_property -dict {PACKAGE_PIN D7 IOSTANDARD LVCMOS33} [get_ports vga_hs_pin] +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports vga_vs_pin] + + +//--------------------------------------VGA红绿蓝信号------------------------------------------------------ +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[0]}] +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[1]}] +set_property -dict {PACKAGE_PIN C5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[2]}] +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[3]}] +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[4]}] +set_property -dict {PACKAGE_PIN A6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[5]}] +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[6]}] +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[7]}] +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[8]}] +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[9]}] +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[10]}] +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[11]}] + + +//----------------------------------------------串口-------------------------------------------------- +set_property -dict {PACKAGE_PIN N5 IOSTANDARD LVCMOS33} [get_ports PC_Uart_rxd] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports PC_Uart_txd] + + +//---------------------------------------------------PS2接口------------------------------------- +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports ps2_clk] +set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports ps2_data] + + +//------------------------------------------------IIC接口--------------------------------------------- +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports pw_iic_scl_io] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports pw_iic_sda_io] + + +//---------------------------------------------------蓝牙--------------------------------------------- +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports BT_Uart_rxd] +set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports BT_Uart_txd] + +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[0]}] +set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[1]}] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[2]}] +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[3]}] +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[4]}] + +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports bt_mcu_int_i] + + + +//-----------------------------------------------------音频接口--------------------------------------- +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports audio_pwm_o] +set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports audio_sd_o ] + + + +//--------------------------------------------------------XADC模数转换----------------------------------- +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_n] +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_p] +set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_n] +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_p] + + +//--------------------------------------------------------DAC数模转换--------------------------- +set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports dac_ile] +set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports dac_cs_n] +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports dac_wr1_n] +set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports dac_wr2_n] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports dac_xfer_n] + +set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS33} [get_ports {dac_data[0]}] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33} [get_ports {dac_data[1]}] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports {dac_data[2]}] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports {dac_data[3]}] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {dac_data[4]}] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {dac_data[5]}] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports {dac_data[6]}] +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports {dac_data[7]}] + + + +//-------------------------------------------------SDRAM芯片接口------------------------------------- +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[18]}] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[17]}] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[16]}] +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[15]}] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {sram_addr[14]}] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[13]}] +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[12]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[11]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[10]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[9]}] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[8]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[7]}] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[6]}] +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[5]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[4]}] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[3]}] +set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[2]}] +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[1]}] +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[0]}] + +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports sram_ce_n] +set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports sram_lb_n] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports sram_oe_n] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports sram_ub_n] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports sram_we_n] + +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {sram_data[15]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {sram_data[14]}] +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {sram_data[13]}] +set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS33} [get_ports {sram_data[12]}] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {sram_data[11]}] +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {sram_data[10]}] +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {sram_data[9]}] +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {sram_data[8]}] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {sram_data[7]}] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {sram_data[6]}] +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {sram_data[5]}] +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {sram_data[4]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {sram_data[3]}] +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {sram_data[2]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {sram_data[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {sram_data[0]}] + + + + +//--------------------------------------32个pmod接口(扩展接口)------------------------------- +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {exp_io[0]}] +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports {exp_io[1]}] +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports {exp_io[2]}] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS33} [get_ports {exp_io[3]}] +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {exp_io[4]}] +set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports {exp_io[5]}] +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports {exp_io[6]}] +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {exp_io[7]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {exp_io[8]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {exp_io[9]}] +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports {exp_io[10]}] +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {exp_io[11]}] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {exp_io[12]}] +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {exp_io[13]}] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {exp_io[14]}] +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {exp_io[15]}] + +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {exp_io[16]}] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {exp_io[17]}] +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports {exp_io[18]}] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {exp_io[19]}] +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports {exp_io[20]}] +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports {exp_io[21]}] +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports {exp_io[22]}] +set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {exp_io[23]}] +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {exp_io[24]}] +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {exp_io[25]}] +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {exp_io[26]}] +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports {exp_io[27]}] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {exp_io[28]}] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {exp_io[29]}] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {exp_io[30]}] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {exp_io[31]}] + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..034caaca --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,13 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f65646974:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 +eof:1404688054 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..9a006883 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,5 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +eof:2791156663 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..9b342093 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..5da9f096 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,44 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.hw/example_4_12b_1_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.hw/example_4_12b_1_EGO1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.hw/example_4_12b_1_EGO1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.v" new file mode 100644 index 00000000..5bed0763 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.v" @@ -0,0 +1,57 @@ +module blood_compatibility_behavioral( + input donor_type1, + input donor_type0, + input recipient_type1, + input recipient_type0, + output reg compatibility +); + +always @(*) begin + case ({donor_type1, donor_type0}) + 2'b00: begin + case ({recipient_type1, recipient_type0}) + 2'b00: compatibility = 1; + 2'b01: compatibility = 1; + 2'b10: compatibility = 1; + 2'b11: compatibility = 1; + endcase + end + 2'b01: begin + case ({recipient_type1, recipient_type0}) + 2'b01: compatibility = 1; + 2'b11: compatibility = 1; + default: compatibility = 0; + endcase + end + 2'b10: begin + case ({recipient_type1, recipient_type0}) + 2'b10: compatibility = 1; + 2'b11: compatibility = 1; + default: compatibility = 0; + endcase + end + 2'b11: begin + case ({recipient_type1, recipient_type0}) + 2'b11: compatibility = 1; + default: compatibility = 0; + endcase + end + endcase +end + +endmodule + +module top_module( + input [7:0] sw_pin, + output [15:0] led_pin +); + +blood_compatibility_behavioral uut( + .donor_type1(sw_pin[1]), + .donor_type0(sw_pin[0]), + .recipient_type1(sw_pin[7]), + .recipient_type0(sw_pin[6]), + .compatibility(led) +); + +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.xpr" new file mode 100644 index 00000000..72fb5564 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_1_EGO1/example_4_12b_1_EGO1.xpr" @@ -0,0 +1,185 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/EGO1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/EGO1.xdc" new file mode 100644 index 00000000..6ae3adfe --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/EGO1.xdc" @@ -0,0 +1,250 @@ +//----------------------------------------------系统时钟和复位------------------------------------ +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports sys_clk_in] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports sys_rst_n] + + +//-----------------------------------------------5个按键--------------------------------------------- +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports btn_4] + + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] + + +//---------------------------------------------拨码开关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + +//------------------------------------------拨码开关(DIP开关)sw8~sw15--------------------- +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[0]}] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[1]}] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[2]}] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[3]}] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports {dip_pin[4]}] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[5]}] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[6]}] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[7]}] + + +//---------------------------------------------LED0~LED15---------------------------------------- +set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN G3 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {led_pin[8]}] +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {led_pin[9]}] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led_pin[10]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led_pin[11]}] +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {led_pin[12]}] +set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports {led_pin[13]}] +set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports {led_pin[14]}] +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {led_pin[15]}] + + +//-----------------------------------8个数码管位选信号----------------------------------------------- +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[0]}] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[1]}] +set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[2]}] +set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[3]}] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[4]}] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[5]}] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[6]}] +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[7]}] + +//--------------------------------------------数码管段选信号--------------------------------------------- +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[0]}] +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[1]}] +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[2]}] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[3]}] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[4]}] +set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[5]}] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[6]}] +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[7]}] + +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[0]}] +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[1]}] +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[2]}] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[3]}] +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[4]}] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[5]}] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[6]}] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[7]}] + + +//--------------------------------------VGA行同步场同步信号----------------------------------------------- +set_property -dict {PACKAGE_PIN D7 IOSTANDARD LVCMOS33} [get_ports vga_hs_pin] +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports vga_vs_pin] + + +//--------------------------------------VGA红绿蓝信号------------------------------------------------------ +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[0]}] +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[1]}] +set_property -dict {PACKAGE_PIN C5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[2]}] +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[3]}] +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[4]}] +set_property -dict {PACKAGE_PIN A6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[5]}] +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[6]}] +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[7]}] +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[8]}] +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[9]}] +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[10]}] +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[11]}] + + +//----------------------------------------------串口-------------------------------------------------- +set_property -dict {PACKAGE_PIN N5 IOSTANDARD LVCMOS33} [get_ports PC_Uart_rxd] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports PC_Uart_txd] + + +//---------------------------------------------------PS2接口------------------------------------- +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports ps2_clk] +set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports ps2_data] + + +//------------------------------------------------IIC接口--------------------------------------------- +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports pw_iic_scl_io] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports pw_iic_sda_io] + + +//---------------------------------------------------蓝牙--------------------------------------------- +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports BT_Uart_rxd] +set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports BT_Uart_txd] + +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[0]}] +set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[1]}] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[2]}] +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[3]}] +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[4]}] + +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports bt_mcu_int_i] + + + +//-----------------------------------------------------音频接口--------------------------------------- +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports audio_pwm_o] +set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports audio_sd_o ] + + + +//--------------------------------------------------------XADC模数转换----------------------------------- +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_n] +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_p] +set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_n] +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_p] + + +//--------------------------------------------------------DAC数模转换--------------------------- +set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports dac_ile] +set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports dac_cs_n] +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports dac_wr1_n] +set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports dac_wr2_n] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports dac_xfer_n] + +set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS33} [get_ports {dac_data[0]}] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33} [get_ports {dac_data[1]}] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports {dac_data[2]}] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports {dac_data[3]}] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {dac_data[4]}] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {dac_data[5]}] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports {dac_data[6]}] +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports {dac_data[7]}] + + + +//-------------------------------------------------SDRAM芯片接口------------------------------------- +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[18]}] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[17]}] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[16]}] +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[15]}] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {sram_addr[14]}] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[13]}] +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[12]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[11]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[10]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[9]}] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[8]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[7]}] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[6]}] +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[5]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[4]}] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[3]}] +set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[2]}] +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[1]}] +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[0]}] + +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports sram_ce_n] +set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports sram_lb_n] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports sram_oe_n] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports sram_ub_n] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports sram_we_n] + +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {sram_data[15]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {sram_data[14]}] +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {sram_data[13]}] +set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS33} [get_ports {sram_data[12]}] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {sram_data[11]}] +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {sram_data[10]}] +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {sram_data[9]}] +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {sram_data[8]}] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {sram_data[7]}] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {sram_data[6]}] +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {sram_data[5]}] +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {sram_data[4]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {sram_data[3]}] +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {sram_data[2]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {sram_data[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {sram_data[0]}] + + + + +//--------------------------------------32个pmod接口(扩展接口)------------------------------- +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {exp_io[0]}] +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports {exp_io[1]}] +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports {exp_io[2]}] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS33} [get_ports {exp_io[3]}] +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {exp_io[4]}] +set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports {exp_io[5]}] +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports {exp_io[6]}] +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {exp_io[7]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {exp_io[8]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {exp_io[9]}] +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports {exp_io[10]}] +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {exp_io[11]}] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {exp_io[12]}] +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {exp_io[13]}] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {exp_io[14]}] +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {exp_io[15]}] + +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {exp_io[16]}] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {exp_io[17]}] +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports {exp_io[18]}] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {exp_io[19]}] +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports {exp_io[20]}] +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports {exp_io[21]}] +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports {exp_io[22]}] +set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {exp_io[23]}] +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {exp_io[24]}] +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {exp_io[25]}] +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {exp_io[26]}] +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports {exp_io[27]}] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {exp_io[28]}] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {exp_io[29]}] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {exp_io[30]}] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {exp_io[31]}] + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..819af935 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,19 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f796573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f65646974:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 +eof:1723336131 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..6aa235e5 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,8 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:31:00:00 +eof:1272963954 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..de67d9ce --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:3 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/synthesis.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/synthesis.wdf" new file mode 100644 index 00000000..660df139 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/synthesis.wdf" @@ -0,0 +1,39 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:786337613335746373673332342d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:746f705f6d6f64756c65:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323273:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:3939372e3532374d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3636372e3135364d42:00:00 +eof:3544211029 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/synthesis_details.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/synthesis_details.wdf" new file mode 100644 index 00000000..78f8d66e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/synthesis_details.wdf" @@ -0,0 +1,3 @@ +version:1 +73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 +eof:2511430288 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..da89731b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,53 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.hw/example_4_12b_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.hw/example_4_12b_EGO1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.hw/example_4_12b_EGO1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/.jobs/vrs_config_1.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/.jobs/vrs_config_1.xml" new file mode 100644 index 00000000..23aa7ef0 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/.jobs/vrs_config_1.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.Vivado_Implementation.queue.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.Vivado_Implementation.queue.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.init_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.init_design.begin.rst" new file mode 100644 index 00000000..679133b4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.init_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.init_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.init_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.opt_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.opt_design.begin.rst" new file mode 100644 index 00000000..679133b4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.opt_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.opt_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.opt_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.phys_opt_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.phys_opt_design.begin.rst" new file mode 100644 index 00000000..679133b4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.phys_opt_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.phys_opt_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.phys_opt_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.place_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.place_design.begin.rst" new file mode 100644 index 00000000..679133b4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.place_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.place_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.place_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.route_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.route_design.begin.rst" new file mode 100644 index 00000000..679133b4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.route_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.route_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.route_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.vivado.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.vivado.begin.rst" new file mode 100644 index 00000000..dd0de21d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.vivado.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.vivado.error.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.vivado.error.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.write_bitstream.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.write_bitstream.begin.rst" new file mode 100644 index 00000000..679133b4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.write_bitstream.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.write_bitstream.error.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/.write_bitstream.error.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/ISEWrap.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/ISEWrap.js" new file mode 100644 index 00000000..97a2ecbc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/ISEWrap.js" @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/ISEWrap.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/ISEWrap.sh" new file mode 100644 index 00000000..f679f2e8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/ISEWrap.sh" @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/gen_run.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/gen_run.xml" new file mode 100644 index 00000000..4189df52 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/gen_run.xml" @@ -0,0 +1,123 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/htr.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/htr.txt" new file mode 100644 index 00000000..4917bafa --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/htr.txt" @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log top_module.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_module.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/init_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/init_design.pb" new file mode 100644 index 00000000..139aa883 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/init_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/opt_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/opt_design.pb" new file mode 100644 index 00000000..8406e630 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/opt_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/phys_opt_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/phys_opt_design.pb" new file mode 100644 index 00000000..d80d3e78 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/phys_opt_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/place_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/place_design.pb" new file mode 100644 index 00000000..0f08175f Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/place_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/project.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/project.wdf" new file mode 100644 index 00000000..16c2e7eb --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/project.wdf" @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3533633032643765323934323461366562633530393739346432336262666361:506172656e742050412070726f6a656374204944:00 +eof:1294518113 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/route_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/route_design.pb" new file mode 100644 index 00000000..58c5c6b3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/route_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/rundef.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/rundef.js" new file mode 100644 index 00000000..15d30f9c --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/rundef.js" @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Vivado/Download/Vivado/2019.2/bin;"; +} else { + PathVal = "D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Vivado/Download/Vivado/2019.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log top_module.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_module.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/runme.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/runme.bat" new file mode 100644 index 00000000..1760626b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/runme.bat" @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/runme.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/runme.sh" new file mode 100644 index 00000000..047ed005 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/runme.sh" @@ -0,0 +1,47 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Vivado/Download/Vivado/2019.2/bin +else + PATH=D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Vivado/Download/Vivado/2019.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log top_module.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top_module.tcl -notrace + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module.tcl" new file mode 100644 index 00000000..b282d8b4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module.tcl" @@ -0,0 +1,186 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param chipscope.maxJobs 4 + create_project -in_memory -part xc7a35tcsg324-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt [current_project] + set_property parent.project_path C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.xpr [current_project] + set_property ip_output_repo C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module.dcp + read_xdc C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc + link_design -top top_module -part xc7a35tcsg324-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force top_module_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file top_module_drc_opted.rpt -pb top_module_drc_opted.pb -rpx top_module_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force top_module_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file top_module_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file top_module_utilization_placed.rpt -pb top_module_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file top_module_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step phys_opt_design +set ACTIVE_STEP phys_opt_design +set rc [catch { + create_msg_db phys_opt_design.pb + phys_opt_design + write_checkpoint -force top_module_physopt.dcp + close_msg_db -file phys_opt_design.pb +} RESULT] +if {$rc} { + step_failed phys_opt_design + return -code error $RESULT +} else { + end_step phys_opt_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force top_module_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file top_module_drc_routed.rpt -pb top_module_drc_routed.pb -rpx top_module_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file top_module_methodology_drc_routed.rpt -pb top_module_methodology_drc_routed.pb -rpx top_module_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file top_module_power_routed.rpt -pb top_module_power_summary_routed.pb -rpx top_module_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file top_module_route_status.rpt -pb top_module_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file top_module_timing_summary_routed.rpt -pb top_module_timing_summary_routed.pb -rpx top_module_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file top_module_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file top_module_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file top_module_bus_skew_routed.rpt -pb top_module_bus_skew_routed.pb -rpx top_module_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force top_module_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + catch { write_mem_info -force top_module.mmi } + write_bitstream -force top_module.bit + catch {write_debug_probes -quiet -force top_module} + catch {file copy -force top_module.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module.vdi" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module.vdi" new file mode 100644 index 00000000..b86487e1 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module.vdi" @@ -0,0 +1,833 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Sat Oct 11 20:42:14 2025 +# Process ID: 8788 +# Current directory: C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1 +# Command line: vivado.exe -log top_module.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source top_module.tcl -notrace +# Log file: C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module.vdi +# Journal file: C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source top_module.tcl -notrace +Command: link_design -top top_module -part xc7a35tcsg324-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 603.691 ; gain = 0.000 +INFO: [Project 1-479] Netlist was created with Vivado 2019.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------系统时钟和复位------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:1] +WARNING: [Vivado 12-584] No ports matched 'sys_clk_in'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_rst_n'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:3] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:3] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------------------5个按键---------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:6] +WARNING: [Vivado 12-584] No ports matched 'btn_0'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:7] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:7] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_1'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:8] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:8] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_2'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:9] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:9] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_3'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:10] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:10] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_4'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:11] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:11] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_1_IBUF'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:14] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:14] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------拨码开关sw0~sw7----------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:17] +WARNING: [Vivado 12-584] No ports matched 'sw_pin[0]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:18] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:18] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[1]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:19] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:19] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[2]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:20] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:20] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[3]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:21] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:21] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[4]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:22] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:22] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[5]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:23] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:23] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[6]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:24] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:24] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[7]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:25] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:25] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//------------------------------------------拨码开关(DIP开关)sw8~sw15---------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:28] +WARNING: [Vivado 12-584] No ports matched 'dip_pin[0]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:29] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:29] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'dip_pin[1]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:30] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:30] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'dip_pin[2]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:31] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:31] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'dip_pin[3]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:32] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:32] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'dip_pin[4]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:33] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:33] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'dip_pin[5]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:34] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:34] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'dip_pin[6]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:35] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:35] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'dip_pin[7]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:36] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:36] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------LED0~LED15----------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:39] +WARNING: [Vivado 12-584] No ports matched 'led_pin[0]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:40] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:40] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[1]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:41] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:41] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[2]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:42] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:42] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[3]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:43] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:43] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[4]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:44] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:44] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[5]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:45] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:45] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[6]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:46] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:46] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[7]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:47] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:47] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[8]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:49] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[9]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:50] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:50] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[10]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:51] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:51] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[11]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:52] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:52] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[12]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:53] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:53] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[13]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:54] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:54] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[14]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:55] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:55] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[15]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:56] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:56] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------8个数码管位选信号-----------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:59] +WARNING: [Vivado 12-584] No ports matched 'seg_cs_pin[0]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:60] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:60] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_cs_pin[1]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:61] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:61] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_cs_pin[2]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:62] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:62] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_cs_pin[3]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:63] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:63] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_cs_pin[4]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:64] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:64] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_cs_pin[5]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:65] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:65] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_cs_pin[6]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:66] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:66] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_cs_pin[7]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:67] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:67] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------数码管段选信号---------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:69] +WARNING: [Vivado 12-584] No ports matched 'seg_data_0_pin[0]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:70] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:70] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_0_pin[1]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:71] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:71] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_0_pin[2]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:72] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:72] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_0_pin[3]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:73] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:73] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_0_pin[4]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:74] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:74] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_0_pin[5]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:75] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:75] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_0_pin[6]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:76] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:76] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_0_pin[7]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:77] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:77] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_1_pin[0]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:79] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:79] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_1_pin[1]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:80] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:80] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_1_pin[2]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:81] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:81] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_1_pin[3]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:82] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:82] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_1_pin[4]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:83] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:83] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_1_pin[5]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:84] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:84] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_1_pin[6]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:85] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:85] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_1_pin[7]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:86] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:86] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------VGA行同步场同步信号-----------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:89] +WARNING: [Vivado 12-584] No ports matched 'vga_hs_pin'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:90] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:90] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_vs_pin'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:91] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:91] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------VGA红绿蓝信号------------------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:94] +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[0]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:95] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:95] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[1]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:96] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:96] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[2]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:97] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:97] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[3]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:98] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:98] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[4]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:99] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:99] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[5]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:100] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:100] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[6]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:101] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:101] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[7]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:102] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:102] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[8]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:103] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:103] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[9]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:104] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:104] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[10]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:105] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:105] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[11]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:106] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:106] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------串口--------------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:109] +WARNING: [Vivado 12-584] No ports matched 'PC_Uart_rxd'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:110] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:110] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'PC_Uart_txd'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:111] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:111] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------------PS2接口-------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:114] +WARNING: [Vivado 12-584] No ports matched 'ps2_clk'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:115] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:115] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ps2_data'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:116] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:116] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//------------------------------------------------IIC接口---------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:119] +WARNING: [Vivado 12-584] No ports matched 'pw_iic_scl_io'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:120] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:120] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'pw_iic_sda_io'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:121] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:121] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------------蓝牙---------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:124] +WARNING: [Vivado 12-584] No ports matched 'BT_Uart_rxd'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:125] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:125] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'BT_Uart_txd'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:126] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:126] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'bt_ctrl_o[0]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:128] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:128] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'bt_ctrl_o[1]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:129] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:129] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'bt_ctrl_o[2]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:130] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:130] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'bt_ctrl_o[3]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:131] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:131] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'bt_ctrl_o[4]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:132] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:132] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'bt_mcu_int_i'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:134] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:134] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------------------------音频接口---------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:138] +WARNING: [Vivado 12-584] No ports matched 'audio_pwm_o'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:139] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:139] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'audio_sd_o'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:140] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:140] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------XADC模数转换-----------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:144] +WARNING: [Vivado 12-584] No ports matched 'XADC_AUX_v_n'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:145] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:145] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'XADC_AUX_v_p'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:146] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:146] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'XADC_VP_VN_v_n'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:147] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:147] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'XADC_VP_VN_v_p'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:148] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:148] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------DAC数模转换---------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:151] +WARNING: [Vivado 12-584] No ports matched 'dac_ile'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:152] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:152] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'dac_cs_n'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:153] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:153] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +INFO: [Common 17-14] Message 'Common 17-55' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:153] +WARNING: [Vivado 12-584] No ports matched 'dac_wr1_n'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:154] +INFO: [Common 17-14] Message 'Vivado 12-584' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:154] +CRITICAL WARNING: [Designutils 20-1307] Command '//-------------------------------------------------SDRAM芯片接口-------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:169] +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------32个pmod接口(扩展接口)-------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:216] +Finished Parsing XDC File [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 711.461 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 101 Warnings, 118 Critical Warnings and 0 Errors encountered. +link_design completed successfully +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.180 . Memory (MB): peak = 715.445 ; gain = 0.000 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 54760375 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1224.383 ; gain = 508.938 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 54760375 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1417.621 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 54760375 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1417.621 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 54760375 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1417.621 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. +INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. +INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). +Phase 4 BUFG optimization | Checksum: 54760375 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1417.621 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 54760375 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1417.621 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 54760375 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1417.621 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1417.621 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 54760375 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1417.621 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 54760375 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1417.621 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 54760375 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1417.621 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1417.621 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 54760375 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1417.621 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +27 Infos, 101 Warnings, 118 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1417.621 ; gain = 702.176 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1417.621 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +INFO: [Common 17-1381] The checkpoint 'C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file top_module_drc_opted.rpt -pb top_module_drc_opted.pb -rpx top_module_drc_opted.rpx +Command: report_drc -file top_module_drc_opted.rpt -pb top_module_drc_opted.pb -rpx top_module_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Vivado/Download/Vivado/2019.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1417.621 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 52d97d59 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1417.621 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1417.621 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 53514294 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.336 . Memory (MB): peak = 1424.492 ; gain = 6.871 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 12db9df35 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.406 . Memory (MB): peak = 1431.602 ; gain = 13.980 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 12db9df35 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.408 . Memory (MB): peak = 1431.602 ; gain = 13.980 +Phase 1 Placer Initialization | Checksum: 12db9df35 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.412 . Memory (MB): peak = 1431.602 ; gain = 13.980 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 12db9df35 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.416 . Memory (MB): peak = 1431.602 ; gain = 13.980 + +Phase 2.2 Global Placement Core +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2.2 Global Placement Core | Checksum: d58eb15d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.600 . Memory (MB): peak = 1431.602 ; gain = 13.980 +Phase 2 Global Placement | Checksum: d58eb15d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.602 . Memory (MB): peak = 1431.602 ; gain = 13.980 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: d58eb15d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.608 . Memory (MB): peak = 1431.602 ; gain = 13.980 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 6c85899d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.615 . Memory (MB): peak = 1431.602 ; gain = 13.980 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: d8351c59 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.620 . Memory (MB): peak = 1431.602 ; gain = 13.980 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: d8351c59 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.621 . Memory (MB): peak = 1431.602 ; gain = 13.980 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1c277f479 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.860 . Memory (MB): peak = 1431.602 ; gain = 13.980 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1c277f479 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.861 . Memory (MB): peak = 1431.602 ; gain = 13.980 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1c277f479 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.861 . Memory (MB): peak = 1431.602 ; gain = 13.980 +Phase 3 Detail Placement | Checksum: 1c277f479 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.862 . Memory (MB): peak = 1431.602 ; gain = 13.980 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1c277f479 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.863 . Memory (MB): peak = 1431.602 ; gain = 13.980 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1c277f479 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.868 . Memory (MB): peak = 1431.602 ; gain = 13.980 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1c277f479 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.869 . Memory (MB): peak = 1431.602 ; gain = 13.980 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1431.602 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: 1c277f479 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.870 . Memory (MB): peak = 1431.602 ; gain = 13.980 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1c277f479 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.870 . Memory (MB): peak = 1431.602 ; gain = 13.980 +Ending Placer Task | Checksum: 138d7b8de + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.870 . Memory (MB): peak = 1431.602 ; gain = 13.980 +INFO: [Common 17-83] Releasing license: Implementation +45 Infos, 102 Warnings, 118 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1431.602 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1432.602 ; gain = 1.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file top_module_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1432.602 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file top_module_utilization_placed.rpt -pb top_module_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file top_module_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1432.602 ; gain = 0.000 +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +53 Infos, 102 Warnings, 118 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1432.602 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1449.316 ; gain = 16.715 +INFO: [Common 17-1381] The checkpoint 'C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_physopt.dcp' has been generated. +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: e5fe3b85 ConstDB: 0 ShapeSum: 52d97d59 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 63ae15a2 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1540.301 ; gain = 79.953 +Post Restoration Checksum: NetGraph: 26fa8912 NumContArr: 3cb38c90 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 63ae15a2 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1546.316 ; gain = 85.969 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 63ae15a2 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1546.316 ; gain = 85.969 +Phase 2 Router Initialization | Checksum: 63ae15a2 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1547.609 ; gain = 87.262 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 5 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 5 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 10e8e424f + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1549.609 ; gain = 89.262 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 1c324b787 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1549.609 ; gain = 89.262 +Phase 4 Rip-up And Reroute | Checksum: 1c324b787 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1549.609 ; gain = 89.262 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 1c324b787 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1549.609 ; gain = 89.262 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 1c324b787 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1549.609 ; gain = 89.262 +Phase 6 Post Hold Fix | Checksum: 1c324b787 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1549.609 ; gain = 89.262 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.000478354 % + Global Horizontal Routing Utilization = 0.00130141 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 0.900901%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 1c324b787 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1549.609 ; gain = 89.262 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 1c324b787 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1551.680 ; gain = 91.332 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 17d4405ee + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1551.680 ; gain = 91.332 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1551.680 ; gain = 91.332 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +63 Infos, 102 Warnings, 118 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1551.680 ; gain = 102.363 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1551.680 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1561.543 ; gain = 9.863 +INFO: [Common 17-1381] The checkpoint 'C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file top_module_drc_routed.rpt -pb top_module_drc_routed.pb -rpx top_module_drc_routed.rpx +Command: report_drc -file top_module_drc_routed.rpt -pb top_module_drc_routed.pb -rpx top_module_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file top_module_methodology_drc_routed.rpt -pb top_module_methodology_drc_routed.pb -rpx top_module_methodology_drc_routed.rpx +Command: report_methodology -file top_module_methodology_drc_routed.rpt -pb top_module_methodology_drc_routed.pb -rpx top_module_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file top_module_power_routed.rpt -pb top_module_power_summary_routed.pb -rpx top_module_power_routed.rpx +Command: report_power -file top_module_power_routed.rpt -pb top_module_power_summary_routed.pb -rpx top_module_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +75 Infos, 103 Warnings, 118 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file top_module_route_status.rpt -pb top_module_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file top_module_timing_summary_routed.rpt -pb top_module_timing_summary_routed.pb -rpx top_module_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file top_module_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file top_module_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file top_module_bus_skew_routed.rpt -pb top_module_bus_skew_routed.pb -rpx top_module_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force top_module.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +ERROR: [DRC NSTD-1] Unspecified I/O Standard: 5 out of 5 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: switches[3:0], and led. +ERROR: [DRC UCIO-1] Unconstrained Logical Port: 5 out of 5 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: switches[3:0], and led. +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 2 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. +INFO: [Common 17-83] Releasing license: Implementation +91 Infos, 105 Warnings, 118 Critical Warnings and 3 Errors encountered. +write_bitstream failed +ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors. + +INFO: [Common 17-206] Exiting Vivado at Sat Oct 11 20:42:46 2025... diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_bus_skew_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_bus_skew_routed.pb" new file mode 100644 index 00000000..3390588d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_bus_skew_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_bus_skew_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_bus_skew_routed.rpt" new file mode 100644 index 00000000..78d8c3df --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_bus_skew_routed.rpt" @@ -0,0 +1,15 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sat Oct 11 20:42:46 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file top_module_bus_skew_routed.rpt -pb top_module_bus_skew_routed.pb -rpx top_module_bus_skew_routed.rpx +| Design : top_module +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +--------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_bus_skew_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_bus_skew_routed.rpx" new file mode 100644 index 00000000..c310931a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_bus_skew_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_clock_utilization_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_clock_utilization_routed.rpt" new file mode 100644 index 00000000..242c0c7b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_clock_utilization_routed.rpt" @@ -0,0 +1,93 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sat Oct 11 20:42:46 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_clock_utilization -file top_module_clock_utilization_routed.rpt +| Design : top_module +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +---------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 0 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_control_sets_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_control_sets_placed.rpt" new file mode 100644 index 00000000..8e5a639b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_control_sets_placed.rpt" @@ -0,0 +1,77 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sat Oct 11 20:42:32 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file top_module_control_sets_placed.rpt +| Design : top_module +| Device : xc7a35t +--------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Total control sets | 0 | +| Minimum number of control sets | 0 | +| Addition due to synthesis replication | 0 | +| Addition due to physical synthesis replication | 0 | +| Unused register locations in slices containing registers | 0 | ++----------------------------------------------------------+-------+ +* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers +** Run report_qor_suggestions for automated merging and remapping suggestions + + +2. Histogram +------------ + ++--------------------+-------+ +| Fanout | Count | ++--------------------+-------+ +| Total control sets | 0 | +| >= 0 to < 4 | 0 | +| >= 4 to < 6 | 0 | +| >= 6 to < 8 | 0 | +| >= 8 to < 10 | 0 | +| >= 10 to < 12 | 0 | +| >= 12 to < 14 | 0 | +| >= 14 to < 16 | 0 | +| >= 16 | 0 | ++--------------------+-------+ +* Control sets can be remapped at either synth_design or opt_design + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++--------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++--------------+---------------+------------------+------------------+----------------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_opted.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_opted.pb" new file mode 100644 index 00000000..0158a2ad Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_opted.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_opted.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_opted.rpt" new file mode 100644 index 00000000..309d4548 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_opted.rpt" @@ -0,0 +1,61 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sat Oct 11 20:42:30 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_drc -file top_module_drc_opted.rpt -pb top_module_drc_opted.pb -rpx top_module_drc_opted.rpx +| Design : top_module +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 3 ++----------+------------------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+------------------+-----------------------------------------------------+------------+ +| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | +| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+------------------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +NSTD-1#1 Critical Warning +Unspecified I/O Standard +5 out of 5 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: switches[3:0], led. +Related violations: + +UCIO-1#1 Critical Warning +Unconstrained Logical Port +5 out of 5 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: switches[3:0], led. +Related violations: + +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_opted.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_opted.rpx" new file mode 100644 index 00000000..3a5c8a8b Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_opted.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_routed.pb" new file mode 100644 index 00000000..0158a2ad Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_routed.rpt" new file mode 100644 index 00000000..d6c13362 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_routed.rpt" @@ -0,0 +1,61 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sat Oct 11 20:42:45 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_drc -file top_module_drc_routed.rpt -pb top_module_drc_routed.pb -rpx top_module_drc_routed.rpx +| Design : top_module +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Fully Routed +------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 3 ++----------+------------------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+------------------+-----------------------------------------------------+------------+ +| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | +| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+------------------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +NSTD-1#1 Critical Warning +Unspecified I/O Standard +5 out of 5 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: switches[3:0], led. +Related violations: + +UCIO-1#1 Critical Warning +Unconstrained Logical Port +5 out of 5 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: switches[3:0], led. +Related violations: + +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_routed.rpx" new file mode 100644 index 00000000..c8582bcb Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_drc_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_io_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_io_placed.rpt" new file mode 100644 index 00000000..341d8a9c --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_io_placed.rpt" @@ -0,0 +1,366 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sat Oct 11 20:42:32 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_io -file top_module_io_placed.rpt +| Design : top_module +| Device : xc7a35t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2013-12-19 +| Package Pin Delay Version : VERS. 2.0 2013-12-19 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 5 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M4 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| N4 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| P3 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P4 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P5 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | +| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| R2 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| R10 | led | High Range | IO_25_14 | OUTPUT | LVCMOS18* | 14 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| T9 | switches[1] | High Range | IO_L24P_T3_A01_D17_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| T10 | switches[0] | High Range | IO_L24N_T3_A00_D16_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | +| T13 | switches[3] | High Range | IO_L23P_T3_A03_D19_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | switches[2] | High Range | IO_L23N_T3_A02_D18_14 | INPUT | LVCMOS18* | 14 | | | | NONE | | UNFIXED | | | | NONE | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 1.80 | | | | | | | | | ++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_methodology_drc_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_methodology_drc_routed.pb" new file mode 100644 index 00000000..210b56b2 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_methodology_drc_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_methodology_drc_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_methodology_drc_routed.rpt" new file mode 100644 index 00000000..1b76a78a --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_methodology_drc_routed.rpt" @@ -0,0 +1,34 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sat Oct 11 20:42:45 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_methodology -file top_module_methodology_drc_routed.rpt -pb top_module_methodology_drc_routed.pb -rpx top_module_methodology_drc_routed.rpx +| Design : top_module +| Device : xc7a35tcsg324-1 +| Speed File : -1 +| Design State : Fully Routed +-------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 0 ++------+----------+-------------+------------+ +| Rule | Severity | Description | Violations | ++------+----------+-------------+------------+ ++------+----------+-------------+------------+ + +2. REPORT DETAILS +----------------- + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_methodology_drc_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_methodology_drc_routed.rpx" new file mode 100644 index 00000000..e4ce3e76 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_methodology_drc_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_opt.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_opt.dcp" new file mode 100644 index 00000000..b754fe5a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_opt.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_physopt.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_physopt.dcp" new file mode 100644 index 00000000..830bfa48 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_physopt.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_placed.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_placed.dcp" new file mode 100644 index 00000000..fae84c8a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_placed.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_power_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_power_routed.rpt" new file mode 100644 index 00000000..4c29c0e8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_power_routed.rpt" @@ -0,0 +1,141 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sat Oct 11 20:42:45 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_power -file top_module_power_routed.rpt -pb top_module_power_summary_routed.pb -rpx top_module_power_routed.rpx +| Design : top_module +| Device : xc7a35tcsg324-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.425 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.354 | +| Device Static (W) | 0.071 | +| Effective TJA (C/W) | 4.8 | +| Max Ambient (C) | 83.0 | +| Junction Temperature (C) | 27.0 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.003 | 1 | --- | --- | +| LUT as Logic | 0.003 | 1 | 20800 | <0.01 | +| Signals | 0.014 | 5 | --- | --- | +| I/O | 0.337 | 5 | 210 | 2.38 | +| Static Power | 0.071 | | | | +| Total | 0.425 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.043 | 0.033 | 0.010 | +| Vccaux | 1.800 | 0.039 | 0.026 | 0.013 | +| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.153 | 0.152 | 0.001 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.8 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++------------+-----------+ +| Name | Power (W) | ++------------+-----------+ +| top_module | 0.354 | +| uut | 0.007 | ++------------+-----------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_power_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_power_routed.rpx" new file mode 100644 index 00000000..46c072cd Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_power_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_power_summary_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_power_summary_routed.pb" new file mode 100644 index 00000000..94bb58c5 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_power_summary_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_route_status.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_route_status.pb" new file mode 100644 index 00000000..0ca4a85c Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_route_status.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_route_status.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_route_status.rpt" new file mode 100644 index 00000000..861acdd3 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_route_status.rpt" @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 10 : + # of nets not needing routing.......... : 5 : + # of internally routed nets........ : 5 : + # of routable nets..................... : 5 : + # of fully routed nets............. : 5 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_routed.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_routed.dcp" new file mode 100644 index 00000000..24a5513c Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_routed.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_timing_summary_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_timing_summary_routed.pb" new file mode 100644 index 00000000..4526e931 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_timing_summary_routed.pb" @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_timing_summary_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_timing_summary_routed.rpt" new file mode 100644 index 00000000..8ee07468 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_timing_summary_routed.rpt" @@ -0,0 +1,175 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sat Oct 11 20:42:46 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file top_module_timing_summary_routed.rpt -pb top_module_timing_summary_routed.pb -rpx top_module_timing_summary_routed.rpx -warn_on_violation +| Design : top_module +| Device : 7a35t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 0 register/latch pins with no clock. + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 0 ports with no output delay specified. + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_timing_summary_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_timing_summary_routed.rpx" new file mode 100644 index 00000000..59eab4c2 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_timing_summary_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_utilization_placed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_utilization_placed.pb" new file mode 100644 index 00000000..61b08f81 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_utilization_placed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_utilization_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_utilization_placed.rpt" new file mode 100644 index 00000000..f4a086c6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module_utilization_placed.rpt" @@ -0,0 +1,196 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sat Oct 11 20:42:32 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_utilization -file top_module_utilization_placed.rpt -pb top_module_utilization_placed.pb +| Design : top_module +| Device : 7a35tcsg324-1 +| Design State : Fully Placed +----------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 1 | 0 | 20800 | <0.01 | +| LUT as Logic | 1 | 0 | 20800 | <0.01 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 0 | 0 | 41600 | 0.00 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------------------------------------+------+-------+-----------+-------+ +| Slice | 1 | 0 | 8150 | 0.01 | +| SLICEL | 1 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 1 | 0 | 20800 | <0.01 | +| using O5 output only | 0 | | | | +| using O6 output only | 1 | | | | +| using O5 and O6 | 0 | | | | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 0 | 0 | 41600 | 0.00 | +| Register driven from within the Slice | 0 | | | | +| Register driven from outside the Slice | 0 | | | | +| Unique Control Sets | 0 | | 8150 | 0.00 | ++------------------------------------------+------+-------+-----------+-------+ +* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 5 | 0 | 210 | 2.38 | +| IOB Master Pads | 2 | | | | +| IOB Slave Pads | 2 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| IBUF | 4 | IO | +| OBUF | 1 | IO | +| LUT4 | 1 | LUT | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/vivado.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/vivado.jou" new file mode 100644 index 00000000..f747d4f9 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/vivado.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Sat Oct 11 20:42:14 2025 +# Process ID: 8788 +# Current directory: C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1 +# Command line: vivado.exe -log top_module.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source top_module.tcl -notrace +# Log file: C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/top_module.vdi +# Journal file: C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source top_module.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/vivado.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/vivado.pb" new file mode 100644 index 00000000..b155e40f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/vivado.pb" @@ -0,0 +1,4 @@ + + + +End Record \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/write_bitstream.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/write_bitstream.pb" new file mode 100644 index 00000000..78b0f0fc Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/impl_1/write_bitstream.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/.Vivado_Synthesis.queue.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/.Vivado_Synthesis.queue.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/.vivado.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/.vivado.begin.rst" new file mode 100644 index 00000000..b9fae81e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/.vivado.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/.vivado.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/.vivado.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/ISEWrap.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/ISEWrap.js" new file mode 100644 index 00000000..97a2ecbc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/ISEWrap.js" @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/ISEWrap.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/ISEWrap.sh" new file mode 100644 index 00000000..f679f2e8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/ISEWrap.sh" @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/__synthesis_is_complete__" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/__synthesis_is_complete__" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/gen_run.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/gen_run.xml" new file mode 100644 index 00000000..1cd29a23 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/gen_run.xml" @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/htr.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/htr.txt" new file mode 100644 index 00000000..f992c150 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/htr.txt" @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log top_module.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_module.tcl diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/rundef.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/rundef.js" new file mode 100644 index 00000000..17c05fec --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/rundef.js" @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Vivado/Download/Vivado/2019.2/bin;"; +} else { + PathVal = "D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Vivado/Download/Vivado/2019.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log top_module.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_module.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/runme.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/runme.bat" new file mode 100644 index 00000000..1760626b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/runme.bat" @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/runme.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/runme.sh" new file mode 100644 index 00000000..2491ee94 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/runme.sh" @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Vivado/Download/Vivado/2019.2/bin +else + PATH=D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Vivado/Download/Vivado/2019.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log top_module.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_module.tcl diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module.dcp" new file mode 100644 index 00000000..7a237bc4 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module.tcl" new file mode 100644 index 00000000..2640af10 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module.tcl" @@ -0,0 +1,54 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +create_project -in_memory -part xc7a35tcsg324-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.cache/wt [current_project] +set_property parent.project_path C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo c:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.v +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc +set_property used_in_implementation false [get_files C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc] + +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +synth_design -top top_module -part xc7a35tcsg324-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef top_module.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file top_module_utilization_synth.rpt -pb top_module_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module.vds" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module.vds" new file mode 100644 index 00000000..9ed060da --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module.vds" @@ -0,0 +1,583 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Sat Oct 11 20:41:41 2025 +# Process ID: 23292 +# Current directory: C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1 +# Command line: vivado.exe -log top_module.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_module.tcl +# Log file: C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module.vds +# Journal file: C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source top_module.tcl -notrace +Command: synth_design -top top_module -part xc7a35tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Device 21-403] Loading part xc7a35tcsg324-1 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 11244 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 835.020 ; gain = 233.094 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'top_module' [C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.v:19] +INFO: [Synth 8-6157] synthesizing module 'blood_compatibility_structural' [C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.v:1] +INFO: [Synth 8-6155] done synthesizing module 'blood_compatibility_structural' (1#1) [C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.v:1] +INFO: [Synth 8-6155] done synthesizing module 'top_module' (2#1) [C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.v:19] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 907.633 ; gain = 305.707 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 907.633 ; gain = 305.707 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 907.633 ; gain = 305.707 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 907.633 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------系统时钟和复位------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:1] +WARNING: [Vivado 12-584] No ports matched 'sys_clk_in'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_rst_n'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:3] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:3] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------------------5个按键---------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:6] +WARNING: [Vivado 12-584] No ports matched 'btn_0'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:7] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:7] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_1'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:8] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:8] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_2'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:9] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:9] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_3'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:10] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:10] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_4'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:11] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:11] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_1_IBUF'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:14] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:14] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------拨码开关sw0~sw7----------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:17] +WARNING: [Vivado 12-584] No ports matched 'sw_pin[0]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:18] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:18] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[1]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:19] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:19] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[2]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:20] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:20] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[3]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:21] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:21] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[4]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:22] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:22] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[5]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:23] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:23] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[6]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:24] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:24] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[7]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:25] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:25] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//------------------------------------------拨码开关(DIP开关)sw8~sw15---------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:28] +WARNING: [Vivado 12-584] No ports matched 'dip_pin[0]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:29] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:29] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'dip_pin[1]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:30] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:30] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'dip_pin[2]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:31] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:31] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'dip_pin[3]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:32] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:32] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'dip_pin[4]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:33] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:33] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'dip_pin[5]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:34] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:34] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'dip_pin[6]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:35] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:35] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'dip_pin[7]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:36] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:36] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------LED0~LED15----------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:39] +WARNING: [Vivado 12-584] No ports matched 'led_pin[0]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:40] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:40] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[1]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:41] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:41] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[2]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:42] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:42] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[3]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:43] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:43] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[4]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:44] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:44] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[5]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:45] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:45] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[6]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:46] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:46] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[7]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:47] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:47] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[8]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:49] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[9]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:50] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:50] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[10]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:51] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:51] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[11]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:52] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:52] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[12]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:53] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:53] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[13]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:54] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:54] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[14]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:55] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:55] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[15]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:56] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:56] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------8个数码管位选信号-----------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:59] +WARNING: [Vivado 12-584] No ports matched 'seg_cs_pin[0]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:60] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:60] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_cs_pin[1]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:61] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:61] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_cs_pin[2]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:62] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:62] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_cs_pin[3]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:63] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:63] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_cs_pin[4]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:64] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:64] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_cs_pin[5]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:65] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:65] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_cs_pin[6]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:66] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:66] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_cs_pin[7]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:67] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:67] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------数码管段选信号---------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:69] +WARNING: [Vivado 12-584] No ports matched 'seg_data_0_pin[0]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:70] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:70] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_0_pin[1]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:71] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:71] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_0_pin[2]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:72] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:72] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_0_pin[3]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:73] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:73] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_0_pin[4]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:74] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:74] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_0_pin[5]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:75] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:75] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_0_pin[6]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:76] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:76] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_0_pin[7]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:77] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:77] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_1_pin[0]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:79] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:79] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_1_pin[1]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:80] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:80] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_1_pin[2]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:81] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:81] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_1_pin[3]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:82] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:82] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_1_pin[4]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:83] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:83] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_1_pin[5]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:84] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:84] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_1_pin[6]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:85] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:85] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'seg_data_1_pin[7]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:86] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:86] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------VGA行同步场同步信号-----------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:89] +WARNING: [Vivado 12-584] No ports matched 'vga_hs_pin'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:90] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:90] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_vs_pin'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:91] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:91] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------VGA红绿蓝信号------------------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:94] +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[0]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:95] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:95] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[1]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:96] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:96] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[2]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:97] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:97] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[3]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:98] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:98] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[4]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:99] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:99] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[5]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:100] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:100] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[6]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:101] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:101] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[7]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:102] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:102] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[8]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:103] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:103] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[9]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:104] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:104] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[10]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:105] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:105] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'vga_data_pin[11]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:106] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:106] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------串口--------------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:109] +WARNING: [Vivado 12-584] No ports matched 'PC_Uart_rxd'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:110] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:110] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'PC_Uart_txd'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:111] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:111] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------------PS2接口-------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:114] +WARNING: [Vivado 12-584] No ports matched 'ps2_clk'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:115] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:115] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ps2_data'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:116] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:116] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//------------------------------------------------IIC接口---------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:119] +WARNING: [Vivado 12-584] No ports matched 'pw_iic_scl_io'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:120] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:120] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'pw_iic_sda_io'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:121] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:121] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------------蓝牙---------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:124] +WARNING: [Vivado 12-584] No ports matched 'BT_Uart_rxd'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:125] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:125] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'BT_Uart_txd'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:126] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:126] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'bt_ctrl_o[0]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:128] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:128] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'bt_ctrl_o[1]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:129] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:129] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'bt_ctrl_o[2]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:130] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:130] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'bt_ctrl_o[3]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:131] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:131] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'bt_ctrl_o[4]'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:132] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:132] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'bt_mcu_int_i'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:134] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:134] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------------------------音频接口---------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:138] +WARNING: [Vivado 12-584] No ports matched 'audio_pwm_o'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:139] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:139] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'audio_sd_o'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:140] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:140] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------XADC模数转换-----------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:144] +WARNING: [Vivado 12-584] No ports matched 'XADC_AUX_v_n'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:145] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:145] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'XADC_AUX_v_p'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:146] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:146] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'XADC_VP_VN_v_n'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:147] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:147] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'XADC_VP_VN_v_p'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:148] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:148] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------DAC数模转换---------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:151] +WARNING: [Vivado 12-584] No ports matched 'dac_ile'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:152] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:152] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'dac_cs_n'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:153] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:153] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'dac_wr1_n'. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:154] +INFO: [Common 17-14] Message 'Vivado 12-584' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:154] +CRITICAL WARNING: [Designutils 20-1307] Command '//-------------------------------------------------SDRAM芯片接口-------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:169] +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------32个pmod接口(扩展接口)-------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc:216] +Finished Parsing XDC File [C:/Users/21211/Desktop/example_4_12b_EGO1/EGO1.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 952.266 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 957.348 ; gain = 5.082 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:10 . Memory (MB): peak = 957.348 ; gain = 355.422 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:10 . Memory (MB): peak = 957.348 ; gain = 355.422 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:10 . Memory (MB): peak = 957.348 ; gain = 355.422 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 957.348 ; gain = 355.422 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 957.348 ; gain = 355.422 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 972.895 ; gain = 370.969 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 972.895 ; gain = 370.969 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 982.703 ; gain = 380.777 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 997.527 ; gain = 395.602 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 997.527 ; gain = 395.602 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 997.527 ; gain = 395.602 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 997.527 ; gain = 395.602 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 997.527 ; gain = 395.602 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 997.527 ; gain = 395.602 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT4 | 1| +|2 |IBUF | 4| +|3 |OBUF | 1| ++------+-----+------+ + +Report Instance Areas: ++------+---------+-------------------------------+------+ +| |Instance |Module |Cells | ++------+---------+-------------------------------+------+ +|1 |top | | 6| +|2 | uut |blood_compatibility_structural | 1| ++------+---------+-------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 997.527 ; gain = 395.602 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 997.527 ; gain = 345.887 +Synthesis Optimization Complete : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 997.527 ; gain = 395.602 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 997.527 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1008.664 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +14 Infos, 102 Warnings, 118 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1008.664 ; gain = 701.242 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1008.664 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file top_module_utilization_synth.rpt -pb top_module_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Sat Oct 11 20:42:07 2025... diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module_utilization_synth.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module_utilization_synth.pb" new file mode 100644 index 00000000..61b08f81 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module_utilization_synth.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module_utilization_synth.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module_utilization_synth.rpt" new file mode 100644 index 00000000..9fce4338 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module_utilization_synth.rpt" @@ -0,0 +1,170 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sat Oct 11 20:42:07 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_utilization -file top_module_utilization_synth.rpt -pb top_module_utilization_synth.pb +| Design : top_module +| Device : 7a35tcsg324-1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 1 | 0 | 20800 | <0.01 | +| LUT as Logic | 1 | 0 | 20800 | <0.01 | +| LUT as Memory | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 0 | 0 | 41600 | 0.00 | +| Register as Flip Flop | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 5 | 0 | 210 | 2.38 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 20 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| IBUF | 4 | IO | +| OBUF | 1 | IO | +| LUT4 | 1 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/vivado.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/vivado.jou" new file mode 100644 index 00000000..a9b2b2ef --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/vivado.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Sat Oct 11 20:41:41 2025 +# Process ID: 23292 +# Current directory: C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1 +# Command line: vivado.exe -log top_module.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source top_module.tcl +# Log file: C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/top_module.vds +# Journal file: C:/Users/21211/Desktop/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source top_module.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/vivado.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/vivado.pb" new file mode 100644 index 00000000..ede1b007 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.runs/synth_1/vivado.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.v" new file mode 100644 index 00000000..f7f5a0b2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.v" @@ -0,0 +1,32 @@ +module blood_compatibility_structural( + input donor_type1, + input donor_type0, + input recipient_type1, + input recipient_type0, + output compatibility +); + +wire w1, w2, w3, w4; + +not u1(w1,donor_type0); +not u2(w2,donor_type1); +nor u3(w3,recipient_type0,w1); +nor u4(w4,recipient_type1,w2); +nor u5(compatibility,w3,w4); + +endmodule + +module top_module( + input [7:0] sw_pin, + output [15:0] led_pin +); + +blood_compatibility_structural uut( + .donor_type1(sw_pin[1]), + .donor_type0(sw_pin[0]), + .recipient_type1(sw_pin[7]), + .recipient_type0(sw_pin[6]), + .compatibility(led_pin[0]) +); + +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.xpr" new file mode 100644 index 00000000..05ab59aa --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_12b_EGO1/example_4_12b_EGO1.xpr" @@ -0,0 +1,184 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/EGO1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/EGO1.xdc" new file mode 100644 index 00000000..6ae3adfe --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/EGO1.xdc" @@ -0,0 +1,250 @@ +//----------------------------------------------系统时钟和复位------------------------------------ +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports sys_clk_in] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports sys_rst_n] + + +//-----------------------------------------------5个按键--------------------------------------------- +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports btn_4] + + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] + + +//---------------------------------------------拨码开关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + +//------------------------------------------拨码开关(DIP开关)sw8~sw15--------------------- +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[0]}] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[1]}] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[2]}] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[3]}] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports {dip_pin[4]}] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[5]}] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[6]}] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[7]}] + + +//---------------------------------------------LED0~LED15---------------------------------------- +set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN G3 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {led_pin[8]}] +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {led_pin[9]}] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led_pin[10]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led_pin[11]}] +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {led_pin[12]}] +set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports {led_pin[13]}] +set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports {led_pin[14]}] +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {led_pin[15]}] + + +//-----------------------------------8个数码管位选信号----------------------------------------------- +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[0]}] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[1]}] +set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[2]}] +set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[3]}] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[4]}] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[5]}] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[6]}] +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[7]}] + +//--------------------------------------------数码管段选信号--------------------------------------------- +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[0]}] +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[1]}] +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[2]}] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[3]}] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[4]}] +set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[5]}] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[6]}] +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[7]}] + +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[0]}] +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[1]}] +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[2]}] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[3]}] +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[4]}] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[5]}] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[6]}] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[7]}] + + +//--------------------------------------VGA行同步场同步信号----------------------------------------------- +set_property -dict {PACKAGE_PIN D7 IOSTANDARD LVCMOS33} [get_ports vga_hs_pin] +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports vga_vs_pin] + + +//--------------------------------------VGA红绿蓝信号------------------------------------------------------ +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[0]}] +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[1]}] +set_property -dict {PACKAGE_PIN C5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[2]}] +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[3]}] +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[4]}] +set_property -dict {PACKAGE_PIN A6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[5]}] +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[6]}] +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[7]}] +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[8]}] +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[9]}] +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[10]}] +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[11]}] + + +//----------------------------------------------串口-------------------------------------------------- +set_property -dict {PACKAGE_PIN N5 IOSTANDARD LVCMOS33} [get_ports PC_Uart_rxd] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports PC_Uart_txd] + + +//---------------------------------------------------PS2接口------------------------------------- +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports ps2_clk] +set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports ps2_data] + + +//------------------------------------------------IIC接口--------------------------------------------- +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports pw_iic_scl_io] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports pw_iic_sda_io] + + +//---------------------------------------------------蓝牙--------------------------------------------- +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports BT_Uart_rxd] +set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports BT_Uart_txd] + +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[0]}] +set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[1]}] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[2]}] +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[3]}] +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[4]}] + +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports bt_mcu_int_i] + + + +//-----------------------------------------------------音频接口--------------------------------------- +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports audio_pwm_o] +set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports audio_sd_o ] + + + +//--------------------------------------------------------XADC模数转换----------------------------------- +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_n] +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_p] +set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_n] +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_p] + + +//--------------------------------------------------------DAC数模转换--------------------------- +set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports dac_ile] +set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports dac_cs_n] +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports dac_wr1_n] +set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports dac_wr2_n] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports dac_xfer_n] + +set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS33} [get_ports {dac_data[0]}] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33} [get_ports {dac_data[1]}] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports {dac_data[2]}] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports {dac_data[3]}] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {dac_data[4]}] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {dac_data[5]}] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports {dac_data[6]}] +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports {dac_data[7]}] + + + +//-------------------------------------------------SDRAM芯片接口------------------------------------- +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[18]}] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[17]}] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[16]}] +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[15]}] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {sram_addr[14]}] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[13]}] +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[12]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[11]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[10]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[9]}] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[8]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[7]}] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[6]}] +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[5]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[4]}] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[3]}] +set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[2]}] +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[1]}] +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[0]}] + +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports sram_ce_n] +set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports sram_lb_n] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports sram_oe_n] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports sram_ub_n] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports sram_we_n] + +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {sram_data[15]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {sram_data[14]}] +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {sram_data[13]}] +set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS33} [get_ports {sram_data[12]}] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {sram_data[11]}] +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {sram_data[10]}] +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {sram_data[9]}] +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {sram_data[8]}] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {sram_data[7]}] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {sram_data[6]}] +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {sram_data[5]}] +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {sram_data[4]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {sram_data[3]}] +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {sram_data[2]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {sram_data[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {sram_data[0]}] + + + + +//--------------------------------------32个pmod接口(扩展接口)------------------------------- +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {exp_io[0]}] +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports {exp_io[1]}] +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports {exp_io[2]}] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS33} [get_ports {exp_io[3]}] +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {exp_io[4]}] +set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports {exp_io[5]}] +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports {exp_io[6]}] +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {exp_io[7]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {exp_io[8]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {exp_io[9]}] +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports {exp_io[10]}] +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {exp_io[11]}] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {exp_io[12]}] +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {exp_io[13]}] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {exp_io[14]}] +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {exp_io[15]}] + +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {exp_io[16]}] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {exp_io[17]}] +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports {exp_io[18]}] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {exp_io[19]}] +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports {exp_io[20]}] +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports {exp_io[21]}] +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports {exp_io[22]}] +set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {exp_io[23]}] +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {exp_io[24]}] +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {exp_io[25]}] +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {exp_io[26]}] +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports {exp_io[27]}] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {exp_io[28]}] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {exp_io[29]}] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {exp_io[30]}] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {exp_io[31]}] + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..3e1f2ec7 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,13 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f6f725f6372656174655f636f6e73747261696e745f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:39:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f77696e646f77:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e77696e6d656e756d67725f6c61796f7574:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 +eof:3133682371 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..37728e9e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,4 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +eof:2411667182 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..6888edec --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:2 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..b021ec31 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,43 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.hw/example_4_17_1_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.hw/example_4_17_1_EGO1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.hw/example_4_17_1_EGO1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.v" new file mode 100644 index 00000000..be451296 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.v" @@ -0,0 +1,54 @@ +module logic_circuit_pre_dataflow( + input a, + input b, + input c, + input d, + output f_pre +); + +assign f_pre = ~a & c | b & ~c & d | a & ~b & ~c; + +endmodule + +module top_module_pre_dataflow( + input [7:0] sw_pin, + output [15:0] led_pin +); + +logic_circuit_pre_dataflow uut( + .a(sw_pin[0]), + .b(sw_pin[1]), + .c(sw_pin[2]), + .d(sw_pin[3]), + .f_pre(led_pin[0]) +); + +endmodule + + +module logic_circuit_post_dataflow( + input a, + input b, + input c, + input d, + output f_post +); + +assign f_post = ~a & c | b & ~c & d | a & ~b & ~c | ~a & b & d | a & ~c & d; + +endmodule + +module top_module_post_dataflow( + input [7:0] sw_pin, + output [15:0] led_pin +); + +logic_circuit_post_dataflow uut( + .a(sw_pin[0]), + .b(sw_pin[1]), + .c(sw_pin[2]), + .d(sw_pin[3]), + .f_post(led_pin[7]) +); + +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.xpr" new file mode 100644 index 00000000..24a469c0 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_1_EGO1/example_4_17_1_EGO1.xpr" @@ -0,0 +1,185 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/EGO1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/EGO1.xdc" new file mode 100644 index 00000000..6ae3adfe --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/EGO1.xdc" @@ -0,0 +1,250 @@ +//----------------------------------------------系统时钟和复位------------------------------------ +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports sys_clk_in] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports sys_rst_n] + + +//-----------------------------------------------5个按键--------------------------------------------- +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports btn_4] + + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] + + +//---------------------------------------------拨码开关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + +//------------------------------------------拨码开关(DIP开关)sw8~sw15--------------------- +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[0]}] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[1]}] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[2]}] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[3]}] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports {dip_pin[4]}] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[5]}] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[6]}] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[7]}] + + +//---------------------------------------------LED0~LED15---------------------------------------- +set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN G3 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {led_pin[8]}] +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {led_pin[9]}] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led_pin[10]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led_pin[11]}] +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {led_pin[12]}] +set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports {led_pin[13]}] +set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports {led_pin[14]}] +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {led_pin[15]}] + + +//-----------------------------------8个数码管位选信号----------------------------------------------- +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[0]}] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[1]}] +set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[2]}] +set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[3]}] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[4]}] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[5]}] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[6]}] +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[7]}] + +//--------------------------------------------数码管段选信号--------------------------------------------- +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[0]}] +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[1]}] +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[2]}] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[3]}] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[4]}] +set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[5]}] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[6]}] +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[7]}] + +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[0]}] +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[1]}] +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[2]}] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[3]}] +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[4]}] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[5]}] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[6]}] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[7]}] + + +//--------------------------------------VGA行同步场同步信号----------------------------------------------- +set_property -dict {PACKAGE_PIN D7 IOSTANDARD LVCMOS33} [get_ports vga_hs_pin] +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports vga_vs_pin] + + +//--------------------------------------VGA红绿蓝信号------------------------------------------------------ +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[0]}] +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[1]}] +set_property -dict {PACKAGE_PIN C5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[2]}] +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[3]}] +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[4]}] +set_property -dict {PACKAGE_PIN A6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[5]}] +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[6]}] +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[7]}] +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[8]}] +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[9]}] +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[10]}] +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[11]}] + + +//----------------------------------------------串口-------------------------------------------------- +set_property -dict {PACKAGE_PIN N5 IOSTANDARD LVCMOS33} [get_ports PC_Uart_rxd] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports PC_Uart_txd] + + +//---------------------------------------------------PS2接口------------------------------------- +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports ps2_clk] +set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports ps2_data] + + +//------------------------------------------------IIC接口--------------------------------------------- +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports pw_iic_scl_io] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports pw_iic_sda_io] + + +//---------------------------------------------------蓝牙--------------------------------------------- +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports BT_Uart_rxd] +set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports BT_Uart_txd] + +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[0]}] +set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[1]}] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[2]}] +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[3]}] +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[4]}] + +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports bt_mcu_int_i] + + + +//-----------------------------------------------------音频接口--------------------------------------- +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports audio_pwm_o] +set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports audio_sd_o ] + + + +//--------------------------------------------------------XADC模数转换----------------------------------- +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_n] +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_p] +set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_n] +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_p] + + +//--------------------------------------------------------DAC数模转换--------------------------- +set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports dac_ile] +set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports dac_cs_n] +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports dac_wr1_n] +set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports dac_wr2_n] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports dac_xfer_n] + +set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS33} [get_ports {dac_data[0]}] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33} [get_ports {dac_data[1]}] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports {dac_data[2]}] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports {dac_data[3]}] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {dac_data[4]}] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {dac_data[5]}] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports {dac_data[6]}] +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports {dac_data[7]}] + + + +//-------------------------------------------------SDRAM芯片接口------------------------------------- +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[18]}] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[17]}] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[16]}] +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[15]}] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {sram_addr[14]}] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[13]}] +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[12]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[11]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[10]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[9]}] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[8]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[7]}] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[6]}] +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[5]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[4]}] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[3]}] +set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[2]}] +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[1]}] +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[0]}] + +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports sram_ce_n] +set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports sram_lb_n] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports sram_oe_n] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports sram_ub_n] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports sram_we_n] + +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {sram_data[15]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {sram_data[14]}] +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {sram_data[13]}] +set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS33} [get_ports {sram_data[12]}] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {sram_data[11]}] +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {sram_data[10]}] +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {sram_data[9]}] +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {sram_data[8]}] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {sram_data[7]}] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {sram_data[6]}] +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {sram_data[5]}] +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {sram_data[4]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {sram_data[3]}] +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {sram_data[2]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {sram_data[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {sram_data[0]}] + + + + +//--------------------------------------32个pmod接口(扩展接口)------------------------------- +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {exp_io[0]}] +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports {exp_io[1]}] +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports {exp_io[2]}] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS33} [get_ports {exp_io[3]}] +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {exp_io[4]}] +set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports {exp_io[5]}] +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports {exp_io[6]}] +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {exp_io[7]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {exp_io[8]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {exp_io[9]}] +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports {exp_io[10]}] +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {exp_io[11]}] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {exp_io[12]}] +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {exp_io[13]}] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {exp_io[14]}] +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {exp_io[15]}] + +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {exp_io[16]}] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {exp_io[17]}] +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports {exp_io[18]}] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {exp_io[19]}] +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports {exp_io[20]}] +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports {exp_io[21]}] +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports {exp_io[22]}] +set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {exp_io[23]}] +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {exp_io[24]}] +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {exp_io[25]}] +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {exp_io[26]}] +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports {exp_io[27]}] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {exp_io[28]}] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {exp_io[29]}] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {exp_io[30]}] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {exp_io[31]}] + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..c7ec4295 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,15 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f6f725f6372656174655f636f6e73747261696e745f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 +eof:3312794537 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..6337e90e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,6 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00 +eof:3956005776 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..6888edec --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:2 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..baa48a5d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,47 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.hw/example_4_17_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.hw/example_4_17_EGO1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.hw/example_4_17_EGO1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.v" new file mode 100644 index 00000000..484f16f4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.v" @@ -0,0 +1,20 @@ +`timescale 1ns/1ps +module example_4_17( + input [7:0] sw_pin, + output [15:0] led_pin +); + wire w1,w2,w3,w4,w5,w6,w7,w8; + not u1(w1,sw_pin[0]); + not u2(w2,sw_pin[1]); + not u3(w3,sw_pin[2]); + + and u4(w4,w1,sw_pin[2]); + and u5(w5,sw_pin[1],sw_pin[3],w3); + and u6(w6,sw_pin[0],w2.w3); + + and u7(w7,w1,sw_pin[1],sw_pin[3]); + and u8(w8,sw_pin[0],sw_pin[3],w3); + + or u9(led_pin[0],w4,w5,w6); + or u10(led_pin[7],w4,w5,w6,w7,w8); +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.xpr" new file mode 100644 index 00000000..650e32d0 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_17_EGO1/example_4_17_EGO1.xpr" @@ -0,0 +1,182 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/EGO1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/EGO1.xdc" new file mode 100644 index 00000000..6ae3adfe --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/EGO1.xdc" @@ -0,0 +1,250 @@ +//----------------------------------------------系统时钟和复位------------------------------------ +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports sys_clk_in] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports sys_rst_n] + + +//-----------------------------------------------5个按键--------------------------------------------- +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports btn_4] + + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] + + +//---------------------------------------------拨码开关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + +//------------------------------------------拨码开关(DIP开关)sw8~sw15--------------------- +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[0]}] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[1]}] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[2]}] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[3]}] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports {dip_pin[4]}] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[5]}] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[6]}] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[7]}] + + +//---------------------------------------------LED0~LED15---------------------------------------- +set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN G3 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {led_pin[8]}] +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {led_pin[9]}] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led_pin[10]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led_pin[11]}] +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {led_pin[12]}] +set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports {led_pin[13]}] +set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports {led_pin[14]}] +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {led_pin[15]}] + + +//-----------------------------------8个数码管位选信号----------------------------------------------- +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[0]}] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[1]}] +set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[2]}] +set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[3]}] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[4]}] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[5]}] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[6]}] +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[7]}] + +//--------------------------------------------数码管段选信号--------------------------------------------- +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[0]}] +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[1]}] +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[2]}] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[3]}] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[4]}] +set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[5]}] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[6]}] +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[7]}] + +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[0]}] +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[1]}] +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[2]}] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[3]}] +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[4]}] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[5]}] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[6]}] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[7]}] + + +//--------------------------------------VGA行同步场同步信号----------------------------------------------- +set_property -dict {PACKAGE_PIN D7 IOSTANDARD LVCMOS33} [get_ports vga_hs_pin] +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports vga_vs_pin] + + +//--------------------------------------VGA红绿蓝信号------------------------------------------------------ +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[0]}] +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[1]}] +set_property -dict {PACKAGE_PIN C5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[2]}] +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[3]}] +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[4]}] +set_property -dict {PACKAGE_PIN A6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[5]}] +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[6]}] +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[7]}] +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[8]}] +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[9]}] +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[10]}] +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[11]}] + + +//----------------------------------------------串口-------------------------------------------------- +set_property -dict {PACKAGE_PIN N5 IOSTANDARD LVCMOS33} [get_ports PC_Uart_rxd] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports PC_Uart_txd] + + +//---------------------------------------------------PS2接口------------------------------------- +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports ps2_clk] +set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports ps2_data] + + +//------------------------------------------------IIC接口--------------------------------------------- +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports pw_iic_scl_io] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports pw_iic_sda_io] + + +//---------------------------------------------------蓝牙--------------------------------------------- +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports BT_Uart_rxd] +set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports BT_Uart_txd] + +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[0]}] +set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[1]}] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[2]}] +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[3]}] +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[4]}] + +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports bt_mcu_int_i] + + + +//-----------------------------------------------------音频接口--------------------------------------- +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports audio_pwm_o] +set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports audio_sd_o ] + + + +//--------------------------------------------------------XADC模数转换----------------------------------- +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_n] +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_p] +set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_n] +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_p] + + +//--------------------------------------------------------DAC数模转换--------------------------- +set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports dac_ile] +set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports dac_cs_n] +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports dac_wr1_n] +set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports dac_wr2_n] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports dac_xfer_n] + +set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS33} [get_ports {dac_data[0]}] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33} [get_ports {dac_data[1]}] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports {dac_data[2]}] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports {dac_data[3]}] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {dac_data[4]}] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {dac_data[5]}] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports {dac_data[6]}] +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports {dac_data[7]}] + + + +//-------------------------------------------------SDRAM芯片接口------------------------------------- +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[18]}] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[17]}] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[16]}] +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[15]}] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {sram_addr[14]}] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[13]}] +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[12]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[11]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[10]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[9]}] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[8]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[7]}] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[6]}] +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[5]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[4]}] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[3]}] +set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[2]}] +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[1]}] +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[0]}] + +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports sram_ce_n] +set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports sram_lb_n] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports sram_oe_n] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports sram_ub_n] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports sram_we_n] + +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {sram_data[15]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {sram_data[14]}] +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {sram_data[13]}] +set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS33} [get_ports {sram_data[12]}] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {sram_data[11]}] +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {sram_data[10]}] +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {sram_data[9]}] +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {sram_data[8]}] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {sram_data[7]}] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {sram_data[6]}] +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {sram_data[5]}] +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {sram_data[4]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {sram_data[3]}] +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {sram_data[2]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {sram_data[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {sram_data[0]}] + + + + +//--------------------------------------32个pmod接口(扩展接口)------------------------------- +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {exp_io[0]}] +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports {exp_io[1]}] +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports {exp_io[2]}] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS33} [get_ports {exp_io[3]}] +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {exp_io[4]}] +set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports {exp_io[5]}] +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports {exp_io[6]}] +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {exp_io[7]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {exp_io[8]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {exp_io[9]}] +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports {exp_io[10]}] +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {exp_io[11]}] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {exp_io[12]}] +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {exp_io[13]}] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {exp_io[14]}] +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {exp_io[15]}] + +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {exp_io[16]}] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {exp_io[17]}] +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports {exp_io[18]}] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {exp_io[19]}] +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports {exp_io[20]}] +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports {exp_io[21]}] +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports {exp_io[22]}] +set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {exp_io[23]}] +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {exp_io[24]}] +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {exp_io[25]}] +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {exp_io[26]}] +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports {exp_io[27]}] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {exp_io[28]}] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {exp_io[29]}] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {exp_io[30]}] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {exp_io[31]}] + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..ba282025 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,15 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3134:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f65646974:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:3132:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 +eof:3472466856 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..87ef1f34 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,6 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:33:00:00 +eof:1809408175 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..30d3330f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:4 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..c3b3eaee --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,47 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.hw/example_4_2_1_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.hw/example_4_2_1_EGO1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.hw/example_4_2_1_EGO1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.v" new file mode 100644 index 00000000..d3205215 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.v" @@ -0,0 +1,33 @@ +module half_adder_behavioral( + input a_in, + input b_in, + output reg s_out, + output reg c_out +); + +always @(*) +begin +//Ϊʽ + case({a_in, b_in}) + 0: begin s_out <= 0;c_out<= 0; end + 1: begin s_out <= 1;c_out<= 0; end + 2: begin s_out <= 1;c_out<= 0; end + 3: begin s_out <= 0;c_out<= 1; end + endcase +end + +endmodule + +module top_module( + nput [7:0] sw_pin, + output [15:0] led_pin +); + +half_adder_behavioral uut( + .a_in(sw_pin[0]), + .b_in(sw_pin[1]), + .s_out(led_pin[0]), + .c_out(led_pin[1]) +); + +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.xpr" new file mode 100644 index 00000000..29b30b86 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_1_EGO1/example_4_2_1_EGO1.xpr" @@ -0,0 +1,182 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/EGO1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/EGO1.xdc" new file mode 100644 index 00000000..6ae3adfe --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/EGO1.xdc" @@ -0,0 +1,250 @@ +//----------------------------------------------系统时钟和复位------------------------------------ +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports sys_clk_in] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports sys_rst_n] + + +//-----------------------------------------------5个按键--------------------------------------------- +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports btn_4] + + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] + + +//---------------------------------------------拨码开关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + +//------------------------------------------拨码开关(DIP开关)sw8~sw15--------------------- +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[0]}] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[1]}] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[2]}] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[3]}] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports {dip_pin[4]}] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[5]}] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[6]}] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[7]}] + + +//---------------------------------------------LED0~LED15---------------------------------------- +set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN G3 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {led_pin[8]}] +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {led_pin[9]}] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led_pin[10]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led_pin[11]}] +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {led_pin[12]}] +set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports {led_pin[13]}] +set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports {led_pin[14]}] +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {led_pin[15]}] + + +//-----------------------------------8个数码管位选信号----------------------------------------------- +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[0]}] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[1]}] +set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[2]}] +set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[3]}] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[4]}] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[5]}] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[6]}] +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[7]}] + +//--------------------------------------------数码管段选信号--------------------------------------------- +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[0]}] +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[1]}] +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[2]}] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[3]}] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[4]}] +set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[5]}] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[6]}] +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[7]}] + +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[0]}] +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[1]}] +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[2]}] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[3]}] +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[4]}] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[5]}] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[6]}] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[7]}] + + +//--------------------------------------VGA行同步场同步信号----------------------------------------------- +set_property -dict {PACKAGE_PIN D7 IOSTANDARD LVCMOS33} [get_ports vga_hs_pin] +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports vga_vs_pin] + + +//--------------------------------------VGA红绿蓝信号------------------------------------------------------ +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[0]}] +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[1]}] +set_property -dict {PACKAGE_PIN C5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[2]}] +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[3]}] +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[4]}] +set_property -dict {PACKAGE_PIN A6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[5]}] +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[6]}] +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[7]}] +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[8]}] +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[9]}] +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[10]}] +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[11]}] + + +//----------------------------------------------串口-------------------------------------------------- +set_property -dict {PACKAGE_PIN N5 IOSTANDARD LVCMOS33} [get_ports PC_Uart_rxd] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports PC_Uart_txd] + + +//---------------------------------------------------PS2接口------------------------------------- +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports ps2_clk] +set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports ps2_data] + + +//------------------------------------------------IIC接口--------------------------------------------- +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports pw_iic_scl_io] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports pw_iic_sda_io] + + +//---------------------------------------------------蓝牙--------------------------------------------- +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports BT_Uart_rxd] +set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports BT_Uart_txd] + +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[0]}] +set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[1]}] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[2]}] +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[3]}] +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[4]}] + +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports bt_mcu_int_i] + + + +//-----------------------------------------------------音频接口--------------------------------------- +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports audio_pwm_o] +set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports audio_sd_o ] + + + +//--------------------------------------------------------XADC模数转换----------------------------------- +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_n] +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_p] +set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_n] +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_p] + + +//--------------------------------------------------------DAC数模转换--------------------------- +set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports dac_ile] +set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports dac_cs_n] +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports dac_wr1_n] +set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports dac_wr2_n] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports dac_xfer_n] + +set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS33} [get_ports {dac_data[0]}] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33} [get_ports {dac_data[1]}] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports {dac_data[2]}] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports {dac_data[3]}] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {dac_data[4]}] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {dac_data[5]}] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports {dac_data[6]}] +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports {dac_data[7]}] + + + +//-------------------------------------------------SDRAM芯片接口------------------------------------- +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[18]}] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[17]}] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[16]}] +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[15]}] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {sram_addr[14]}] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[13]}] +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[12]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[11]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[10]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[9]}] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[8]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[7]}] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[6]}] +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[5]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[4]}] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[3]}] +set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[2]}] +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[1]}] +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[0]}] + +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports sram_ce_n] +set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports sram_lb_n] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports sram_oe_n] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports sram_ub_n] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports sram_we_n] + +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {sram_data[15]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {sram_data[14]}] +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {sram_data[13]}] +set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS33} [get_ports {sram_data[12]}] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {sram_data[11]}] +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {sram_data[10]}] +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {sram_data[9]}] +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {sram_data[8]}] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {sram_data[7]}] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {sram_data[6]}] +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {sram_data[5]}] +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {sram_data[4]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {sram_data[3]}] +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {sram_data[2]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {sram_data[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {sram_data[0]}] + + + + +//--------------------------------------32个pmod接口(扩展接口)------------------------------- +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {exp_io[0]}] +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports {exp_io[1]}] +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports {exp_io[2]}] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS33} [get_ports {exp_io[3]}] +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {exp_io[4]}] +set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports {exp_io[5]}] +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports {exp_io[6]}] +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {exp_io[7]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {exp_io[8]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {exp_io[9]}] +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports {exp_io[10]}] +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {exp_io[11]}] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {exp_io[12]}] +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {exp_io[13]}] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {exp_io[14]}] +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {exp_io[15]}] + +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {exp_io[16]}] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {exp_io[17]}] +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports {exp_io[18]}] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {exp_io[19]}] +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports {exp_io[20]}] +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports {exp_io[21]}] +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports {exp_io[22]}] +set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {exp_io[23]}] +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {exp_io[24]}] +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {exp_io[25]}] +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {exp_io[26]}] +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports {exp_io[27]}] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {exp_io[28]}] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {exp_io[29]}] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {exp_io[30]}] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {exp_io[31]}] + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..2904a958 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,14 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f65646974:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 +eof:1469502523 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..9a006883 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,5 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +eof:2791156663 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..9b342093 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..2ae92d00 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,45 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.hw/example_4_2_2_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.hw/example_4_2_2_EGO1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.hw/example_4_2_2_EGO1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.v" new file mode 100644 index 00000000..5d8a65ba --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.v" @@ -0,0 +1,25 @@ +module half_adder_dataflow( + input a_in, + input b_in, + output s_out, + output c_out +); + +assign s_out = a_in ^ b_in; +assign c_out = a_in & b_in; + +endmodule + +module top_module( + input [7:0] sw_pin, + output [15:0] led_pin +); + +half_adder_dataflow uut( + .a_in(sw_pin[0]), + .b_in(sw_pin[1]), + .s_out(led_pin[0]), + .c_out(led_pin[1]) +); + +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.xpr" new file mode 100644 index 00000000..2e4631d2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_2_EGO1/example_4_2_2_EGO1.xpr" @@ -0,0 +1,185 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/EGO1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/EGO1.xdc" new file mode 100644 index 00000000..6ae3adfe --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/EGO1.xdc" @@ -0,0 +1,250 @@ +//----------------------------------------------系统时钟和复位------------------------------------ +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports sys_clk_in] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports sys_rst_n] + + +//-----------------------------------------------5个按键--------------------------------------------- +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports btn_4] + + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] + + +//---------------------------------------------拨码开关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + +//------------------------------------------拨码开关(DIP开关)sw8~sw15--------------------- +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[0]}] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[1]}] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[2]}] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[3]}] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports {dip_pin[4]}] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[5]}] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[6]}] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[7]}] + + +//---------------------------------------------LED0~LED15---------------------------------------- +set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN G3 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {led_pin[8]}] +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {led_pin[9]}] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led_pin[10]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led_pin[11]}] +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {led_pin[12]}] +set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports {led_pin[13]}] +set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports {led_pin[14]}] +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {led_pin[15]}] + + +//-----------------------------------8个数码管位选信号----------------------------------------------- +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[0]}] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[1]}] +set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[2]}] +set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[3]}] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[4]}] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[5]}] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[6]}] +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[7]}] + +//--------------------------------------------数码管段选信号--------------------------------------------- +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[0]}] +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[1]}] +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[2]}] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[3]}] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[4]}] +set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[5]}] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[6]}] +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[7]}] + +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[0]}] +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[1]}] +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[2]}] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[3]}] +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[4]}] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[5]}] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[6]}] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[7]}] + + +//--------------------------------------VGA行同步场同步信号----------------------------------------------- +set_property -dict {PACKAGE_PIN D7 IOSTANDARD LVCMOS33} [get_ports vga_hs_pin] +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports vga_vs_pin] + + +//--------------------------------------VGA红绿蓝信号------------------------------------------------------ +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[0]}] +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[1]}] +set_property -dict {PACKAGE_PIN C5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[2]}] +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[3]}] +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[4]}] +set_property -dict {PACKAGE_PIN A6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[5]}] +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[6]}] +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[7]}] +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[8]}] +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[9]}] +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[10]}] +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[11]}] + + +//----------------------------------------------串口-------------------------------------------------- +set_property -dict {PACKAGE_PIN N5 IOSTANDARD LVCMOS33} [get_ports PC_Uart_rxd] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports PC_Uart_txd] + + +//---------------------------------------------------PS2接口------------------------------------- +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports ps2_clk] +set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports ps2_data] + + +//------------------------------------------------IIC接口--------------------------------------------- +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports pw_iic_scl_io] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports pw_iic_sda_io] + + +//---------------------------------------------------蓝牙--------------------------------------------- +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports BT_Uart_rxd] +set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports BT_Uart_txd] + +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[0]}] +set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[1]}] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[2]}] +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[3]}] +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[4]}] + +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports bt_mcu_int_i] + + + +//-----------------------------------------------------音频接口--------------------------------------- +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports audio_pwm_o] +set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports audio_sd_o ] + + + +//--------------------------------------------------------XADC模数转换----------------------------------- +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_n] +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_p] +set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_n] +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_p] + + +//--------------------------------------------------------DAC数模转换--------------------------- +set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports dac_ile] +set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports dac_cs_n] +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports dac_wr1_n] +set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports dac_wr2_n] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports dac_xfer_n] + +set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS33} [get_ports {dac_data[0]}] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33} [get_ports {dac_data[1]}] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports {dac_data[2]}] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports {dac_data[3]}] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {dac_data[4]}] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {dac_data[5]}] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports {dac_data[6]}] +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports {dac_data[7]}] + + + +//-------------------------------------------------SDRAM芯片接口------------------------------------- +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[18]}] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[17]}] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[16]}] +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[15]}] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {sram_addr[14]}] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[13]}] +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[12]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[11]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[10]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[9]}] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[8]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[7]}] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[6]}] +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[5]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[4]}] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[3]}] +set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[2]}] +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[1]}] +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[0]}] + +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports sram_ce_n] +set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports sram_lb_n] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports sram_oe_n] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports sram_ub_n] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports sram_we_n] + +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {sram_data[15]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {sram_data[14]}] +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {sram_data[13]}] +set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS33} [get_ports {sram_data[12]}] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {sram_data[11]}] +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {sram_data[10]}] +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {sram_data[9]}] +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {sram_data[8]}] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {sram_data[7]}] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {sram_data[6]}] +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {sram_data[5]}] +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {sram_data[4]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {sram_data[3]}] +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {sram_data[2]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {sram_data[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {sram_data[0]}] + + + + +//--------------------------------------32个pmod接口(扩展接口)------------------------------- +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {exp_io[0]}] +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports {exp_io[1]}] +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports {exp_io[2]}] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS33} [get_ports {exp_io[3]}] +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {exp_io[4]}] +set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports {exp_io[5]}] +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports {exp_io[6]}] +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {exp_io[7]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {exp_io[8]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {exp_io[9]}] +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports {exp_io[10]}] +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {exp_io[11]}] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {exp_io[12]}] +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {exp_io[13]}] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {exp_io[14]}] +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {exp_io[15]}] + +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {exp_io[16]}] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {exp_io[17]}] +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports {exp_io[18]}] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {exp_io[19]}] +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports {exp_io[20]}] +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports {exp_io[21]}] +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports {exp_io[22]}] +set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {exp_io[23]}] +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {exp_io[24]}] +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {exp_io[25]}] +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {exp_io[26]}] +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports {exp_io[27]}] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {exp_io[28]}] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {exp_io[29]}] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {exp_io[30]}] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {exp_io[31]}] + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..7c78e9aa --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,29 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3236:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:39:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68706f7075707469746c655f636c6f7365:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:38:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f6f70656e5f746172676574:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f70726f6772616d5f646576696365:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f737065636966795f62697473747265616d5f66696c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:717569636b68656c705f68656c70:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7461736b62616e6e65725f636c6f7365:33:00:00 +eof:3961905182 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..70cb29c6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,11 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:32:00:00 +eof:3796014534 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..0161c5dc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:6 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..8c041e30 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,66 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.hw/example_4_2_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.hw/example_4_2_EGO1.lpr" new file mode 100644 index 00000000..b7d45757 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.hw/example_4_2_EGO1.lpr" @@ -0,0 +1,8 @@ + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.hw/hw_1/hw.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.hw/hw_1/hw.xml" new file mode 100644 index 00000000..8a2119d5 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.hw/hw_1/hw.xml" @@ -0,0 +1,9 @@ + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.hw/webtalk/.xsim_webtallk.info" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.hw/webtalk/.xsim_webtallk.info" new file mode 100644 index 00000000..96e16d51 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.hw/webtalk/.xsim_webtallk.info" @@ -0,0 +1,5 @@ +1729413863 +0 +2 +0 +e945e4e3-e93b-41eb-9034-528d9d3ea2f0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.hw/webtalk/usage_statistics_ext_labtool.html" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.hw/webtalk/usage_statistics_ext_labtool.html" new file mode 100644 index 00000000..f7c9e75e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.hw/webtalk/usage_statistics_ext_labtool.html" @@ -0,0 +1,45 @@ +Device Usage Statistics Report +

LABTOOL Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2708876
date_generatedSun Oct 20 16:44:23 2024os_platformWIN64
product_versionVivado v2019.2 (64-bit)project_ide945e4e3-e93b-41eb-9034-528d9d3ea2f0
project_iteration1random_ida6cb3ba0-8200-4502-8b75-dba5835a4932
registration_ida6cb3ba0-8200-4502-8b75-dba5835a4932route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowlabtool

+ + + + + + + + +
user_environment
cpu_nameAMD Ryzen 9 7945HX with Radeon Graphics cpu_speed2495 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram16.000 GBtotal_processors1

+ + +
vivado_usage

+ + + +
labtool
+ + + + + +
usage
cable=Xilinx-tulA/tul-tulA/15000000:chain=0362D093pgmcnt=00:00:00
+

+ + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.hw/webtalk/usage_statistics_ext_labtool.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.hw/webtalk/usage_statistics_ext_labtool.xml" new file mode 100644 index 00000000..7f19dcde --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.hw/webtalk/usage_statistics_ext_labtool.xml" @@ -0,0 +1,39 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+ + + +
+
+
+
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.v" new file mode 100644 index 00000000..bb19ec13 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.v" @@ -0,0 +1,34 @@ +module half_adder_structural( + input a_in, + input b_in, + output s_out, + output c_out +); + +// ڲź +wire w1, w2, w3; + +// ʵ߼ +and u1(w1, a_in, b_in); +xor u2(w2, a_in, b_in); +not u3(w3, w1); + +// +assign s_out = w2; +assign c_out = w1; + +endmodule + +module top_module( + input sw_pin[7:0], + output [15:0] led_pin +); + +half_adder_structural uut( + .a_in(sw_pin[0]), + .b_in(sw_pin[1]), + .s_out(led_pin[0]), + .c_out(led_pin[1]) +); + +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.xpr" new file mode 100644 index 00000000..7f44d345 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/example_4_2_EGO1/example_4_2_EGO1.xpr" @@ -0,0 +1,182 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/\347\254\2543\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/\347\254\2543\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" new file mode 100644 index 00000000..a8a67c84 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/\347\254\2543\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:162e4ce1c528829e0155dab69fe20a7b37aff477a3fa2f4f136894629caec862 +size 3226874 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/\347\254\2544\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260.circ" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/\347\254\2544\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260.circ" new file mode 100644 index 00000000..8a172783 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\270\211/\347\254\2544\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260.circ" @@ -0,0 +1,4130 @@ + + +This file is intended to be loaded by Logisim http://logisim.altervista.org + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + addr/data: 8 8 +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + addr/data: 4 4 +10*f + + + + + + + + + + addr/data: 4 4 +0 1 3 2 6 7 5 4 +c d + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + addr/data: 4 1 +0 0 1 5*0 4*1 0 0 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + addr/data: 4 4 +4*0 1 2 3 4 b c d +e f + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + addr/data: 4 4 +0 0 0 10*f + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + addr/data: 4 1 +5*0 5*1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + addr/data: 4 1 +10*1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + addr/data: 4 1 +1 0 0 1 0 1 1 0 +0 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + addr/data: 4 1 +10*1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + addr/data: 4 2 +0 0 2 3 2 3 1 1 +2 2 1 0 1 0 3 3 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/EGO1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/EGO1.xdc" new file mode 100644 index 00000000..18c97a11 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/EGO1.xdc" @@ -0,0 +1,253 @@ +//----------------------------------------------系统时钟和复位------------------------------------ +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports sys_clk_in] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports sys_rst_n] + + +//-----------------------------------------------5个按键--------------------------------------------- +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports btn_4] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_0_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_2_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_3_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_4_IBUF] + + +//---------------------------------------------拨码开关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + +//------------------------------------------拨码开关(DIP开关)sw8~sw15--------------------- +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[0]}] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[1]}] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[2]}] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[3]}] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports {dip_pin[4]}] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[5]}] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[6]}] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[7]}] + + +//---------------------------------------------LED0~LED15---------------------------------------- +set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN G3 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {led_pin[8]}] +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {led_pin[9]}] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led_pin[10]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led_pin[11]}] +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {led_pin[12]}] +set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports {led_pin[13]}] +set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports {led_pin[14]}] +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {led_pin[15]}] + + +//-----------------------------------8个数码管位选信号----------------------------------------------- +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[0]}] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[1]}] +set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[2]}] +set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[3]}] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[4]}] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[5]}] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[6]}] +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[7]}] + +//--------------------------------------------数码管段选信号--------------------------------------------- +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[0]}] +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[1]}] +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[2]}] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[3]}] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[4]}] +set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[5]}] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[6]}] +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[7]}] + +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[0]}] +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[1]}] +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[2]}] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[3]}] +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[4]}] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[5]}] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[6]}] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[7]}] + + +//--------------------------------------VGA行同步场同步信号----------------------------------------------- +set_property -dict {PACKAGE_PIN D7 IOSTANDARD LVCMOS33} [get_ports vga_hs_pin] +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports vga_vs_pin] + + +//--------------------------------------VGA红绿蓝信号------------------------------------------------------ +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[0]}] +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[1]}] +set_property -dict {PACKAGE_PIN C5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[2]}] +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[3]}] +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[4]}] +set_property -dict {PACKAGE_PIN A6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[5]}] +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[6]}] +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[7]}] +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[8]}] +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[9]}] +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[10]}] +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[11]}] + + +//----------------------------------------------串口-------------------------------------------------- +set_property -dict {PACKAGE_PIN N5 IOSTANDARD LVCMOS33} [get_ports PC_Uart_rxd] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports PC_Uart_txd] + + +//---------------------------------------------------PS2接口------------------------------------- +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports ps2_clk] +set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports ps2_data] + + +//------------------------------------------------IIC接口--------------------------------------------- +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports pw_iic_scl_io] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports pw_iic_sda_io] + + +//---------------------------------------------------蓝牙--------------------------------------------- +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports BT_Uart_rxd] +set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports BT_Uart_txd] + +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[0]}] +set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[1]}] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[2]}] +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[3]}] +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[4]}] + +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports bt_mcu_int_i] + + + +//-----------------------------------------------------音频接口--------------------------------------- +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports audio_pwm_o] +set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports audio_sd_o ] + + + +//--------------------------------------------------------XADC模数转换----------------------------------- +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_n] +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_p] +set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_n] +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_p] + + +//--------------------------------------------------------DAC数模转换--------------------------- +set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports dac_ile] +set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports dac_cs_n] +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports dac_wr1_n] +set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports dac_wr2_n] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports dac_xfer_n] + +set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS33} [get_ports {dac_data[0]}] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33} [get_ports {dac_data[1]}] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports {dac_data[2]}] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports {dac_data[3]}] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {dac_data[4]}] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {dac_data[5]}] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports {dac_data[6]}] +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports {dac_data[7]}] + + + +//-------------------------------------------------SDRAM芯片接口------------------------------------- +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[18]}] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[17]}] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[16]}] +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[15]}] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {sram_addr[14]}] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[13]}] +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[12]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[11]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[10]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[9]}] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[8]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[7]}] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[6]}] +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[5]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[4]}] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[3]}] +set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[2]}] +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[1]}] +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[0]}] + +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports sram_ce_n] +set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports sram_lb_n] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports sram_oe_n] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports sram_ub_n] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports sram_we_n] + +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {sram_data[15]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {sram_data[14]}] +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {sram_data[13]}] +set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS33} [get_ports {sram_data[12]}] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {sram_data[11]}] +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {sram_data[10]}] +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {sram_data[9]}] +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {sram_data[8]}] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {sram_data[7]}] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {sram_data[6]}] +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {sram_data[5]}] +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {sram_data[4]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {sram_data[3]}] +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {sram_data[2]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {sram_data[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {sram_data[0]}] + + + + +//--------------------------------------32个pmod接口(扩展接口)------------------------------- +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {exp_io[0]}] +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports {exp_io[1]}] +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports {exp_io[2]}] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS33} [get_ports {exp_io[3]}] +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {exp_io[4]}] +set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports {exp_io[5]}] +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports {exp_io[6]}] +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {exp_io[7]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {exp_io[8]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {exp_io[9]}] +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports {exp_io[10]}] +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {exp_io[11]}] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {exp_io[12]}] +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {exp_io[13]}] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {exp_io[14]}] +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {exp_io[15]}] + +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {exp_io[16]}] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {exp_io[17]}] +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports {exp_io[18]}] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {exp_io[19]}] +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports {exp_io[20]}] +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports {exp_io[21]}] +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports {exp_io[22]}] +set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {exp_io[23]}] +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {exp_io[24]}] +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {exp_io[25]}] +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {exp_io[26]}] +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports {exp_io[27]}] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {exp_io[28]}] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {exp_io[29]}] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {exp_io[30]}] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {exp_io[31]}] + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..734de337 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,20 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3231:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f6d65737361676573:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f636865636b706f696e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f65646974:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f7265706f727473:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f6f70656e5f73656c65637465645f736f757263655f66696c6573:33:00:00 +eof:119755546 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..2708d257 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,5 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00 +eof:2767115970 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..6888edec --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:2 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..36822e60 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,51 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.hw/example_6_11_1_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.hw/example_6_11_1_EGO1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.hw/example_6_11_1_EGO1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.srcs/sources_1/new/example_6_11_1_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.srcs/sources_1/new/example_6_11_1_EGO1.v" new file mode 100644 index 00000000..6cd27629 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.srcs/sources_1/new/example_6_11_1_EGO1.v" @@ -0,0 +1,67 @@ +//Ϊʽʵ6-11ĵ巢x2ӿS1ACE1ΪKEY1 +//״̬y2, y1Zֱ𿪷ߵ2LEDԼұߵLEDơ +`timescale 1ns / 1ps +module example_6_11 ( + input x2, x1, + input y2, y1, + output reg ny2, ny1, z +); + always @(*) //Ϊʽ + begin + if(x2==0 && x1==0) begin + case({y2, y1}) + 0: begin ny2 <= 0; ny1 <= 0; z <= 0; end + 1: begin ny2 <= 1; ny1 <= 1; z <= 0; end + 2: begin ny2 <= 1; ny1 <= 1; z <= 0; end + 3: begin ny2 <= 0; ny1 <= 0; z <= 0; end + endcase + end + + if(x2==0 && x1==1) begin + case({y2, y1}) + 0: begin ny2 <= 0; ny1 <= 1; z <= 0; end + 1: begin ny2 <= 0; ny1 <= 1; z <= 0; end + 2: begin ny2 <= 0; ny1 <= 0; z <= 0; end + 3: begin ny2 <= 0; ny1 <= 0; z <= 0; end + endcase + end + + if(x2==1 && x1==1) begin + case({y2, y1}) + 0: begin ny2 <= 0; ny1 <= 1; z <= 0; end + 1: begin ny2 <= 0; ny1 <= 1; z <= 0; end + 3: begin ny2 <= 0; ny1 <= 0; z <= 0; end + 2: begin ny2 <= 0; ny1 <= 0; z <= 0; end + endcase + end + + if(x2==1 && x1==0) begin + case({y2, y1}) + 0: begin ny2 <= 0; ny1 <= 0; z <= 0; end + 1: begin ny2 <= 0; ny1 <= 1; z <= 0; end + 3: begin ny2 <= 1; ny1 <= 0; z <= 0; end + 2: begin ny2 <= 1; ny1 <= 0; z <= 1; end + endcase + end + end +endmodule + +module example_6_11_1( + input btn_1, + input clk, + output [7:0] led_pin ////8LED +); +reg y2, y1; + +example_6_11_1 U(.x2(clk), .x1(btn_1), .y2(y2), .y1(y1), .ny2(led_pin[7]), .ny1(led_pin[6]), .z(led_pin[0])); + initial begin + y2 = 0; + y1 = 0; + end + + always @(*) //Ϊʽ + begin + y2 <= led_pin[7]; + y1 <= led_pin[6]; + end +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.xpr" new file mode 100644 index 00000000..6f8a4ee5 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_1_EGO1/example_6_11_1_EGO1.xpr" @@ -0,0 +1,188 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/EGO1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/EGO1.xdc" new file mode 100644 index 00000000..dfbd933a --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/EGO1.xdc" @@ -0,0 +1,199 @@ +//----------------------------------------------系统时钟------------------------------------ +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports sys_clk_50m] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports sys_clk_100m] +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports sys_clk_3hz] + + +//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------ +set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + + + +//---------------------------------------------拨码?关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + + +//-----------------------------------------------9个按?-------------------------------------- +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports btn_4] +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports btn_5] +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports btn_6] +set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports btn_7] +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports btn_8] + + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_0_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_2_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_3_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_4_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_5_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_6_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_7_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_8_IBUF] + + +//-----------------------------------6个数码管----------------------------------------------------------- +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[0]}] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[1]}] +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[2]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {digitron_out[3]}] +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS33} [get_ports {digitron_out[4]}] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[5]}] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[6]}] +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[7]}] + +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[0]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[1]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[2]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[3]}] + +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {digitron_a[0]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {digitron_a[2]}] +set_property -dict {PACKAGE_PIN AB18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[3]}] + +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33} [get_ports {digitron_b[0]}] +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[1]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[2]}] +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports {digitron_b[3]}] + + + +//----------------------------------------------串口--------------------------------------------- +set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports uart_rxd] +set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports uart_txd] + + + +//----------------------------------------------蜂鸣?----------------------------------------- +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports buzzer] + + + +//--------------------------------------------------------XADC数模转换------------------- +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports ad15p] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports ad15n] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports ad7p] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports ad7n] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports ad14p] +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports ad14n] +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports ad6p] +set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports ad6n] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports ad5p] +set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS33} [get_ports ad5n] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports ad13p] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports ad13n] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports ad4p] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports ad4n] + + + + +//--------------------------------------------------------DDR3L------------------------------------- +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_p] +set_property -dict {PACKAGE_PIN AA3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_n] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_p] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_n] + +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq0] +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq1] +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq2] +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq3] +set_property -dict {PACKAGE_PIN AA5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq4] +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq5] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq6] +set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq7] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq8] +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq9] +set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq10] +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq11] +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq12] +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq13] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq14] +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq15] + +set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a0] +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a1] +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a2] +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a3] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a4] +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a5] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a6] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a7] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a8] +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a9] +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a10] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a11] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a12] + +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba0] +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba1] +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba2] + +set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm0] +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm1] + +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports ddr3l_odt] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_p] +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_n] +set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cke] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports ddr3l_cs] +set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ras] +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports ddr3l_we] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports ddr3l_reset] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cas] + +# set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets led_pin_OBUF[6]] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..22443d5e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,17 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3135:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f65646974:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:31:00:00 +eof:424576912 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..67814d79 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,5 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00 +eof:1406353603 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..9b342093 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..e021dc84 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,48 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.hw/example_6_11_2_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.hw/example_6_11_2_EGO1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.hw/example_6_11_2_EGO1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.srcs/sim_1/new/example_6_11_2_sim_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.srcs/sim_1/new/example_6_11_2_sim_EGO1.v" new file mode 100644 index 00000000..40694b17 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.srcs/sim_1/new/example_6_11_2_sim_EGO1.v" @@ -0,0 +1,25 @@ +//6.11ķ +`timescale 1ns / 1ps +module example_6_11_2_sim(); + reg x1,x2; + reg y2, y1; + wire z, ny2, ny1; + + example_6_11_2 U(.x1(x1),.x2(x2), .y2(y2), .y1(y1), .ny2(ny2), .ny1(ny1), .z(z)); + initial begin + #0 + y2=0; + y1=0; + + x1=0; + x2=0; + #20 + x1=1; + + #60 + x1=0; + end + + always #5 begin y2 <= ny2; y1 <= ny1; end + always #10 begin x2 <= ~x2; end +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.v" new file mode 100644 index 00000000..d572f0c7 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.v" @@ -0,0 +1,88 @@ +//ṹʽģΪʽʵ6.11ĵ巢루x1x2Ϊϵߵ2أ״̬y2y1ZΪߵ2LEDԼұߵ1LEDơ + +`timescale 1ns / 1ps + +module not_gate( + input a, + output f +); + reg y; + always @(*) //Ϊʽ + begin + y <= ~a; + end + assign f = y; +endmodule + +module nand_gate2( + input a, + input b, + output f +); + reg y; + always @(*) //Ϊʽ + begin + y <= ~(a & b); + end + assign f = y; +endmodule + +module nand_gate3( + input a, + input b, + input c, + output f +); + reg y; + always @(*) //Ϊʽ + begin + y <= ~(a & b & c); + end + assign f = y; +endmodule + + +module example_6_11( + input x1,x2, + input wire clk, + input y2, y1, + output ny2, ny1, z +); + + wire t1, t2, t3, t4, t5, t6, t7; + + not_gate u1(.a(x1),.f(t1)); //ṹʽ + not_gate u2(.a(x2),.f(t2)); //ṹʽ + + nand_gate2 U3(.a(x2),.b(y2),.f(t3)); + not_gate U4(.a(t3),.f(z)); + + nand_gate3 U5(.a(t1),.b(t2),.c(y1),.f(t4)); //ṹʽ + nand_gate2 U6(.a(t3),.b(y1),.f(t5)); //ṹʽ + + nand_gate2 U7(.a(t4),.b(t3),.f(ny2)); //ṹʽ + nand_gate2 U8(.a(t1),.b(t5),.f(ny1)); //ṹʽ + +endmodule + +module example_6_11_exe( + input btn_1,//btn_2, //8 + output [7:0] led_pin //8led +); + + reg y2, y1; + + example_6_11 U( .x1(btn_1), .y2(y2), .y1(y1), .ny2(led_pin[7]), .ny1(led_pin[6]), .z(led_pin[0])); + + initial begin + y2=0; + y1=0; + end + + always @(*) //Ϊʽ + begin + y2 <= led_pin[7]; + y1 <= led_pin[6]; + end + +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.xpr" new file mode 100644 index 00000000..f84c7904 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_2_EGO1/example_6_11_2_EGO1.xpr" @@ -0,0 +1,192 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/EGO1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/EGO1.xdc" new file mode 100644 index 00000000..18c97a11 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/EGO1.xdc" @@ -0,0 +1,253 @@ +//----------------------------------------------系统时钟和复位------------------------------------ +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports sys_clk_in] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports sys_rst_n] + + +//-----------------------------------------------5个按键--------------------------------------------- +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports btn_4] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_0_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_2_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_3_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_4_IBUF] + + +//---------------------------------------------拨码开关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + +//------------------------------------------拨码开关(DIP开关)sw8~sw15--------------------- +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[0]}] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[1]}] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[2]}] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[3]}] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports {dip_pin[4]}] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[5]}] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[6]}] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[7]}] + + +//---------------------------------------------LED0~LED15---------------------------------------- +set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN G3 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {led_pin[8]}] +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {led_pin[9]}] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led_pin[10]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led_pin[11]}] +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {led_pin[12]}] +set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports {led_pin[13]}] +set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports {led_pin[14]}] +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {led_pin[15]}] + + +//-----------------------------------8个数码管位选信号----------------------------------------------- +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[0]}] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[1]}] +set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[2]}] +set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[3]}] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[4]}] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[5]}] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[6]}] +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[7]}] + +//--------------------------------------------数码管段选信号--------------------------------------------- +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[0]}] +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[1]}] +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[2]}] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[3]}] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[4]}] +set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[5]}] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[6]}] +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[7]}] + +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[0]}] +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[1]}] +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[2]}] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[3]}] +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[4]}] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[5]}] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[6]}] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[7]}] + + +//--------------------------------------VGA行同步场同步信号----------------------------------------------- +set_property -dict {PACKAGE_PIN D7 IOSTANDARD LVCMOS33} [get_ports vga_hs_pin] +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports vga_vs_pin] + + +//--------------------------------------VGA红绿蓝信号------------------------------------------------------ +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[0]}] +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[1]}] +set_property -dict {PACKAGE_PIN C5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[2]}] +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[3]}] +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[4]}] +set_property -dict {PACKAGE_PIN A6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[5]}] +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[6]}] +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[7]}] +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[8]}] +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[9]}] +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[10]}] +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[11]}] + + +//----------------------------------------------串口-------------------------------------------------- +set_property -dict {PACKAGE_PIN N5 IOSTANDARD LVCMOS33} [get_ports PC_Uart_rxd] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports PC_Uart_txd] + + +//---------------------------------------------------PS2接口------------------------------------- +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports ps2_clk] +set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports ps2_data] + + +//------------------------------------------------IIC接口--------------------------------------------- +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports pw_iic_scl_io] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports pw_iic_sda_io] + + +//---------------------------------------------------蓝牙--------------------------------------------- +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports BT_Uart_rxd] +set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports BT_Uart_txd] + +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[0]}] +set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[1]}] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[2]}] +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[3]}] +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[4]}] + +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports bt_mcu_int_i] + + + +//-----------------------------------------------------音频接口--------------------------------------- +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports audio_pwm_o] +set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports audio_sd_o ] + + + +//--------------------------------------------------------XADC模数转换----------------------------------- +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_n] +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_p] +set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_n] +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_p] + + +//--------------------------------------------------------DAC数模转换--------------------------- +set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports dac_ile] +set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports dac_cs_n] +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports dac_wr1_n] +set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports dac_wr2_n] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports dac_xfer_n] + +set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS33} [get_ports {dac_data[0]}] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33} [get_ports {dac_data[1]}] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports {dac_data[2]}] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports {dac_data[3]}] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {dac_data[4]}] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {dac_data[5]}] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports {dac_data[6]}] +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports {dac_data[7]}] + + + +//-------------------------------------------------SDRAM芯片接口------------------------------------- +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[18]}] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[17]}] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[16]}] +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[15]}] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {sram_addr[14]}] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[13]}] +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[12]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[11]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[10]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[9]}] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[8]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[7]}] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[6]}] +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[5]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[4]}] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[3]}] +set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[2]}] +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[1]}] +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[0]}] + +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports sram_ce_n] +set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports sram_lb_n] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports sram_oe_n] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports sram_ub_n] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports sram_we_n] + +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {sram_data[15]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {sram_data[14]}] +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {sram_data[13]}] +set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS33} [get_ports {sram_data[12]}] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {sram_data[11]}] +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {sram_data[10]}] +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {sram_data[9]}] +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {sram_data[8]}] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {sram_data[7]}] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {sram_data[6]}] +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {sram_data[5]}] +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {sram_data[4]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {sram_data[3]}] +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {sram_data[2]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {sram_data[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {sram_data[0]}] + + + + +//--------------------------------------32个pmod接口(扩展接口)------------------------------- +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {exp_io[0]}] +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports {exp_io[1]}] +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports {exp_io[2]}] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS33} [get_ports {exp_io[3]}] +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {exp_io[4]}] +set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports {exp_io[5]}] +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports {exp_io[6]}] +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {exp_io[7]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {exp_io[8]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {exp_io[9]}] +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports {exp_io[10]}] +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {exp_io[11]}] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {exp_io[12]}] +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {exp_io[13]}] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {exp_io[14]}] +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {exp_io[15]}] + +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {exp_io[16]}] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {exp_io[17]}] +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports {exp_io[18]}] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {exp_io[19]}] +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports {exp_io[20]}] +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports {exp_io[21]}] +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports {exp_io[22]}] +set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {exp_io[23]}] +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {exp_io[24]}] +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {exp_io[25]}] +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {exp_io[26]}] +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports {exp_io[27]}] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {exp_io[28]}] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {exp_io[29]}] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {exp_io[30]}] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {exp_io[31]}] + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..b25dc843 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,11 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3134:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7372635f7265706c6163655f66696c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:32:00:00 +eof:4100453453 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..fb5e6fec --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,5 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757064617465736f7572636566696c6573:31:00:00 +eof:500755739 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..6888edec --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:2 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..1b6e0c43 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,42 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.hw/example_6_11_3_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.hw/example_6_11_3_EGO1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.hw/example_6_11_3_EGO1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.v" new file mode 100644 index 00000000..99bfcf57 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.v" @@ -0,0 +1,67 @@ +//Ϊʽʵ6-11ĵ巢x2ӿS1ACE1ΪKEY1 +//״̬y2, y1Zֱ𿪷ߵ2LEDԼұߵLEDơ +`timescale 1ns / 1ps +module example_6_11_3 ( + input x2, x1, + input y2, y1, + output reg ny2, ny1, z +); + always @(*) //Ϊʽ + begin + if(x2==0 && x1==0) begin + case({y2, y1}) + 0: begin ny2 <= 0; ny1 <= 0; z <= 0; end + 1: begin ny2 <= 1; ny1 <= 1; z <= 0; end + 2: begin ny2 <= 1; ny1 <= 1; z <= 0; end + 3: begin ny2 <= 0; ny1 <= 0; z <= 0; end + endcase + end + + if(x2==0 && x1==1) begin + case({y2, y1}) + 0: begin ny2 <= 0; ny1 <= 1; z <= 0; end + 1: begin ny2 <= 0; ny1 <= 1; z <= 0; end + 2: begin ny2 <= 0; ny1 <= 0; z <= 0; end + 3: begin ny2 <= 0; ny1 <= 0; z <= 0; end + endcase + end + + if(x2==1 && x1==1) begin + case({y2, y1}) + 0: begin ny2 <= 0; ny1 <= 1; z <= 0; end + 1: begin ny2 <= 0; ny1 <= 1; z <= 0; end + 3: begin ny2 <= 0; ny1 <= 0; z <= 0; end + 2: begin ny2 <= 0; ny1 <= 0; z <= 0; end + endcase + end + + if(x2==1 && x1==0) begin + case({y2, y1}) + 0: begin ny2 <= 0; ny1 <= 0; z <= 0; end + 1: begin ny2 <= 0; ny1 <= 1; z <= 0; end + 3: begin ny2 <= 1; ny1 <= 0; z <= 0; end + 2: begin ny2 <= 1; ny1 <= 0; z <= 1; end + endcase + end + end +endmodule + +module example_6_11_1( + input btn_1, + input clk, + output [7:0] led_pin ////8LED +); +reg y2, y1; + +example_6_11_3 U(.x2(clk), .x1(btn_1), .y2(y2), .y1(y1), .ny2(led_pin[7]), .ny1(led_pin[6]), .z(led_pin[0])); + initial begin + y2 = 0; + y1 = 0; + end + + always @(*) //Ϊʽ + begin + y2 <= led_pin[7]; + y1 <= led_pin[6]; + end +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.xpr" new file mode 100644 index 00000000..05e4145c --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_EGO1.xpr" @@ -0,0 +1,186 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_sim_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_sim_EGO1.v" new file mode 100644 index 00000000..a1b251db --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_3_EGO1/example_6_11_3_sim_EGO1.v" @@ -0,0 +1,25 @@ +//6.11ķ +`timescale 1ns / 1ps +module example_6_11_3_sim(); + reg x1,x2; + reg y2, y1; + wire z, ny2, ny1; + + example_6_11_3 U(.x1(x1),.x2(x2), .y2(y2), .y1(y1), .ny2(ny2), .ny1(ny1), .z(z)); + initial begin + #0 + y2=0; + y1=0; + + x1=0; + x2=0; + #20 + x1=1; + + #60 + x1=0; + end + + always #5 begin y2 <= ny2; y1 <= ny1; end + always #10 begin x2 <= ~x2; end +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/EGO1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/EGO1.xdc" new file mode 100644 index 00000000..dfbd933a --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/EGO1.xdc" @@ -0,0 +1,199 @@ +//----------------------------------------------系统时钟------------------------------------ +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports sys_clk_50m] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports sys_clk_100m] +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports sys_clk_3hz] + + +//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------ +set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + + + +//---------------------------------------------拨码?关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + + +//-----------------------------------------------9个按?-------------------------------------- +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports btn_4] +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports btn_5] +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports btn_6] +set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports btn_7] +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports btn_8] + + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_0_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_2_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_3_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_4_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_5_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_6_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_7_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_8_IBUF] + + +//-----------------------------------6个数码管----------------------------------------------------------- +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[0]}] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[1]}] +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[2]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {digitron_out[3]}] +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS33} [get_ports {digitron_out[4]}] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[5]}] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[6]}] +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[7]}] + +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[0]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[1]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[2]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[3]}] + +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {digitron_a[0]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {digitron_a[2]}] +set_property -dict {PACKAGE_PIN AB18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[3]}] + +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33} [get_ports {digitron_b[0]}] +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[1]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[2]}] +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports {digitron_b[3]}] + + + +//----------------------------------------------串口--------------------------------------------- +set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports uart_rxd] +set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports uart_txd] + + + +//----------------------------------------------蜂鸣?----------------------------------------- +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports buzzer] + + + +//--------------------------------------------------------XADC数模转换------------------- +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports ad15p] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports ad15n] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports ad7p] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports ad7n] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports ad14p] +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports ad14n] +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports ad6p] +set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports ad6n] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports ad5p] +set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS33} [get_ports ad5n] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports ad13p] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports ad13n] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports ad4p] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports ad4n] + + + + +//--------------------------------------------------------DDR3L------------------------------------- +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_p] +set_property -dict {PACKAGE_PIN AA3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_n] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_p] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_n] + +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq0] +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq1] +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq2] +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq3] +set_property -dict {PACKAGE_PIN AA5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq4] +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq5] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq6] +set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq7] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq8] +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq9] +set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq10] +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq11] +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq12] +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq13] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq14] +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq15] + +set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a0] +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a1] +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a2] +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a3] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a4] +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a5] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a6] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a7] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a8] +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a9] +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a10] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a11] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a12] + +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba0] +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba1] +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba2] + +set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm0] +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm1] + +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports ddr3l_odt] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_p] +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_n] +set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cke] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports ddr3l_cs] +set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ras] +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports ddr3l_we] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports ddr3l_reset] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cas] + +# set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets led_pin_OBUF[6]] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..eb4fcca2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,46 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f73696d756c6174696f6e5f73706563696669635f68646c5f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6e6f:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3530:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f796573:3233:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636c6f7365706c616e6e65725f796573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3436:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3533:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c6f676d6f6e69746f725f6d6f6e69746f72:3131:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f65646974:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f666c6f77:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6f70656e5f726563656e745f70726f6a656374:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e65746c69737474726565766965775f6e65746c6973745f74726565:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f627265616b:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72657374617274:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72756e:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72756e5f616c6c:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7372635f7265706c6163655f66696c65:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f64617368626f617264:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:37:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f6f70656e5f746172676574:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f63616e63656c:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f736176655f66696c65:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f63616e63656c:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e6c69766572756e666f72636f6d705f737065636966795f74696d655f616e645f756e697473:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f726566726573685f686965726172636879:31:00:00 +eof:2935967890 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..92732f17 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,23 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:35:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:36:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:3133:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:36:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:3237:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:3230:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e627265616b:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72657374617274:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e616c6c:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e666f7274696d65:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757064617465736f7572636566696c6573:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b72746c616e616c79736973:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b73796e746865736973:31:00:00 +eof:1661221056 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..cfa1c8b4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/project.wpc" @@ -0,0 +1,4 @@ +version:1 +57656254616c6b5472616e736d697373696f6e417474656d70746564:4 +6d6f64655f636f756e7465727c4755494d6f6465:10 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/synthesis.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/synthesis.wdf" new file mode 100644 index 00000000..c7307a40 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/synthesis.wdf" @@ -0,0 +1,39 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:786337613735746667673438342d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:6578616d706c655f365f31315f657865:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a333073:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313031362e3036324d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3638352e3339354d42:00:00 +eof:284394247 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/synthesis_details.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/synthesis_details.wdf" new file mode 100644 index 00000000..78f8d66e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/synthesis_details.wdf" @@ -0,0 +1,3 @@ +version:1 +73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 +eof:2511430288 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..b40e0a71 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,95 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/xsim.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/xsim.wdf" new file mode 100644 index 00000000..50afb2c7 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.cache/wt/xsim.wdf" @@ -0,0 +1,4 @@ +version:1 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 +eof:241934075 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.hw/example_6_11_ACE1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.hw/example_6_11_ACE1.lpr" new file mode 100644 index 00000000..b7d45757 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.hw/example_6_11_ACE1.lpr" @@ -0,0 +1,8 @@ + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.hw/example_6_11_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.hw/example_6_11_EGO1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.hw/example_6_11_EGO1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.hw/hw_1/hw.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.hw/hw_1/hw.xml" new file mode 100644 index 00000000..e41d40fc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.hw/hw_1/hw.xml" @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.ip_user_files/README.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.ip_user_files/README.txt" new file mode 100644 index 00000000..023052ca --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.ip_user_files/README.txt" @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_1.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_1.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_1.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_10.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_10.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_10.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_11.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_11.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_11.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_12.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_12.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_12.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_13.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_13.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_13.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_14.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_14.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_14.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_15.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_15.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_15.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_16.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_16.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_16.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_17.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_17.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_17.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_18.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_18.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_18.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_19.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_19.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_19.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_2.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_2.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_2.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_20.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_20.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_20.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_21.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_21.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_21.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_22.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_22.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_22.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_23.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_23.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_23.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_24.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_24.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_24.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_3.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_3.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_3.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_4.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_4.xml" new file mode 100644 index 00000000..bb5258ef --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_4.xml" @@ -0,0 +1,9 @@ + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_5.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_5.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_5.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_6.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_6.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_6.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_7.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_7.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_7.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_8.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_8.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_8.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_9.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_9.xml" new file mode 100644 index 00000000..ea8c787d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/.jobs/vrs_config_9.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.Vivado_Implementation.queue.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.Vivado_Implementation.queue.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.init_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.init_design.begin.rst" new file mode 100644 index 00000000..3c311653 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.init_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.init_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.init_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.opt_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.opt_design.begin.rst" new file mode 100644 index 00000000..3c311653 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.opt_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.opt_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.opt_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.phys_opt_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.phys_opt_design.begin.rst" new file mode 100644 index 00000000..3c311653 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.phys_opt_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.phys_opt_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.phys_opt_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.place_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.place_design.begin.rst" new file mode 100644 index 00000000..3c311653 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.place_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.place_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.place_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.route_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.route_design.begin.rst" new file mode 100644 index 00000000..3c311653 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.route_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.route_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.route_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.vivado.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.vivado.begin.rst" new file mode 100644 index 00000000..2a33a619 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.vivado.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.vivado.error.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.vivado.error.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.write_bitstream.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.write_bitstream.begin.rst" new file mode 100644 index 00000000..3c311653 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.write_bitstream.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.write_bitstream.error.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/.write_bitstream.error.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/ISEWrap.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/ISEWrap.js" new file mode 100644 index 00000000..97a2ecbc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/ISEWrap.js" @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/ISEWrap.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/ISEWrap.sh" new file mode 100644 index 00000000..f679f2e8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/ISEWrap.sh" @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe.tcl" new file mode 100644 index 00000000..43062461 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe.tcl" @@ -0,0 +1,186 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param chipscope.maxJobs 8 + create_project -in_memory -part xc7a75tfgg484-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.cache/wt [current_project] + set_property parent.project_path D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.xpr [current_project] + set_property ip_output_repo D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/synth_1/example_6_11_exe.dcp + read_xdc D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc + link_design -top example_6_11_exe -part xc7a75tfgg484-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force example_6_11_exe_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file example_6_11_exe_drc_opted.rpt -pb example_6_11_exe_drc_opted.pb -rpx example_6_11_exe_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force example_6_11_exe_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file example_6_11_exe_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file example_6_11_exe_utilization_placed.rpt -pb example_6_11_exe_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file example_6_11_exe_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step phys_opt_design +set ACTIVE_STEP phys_opt_design +set rc [catch { + create_msg_db phys_opt_design.pb + phys_opt_design + write_checkpoint -force example_6_11_exe_physopt.dcp + close_msg_db -file phys_opt_design.pb +} RESULT] +if {$rc} { + step_failed phys_opt_design + return -code error $RESULT +} else { + end_step phys_opt_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force example_6_11_exe_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file example_6_11_exe_drc_routed.rpt -pb example_6_11_exe_drc_routed.pb -rpx example_6_11_exe_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file example_6_11_exe_methodology_drc_routed.rpt -pb example_6_11_exe_methodology_drc_routed.pb -rpx example_6_11_exe_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file example_6_11_exe_power_routed.rpt -pb example_6_11_exe_power_summary_routed.pb -rpx example_6_11_exe_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file example_6_11_exe_route_status.rpt -pb example_6_11_exe_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file example_6_11_exe_timing_summary_routed.rpt -pb example_6_11_exe_timing_summary_routed.pb -rpx example_6_11_exe_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file example_6_11_exe_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file example_6_11_exe_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file example_6_11_exe_bus_skew_routed.rpt -pb example_6_11_exe_bus_skew_routed.pb -rpx example_6_11_exe_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force example_6_11_exe_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + catch { write_mem_info -force example_6_11_exe.mmi } + write_bitstream -force example_6_11_exe.bit + catch {write_debug_probes -quiet -force example_6_11_exe} + catch {file copy -force example_6_11_exe.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe.vdi" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe.vdi" new file mode 100644 index 00000000..e65d6b81 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe.vdi" @@ -0,0 +1,851 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Tue Dec 5 20:36:20 2023 +# Process ID: 2644 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/impl_1 +# Command line: vivado.exe -log example_6_11_exe.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source example_6_11_exe.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/impl_1/example_6_11_exe.vdi +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source example_6_11_exe.tcl -notrace +Command: link_design -top example_6_11_exe -part xc7a75tfgg484-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7a75tfgg484-1 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 620.293 ; gain = 0.000 +INFO: [Project 1-479] Netlist was created with Vivado 2019.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------系统时钟------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:1] +WARNING: [Vivado 12-584] No ports matched 'sys_clk_50m'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_100m'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:3] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:3] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_3hz'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:4] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:4] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:7] +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------拨码?关sw0~sw7----------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:19] +WARNING: [Vivado 12-584] No ports matched 'sw_pin[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:20] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:20] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:21] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:21] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:22] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:22] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:23] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:23] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[4]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:24] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:24] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[5]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:25] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:25] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[6]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:26] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:26] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[7]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:27] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:27] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------------------9个按?--------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:31] +WARNING: [Vivado 12-584] No ports matched 'btn_0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:32] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:32] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:35] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:35] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:36] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:36] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:37] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:37] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:38] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:38] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:39] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:39] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:40] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:40] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_0_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:43] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:43] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_3_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:46] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:46] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_4_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:47] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:47] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_5_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:48] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:48] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_6_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:49] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_7_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:50] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:50] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_8_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:51] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:51] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------6个数码管-----------------------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:54] +WARNING: [Vivado 12-584] No ports matched 'digitron_out[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:55] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:55] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:56] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:56] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:57] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:57] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:58] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:58] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[4]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:59] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:59] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[5]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:60] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:60] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[6]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:61] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:61] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[7]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:62] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:62] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:64] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:64] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:65] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:65] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:66] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:66] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:67] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:67] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:69] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:69] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:70] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:70] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:71] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:71] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:72] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:72] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:74] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:74] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:75] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:75] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:76] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:76] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:77] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:77] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------串口---------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:81] +WARNING: [Vivado 12-584] No ports matched 'uart_rxd'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:82] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:82] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'uart_txd'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:83] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:83] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------蜂鸣?-----------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:87] +WARNING: [Vivado 12-584] No ports matched 'buzzer'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:88] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:88] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------XADC数模转换-------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:92] +WARNING: [Vivado 12-584] No ports matched 'ad15p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:93] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:93] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad15n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:94] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:94] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:95] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:95] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:96] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:96] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:97] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:97] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:98] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:98] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:99] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:99] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:100] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:100] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:101] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:101] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:102] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:102] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:103] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:103] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:104] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:104] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:105] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:105] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:106] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:106] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------DDR3L-------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:111] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:112] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:112] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:113] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:113] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:114] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:114] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:115] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:115] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:117] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:117] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:118] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:118] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:119] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:119] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:120] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:120] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:121] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:121] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:122] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:122] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:123] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:123] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:124] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:124] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:125] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:125] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq9'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:126] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:126] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq10'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:127] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:127] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq11'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:128] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:128] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq12'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:129] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:129] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq13'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:130] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:130] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq14'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:131] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:131] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq15'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:132] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:132] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:134] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:134] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:135] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:135] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:136] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:136] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:137] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:137] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:138] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:138] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:139] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:139] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:140] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:140] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:141] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:141] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:142] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:142] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a9'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:143] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:143] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a10'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:144] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:144] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a11'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:145] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:145] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a12'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:146] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:146] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:148] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:148] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:149] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:149] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:150] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:150] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:152] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:152] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:153] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:153] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +INFO: [Common 17-14] Message 'Common 17-55' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:153] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_odt'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:155] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:156] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:157] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cke'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:158] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cs'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:159] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ras'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:160] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_we'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:161] +INFO: [Common 17-14] Message 'Vivado 12-584' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:161] +Finished Parsing XDC File [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 729.797 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 107 Warnings, 109 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 733.809 ; gain = 423.066 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.646 . Memory (MB): peak = 754.633 ; gain = 20.824 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 1260fa39a + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1275.992 ; gain = 521.359 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 1260fa39a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1468.500 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 1260fa39a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1468.500 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 1260fa39a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1468.500 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. +INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. +INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). +Phase 4 BUFG optimization | Checksum: 1260fa39a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1468.500 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 1260fa39a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1468.500 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 1260fa39a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1468.500 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1468.500 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1260fa39a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1468.500 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1260fa39a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1468.500 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 1260fa39a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1468.500 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1468.500 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 1260fa39a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1468.500 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +27 Infos, 107 Warnings, 109 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1468.500 ; gain = 734.691 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1468.500 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 1468.500 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/impl_1/example_6_11_exe_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file example_6_11_exe_drc_opted.rpt -pb example_6_11_exe_drc_opted.pb -rpx example_6_11_exe_drc_opted.rpx +Command: report_drc -file example_6_11_exe_drc_opted.rpt -pb example_6_11_exe_drc_opted.pb -rpx example_6_11_exe_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/impl_1/example_6_11_exe_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +CRITICAL WARNING: [DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[6]. Please evaluate your design. The cells in the loop are: led_pin_OBUF[6]_inst_i_1. +CRITICAL WARNING: [DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[6]_inst_i_2_n_0. Please evaluate your design. The cells in the loop are: led_pin_OBUF[6]_inst_i_2. +CRITICAL WARNING: [DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[7]. Please evaluate your design. The cells in the loop are: led_pin_OBUF[7]_inst_i_1. +CRITICAL WARNING: [DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[7]_inst_i_2_n_0. Please evaluate your design. The cells in the loop are: led_pin_OBUF[7]_inst_i_2. +CRITICAL WARNING: [DRC LUTLP-1] Combinatorial Loop Alert: 4 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[6]. Please evaluate your design. The cells in the loop are: led_pin_OBUF[6]_inst_i_1, led_pin_OBUF[6]_inst_i_2, led_pin_OBUF[7]_inst_i_1, and led_pin_OBUF[7]_inst_i_2. +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 5 Critical Warnings +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1468.500 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 101bc1ad6 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1468.500 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1468.500 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 101bc1ad6 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.669 . Memory (MB): peak = 1474.312 ; gain = 5.812 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1b1dba152 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.681 . Memory (MB): peak = 1474.312 ; gain = 5.812 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1b1dba152 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.682 . Memory (MB): peak = 1474.312 ; gain = 5.812 +Phase 1 Placer Initialization | Checksum: 1b1dba152 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.685 . Memory (MB): peak = 1474.312 ; gain = 5.812 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 1b1dba152 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.686 . Memory (MB): peak = 1474.312 ; gain = 5.812 + +Phase 2.2 Global Placement Core +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2.2 Global Placement Core | Checksum: 17c275e8c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1474.312 ; gain = 5.812 +Phase 2 Global Placement | Checksum: 17c275e8c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1474.312 ; gain = 5.812 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 17c275e8c + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1474.312 ; gain = 5.812 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 11e62e2c8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1474.312 ; gain = 5.812 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 14f0beb65 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1474.312 ; gain = 5.812 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 14f0beb65 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1474.312 ; gain = 5.812 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1e78cf0e8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1474.312 ; gain = 5.812 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1e78cf0e8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1474.312 ; gain = 5.812 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1e78cf0e8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1474.312 ; gain = 5.812 +Phase 3 Detail Placement | Checksum: 1e78cf0e8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1474.312 ; gain = 5.812 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1e78cf0e8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1474.312 ; gain = 5.812 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1e78cf0e8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1474.312 ; gain = 5.812 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1e78cf0e8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1474.312 ; gain = 5.812 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1474.312 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: 1e78cf0e8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1474.312 ; gain = 5.812 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1e78cf0e8 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1474.312 ; gain = 5.812 +Ending Placer Task | Checksum: 10a6face4 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1474.312 ; gain = 5.812 +INFO: [Common 17-83] Releasing license: Implementation +45 Infos, 108 Warnings, 114 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1474.312 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1489.855 ; gain = 15.543 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/impl_1/example_6_11_exe_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file example_6_11_exe_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1489.855 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file example_6_11_exe_utilization_placed.rpt -pb example_6_11_exe_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file example_6_11_exe_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1489.855 ; gain = 0.000 +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +53 Infos, 108 Warnings, 114 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1497.211 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1515.109 ; gain = 17.898 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/impl_1/example_6_11_exe_physopt.dcp' has been generated. +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +CRITICAL WARNING: [DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[6]. Please evaluate your design. The cells in the loop are: led_pin_OBUF[6]_inst_i_1. +CRITICAL WARNING: [DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[6]_inst_i_2_n_0. Please evaluate your design. The cells in the loop are: led_pin_OBUF[6]_inst_i_2. +CRITICAL WARNING: [DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[7]. Please evaluate your design. The cells in the loop are: led_pin_OBUF[7]_inst_i_1. +CRITICAL WARNING: [DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[7]_inst_i_2_n_0. Please evaluate your design. The cells in the loop are: led_pin_OBUF[7]_inst_i_2. +CRITICAL WARNING: [DRC LUTLP-1] Combinatorial Loop Alert: 4 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[6]. Please evaluate your design. The cells in the loop are: led_pin_OBUF[6]_inst_i_1, led_pin_OBUF[6]_inst_i_2, led_pin_OBUF[7]_inst_i_1, and led_pin_OBUF[7]_inst_i_2. +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 5 Critical Warnings +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 64fe19f5 ConstDB: 0 ShapeSum: a57192ef RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 15291f531 + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 1641.004 ; gain = 115.785 +Post Restoration Checksum: NetGraph: a757fc9b NumContArr: ab39f896 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 15291f531 + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 1646.773 ; gain = 121.555 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 15291f531 + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 1646.773 ; gain = 121.555 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 309e1ef3 + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 1650.797 ; gain = 125.578 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 7 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 7 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 10ee62498 + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 1653.828 ; gain = 128.609 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: cca7964d + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 1653.828 ; gain = 128.609 +Phase 4 Rip-up And Reroute | Checksum: cca7964d + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 1653.828 ; gain = 128.609 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: cca7964d + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 1653.828 ; gain = 128.609 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: cca7964d + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 1653.828 ; gain = 128.609 +Phase 6 Post Hold Fix | Checksum: cca7964d + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 1653.828 ; gain = 128.609 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.00513557 % + Global Horizontal Routing Utilization = 0.00738846 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: cca7964d + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 1653.828 ; gain = 128.609 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: cca7964d + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 1655.875 ; gain = 130.656 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 931b179e + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 1655.875 ; gain = 130.656 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 1655.875 ; gain = 130.656 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +63 Infos, 108 Warnings, 119 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 1655.875 ; gain = 140.766 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1655.875 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1665.789 ; gain = 9.914 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/impl_1/example_6_11_exe_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file example_6_11_exe_drc_routed.rpt -pb example_6_11_exe_drc_routed.pb -rpx example_6_11_exe_drc_routed.rpx +Command: report_drc -file example_6_11_exe_drc_routed.rpt -pb example_6_11_exe_drc_routed.pb -rpx example_6_11_exe_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/impl_1/example_6_11_exe_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file example_6_11_exe_methodology_drc_routed.rpt -pb example_6_11_exe_methodology_drc_routed.pb -rpx example_6_11_exe_methodology_drc_routed.rpx +Command: report_methodology -file example_6_11_exe_methodology_drc_routed.rpt -pb example_6_11_exe_methodology_drc_routed.pb -rpx example_6_11_exe_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/impl_1/example_6_11_exe_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file example_6_11_exe_power_routed.rpt -pb example_6_11_exe_power_summary_routed.pb -rpx example_6_11_exe_power_routed.rpx +Command: report_power -file example_6_11_exe_power_routed.rpt -pb example_6_11_exe_power_summary_routed.pb -rpx example_6_11_exe_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +75 Infos, 109 Warnings, 119 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file example_6_11_exe_route_status.rpt -pb example_6_11_exe_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file example_6_11_exe_timing_summary_routed.rpt -pb example_6_11_exe_timing_summary_routed.pb -rpx example_6_11_exe_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file example_6_11_exe_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file example_6_11_exe_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file example_6_11_exe_bus_skew_routed.rpt -pb example_6_11_exe_bus_skew_routed.pb -rpx example_6_11_exe_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force example_6_11_exe.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +ERROR: [DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[6]. Please evaluate your design. The cells in the loop are: led_pin_OBUF[6]_inst_i_1. +ERROR: [DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[6]_inst_i_2_n_0. Please evaluate your design. The cells in the loop are: led_pin_OBUF[6]_inst_i_2. +ERROR: [DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[7]. Please evaluate your design. The cells in the loop are: led_pin_OBUF[7]_inst_i_1. +ERROR: [DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[7]_inst_i_2_n_0. Please evaluate your design. The cells in the loop are: led_pin_OBUF[7]_inst_i_2. +ERROR: [DRC LUTLP-1] Combinatorial Loop Alert: 4 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[6]. Please evaluate your design. The cells in the loop are: led_pin_OBUF[6]_inst_i_1, led_pin_OBUF[6]_inst_i_2, led_pin_OBUF[7]_inst_i_1, and led_pin_OBUF[7]_inst_i_2. +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 5 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. +INFO: [Common 17-83] Releasing license: Implementation +91 Infos, 111 Warnings, 119 Critical Warnings and 6 Errors encountered. +write_bitstream failed +ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors. + +INFO: [Common 17-206] Exiting Vivado at Tue Dec 5 20:37:27 2023... diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_bus_skew_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_bus_skew_routed.pb" new file mode 100644 index 00000000..3390588d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_bus_skew_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_bus_skew_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_bus_skew_routed.rpt" new file mode 100644 index 00000000..3df17edf --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_bus_skew_routed.rpt" @@ -0,0 +1,15 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Dec 5 20:37:25 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file example_6_11_exe_bus_skew_routed.rpt -pb example_6_11_exe_bus_skew_routed.pb -rpx example_6_11_exe_bus_skew_routed.rpx +| Design : example_6_11_exe +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_bus_skew_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_bus_skew_routed.rpx" new file mode 100644 index 00000000..2f3fe9c2 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_bus_skew_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_clock_utilization_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_clock_utilization_routed.rpt" new file mode 100644 index 00000000..2ec9bae2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_clock_utilization_routed.rpt" @@ -0,0 +1,96 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Dec 5 20:37:25 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_clock_utilization -file example_6_11_exe_clock_utilization_routed.rpt +| Design : example_6_11_exe +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +---------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 0 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 96 | 0 | 0 | 0 | +| BUFIO | 0 | 24 | 0 | 0 | 0 | +| BUFMR | 0 | 12 | 0 | 0 | 0 | +| BUFR | 0 | 24 | 0 | 0 | 0 | +| MMCM | 0 | 6 | 0 | 0 | 0 | +| PLL | 0 | 6 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1500 | 0 | 550 | 0 | 40 | 0 | 20 | 0 | 40 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1350 | 0 | 500 | 0 | 30 | 0 | 15 | 0 | 40 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_control_sets_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_control_sets_placed.rpt" new file mode 100644 index 00000000..48dc0124 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_control_sets_placed.rpt" @@ -0,0 +1,77 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Dec 5 20:36:50 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file example_6_11_exe_control_sets_placed.rpt +| Design : example_6_11_exe +| Device : xc7a75t +--------------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Total control sets | 0 | +| Minimum number of control sets | 0 | +| Addition due to synthesis replication | 0 | +| Addition due to physical synthesis replication | 0 | +| Unused register locations in slices containing registers | 0 | ++----------------------------------------------------------+-------+ +* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers +** Run report_qor_suggestions for automated merging and remapping suggestions + + +2. Histogram +------------ + ++--------------------+-------+ +| Fanout | Count | ++--------------------+-------+ +| Total control sets | 0 | +| >= 0 to < 4 | 0 | +| >= 4 to < 6 | 0 | +| >= 6 to < 8 | 0 | +| >= 8 to < 10 | 0 | +| >= 10 to < 12 | 0 | +| >= 12 to < 14 | 0 | +| >= 14 to < 16 | 0 | +| >= 16 | 0 | ++--------------------+-------+ +* Control sets can be remapped at either synth_design or opt_design + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++--------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++--------------+---------------+------------------+------------------+----------------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_opted.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_opted.pb" new file mode 100644 index 00000000..9d083141 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_opted.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_opted.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_opted.rpt" new file mode 100644 index 00000000..f04b6828 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_opted.rpt" @@ -0,0 +1,75 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Dec 5 20:36:47 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_drc -file example_6_11_exe_drc_opted.rpt -pb example_6_11_exe_drc_opted.pb -rpx example_6_11_exe_drc_opted.rpx +| Design : example_6_11_exe +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 6 ++----------+------------------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+------------------+-----------------------------------------------------+------------+ +| LUTLP-1 | Critical Warning | Combinatorial Loop Alert | 5 | +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+------------------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +LUTLP-1#1 Critical Warning +Combinatorial Loop Alert +1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[6]. Please evaluate your design. The cells in the loop are: led_pin_OBUF[6]_inst_i_1. +Related violations: + +LUTLP-1#2 Critical Warning +Combinatorial Loop Alert +1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[6]_inst_i_2_n_0. Please evaluate your design. The cells in the loop are: led_pin_OBUF[6]_inst_i_2. +Related violations: + +LUTLP-1#3 Critical Warning +Combinatorial Loop Alert +1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[7]. Please evaluate your design. The cells in the loop are: led_pin_OBUF[7]_inst_i_1. +Related violations: + +LUTLP-1#4 Critical Warning +Combinatorial Loop Alert +1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[7]_inst_i_2_n_0. Please evaluate your design. The cells in the loop are: led_pin_OBUF[7]_inst_i_2. +Related violations: + +LUTLP-1#5 Critical Warning +Combinatorial Loop Alert +4 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[6]. Please evaluate your design. The cells in the loop are: led_pin_OBUF[6]_inst_i_1, led_pin_OBUF[6]_inst_i_2, led_pin_OBUF[7]_inst_i_1, led_pin_OBUF[7]_inst_i_2. +Related violations: + +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_opted.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_opted.rpx" new file mode 100644 index 00000000..98a1075d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_opted.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_routed.pb" new file mode 100644 index 00000000..9d083141 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_routed.rpt" new file mode 100644 index 00000000..a79ac8d7 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_routed.rpt" @@ -0,0 +1,75 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Dec 5 20:37:24 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_drc -file example_6_11_exe_drc_routed.rpt -pb example_6_11_exe_drc_routed.pb -rpx example_6_11_exe_drc_routed.rpx +| Design : example_6_11_exe +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Fully Routed +------------------------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 6 ++----------+------------------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+------------------+-----------------------------------------------------+------------+ +| LUTLP-1 | Critical Warning | Combinatorial Loop Alert | 5 | +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+------------------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +LUTLP-1#1 Critical Warning +Combinatorial Loop Alert +1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[6]. Please evaluate your design. The cells in the loop are: led_pin_OBUF[6]_inst_i_1. +Related violations: + +LUTLP-1#2 Critical Warning +Combinatorial Loop Alert +1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[6]_inst_i_2_n_0. Please evaluate your design. The cells in the loop are: led_pin_OBUF[6]_inst_i_2. +Related violations: + +LUTLP-1#3 Critical Warning +Combinatorial Loop Alert +1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[7]. Please evaluate your design. The cells in the loop are: led_pin_OBUF[7]_inst_i_1. +Related violations: + +LUTLP-1#4 Critical Warning +Combinatorial Loop Alert +1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[7]_inst_i_2_n_0. Please evaluate your design. The cells in the loop are: led_pin_OBUF[7]_inst_i_2. +Related violations: + +LUTLP-1#5 Critical Warning +Combinatorial Loop Alert +4 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'. One net in the loop is led_pin_OBUF[6]. Please evaluate your design. The cells in the loop are: led_pin_OBUF[6]_inst_i_1, led_pin_OBUF[6]_inst_i_2, led_pin_OBUF[7]_inst_i_1, led_pin_OBUF[7]_inst_i_2. +Related violations: + +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_routed.rpx" new file mode 100644 index 00000000..5cb4851a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_drc_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_io_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_io_placed.rpt" new file mode 100644 index 00000000..151e51ad --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_io_placed.rpt" @@ -0,0 +1,526 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Dec 5 20:36:50 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_io -file example_6_11_exe_io_placed.rpt +| Design : example_6_11_exe +| Device : xc7a75t +| Speed File : -1 +| Package : fgg484 +| Package Version : FINAL 2012-11-02 +| Package Pin Delay Version : VERS. 2.0 2012-11-02 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 10 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A4 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A6 | | | MGTPTXN2_216 | Gigabit | | | | | | | | | | | | | | | | +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A8 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A10 | | | MGTPRXN2_216 | Gigabit | | | | | | | | | | | | | | | | +| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A19 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A20 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A21 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA3 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA4 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| AA8 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA9 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA10 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA11 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA13 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA14 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA15 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA16 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| AA18 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| AA19 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| AA20 | led_pin[1] | High Range | IO_L8P_T1_D11_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| AA21 | led_pin[0] | High Range | IO_L8N_T1_D12_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB2 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB3 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| AB5 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB8 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB10 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB11 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB12 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB13 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| AB15 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB16 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB17 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB20 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| AB21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| AB22 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | btn_2 | High Range | IO_L2N_T0_AD12N_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | | +| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B4 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| B5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B6 | | | MGTPTXP2_216 | Gigabit | | | | | | | | | | | | | | | | +| B7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B8 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| B9 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B10 | | | MGTPRXP2_216 | Gigabit | | | | | | | | | | | | | | | | +| B11 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B15 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B16 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B20 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| B21 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| B22 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| C1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C2 | btn_1 | High Range | IO_L2P_T0_AD12P_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | | +| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C4 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C5 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C7 | | | MGTPTXN3_216 | Gigabit | | | | | | | | | | | | | | | | +| C8 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C9 | | | MGTPRXN3_216 | Gigabit | | | | | | | | | | | | | | | | +| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C11 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| C12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| C14 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C18 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C19 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C20 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| C21 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C22 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| D2 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D5 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| D6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| D7 | | | MGTPTXP3_216 | Gigabit | | | | | | | | | | | | | | | | +| D8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D9 | | | MGTPRXP3_216 | Gigabit | | | | | | | | | | | | | | | | +| D10 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| D11 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D14 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D16 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| D17 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| D19 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D20 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D21 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D22 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E6 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | | +| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E8 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | | +| E11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E12 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E14 | | High Range | IO_L4N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E15 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| E16 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L2N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| E19 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E21 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| E22 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F6 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | | +| F7 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| F8 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | | +| F9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| F10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| F13 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F15 | | High Range | IO_0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L2P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| F19 | | High Range | IO_L18P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| F20 | | High Range | IO_L18N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| F21 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | | +| F22 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| G1 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G15 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| G16 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G19 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G20 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G21 | | High Range | IO_L24P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| G22 | | High Range | IO_L24N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| H1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H2 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| H4 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| H14 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| H17 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H19 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H20 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H22 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| J1 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J2 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J4 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J14 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J17 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J19 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J20 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J21 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J22 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| K4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K6 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K16 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| K19 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| K20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K21 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| K22 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| L6 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| L12 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| L13 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| L18 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| L19 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| L20 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| L21 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M1 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| M4 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| M5 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| M6 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| M10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| M14 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| M15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| M16 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| M17 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| M21 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| M22 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| N1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| N2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N3 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| N4 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| N12 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| N13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| N14 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| N19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| N20 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| N21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| N22 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| P1 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P2 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| P5 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| P6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P14 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| P19 | led_pin[6] | High Range | IO_L5P_T0_D06_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P20 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| P21 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| P22 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| R2 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| R6 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R13 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| R14 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| R15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| R16 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| R19 | led_pin[5] | High Range | IO_L5N_T0_D07_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R21 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| R22 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| T3 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| T13 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| T19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T20 | led_pin[4] | High Range | IO_L6N_T0_D08_VREF_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T21 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| T22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U5 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U6 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| U9 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| U10 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| U11 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| U12 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| U13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U15 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| U16 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| U19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U20 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| U21 | led_pin[7] | High Range | IO_L4N_T0_D05_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U22 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V2 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| V4 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| V7 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V12 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| V13 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V14 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| V17 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| V19 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| V20 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V22 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| W1 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W2 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| W4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W5 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W6 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W9 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| W10 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| W11 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W12 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W13 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| W14 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| W15 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| W16 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| W17 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| W20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| W21 | led_pin[3] | High Range | IO_L7P_T1_D09_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| W22 | led_pin[2] | High Range | IO_L7N_T1_D10_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| Y1 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y3 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y4 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y7 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y8 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y9 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y10 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| Y11 | | High Range | IO_L11P_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y12 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y13 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y14 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y16 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y17 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| Y19 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| Y20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| Y21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| Y22 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_methodology_drc_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_methodology_drc_routed.pb" new file mode 100644 index 00000000..dd2b1ec9 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_methodology_drc_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_methodology_drc_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_methodology_drc_routed.rpt" new file mode 100644 index 00000000..3d7171a8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_methodology_drc_routed.rpt" @@ -0,0 +1,45 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Dec 5 20:37:25 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_methodology -file example_6_11_exe_methodology_drc_routed.rpt -pb example_6_11_exe_methodology_drc_routed.pb -rpx example_6_11_exe_methodology_drc_routed.rpx +| Design : example_6_11_exe +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Fully Routed +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 2 ++-----------+----------+--------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+--------------------------+------------+ +| TIMING-23 | Warning | Combinational loop found | 2 | ++-----------+----------+--------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-23#1 Warning +Combinational loop found +A timing loop has been detected on a combinational path. A timing arc has been disabled between led_pin_OBUF[7]_inst_i_1/I0 and led_pin_OBUF[7]_inst_i_1/O to disable the timing loop +Related violations: + +TIMING-23#2 Warning +Combinational loop found +A timing loop has been detected on a combinational path. A timing arc has been disabled between led_pin_OBUF[7]_inst_i_2/I3 and led_pin_OBUF[7]_inst_i_2/O to disable the timing loop +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_methodology_drc_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_methodology_drc_routed.rpx" new file mode 100644 index 00000000..686d007e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_methodology_drc_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_opt.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_opt.dcp" new file mode 100644 index 00000000..a81e2ed7 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_opt.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_physopt.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_physopt.dcp" new file mode 100644 index 00000000..cfa5af7a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_physopt.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_placed.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_placed.dcp" new file mode 100644 index 00000000..719191c1 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_placed.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_power_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_power_routed.rpt" new file mode 100644 index 00000000..7aca53e6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_power_routed.rpt" @@ -0,0 +1,141 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Dec 5 20:37:25 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_power -file example_6_11_exe_power_routed.rpt -pb example_6_11_exe_power_summary_routed.pb -rpx example_6_11_exe_power_routed.rpx +| Design : example_6_11_exe +| Device : xc7a75tfgg484-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 2.672 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 2.569 | +| Device Static (W) | 0.102 | +| Effective TJA (C/W) | 2.7 | +| Max Ambient (C) | 77.9 | +| Junction Temperature (C) | 32.1 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.017 | 7 | --- | --- | +| LUT as Logic | 0.017 | 5 | 47200 | 0.01 | +| Others | 0.000 | 2 | --- | --- | +| Signals | 0.051 | 7 | --- | --- | +| I/O | 2.502 | 10 | 285 | 3.51 | +| Static Power | 0.102 | | | | +| Total | 2.672 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.095 | 0.076 | 0.020 | +| Vccaux | 1.800 | 0.110 | 0.091 | 0.019 | +| Vcco33 | 3.300 | 0.710 | 0.706 | 0.004 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+----------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+----------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | High | User specified more than 25% of internal nodes | | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+----------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 2.7 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++------------------+-----------+ +| Name | Power (W) | ++------------------+-----------+ +| example_6_11_exe | 2.569 | ++------------------+-----------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_power_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_power_routed.rpx" new file mode 100644 index 00000000..2ec63809 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_power_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_power_summary_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_power_summary_routed.pb" new file mode 100644 index 00000000..bc2810b8 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_power_summary_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_route_status.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_route_status.pb" new file mode 100644 index 00000000..aac12688 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_route_status.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_route_status.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_route_status.rpt" new file mode 100644 index 00000000..c3f6e42e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_route_status.rpt" @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 19 : + # of nets not needing routing.......... : 10 : + # of internally routed nets........ : 10 : + # of routable nets..................... : 9 : + # of fully routed nets............. : 9 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_routed.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_routed.dcp" new file mode 100644 index 00000000..27440bbe Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_routed.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_timing_summary_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_timing_summary_routed.pb" new file mode 100644 index 00000000..4526e931 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_timing_summary_routed.pb" @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_timing_summary_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_timing_summary_routed.rpt" new file mode 100644 index 00000000..72aba71c --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_timing_summary_routed.rpt" @@ -0,0 +1,175 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Dec 5 20:37:25 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file example_6_11_exe_timing_summary_routed.rpt -pb example_6_11_exe_timing_summary_routed.pb -rpx example_6_11_exe_timing_summary_routed.rpx -warn_on_violation +| Design : example_6_11_exe +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 0 register/latch pins with no clock. + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 0 ports with no output delay specified. + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 7 combinational loops in the design. (HIGH) + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_timing_summary_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_timing_summary_routed.rpx" new file mode 100644 index 00000000..5de0f63c Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_timing_summary_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_utilization_placed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_utilization_placed.pb" new file mode 100644 index 00000000..d4c14010 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_utilization_placed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_utilization_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_utilization_placed.rpt" new file mode 100644 index 00000000..6d1a729e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/example_6_11_exe_utilization_placed.rpt" @@ -0,0 +1,203 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Dec 5 20:36:50 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_utilization -file example_6_11_exe_utilization_placed.rpt -pb example_6_11_exe_utilization_placed.pb +| Design : example_6_11_exe +| Device : 7a75tfgg484-1 +| Design State : Fully Placed +----------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 5 | 0 | 47200 | 0.01 | +| LUT as Logic | 5 | 0 | 47200 | 0.01 | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| Slice Registers | 0 | 0 | 94400 | 0.00 | +| Register as Flip Flop | 0 | 0 | 94400 | 0.00 | +| Register as Latch | 0 | 0 | 94400 | 0.00 | +| F7 Muxes | 0 | 0 | 31700 | 0.00 | +| F8 Muxes | 0 | 0 | 15850 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------------------------------------+------+-------+-----------+-------+ +| Slice | 2 | 0 | 15850 | 0.01 | +| SLICEL | 2 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 5 | 0 | 47200 | 0.01 | +| using O5 output only | 0 | | | | +| using O6 output only | 5 | | | | +| using O5 and O6 | 0 | | | | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 0 | 0 | 94400 | 0.00 | +| Register driven from within the Slice | 0 | | | | +| Register driven from outside the Slice | 0 | | | | +| Unique Control Sets | 0 | | 15850 | 0.00 | ++------------------------------------------+------+-------+-----------+-------+ +* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 105 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 105 | 0.00 | +| RAMB18 | 0 | 0 | 210 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 180 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 10 | 10 | 285 | 3.51 | +| IOB Master Pads | 4 | | | | +| IOB Slave Pads | 6 | | | | +| Bonded IPADs | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 6 | 0.00 | +| PHASER_REF | 0 | 0 | 6 | 0.00 | +| OUT_FIFO | 0 | 0 | 24 | 0.00 | +| IN_FIFO | 0 | 0 | 24 | 0.00 | +| IDELAYCTRL | 0 | 0 | 6 | 0.00 | +| IBUFDS | 0 | 0 | 274 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 24 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 24 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 300 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 0 | 0 | 6 | 0.00 | +| PLLE2_ADV | 0 | 0 | 6 | 0.00 | +| BUFMRCE | 0 | 0 | 12 | 0.00 | +| BUFHCE | 0 | 0 | 96 | 0.00 | +| BUFR | 0 | 0 | 24 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUFT | 5 | IO | +| OBUF | 3 | IO | +| LUT5 | 2 | LUT | +| IBUF | 2 | IO | +| LUT6 | 1 | LUT | +| LUT3 | 1 | LUT | +| LUT2 | 1 | LUT | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/gen_run.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/gen_run.xml" new file mode 100644 index 00000000..49e06cfe --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/gen_run.xml" @@ -0,0 +1,105 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/htr.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/htr.txt" new file mode 100644 index 00000000..aff28d13 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/htr.txt" @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log example_6_11_exe.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_6_11_exe.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/init_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/init_design.pb" new file mode 100644 index 00000000..2c68f3c1 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/init_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/opt_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/opt_design.pb" new file mode 100644 index 00000000..3bfc348c Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/opt_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/phys_opt_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/phys_opt_design.pb" new file mode 100644 index 00000000..a76010fd Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/phys_opt_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/place_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/place_design.pb" new file mode 100644 index 00000000..d3689988 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/place_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/project.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/project.wdf" new file mode 100644 index 00000000..81b71368 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/project.wdf" @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3536313538613332343261343435613238306265306537643464326539373439:506172656e742050412070726f6a656374204944:00 +eof:2608133965 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/route_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/route_design.pb" new file mode 100644 index 00000000..036137aa Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/route_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/rundef.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/rundef.js" new file mode 100644 index 00000000..7cfbdb8f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/rundef.js" @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;"; +} else { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log example_6_11_exe.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_6_11_exe.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/runme.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/runme.bat" new file mode 100644 index 00000000..1760626b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/runme.bat" @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/runme.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/runme.sh" new file mode 100644 index 00000000..7c8c0186 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/runme.sh" @@ -0,0 +1,47 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin +else + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log example_6_11_exe.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_6_11_exe.tcl -notrace + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/vivado.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/vivado.jou" new file mode 100644 index 00000000..6c72ceb0 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/vivado.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Tue Dec 5 20:36:20 2023 +# Process ID: 2644 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/impl_1 +# Command line: vivado.exe -log example_6_11_exe.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source example_6_11_exe.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/impl_1/example_6_11_exe.vdi +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source example_6_11_exe.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/vivado.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/vivado.pb" new file mode 100644 index 00000000..b155e40f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/vivado.pb" @@ -0,0 +1,4 @@ + + + +End Record \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/write_bitstream.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/write_bitstream.pb" new file mode 100644 index 00000000..c8a12e33 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/impl_1/write_bitstream.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/.Vivado_Synthesis.queue.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/.Vivado_Synthesis.queue.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/.Xil/example_6_11_exe_propImpl.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/.Xil/example_6_11_exe_propImpl.xdc" new file mode 100644 index 00000000..9a67858d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/.Xil/example_6_11_exe_propImpl.xdc" @@ -0,0 +1,261 @@ +set_property SRC_FILE_INFO {cfile:D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc rfile:../../../ACE1.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design] +//----------------------------------------------系统时钟------------------------------------ +set_property src_info {type:XDC file:1 line:2 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports sys_clk_50m] +set_property src_info {type:XDC file:1 line:3 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports sys_clk_100m] +set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports sys_clk_3hz] +set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] +//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------ +set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] +set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design] +//---------------------------------------------拨码?关sw0~sw7---------------------------------- +set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] +set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design] +//-----------------------------------------------9个按?-------------------------------------- +set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports btn_4] +set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports btn_5] +set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports btn_6] +set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports btn_7] +set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports btn_8] +set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_0_IBUF] +set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] +set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_2_IBUF] +set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_3_IBUF] +set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_4_IBUF] +set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_5_IBUF] +set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_6_IBUF] +set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_7_IBUF] +set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_8_IBUF] +set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design] +//-----------------------------------6个数码管----------------------------------------------------------- +set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[0]}] +set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[1]}] +set_property src_info {type:XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[2]}] +set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {digitron_out[3]}] +set_property src_info {type:XDC file:1 line:59 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS33} [get_ports {digitron_out[4]}] +set_property src_info {type:XDC file:1 line:60 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[5]}] +set_property src_info {type:XDC file:1 line:61 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[6]}] +set_property src_info {type:XDC file:1 line:62 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[7]}] +set_property src_info {type:XDC file:1 line:64 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[0]}] +set_property src_info {type:XDC file:1 line:65 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[1]}] +set_property src_info {type:XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[2]}] +set_property src_info {type:XDC file:1 line:67 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[3]}] +set_property src_info {type:XDC file:1 line:69 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {digitron_a[0]}] +set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[1]}] +set_property src_info {type:XDC file:1 line:71 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {digitron_a[2]}] +set_property src_info {type:XDC file:1 line:72 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[3]}] +set_property src_info {type:XDC file:1 line:74 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33} [get_ports {digitron_b[0]}] +set_property src_info {type:XDC file:1 line:75 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[1]}] +set_property src_info {type:XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[2]}] +set_property src_info {type:XDC file:1 line:77 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports {digitron_b[3]}] +set_property src_info {type:XDC file:1 line:81 export:INPUT save:INPUT read:READ} [current_design] +//----------------------------------------------串口--------------------------------------------- +set_property src_info {type:XDC file:1 line:82 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports uart_rxd] +set_property src_info {type:XDC file:1 line:83 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports uart_txd] +set_property src_info {type:XDC file:1 line:87 export:INPUT save:INPUT read:READ} [current_design] +//----------------------------------------------蜂鸣?----------------------------------------- +set_property src_info {type:XDC file:1 line:88 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports buzzer] +set_property src_info {type:XDC file:1 line:92 export:INPUT save:INPUT read:READ} [current_design] +//--------------------------------------------------------XADC数模转换------------------- +set_property src_info {type:XDC file:1 line:93 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports ad15p] +set_property src_info {type:XDC file:1 line:94 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports ad15n] +set_property src_info {type:XDC file:1 line:95 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports ad7p] +set_property src_info {type:XDC file:1 line:96 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports ad7n] +set_property src_info {type:XDC file:1 line:97 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports ad14p] +set_property src_info {type:XDC file:1 line:98 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports ad14n] +set_property src_info {type:XDC file:1 line:99 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports ad6p] +set_property src_info {type:XDC file:1 line:100 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports ad6n] +set_property src_info {type:XDC file:1 line:101 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports ad5p] +set_property src_info {type:XDC file:1 line:102 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS33} [get_ports ad5n] +set_property src_info {type:XDC file:1 line:103 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports ad13p] +set_property src_info {type:XDC file:1 line:104 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports ad13n] +set_property src_info {type:XDC file:1 line:105 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports ad4p] +set_property src_info {type:XDC file:1 line:106 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports ad4n] +set_property src_info {type:XDC file:1 line:111 export:INPUT save:INPUT read:READ} [current_design] +//--------------------------------------------------------DDR3L------------------------------------- +set_property src_info {type:XDC file:1 line:112 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_p] +set_property src_info {type:XDC file:1 line:113 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_n] +set_property src_info {type:XDC file:1 line:114 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_p] +set_property src_info {type:XDC file:1 line:115 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_n] +set_property src_info {type:XDC file:1 line:117 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq0] +set_property src_info {type:XDC file:1 line:118 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq1] +set_property src_info {type:XDC file:1 line:119 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq2] +set_property src_info {type:XDC file:1 line:120 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq3] +set_property src_info {type:XDC file:1 line:121 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq4] +set_property src_info {type:XDC file:1 line:122 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq5] +set_property src_info {type:XDC file:1 line:123 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq6] +set_property src_info {type:XDC file:1 line:124 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq7] +set_property src_info {type:XDC file:1 line:125 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq8] +set_property src_info {type:XDC file:1 line:126 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq9] +set_property src_info {type:XDC file:1 line:127 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq10] +set_property src_info {type:XDC file:1 line:128 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq11] +set_property src_info {type:XDC file:1 line:129 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq12] +set_property src_info {type:XDC file:1 line:130 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq13] +set_property src_info {type:XDC file:1 line:131 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq14] +set_property src_info {type:XDC file:1 line:132 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq15] +set_property src_info {type:XDC file:1 line:134 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a0] +set_property src_info {type:XDC file:1 line:135 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a1] +set_property src_info {type:XDC file:1 line:136 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a2] +set_property src_info {type:XDC file:1 line:137 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a3] +set_property src_info {type:XDC file:1 line:138 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a4] +set_property src_info {type:XDC file:1 line:139 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a5] +set_property src_info {type:XDC file:1 line:140 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a6] +set_property src_info {type:XDC file:1 line:141 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a7] +set_property src_info {type:XDC file:1 line:142 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a8] +set_property src_info {type:XDC file:1 line:143 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a9] +set_property src_info {type:XDC file:1 line:144 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a10] +set_property src_info {type:XDC file:1 line:145 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a11] +set_property src_info {type:XDC file:1 line:146 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a12] +set_property src_info {type:XDC file:1 line:148 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba0] +set_property src_info {type:XDC file:1 line:149 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba1] +set_property src_info {type:XDC file:1 line:150 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba2] +set_property src_info {type:XDC file:1 line:152 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm0] +set_property src_info {type:XDC file:1 line:153 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm1] +set_property src_info {type:XDC file:1 line:155 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports ddr3l_odt] +set_property src_info {type:XDC file:1 line:156 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_p] +set_property src_info {type:XDC file:1 line:157 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_n] +set_property src_info {type:XDC file:1 line:158 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cke] +set_property src_info {type:XDC file:1 line:159 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports ddr3l_cs] +set_property src_info {type:XDC file:1 line:160 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ras] +set_property src_info {type:XDC file:1 line:161 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports ddr3l_we] +set_property src_info {type:XDC file:1 line:162 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports ddr3l_reset] +set_property src_info {type:XDC file:1 line:163 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cas] diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/.vivado.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/.vivado.begin.rst" new file mode 100644 index 00000000..f2bef197 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/.vivado.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/.vivado.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/.vivado.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/ISEWrap.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/ISEWrap.js" new file mode 100644 index 00000000..97a2ecbc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/ISEWrap.js" @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/ISEWrap.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/ISEWrap.sh" new file mode 100644 index 00000000..f679f2e8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/ISEWrap.sh" @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/__synthesis_is_complete__" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/__synthesis_is_complete__" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/example_6_11_exe.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/example_6_11_exe.dcp" new file mode 100644 index 00000000..954c8da5 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/example_6_11_exe.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/example_6_11_exe.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/example_6_11_exe.tcl" new file mode 100644 index 00000000..8b7a2c03 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/example_6_11_exe.tcl" @@ -0,0 +1,55 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param chipscope.maxJobs 8 +create_project -in_memory -part xc7a75tfgg484-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.cache/wt [current_project] +set_property parent.project_path D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo d:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.v +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc +set_property used_in_implementation false [get_files D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc] + +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +synth_design -top example_6_11_exe -part xc7a75tfgg484-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef example_6_11_exe.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file example_6_11_exe_utilization_synth.rpt -pb example_6_11_exe_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/example_6_11_exe.vds" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/example_6_11_exe.vds" new file mode 100644 index 00000000..1ee0f94a --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/example_6_11_exe.vds" @@ -0,0 +1,606 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Tue Dec 5 20:35:36 2023 +# Process ID: 7712 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/synth_1 +# Command line: vivado.exe -log example_6_11_exe.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_11_exe.tcl +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/synth_1/example_6_11_exe.vds +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source example_6_11_exe.tcl -notrace +Command: synth_design -top example_6_11_exe -part xc7a75tfgg484-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a75t' +INFO: [Device 21-403] Loading part xc7a75tfgg484-1 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 16660 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 852.137 ; gain = 234.758 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'example_6_11_exe' [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.v:129] +INFO: [Synth 8-6157] synthesizing module 'example_6_11' [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.v:98] +INFO: [Synth 8-6157] synthesizing module 'not_gate' [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.v:5] +INFO: [Synth 8-6155] done synthesizing module 'not_gate' (1#1) [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.v:5] +INFO: [Synth 8-6157] synthesizing module 'and_gate2' [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.v:44] +INFO: [Synth 8-6155] done synthesizing module 'and_gate2' (2#1) [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.v:44] +INFO: [Synth 8-6157] synthesizing module 'and_gate3' [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.v:57] +INFO: [Synth 8-6155] done synthesizing module 'and_gate3' (3#1) [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.v:57] +INFO: [Synth 8-6157] synthesizing module 'or_gate2' [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.v:71] +INFO: [Synth 8-6155] done synthesizing module 'or_gate2' (4#1) [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.v:71] +INFO: [Synth 8-6157] synthesizing module 'or_gate3' [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.v:84] +INFO: [Synth 8-6155] done synthesizing module 'or_gate3' (5#1) [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.v:84] +INFO: [Synth 8-6155] done synthesizing module 'example_6_11' (6#1) [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.v:98] +INFO: [Synth 8-6155] done synthesizing module 'example_6_11_exe' (7#1) [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.v:129] +WARNING: [Synth 8-3331] design example_6_11_exe has unconnected port led_pin[5] +WARNING: [Synth 8-3331] design example_6_11_exe has unconnected port led_pin[4] +WARNING: [Synth 8-3331] design example_6_11_exe has unconnected port led_pin[3] +WARNING: [Synth 8-3331] design example_6_11_exe has unconnected port led_pin[2] +WARNING: [Synth 8-3331] design example_6_11_exe has unconnected port led_pin[1] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 925.195 ; gain = 307.816 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 925.195 ; gain = 307.816 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 925.195 ; gain = 307.816 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 925.195 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------系统时钟------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:1] +WARNING: [Vivado 12-584] No ports matched 'sys_clk_50m'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_100m'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:3] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:3] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_3hz'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:4] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:4] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:7] +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------拨码?关sw0~sw7----------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:19] +WARNING: [Vivado 12-584] No ports matched 'sw_pin[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:20] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:20] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:21] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:21] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:22] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:22] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:23] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:23] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[4]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:24] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:24] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[5]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:25] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:25] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[6]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:26] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:26] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[7]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:27] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:27] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------------------9个按?--------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:31] +WARNING: [Vivado 12-584] No ports matched 'btn_0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:32] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:32] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:35] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:35] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:36] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:36] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:37] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:37] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:38] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:38] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:39] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:39] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:40] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:40] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_0_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:43] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:43] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_1_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:44] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:44] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_2_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:45] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:45] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_3_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:46] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:46] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_4_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:47] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:47] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_5_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:48] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:48] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_6_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:49] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_7_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:50] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:50] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_8_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:51] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:51] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------6个数码管-----------------------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:54] +WARNING: [Vivado 12-584] No ports matched 'digitron_out[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:55] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:55] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:56] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:56] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:57] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:57] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:58] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:58] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[4]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:59] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:59] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[5]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:60] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:60] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[6]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:61] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:61] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[7]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:62] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:62] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:64] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:64] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:65] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:65] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:66] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:66] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:67] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:67] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:69] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:69] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:70] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:70] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:71] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:71] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:72] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:72] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:74] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:74] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:75] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:75] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:76] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:76] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:77] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:77] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------串口---------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:81] +WARNING: [Vivado 12-584] No ports matched 'uart_rxd'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:82] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:82] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'uart_txd'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:83] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:83] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------蜂鸣?-----------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:87] +WARNING: [Vivado 12-584] No ports matched 'buzzer'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:88] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:88] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------XADC数模转换-------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:92] +WARNING: [Vivado 12-584] No ports matched 'ad15p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:93] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:93] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad15n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:94] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:94] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:95] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:95] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:96] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:96] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:97] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:97] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:98] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:98] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:99] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:99] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:100] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:100] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:101] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:101] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:102] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:102] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:103] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:103] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:104] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:104] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:105] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:105] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:106] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:106] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------DDR3L-------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:111] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:112] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:112] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:113] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:113] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:114] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:114] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:115] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:115] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:117] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:117] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:118] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:118] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:119] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:119] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:120] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:120] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:121] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:121] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:122] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:122] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:123] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:123] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:124] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:124] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:125] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:125] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq9'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:126] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:126] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq10'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:127] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:127] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq11'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:128] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:128] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq12'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:129] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:129] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq13'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:130] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:130] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq14'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:131] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:131] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq15'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:132] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:132] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:134] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:134] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:135] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:135] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:136] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:136] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:137] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:137] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:138] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:138] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:139] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:139] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:140] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:140] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:141] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:141] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:142] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:142] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a9'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:143] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:143] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a10'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:144] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:144] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a11'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:145] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:145] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a12'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:146] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:146] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:148] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:148] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:149] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:149] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:150] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:150] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:152] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:153] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_odt'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:155] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:156] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:157] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cke'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:158] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cs'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:159] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ras'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:160] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_we'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:161] +INFO: [Common 17-14] Message 'Vivado 12-584' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc:161] +Finished Parsing XDC File [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/ACE1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/example_6_11_exe_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/example_6_11_exe_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 979.078 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 979.078 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 979.078 ; gain = 361.699 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a75tfgg484-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 979.078 ; gain = 361.699 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 979.078 ; gain = 361.699 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 979.078 ; gain = 361.699 +--------------------------------------------------------------------------------- +INFO: [Synth 8-223] decloning instance 'U/U3' (and_gate2) to 'U/U10' + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 180 (col length:80) +BRAMs: 210 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3331] design example_6_11_exe has unconnected port led_pin[5] +WARNING: [Synth 8-3331] design example_6_11_exe has unconnected port led_pin[4] +WARNING: [Synth 8-3331] design example_6_11_exe has unconnected port led_pin[3] +WARNING: [Synth 8-3331] design example_6_11_exe has unconnected port led_pin[2] +WARNING: [Synth 8-3331] design example_6_11_exe has unconnected port led_pin[1] +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 979.078 ; gain = 361.699 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:21 . Memory (MB): peak = 990.605 ; gain = 373.227 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:21 . Memory (MB): peak = 990.605 ; gain = 373.227 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:21 . Memory (MB): peak = 1000.188 ; gain = 382.809 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1016.062 ; gain = 398.684 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1016.062 ; gain = 398.684 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1016.062 ; gain = 398.684 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1016.062 ; gain = 398.684 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1016.062 ; gain = 398.684 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1016.062 ; gain = 398.684 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |LUT2 | 1| +|2 |LUT3 | 1| +|3 |LUT5 | 2| +|4 |LUT6 | 1| +|5 |IBUF | 2| +|6 |OBUF | 3| +|7 |OBUFT | 5| ++------+------+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 15| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1016.062 ; gain = 398.684 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 5 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1016.062 ; gain = 344.801 +Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1016.062 ; gain = 398.684 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1016.062 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1029.273 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +26 Infos, 119 Warnings, 109 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1029.273 ; gain = 723.324 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1029.273 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/synth_1/example_6_11_exe.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file example_6_11_exe_utilization_synth.rpt -pb example_6_11_exe_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Tue Dec 5 20:36:12 2023... diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/example_6_11_exe_utilization_synth.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/example_6_11_exe_utilization_synth.pb" new file mode 100644 index 00000000..d4c14010 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/example_6_11_exe_utilization_synth.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/example_6_11_exe_utilization_synth.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/example_6_11_exe_utilization_synth.rpt" new file mode 100644 index 00000000..88dee5ac --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/example_6_11_exe_utilization_synth.rpt" @@ -0,0 +1,177 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Tue Dec 5 20:36:12 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_utilization -file example_6_11_exe_utilization_synth.rpt -pb example_6_11_exe_utilization_synth.pb +| Design : example_6_11_exe +| Device : 7a75tfgg484-1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 5 | 0 | 47200 | 0.01 | +| LUT as Logic | 5 | 0 | 47200 | 0.01 | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| Slice Registers | 0 | 0 | 94400 | 0.00 | +| Register as Flip Flop | 0 | 0 | 94400 | 0.00 | +| Register as Latch | 0 | 0 | 94400 | 0.00 | +| F7 Muxes | 0 | 0 | 31700 | 0.00 | +| F8 Muxes | 0 | 0 | 15850 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 105 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 105 | 0.00 | +| RAMB18 | 0 | 0 | 210 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 180 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 10 | 0 | 285 | 3.51 | +| Bonded IPADs | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 6 | 0.00 | +| PHASER_REF | 0 | 0 | 6 | 0.00 | +| OUT_FIFO | 0 | 0 | 24 | 0.00 | +| IN_FIFO | 0 | 0 | 24 | 0.00 | +| IDELAYCTRL | 0 | 0 | 6 | 0.00 | +| IBUFDS | 0 | 0 | 274 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 24 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 24 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 300 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 0 | 0 | 6 | 0.00 | +| PLLE2_ADV | 0 | 0 | 6 | 0.00 | +| BUFMRCE | 0 | 0 | 12 | 0.00 | +| BUFHCE | 0 | 0 | 96 | 0.00 | +| BUFR | 0 | 0 | 24 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUFT | 5 | IO | +| OBUF | 3 | IO | +| LUT5 | 2 | LUT | +| IBUF | 2 | IO | +| LUT6 | 1 | LUT | +| LUT3 | 1 | LUT | +| LUT2 | 1 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/gen_run.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/gen_run.xml" new file mode 100644 index 00000000..b6b85409 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/gen_run.xml" @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/htr.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/htr.txt" new file mode 100644 index 00000000..2472a6c4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/htr.txt" @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log example_6_11_exe.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_11_exe.tcl diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/rundef.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/rundef.js" new file mode 100644 index 00000000..8273e24e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/rundef.js" @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;"; +} else { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log example_6_11_exe.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_11_exe.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/runme.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/runme.bat" new file mode 100644 index 00000000..1760626b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/runme.bat" @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/runme.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/runme.sh" new file mode 100644 index 00000000..8a6aa4e6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/runme.sh" @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin +else + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log example_6_11_exe.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_11_exe.tcl diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/vivado.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/vivado.jou" new file mode 100644 index 00000000..06cf04f1 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/vivado.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Tue Dec 5 20:35:36 2023 +# Process ID: 7712 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/synth_1 +# Command line: vivado.exe -log example_6_11_exe.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_11_exe.tcl +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/synth_1/example_6_11_exe.vds +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source example_6_11_exe.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/vivado.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/vivado.pb" new file mode 100644 index 00000000..0eefc12b Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.runs/synth_1/vivado.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/compile.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/compile.bat" new file mode 100644 index 00000000..787e9b47 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/compile.bat" @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2019.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Tue Dec 05 21:32:03 +0800 2023 +REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +REM +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvlog --incr --relax -prj example_6_11_sim_vlog.prj" +call xvlog --incr --relax -prj example_6_11_sim_vlog.prj -log xvlog.log +call type xvlog.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/elaborate.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/elaborate.bat" new file mode 100644 index 00000000..b12123d9 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/elaborate.bat" @@ -0,0 +1,24 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2019.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Tue Dec 05 21:32:04 +0800 2023 +REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +REM +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +echo "xelab -wto 56158a3242a445a280be0e7d4d2e9749 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot example_6_11_sim_behav xil_defaultlib.example_6_11_sim xil_defaultlib.glbl -log elaborate.log" +call xelab -wto 56158a3242a445a280be0e7d4d2e9749 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot example_6_11_sim_behav xil_defaultlib.example_6_11_sim xil_defaultlib.glbl -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/example_6_11_sim.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/example_6_11_sim.tcl" new file mode 100644 index 00000000..1094e45d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/example_6_11_sim.tcl" @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/example_6_11_sim_behav.wdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/example_6_11_sim_behav.wdb" new file mode 100644 index 00000000..c42a92f7 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/example_6_11_sim_behav.wdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/example_6_11_sim_vlog.prj" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/example_6_11_sim_vlog.prj" new file mode 100644 index 00000000..e0fa5412 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/example_6_11_sim_vlog.prj" @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../example_6_11_ACE1.v" \ +"../../../../../example_6_11_sim_ACE1.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/glbl.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/glbl.v" new file mode 100644 index 00000000..be642335 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/glbl.v" @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/simulate.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/simulate.bat" new file mode 100644 index 00000000..bcea57f2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/simulate.bat" @@ -0,0 +1,24 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2019.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Tue Dec 05 21:32:05 +0800 2023 +REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +REM +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +echo "xsim example_6_11_sim_behav -key {Behavioral:sim_1:Functional:example_6_11_sim} -tclbatch example_6_11_sim.tcl -log simulate.log" +call xsim example_6_11_sim_behav -key {Behavioral:sim_1:Functional:example_6_11_sim} -tclbatch example_6_11_sim.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/webtalk.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/webtalk.jou" new file mode 100644 index 00000000..a5cd0e1b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/webtalk.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Tue Dec 5 21:30:55 2023 +# Process ID: 7640 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/xsim_webtalk.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/webtalk_34220.backup.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/webtalk_34220.backup.jou" new file mode 100644 index 00000000..213a47fa --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/webtalk_34220.backup.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Tue Dec 5 21:17:08 2023 +# Process ID: 34220 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/xsim_webtalk.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xelab.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xelab.pb" new file mode 100644 index 00000000..569ed765 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xelab.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/Compile_Options.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/Compile_Options.txt" new file mode 100644 index 00000000..b2631aad --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/Compile_Options.txt" @@ -0,0 +1 @@ +-wto "56158a3242a445a280be0e7d4d2e9749" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "example_6_11_sim_behav" "xil_defaultlib.example_6_11_sim" "xil_defaultlib.glbl" -log "elaborate.log" diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/TempBreakPointFile.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/TempBreakPointFile.txt" new file mode 100644 index 00000000..fdbc612e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/TempBreakPointFile.txt" @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/.xsim_webtallk.info" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/.xsim_webtallk.info" new file mode 100644 index 00000000..9a49d913 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/.xsim_webtallk.info" @@ -0,0 +1,5 @@ +1701782227 +1701783054 +7 +1 +56158a3242a445a280be0e7d4d2e9749 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/usage_statistics_ext_xsim.html" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/usage_statistics_ext_xsim.html" new file mode 100644 index 00000000..bfb4e075 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/usage_statistics_ext_xsim.html" @@ -0,0 +1,54 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2708876
date_generatedTue Dec 5 21:30:54 2023os_platformWIN64
product_versionXSIM v2019.2 (64-bit)project_id56158a3242a445a280be0e7d4d2e9749
project_iteration2random_idd24833b7-4cbd-4f74-b7c7-3cb815d77764
registration_idd24833b7-4cbd-4f74-b7c7-3cb815d77764route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_nameAMD Ryzen 9 7945HX with Radeon Graphics cpu_speed2495 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram16.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + + +
command_line_options
command=xsimrunall=true
+
+ + + + + + + +
usage
iteration=1runtime=120 nssimulation_memory=8464_KBsimulation_time=3.62_sec
trace_waveform=true
+

+ + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/usage_statistics_ext_xsim.wdm" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/usage_statistics_ext_xsim.wdm" new file mode 100644 index 00000000..04105306 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/usage_statistics_ext_xsim.wdm" @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + context="xsim\\command_line_options"; + xml_map="xsim\\command_line_options"; + html_map="xsim\\command_line_options"; + html_format="UnisimStatsStyle"; + }, + { + context="xsim\\usage"; + xml_map="xsim\\usage"; + html_map="xsim\\usage"; + html_format="UnisimStatsStyle"; + } + ); + } +); + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/usage_statistics_ext_xsim.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/usage_statistics_ext_xsim.xml" new file mode 100644 index 00000000..a29f0f92 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/usage_statistics_ext_xsim.xml" @@ -0,0 +1,45 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ + +
+
+ + + + + +
+
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/xsim_webtalk.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/xsim_webtalk.tcl" new file mode 100644 index 00000000..c2c70507 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/xsim_webtalk.tcl" @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Tue Dec 5 21:36:37 2023" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2019.2 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2708876" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "d24833b7-4cbd-4f74-b7c7-3cb815d77764" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "56158a3242a445a280be0e7d4d2e9749" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "6" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Windows Server 2016 or Windows 10" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "AMD Ryzen 9 7945HX with Radeon Graphics " -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2495 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "120 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "3" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.00_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "8040_KB" -context "xsim\\usage" +webtalk_transmit -clientid 3179657099 -regid "" -xml D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/usage_statistics_ext_xsim.xml -html D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/usage_statistics_ext_xsim.html -wdm D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.dbg" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.dbg" new file mode 100644 index 00000000..f88bd69c Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.dbg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.mem" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.mem" new file mode 100644 index 00000000..3539b4ea Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.mem" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.reloc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.reloc" new file mode 100644 index 00000000..6297ddda Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.reloc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.rlx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.rlx" new file mode 100644 index 00000000..845fb556 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.rlx" @@ -0,0 +1,12 @@ + +{ + crc : 5119877695422669032 , + ccp_crc : 0 , + cmdline : " -wto 56158a3242a445a280be0e7d4d2e9749 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot example_6_11_sim_behav xil_defaultlib.example_6_11_sim xil_defaultlib.glbl" , + buildDate : "Nov 6 2019" , + buildTime : "21:57:16" , + linkCmd : "D:\\Xilinx\\Vivado\\2019.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/example_6_11_sim_behav/xsimk.exe\" \"xsim.dir/example_6_11_sim_behav/obj/xsim_0.win64.obj\" \"xsim.dir/example_6_11_sim_behav/obj/xsim_1.win64.obj\" -L\"D:\\Xilinx\\Vivado\\2019.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.rtti" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.rtti" new file mode 100644 index 00000000..79aa91ab Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.rtti" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.svtype" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.svtype" new file mode 100644 index 00000000..55847a84 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.svtype" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.type" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.type" new file mode 100644 index 00000000..14a09a21 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.type" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.xdbg" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.xdbg" new file mode 100644 index 00000000..7913f1f9 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsim.xdbg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsimSettings.ini" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsimSettings.ini" new file mode 100644 index 00000000..c32014cc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_11_sim_behav/xsimSettings.ini" @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPEPROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +PROTO_DATA_TYPE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_11.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_11.sdb" new file mode 100644 index 00000000..ce3e9bed Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_11.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_11_sim.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_11_sim.sdb" new file mode 100644 index 00000000..6926b7ad Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_11_sim.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb" new file mode 100644 index 00000000..699a9dca Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/nand_gate2.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/nand_gate2.sdb" new file mode 100644 index 00000000..9140e7b7 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/nand_gate2.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/nand_gate3.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/nand_gate3.sdb" new file mode 100644 index 00000000..4d7e3a83 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/nand_gate3.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/not_gate.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/not_gate.sdb" new file mode 100644 index 00000000..035b14f2 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/not_gate.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx" new file mode 100644 index 00000000..cbde4a8f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx" @@ -0,0 +1,7 @@ +0.6 +2019.2 +Nov 6 2019 +21:57:16 +D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.sim/sim_1/behav/xsim/glbl.v,1573089660,verilog,,,,glbl,,,,,,,, +D:/DigitalLogic/ACE1/Test5_Design/example_6_11_ACE1/example_6_11_ACE1.v,1701783015,verilog,,D:/DigitalLogic/ACE1/Test5_Design/example_6_11_sim_ACE1.v,,example_6_11;nand_gate2;nand_gate3;not_gate,,,,,,,, +D:/DigitalLogic/ACE1/Test5_Design/example_6_11_sim_ACE1.v,1701783116,verilog,,,,example_6_11_sim,,,,,,,, diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.ini" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.ini" new file mode 100644 index 00000000..e8199b25 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xsim.ini" @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xvlog.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xvlog.pb" new file mode 100644 index 00000000..35fc26ce Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.sim/sim_1/behav/xsim/xvlog.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.v" new file mode 100644 index 00000000..98fb0083 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.v" @@ -0,0 +1,66 @@ +//ṹʽģΪʽʵ6.11ĵ巢루x1x2Ϊϵߵ2أ״̬y2y1ZΪߵ2LEDԼұߵ1LEDơ + +`timescale 1ns / 1ps + +module not_gate( + input a, + output f +); + reg y; + always @(*) //Ϊʽ + begin + y <= ~a; + end + assign f = y; +endmodule + +module nand_gate2( + input a, + input b, + output f +); + reg y; + always @(*) //Ϊʽ + begin + y <= ~(a & b); + end + assign f = y; +endmodule + +module nand_gate3( + input a, + input b, + input c, + output f +); + reg y; + always @(*) //Ϊʽ + begin + y <= ~(a & b & c); + end + assign f = y; +endmodule + + +module example_6_11_2( + input x1,x2, + input wire clk, + input y2, y1, + output ny2, ny1, z +); + + wire t1, t2, t3, t4, t5, t6, t7; + + not_gate u1(.a(x1),.f(t1)); //ṹʽ + not_gate u2(.a(x2),.f(t2)); //ṹʽ + + nand_gate2 U3(.a(x2),.b(y2),.f(t3)); + not_gate U4(.a(t3),.f(z)); + + nand_gate3 U5(.a(t1),.b(t2),.c(y1),.f(t4)); //ṹʽ + nand_gate2 U6(.a(t3),.b(y1),.f(t5)); //ṹʽ + + nand_gate2 U7(.a(t4),.b(t3),.f(ny2)); //ṹʽ + nand_gate2 U8(.a(t1),.b(t5),.f(ny1)); //ṹʽ + +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.xpr" new file mode 100644 index 00000000..187daab0 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_11_EGO1/example_6_11_EGO1.xpr" @@ -0,0 +1,180 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/EGO1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/EGO1.xdc" new file mode 100644 index 00000000..18c97a11 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/EGO1.xdc" @@ -0,0 +1,253 @@ +//----------------------------------------------系统时钟和复位------------------------------------ +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports sys_clk_in] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports sys_rst_n] + + +//-----------------------------------------------5个按键--------------------------------------------- +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports btn_4] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_0_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_2_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_3_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_4_IBUF] + + +//---------------------------------------------拨码开关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + +//------------------------------------------拨码开关(DIP开关)sw8~sw15--------------------- +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[0]}] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[1]}] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[2]}] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[3]}] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports {dip_pin[4]}] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[5]}] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[6]}] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[7]}] + + +//---------------------------------------------LED0~LED15---------------------------------------- +set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN G3 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {led_pin[8]}] +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {led_pin[9]}] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led_pin[10]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led_pin[11]}] +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {led_pin[12]}] +set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports {led_pin[13]}] +set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports {led_pin[14]}] +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {led_pin[15]}] + + +//-----------------------------------8个数码管位选信号----------------------------------------------- +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[0]}] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[1]}] +set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[2]}] +set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[3]}] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[4]}] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[5]}] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[6]}] +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[7]}] + +//--------------------------------------------数码管段选信号--------------------------------------------- +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[0]}] +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[1]}] +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[2]}] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[3]}] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[4]}] +set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[5]}] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[6]}] +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[7]}] + +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[0]}] +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[1]}] +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[2]}] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[3]}] +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[4]}] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[5]}] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[6]}] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[7]}] + + +//--------------------------------------VGA行同步场同步信号----------------------------------------------- +set_property -dict {PACKAGE_PIN D7 IOSTANDARD LVCMOS33} [get_ports vga_hs_pin] +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports vga_vs_pin] + + +//--------------------------------------VGA红绿蓝信号------------------------------------------------------ +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[0]}] +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[1]}] +set_property -dict {PACKAGE_PIN C5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[2]}] +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[3]}] +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[4]}] +set_property -dict {PACKAGE_PIN A6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[5]}] +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[6]}] +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[7]}] +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[8]}] +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[9]}] +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[10]}] +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[11]}] + + +//----------------------------------------------串口-------------------------------------------------- +set_property -dict {PACKAGE_PIN N5 IOSTANDARD LVCMOS33} [get_ports PC_Uart_rxd] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports PC_Uart_txd] + + +//---------------------------------------------------PS2接口------------------------------------- +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports ps2_clk] +set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports ps2_data] + + +//------------------------------------------------IIC接口--------------------------------------------- +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports pw_iic_scl_io] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports pw_iic_sda_io] + + +//---------------------------------------------------蓝牙--------------------------------------------- +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports BT_Uart_rxd] +set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports BT_Uart_txd] + +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[0]}] +set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[1]}] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[2]}] +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[3]}] +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[4]}] + +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports bt_mcu_int_i] + + + +//-----------------------------------------------------音频接口--------------------------------------- +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports audio_pwm_o] +set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports audio_sd_o ] + + + +//--------------------------------------------------------XADC模数转换----------------------------------- +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_n] +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_p] +set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_n] +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_p] + + +//--------------------------------------------------------DAC数模转换--------------------------- +set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports dac_ile] +set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports dac_cs_n] +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports dac_wr1_n] +set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports dac_wr2_n] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports dac_xfer_n] + +set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS33} [get_ports {dac_data[0]}] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33} [get_ports {dac_data[1]}] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports {dac_data[2]}] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports {dac_data[3]}] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {dac_data[4]}] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {dac_data[5]}] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports {dac_data[6]}] +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports {dac_data[7]}] + + + +//-------------------------------------------------SDRAM芯片接口------------------------------------- +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[18]}] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[17]}] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[16]}] +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[15]}] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {sram_addr[14]}] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[13]}] +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[12]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[11]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[10]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[9]}] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[8]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[7]}] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[6]}] +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[5]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[4]}] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[3]}] +set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[2]}] +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[1]}] +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[0]}] + +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports sram_ce_n] +set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports sram_lb_n] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports sram_oe_n] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports sram_ub_n] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports sram_we_n] + +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {sram_data[15]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {sram_data[14]}] +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {sram_data[13]}] +set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS33} [get_ports {sram_data[12]}] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {sram_data[11]}] +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {sram_data[10]}] +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {sram_data[9]}] +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {sram_data[8]}] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {sram_data[7]}] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {sram_data[6]}] +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {sram_data[5]}] +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {sram_data[4]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {sram_data[3]}] +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {sram_data[2]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {sram_data[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {sram_data[0]}] + + + + +//--------------------------------------32个pmod接口(扩展接口)------------------------------- +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {exp_io[0]}] +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports {exp_io[1]}] +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports {exp_io[2]}] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS33} [get_ports {exp_io[3]}] +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {exp_io[4]}] +set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports {exp_io[5]}] +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports {exp_io[6]}] +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {exp_io[7]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {exp_io[8]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {exp_io[9]}] +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports {exp_io[10]}] +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {exp_io[11]}] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {exp_io[12]}] +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {exp_io[13]}] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {exp_io[14]}] +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {exp_io[15]}] + +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {exp_io[16]}] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {exp_io[17]}] +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports {exp_io[18]}] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {exp_io[19]}] +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports {exp_io[20]}] +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports {exp_io[21]}] +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports {exp_io[22]}] +set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {exp_io[23]}] +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {exp_io[24]}] +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {exp_io[25]}] +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {exp_io[26]}] +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports {exp_io[27]}] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {exp_io[28]}] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {exp_io[29]}] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {exp_io[30]}] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {exp_io[31]}] + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..e8a25de9 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,8 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3133:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7372635f7265706c6163655f66696c65:33:00:00 +eof:1712339517 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..c12f7fc0 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,4 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757064617465736f7572636566696c6573:33:00:00 +eof:1852879985 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..9b342093 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..bc070d17 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,38 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.hw/example_6_4_1_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.hw/example_6_4_1_EGO1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.hw/example_6_4_1_EGO1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/.jobs/vrs_config_1.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/.jobs/vrs_config_1.xml" new file mode 100644 index 00000000..4b7e7d05 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/.jobs/vrs_config_1.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.Vivado_Implementation.queue.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.Vivado_Implementation.queue.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.init_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.init_design.begin.rst" new file mode 100644 index 00000000..a71c8ef6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.init_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.init_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.init_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.opt_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.opt_design.begin.rst" new file mode 100644 index 00000000..a71c8ef6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.opt_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.opt_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.opt_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.phys_opt_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.phys_opt_design.begin.rst" new file mode 100644 index 00000000..a71c8ef6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.phys_opt_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.phys_opt_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.phys_opt_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.place_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.place_design.begin.rst" new file mode 100644 index 00000000..a71c8ef6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.place_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.place_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.place_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.route_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.route_design.begin.rst" new file mode 100644 index 00000000..a71c8ef6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.route_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.route_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.route_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.vivado.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.vivado.begin.rst" new file mode 100644 index 00000000..ed08bbcd --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.vivado.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.vivado.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.vivado.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.write_bitstream.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.write_bitstream.begin.rst" new file mode 100644 index 00000000..a71c8ef6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.write_bitstream.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.write_bitstream.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/.write_bitstream.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/ISEWrap.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/ISEWrap.js" new file mode 100644 index 00000000..97a2ecbc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/ISEWrap.js" @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/ISEWrap.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/ISEWrap.sh" new file mode 100644 index 00000000..f679f2e8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/ISEWrap.sh" @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe.bit" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe.bit" new file mode 100644 index 00000000..4ecd013a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe.bit" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe.tcl" new file mode 100644 index 00000000..0b65d20a --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe.tcl" @@ -0,0 +1,187 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param chipscope.maxJobs 8 + set_param xicom.use_bs_reader 1 + create_project -in_memory -part xc7a75tfgg484-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.cache/wt [current_project] + set_property parent.project_path D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.xpr [current_project] + set_property ip_output_repo D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/synth_1/example_6_4_1_exe.dcp + read_xdc D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc + link_design -top example_6_4_1_exe -part xc7a75tfgg484-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force example_6_4_1_exe_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file example_6_4_1_exe_drc_opted.rpt -pb example_6_4_1_exe_drc_opted.pb -rpx example_6_4_1_exe_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force example_6_4_1_exe_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file example_6_4_1_exe_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file example_6_4_1_exe_utilization_placed.rpt -pb example_6_4_1_exe_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file example_6_4_1_exe_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step phys_opt_design +set ACTIVE_STEP phys_opt_design +set rc [catch { + create_msg_db phys_opt_design.pb + phys_opt_design + write_checkpoint -force example_6_4_1_exe_physopt.dcp + close_msg_db -file phys_opt_design.pb +} RESULT] +if {$rc} { + step_failed phys_opt_design + return -code error $RESULT +} else { + end_step phys_opt_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force example_6_4_1_exe_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file example_6_4_1_exe_drc_routed.rpt -pb example_6_4_1_exe_drc_routed.pb -rpx example_6_4_1_exe_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file example_6_4_1_exe_methodology_drc_routed.rpt -pb example_6_4_1_exe_methodology_drc_routed.pb -rpx example_6_4_1_exe_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file example_6_4_1_exe_power_routed.rpt -pb example_6_4_1_exe_power_summary_routed.pb -rpx example_6_4_1_exe_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file example_6_4_1_exe_route_status.rpt -pb example_6_4_1_exe_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file example_6_4_1_exe_timing_summary_routed.rpt -pb example_6_4_1_exe_timing_summary_routed.pb -rpx example_6_4_1_exe_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file example_6_4_1_exe_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file example_6_4_1_exe_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file example_6_4_1_exe_bus_skew_routed.rpt -pb example_6_4_1_exe_bus_skew_routed.pb -rpx example_6_4_1_exe_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force example_6_4_1_exe_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + catch { write_mem_info -force example_6_4_1_exe.mmi } + write_bitstream -force example_6_4_1_exe.bit + catch {write_debug_probes -quiet -force example_6_4_1_exe} + catch {file copy -force example_6_4_1_exe.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe.vdi" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe.vdi" new file mode 100644 index 00000000..8d90d4fc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe.vdi" @@ -0,0 +1,854 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 27 19:08:13 2023 +# Process ID: 29568 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/impl_1 +# Command line: vivado.exe -log example_6_4_1_exe.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source example_6_4_1_exe.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/impl_1/example_6_4_1_exe.vdi +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source example_6_4_1_exe.tcl -notrace +Command: link_design -top example_6_4_1_exe -part xc7a75tfgg484-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7a75tfgg484-1 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 620.496 ; gain = 0.000 +INFO: [Project 1-479] Netlist was created with Vivado 2019.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------系统时钟------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:1] +WARNING: [Vivado 12-584] No ports matched 'sys_clk_50m'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_100m'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:3] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:3] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_3hz'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:4] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:4] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:7] +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------拨码?关sw0~sw7----------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:19] +WARNING: [Vivado 12-584] No ports matched 'sw_pin[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:20] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:20] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:21] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:21] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:22] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:22] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:23] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:23] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[4]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:24] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:24] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[5]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:25] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:25] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[6]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:26] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:26] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[7]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:27] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:27] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------------------9个按?--------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:31] +WARNING: [Vivado 12-584] No ports matched 'btn_0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:32] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:32] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:34] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:34] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:35] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:35] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:36] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:36] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:37] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:37] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:38] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:38] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:39] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:39] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:40] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:40] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_0_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:43] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:43] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_2_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:45] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:45] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_3_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:46] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:46] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_4_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:47] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:47] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_5_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:48] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:48] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_6_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:49] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_7_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:50] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:50] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_8_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:51] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:51] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------6个数码管-----------------------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:54] +WARNING: [Vivado 12-584] No ports matched 'digitron_out[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:55] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:55] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:56] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:56] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:57] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:57] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:58] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:58] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[4]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:59] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:59] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[5]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:60] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:60] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[6]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:61] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:61] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[7]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:62] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:62] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:64] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:64] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:65] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:65] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:66] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:66] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:67] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:67] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:69] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:69] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:70] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:70] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:71] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:71] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:72] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:72] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:74] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:74] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:75] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:75] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:76] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:76] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:77] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:77] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------串口---------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:81] +WARNING: [Vivado 12-584] No ports matched 'uart_rxd'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:82] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:82] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'uart_txd'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:83] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:83] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------蜂鸣?-----------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:87] +WARNING: [Vivado 12-584] No ports matched 'buzzer'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:88] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:88] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------XADC数模转换-------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:92] +WARNING: [Vivado 12-584] No ports matched 'ad15p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:93] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:93] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad15n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:94] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:94] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:95] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:95] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:96] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:96] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:97] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:97] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:98] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:98] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:99] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:99] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:100] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:100] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:101] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:101] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:102] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:102] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:103] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:103] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:104] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:104] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:105] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:105] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:106] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:106] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------DDR3L-------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:111] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:112] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:112] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:113] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:113] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:114] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:114] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:115] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:115] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:117] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:117] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:118] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:118] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:119] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:119] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:120] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:120] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:121] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:121] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:122] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:122] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:123] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:123] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:124] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:124] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:125] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:125] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq9'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:126] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:126] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq10'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:127] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:127] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq11'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:128] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:128] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq12'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:129] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:129] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq13'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:130] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:130] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq14'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:131] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:131] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq15'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:132] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:132] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:134] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:134] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:135] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:135] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:136] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:136] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:137] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:137] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:138] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:138] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:139] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:139] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:140] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:140] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:141] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:141] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:142] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:142] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a9'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:143] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:143] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a10'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:144] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:144] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a11'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:145] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:145] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a12'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:146] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:146] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:148] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:148] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:149] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:149] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:150] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:150] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +INFO: [Common 17-14] Message 'Common 17-55' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:150] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:152] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:153] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_odt'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:155] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:156] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:157] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cke'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:158] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cs'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:159] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ras'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:160] +INFO: [Common 17-14] Message 'Vivado 12-584' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:160] +Finished Parsing XDC File [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 729.629 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 108 Warnings, 109 Critical Warnings and 0 Errors encountered. +link_design completed successfully +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.411 . Memory (MB): peak = 753.965 ; gain = 20.316 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 15959f71b + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1264.074 ; gain = 510.109 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 15959f71b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1458.977 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 15959f71b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1458.977 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 15959f71b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1458.977 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. +INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. +INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). +Phase 4 BUFG optimization | Checksum: 15959f71b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1458.977 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 15959f71b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1458.977 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 15959f71b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1458.977 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1458.977 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 15959f71b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1458.977 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 15959f71b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1458.977 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 15959f71b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1458.977 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1458.977 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 15959f71b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1458.977 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +27 Infos, 108 Warnings, 109 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1458.977 ; gain = 725.328 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1458.977 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1458.977 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/impl_1/example_6_4_1_exe_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file example_6_4_1_exe_drc_opted.rpt -pb example_6_4_1_exe_drc_opted.pb -rpx example_6_4_1_exe_drc_opted.rpx +Command: report_drc -file example_6_4_1_exe_drc_opted.rpt -pb example_6_4_1_exe_drc_opted.pb -rpx example_6_4_1_exe_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/impl_1/example_6_4_1_exe_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1458.977 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 10808facc + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1458.977 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1458.977 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. + + btn_1_IBUF_inst (IBUF.O) is locked to IOB_X1Y146 + btn_1_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 +Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fad09731 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.451 . Memory (MB): peak = 1461.875 ; gain = 2.898 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 18514809d + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.492 . Memory (MB): peak = 1461.875 ; gain = 2.898 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 18514809d + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.495 . Memory (MB): peak = 1461.875 ; gain = 2.898 +Phase 1 Placer Initialization | Checksum: 18514809d + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.501 . Memory (MB): peak = 1461.875 ; gain = 2.898 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 18514809d + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.511 . Memory (MB): peak = 1461.875 ; gain = 2.898 + +Phase 2.2 Global Placement Core +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2.2 Global Placement Core | Checksum: 122409faf + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.756 . Memory (MB): peak = 1461.875 ; gain = 2.898 +Phase 2 Global Placement | Checksum: 122409faf + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.760 . Memory (MB): peak = 1461.875 ; gain = 2.898 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 122409faf + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.762 . Memory (MB): peak = 1461.875 ; gain = 2.898 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1984889f9 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.765 . Memory (MB): peak = 1461.875 ; gain = 2.898 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 122409faf + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.771 . Memory (MB): peak = 1461.875 ; gain = 2.898 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 122409faf + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.772 . Memory (MB): peak = 1461.875 ; gain = 2.898 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 2111db613 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.880 . Memory (MB): peak = 1461.875 ; gain = 2.898 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 2111db613 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.882 . Memory (MB): peak = 1461.875 ; gain = 2.898 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 2111db613 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.883 . Memory (MB): peak = 1461.875 ; gain = 2.898 +Phase 3 Detail Placement | Checksum: 2111db613 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.883 . Memory (MB): peak = 1461.875 ; gain = 2.898 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 2111db613 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.885 . Memory (MB): peak = 1461.875 ; gain = 2.898 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 2111db613 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.889 . Memory (MB): peak = 1461.875 ; gain = 2.898 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 2111db613 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.889 . Memory (MB): peak = 1461.875 ; gain = 2.898 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.875 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: 12fda318a + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.890 . Memory (MB): peak = 1461.875 ; gain = 2.898 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 12fda318a + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.890 . Memory (MB): peak = 1461.875 ; gain = 2.898 +Ending Placer Task | Checksum: 89962382 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.890 . Memory (MB): peak = 1461.875 ; gain = 2.898 +INFO: [Common 17-83] Releasing license: Implementation +45 Infos, 110 Warnings, 109 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.875 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1474.891 ; gain = 13.016 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/impl_1/example_6_4_1_exe_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file example_6_4_1_exe_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1474.891 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file example_6_4_1_exe_utilization_placed.rpt -pb example_6_4_1_exe_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file example_6_4_1_exe_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1474.891 ; gain = 0.000 +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +53 Infos, 110 Warnings, 109 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1478.711 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1496.605 ; gain = 17.895 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/impl_1/example_6_4_1_exe_physopt.dcp' has been generated. +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. +Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. + This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. + + btn_1_IBUF_inst (IBUF.O) is locked to IOB_X1Y146 + btn_1_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 87214625 ConstDB: 0 ShapeSum: 274dd5d RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 1ea26d20e + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1624.945 ; gain = 119.266 +Post Restoration Checksum: NetGraph: fdf59e42 NumContArr: ec3133cc Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 1ea26d20e + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1630.934 ; gain = 125.254 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 1ea26d20e + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1630.934 ; gain = 125.254 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 9c85345e + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1637.141 ; gain = 131.461 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 5 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 5 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 1867a2745 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1640.676 ; gain = 134.996 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 159e880a3 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1640.676 ; gain = 134.996 +Phase 4 Rip-up And Reroute | Checksum: 159e880a3 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1640.676 ; gain = 134.996 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 159e880a3 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1640.676 ; gain = 134.996 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 159e880a3 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1640.676 ; gain = 134.996 +Phase 6 Post Hold Fix | Checksum: 159e880a3 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1640.676 ; gain = 134.996 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.00256779 % + Global Horizontal Routing Utilization = 0.0024865 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 159e880a3 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1640.676 ; gain = 134.996 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 159e880a3 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1642.727 ; gain = 137.047 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 143634476 + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1642.727 ; gain = 137.047 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 1642.727 ; gain = 137.047 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +63 Infos, 111 Warnings, 109 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 1642.727 ; gain = 146.121 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1642.727 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1652.559 ; gain = 9.832 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/impl_1/example_6_4_1_exe_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file example_6_4_1_exe_drc_routed.rpt -pb example_6_4_1_exe_drc_routed.pb -rpx example_6_4_1_exe_drc_routed.rpx +Command: report_drc -file example_6_4_1_exe_drc_routed.rpt -pb example_6_4_1_exe_drc_routed.pb -rpx example_6_4_1_exe_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/impl_1/example_6_4_1_exe_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file example_6_4_1_exe_methodology_drc_routed.rpt -pb example_6_4_1_exe_methodology_drc_routed.pb -rpx example_6_4_1_exe_methodology_drc_routed.rpx +Command: report_methodology -file example_6_4_1_exe_methodology_drc_routed.rpt -pb example_6_4_1_exe_methodology_drc_routed.pb -rpx example_6_4_1_exe_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/impl_1/example_6_4_1_exe_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file example_6_4_1_exe_power_routed.rpt -pb example_6_4_1_exe_power_summary_routed.pb -rpx example_6_4_1_exe_power_routed.rpx +Command: report_power -file example_6_4_1_exe_power_routed.rpt -pb example_6_4_1_exe_power_summary_routed.pb -rpx example_6_4_1_exe_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +75 Infos, 112 Warnings, 109 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file example_6_4_1_exe_route_status.rpt -pb example_6_4_1_exe_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file example_6_4_1_exe_timing_summary_routed.rpt -pb example_6_4_1_exe_timing_summary_routed.pb -rpx example_6_4_1_exe_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file example_6_4_1_exe_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file example_6_4_1_exe_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file example_6_4_1_exe_bus_skew_routed.rpt -pb example_6_4_1_exe_bus_skew_routed.pb -rpx example_6_4_1_exe_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force example_6_4_1_exe.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./example_6_4_1_exe.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +94 Infos, 114 Warnings, 109 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2142.598 ; gain = 459.395 +INFO: [Common 17-206] Exiting Vivado at Mon Nov 27 19:08:59 2023... diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_bus_skew_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_bus_skew_routed.pb" new file mode 100644 index 00000000..3390588d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_bus_skew_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_bus_skew_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_bus_skew_routed.rpt" new file mode 100644 index 00000000..3f5ff09f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_bus_skew_routed.rpt" @@ -0,0 +1,15 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 19:08:50 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file example_6_4_1_exe_bus_skew_routed.rpt -pb example_6_4_1_exe_bus_skew_routed.pb -rpx example_6_4_1_exe_bus_skew_routed.rpx +| Design : example_6_4_1_exe +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Bus Skew Report + +No bus skew constraints + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_bus_skew_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_bus_skew_routed.rpx" new file mode 100644 index 00000000..b195df8e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_bus_skew_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_clock_utilization_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_clock_utilization_routed.rpt" new file mode 100644 index 00000000..db13750b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_clock_utilization_routed.rpt" @@ -0,0 +1,150 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 19:08:50 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_clock_utilization -file example_6_4_1_exe_clock_utilization_routed.rpt +| Design : example_6_4_1_exe +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +----------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X0Y1 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 96 | 0 | 0 | 0 | +| BUFIO | 0 | 24 | 0 | 0 | 0 | +| BUFMR | 0 | 12 | 0 | 0 | 0 | +| BUFR | 0 | 24 | 0 | 0 | 0 | +| MMCM | 0 | 6 | 0 | 0 | 0 | +| PLL | 0 | 6 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+------------------------+-----------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+------------------------+-----------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 4 | 0 | | | btn_1_IBUF_BUFG_inst/O | btn_1_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+------------------------+-----------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-------------------+------------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-------------------+------------+ +| src0 | g0 | IBUF/O | IOB_X1Y146 | IOB_X1Y146 | X1Y2 | 1 | 0 | | | btn_1_IBUF_inst/O | btn_1_IBUF | ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-------------------+------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1500 | 0 | 550 | 0 | 40 | 0 | 20 | 0 | 40 | +| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1350 | 0 | 500 | 0 | 30 | 0 | 15 | 0 | 40 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 1 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------+ +| g0 | BUFG/O | n/a | | | | 4 | 0 | 0 | 0 | btn_1_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------+ +* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 4 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + +7. Clock Region Cell Placement per Global Clock: Region X0Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-----------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-----------------+ +| g0 | n/a | BUFG/O | None | 4 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | btn_1_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-----------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells btn_1_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X1Y146 [get_ports btn_1] + +# Clock net "btn_1_IBUF_BUFG" driven by instance "btn_1_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_btn_1_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_btn_1_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="btn_1_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_btn_1_IBUF_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1} +#endgroup diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_control_sets_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_control_sets_placed.rpt" new file mode 100644 index 00000000..77ce6f3b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_control_sets_placed.rpt" @@ -0,0 +1,79 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 19:08:30 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file example_6_4_1_exe_control_sets_placed.rpt +| Design : example_6_4_1_exe +| Device : xc7a75t +---------------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Total control sets | 1 | +| Minimum number of control sets | 1 | +| Addition due to synthesis replication | 0 | +| Addition due to physical synthesis replication | 0 | +| Unused register locations in slices containing registers | 4 | ++----------------------------------------------------------+-------+ +* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers +** Run report_qor_suggestions for automated merging and remapping suggestions + + +2. Histogram +------------ + ++--------------------+-------+ +| Fanout | Count | ++--------------------+-------+ +| Total control sets | 1 | +| >= 0 to < 4 | 0 | +| >= 4 to < 6 | 1 | +| >= 6 to < 8 | 0 | +| >= 8 to < 10 | 0 | +| >= 10 to < 12 | 0 | +| >= 12 to < 14 | 0 | +| >= 14 to < 16 | 0 | +| >= 16 | 0 | ++--------------------+-------+ +* Control sets can be remapped at either synth_design or opt_design + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 4 | 1 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++------------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++------------------+---------------+------------------+------------------+----------------+ +| ~btn_1_IBUF_BUFG | | | 1 | 4 | ++------------------+---------------+------------------+------------------+----------------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_opted.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_opted.pb" new file mode 100644 index 00000000..5aa0de05 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_opted.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_opted.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_opted.rpt" new file mode 100644 index 00000000..2165b0ea --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_opted.rpt" @@ -0,0 +1,61 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 19:08:28 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_drc -file example_6_4_1_exe_drc_opted.rpt -pb example_6_4_1_exe_drc_opted.pb -rpx example_6_4_1_exe_drc_opted.rpx +| Design : example_6_4_1_exe +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 2 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| PLCK-12 | Warning | Clock Placer Checks | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +PLCK-12#1 Warning +Clock Placer Checks +Poor placement for routing between an IO pin and BUFG. +Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. + This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. + + btn_1_IBUF_inst (IBUF.O) is locked to C2 + btn_1_IBUF_BUFG_inst (BUFG.I) cannot be placed + +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_opted.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_opted.rpx" new file mode 100644 index 00000000..b748bc79 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_opted.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_routed.pb" new file mode 100644 index 00000000..5aa0de05 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_routed.rpt" new file mode 100644 index 00000000..e2f3d506 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_routed.rpt" @@ -0,0 +1,61 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 19:08:49 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_drc -file example_6_4_1_exe_drc_routed.rpt -pb example_6_4_1_exe_drc_routed.pb -rpx example_6_4_1_exe_drc_routed.rpx +| Design : example_6_4_1_exe +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Fully Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 2 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| PLCK-12 | Warning | Clock Placer Checks | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +PLCK-12#1 Warning +Clock Placer Checks +Poor placement for routing between an IO pin and BUFG. +Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. + This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. + + btn_1_IBUF_inst (IBUF.O) is locked to C2 + btn_1_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 + +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_routed.rpx" new file mode 100644 index 00000000..da51b13f Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_drc_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_io_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_io_placed.rpt" new file mode 100644 index 00000000..cad955b5 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_io_placed.rpt" @@ -0,0 +1,526 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 19:08:30 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_io -file example_6_4_1_exe_io_placed.rpt +| Design : example_6_4_1_exe +| Device : xc7a75t +| Speed File : -1 +| Package : fgg484 +| Package Version : FINAL 2012-11-02 +| Package Pin Delay Version : VERS. 2.0 2012-11-02 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 9 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A4 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A6 | | | MGTPTXN2_216 | Gigabit | | | | | | | | | | | | | | | | +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A8 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A10 | | | MGTPRXN2_216 | Gigabit | | | | | | | | | | | | | | | | +| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A19 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A20 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A21 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA3 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA4 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| AA8 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA9 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA10 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA11 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA13 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA14 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA15 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA16 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| AA18 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| AA19 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| AA20 | led_pin[1] | High Range | IO_L8P_T1_D11_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| AA21 | led_pin[0] | High Range | IO_L8N_T1_D12_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB2 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB3 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| AB5 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB8 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB10 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB11 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB12 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB13 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| AB15 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB16 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB17 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB20 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| AB21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| AB22 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B4 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| B5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B6 | | | MGTPTXP2_216 | Gigabit | | | | | | | | | | | | | | | | +| B7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B8 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| B9 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B10 | | | MGTPRXP2_216 | Gigabit | | | | | | | | | | | | | | | | +| B11 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B15 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B16 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B20 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| B21 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| B22 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| C1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C2 | btn_1 | High Range | IO_L2P_T0_AD12P_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | | +| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C4 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C5 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C7 | | | MGTPTXN3_216 | Gigabit | | | | | | | | | | | | | | | | +| C8 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C9 | | | MGTPRXN3_216 | Gigabit | | | | | | | | | | | | | | | | +| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C11 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| C12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| C14 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C18 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C19 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C20 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| C21 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C22 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| D2 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D5 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| D6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| D7 | | | MGTPTXP3_216 | Gigabit | | | | | | | | | | | | | | | | +| D8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D9 | | | MGTPRXP3_216 | Gigabit | | | | | | | | | | | | | | | | +| D10 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| D11 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D14 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D16 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| D17 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| D19 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D20 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D21 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D22 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E6 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | | +| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E8 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | | +| E11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E12 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E14 | | High Range | IO_L4N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E15 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| E16 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L2N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| E19 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E21 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| E22 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F6 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | | +| F7 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| F8 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | | +| F9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| F10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| F13 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F15 | | High Range | IO_0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L2P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| F19 | | High Range | IO_L18P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| F20 | | High Range | IO_L18N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| F21 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | | +| F22 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| G1 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G15 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| G16 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G19 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G20 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G21 | | High Range | IO_L24P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| G22 | | High Range | IO_L24N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| H1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H2 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| H4 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| H14 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| H17 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H19 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H20 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H22 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| J1 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J2 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J4 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J14 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J17 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J19 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J20 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J21 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J22 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| K4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K6 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K16 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| K19 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| K20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K21 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| K22 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| L6 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| L12 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| L13 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| L18 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| L19 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| L20 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| L21 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M1 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| M4 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| M5 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| M6 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| M10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| M14 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| M15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| M16 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| M17 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| M21 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| M22 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| N1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| N2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N3 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| N4 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| N12 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| N13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| N14 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| N19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| N20 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| N21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| N22 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| P1 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P2 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| P5 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| P6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P14 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| P19 | led_pin[6] | High Range | IO_L5P_T0_D06_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P20 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| P21 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| P22 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| R2 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| R6 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R13 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| R14 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| R15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| R16 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| R19 | led_pin[5] | High Range | IO_L5N_T0_D07_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R21 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| R22 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| T3 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| T13 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| T19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T20 | led_pin[4] | High Range | IO_L6N_T0_D08_VREF_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T21 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| T22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U5 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U6 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| U9 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| U10 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| U11 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| U12 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| U13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U15 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| U16 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| U19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U20 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| U21 | led_pin[7] | High Range | IO_L4N_T0_D05_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U22 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V2 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| V4 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| V7 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V12 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| V13 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V14 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| V17 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| V19 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| V20 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V22 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| W1 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W2 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| W4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W5 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W6 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W9 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| W10 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| W11 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W12 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W13 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| W14 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| W15 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| W16 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| W17 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| W20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| W21 | led_pin[3] | High Range | IO_L7P_T1_D09_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| W22 | led_pin[2] | High Range | IO_L7N_T1_D10_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| Y1 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y3 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y4 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y7 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y8 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y9 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y10 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| Y11 | | High Range | IO_L11P_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y12 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y13 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y14 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y16 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y17 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| Y19 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| Y20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| Y21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| Y22 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_methodology_drc_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_methodology_drc_routed.pb" new file mode 100644 index 00000000..e5a03fb8 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_methodology_drc_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_methodology_drc_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_methodology_drc_routed.rpt" new file mode 100644 index 00000000..590e129d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_methodology_drc_routed.rpt" @@ -0,0 +1,55 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 19:08:50 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_methodology -file example_6_4_1_exe_methodology_drc_routed.rpt -pb example_6_4_1_exe_methodology_drc_routed.pb -rpx example_6_4_1_exe_methodology_drc_routed.rpx +| Design : example_6_4_1_exe +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Fully Routed +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 4 ++-----------+------------------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+------------------+-----------------------------+------------+ +| TIMING-17 | Critical Warning | Non-clocked sequential cell | 4 | ++-----------+------------------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Critical Warning +Non-clocked sequential cell +The clock pin U/ny1_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Critical Warning +Non-clocked sequential cell +The clock pin U/ny2_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Critical Warning +Non-clocked sequential cell +The clock pin U/ny3_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#4 Critical Warning +Non-clocked sequential cell +The clock pin U/z_reg/C is not reached by a timing clock +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_methodology_drc_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_methodology_drc_routed.rpx" new file mode 100644 index 00000000..1a693563 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_methodology_drc_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_opt.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_opt.dcp" new file mode 100644 index 00000000..fb126217 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_opt.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_physopt.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_physopt.dcp" new file mode 100644 index 00000000..2c4e5934 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_physopt.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_placed.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_placed.dcp" new file mode 100644 index 00000000..87590611 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_placed.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_power_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_power_routed.rpt" new file mode 100644 index 00000000..e28cb76e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_power_routed.rpt" @@ -0,0 +1,144 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 19:08:50 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_power -file example_6_4_1_exe_power_routed.rpt -pb example_6_4_1_exe_power_summary_routed.pb -rpx example_6_4_1_exe_power_routed.rpx +| Design : example_6_4_1_exe +| Device : xc7a75tfgg484-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 11.916 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 11.773 | +| Device Static (W) | 0.143 | +| Effective TJA (C/W) | 2.7 | +| Max Ambient (C) | 53.1 | +| Junction Temperature (C) | 56.9 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.045 | 13 | --- | --- | +| LUT as Logic | 0.034 | 2 | 47200 | <0.01 | +| BUFG | 0.006 | 1 | 32 | 3.13 | +| Register | 0.004 | 4 | 94400 | <0.01 | +| Others | 0.000 | 4 | --- | --- | +| Signals | 0.066 | 6 | --- | --- | +| I/O | 11.663 | 9 | 285 | 3.16 | +| Static Power | 0.143 | | | | +| Total | 11.916 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.167 | 0.114 | 0.052 | +| Vccaux | 1.800 | 0.450 | 0.427 | 0.022 | +| Vcco33 | 3.300 | 3.304 | 3.300 | 0.004 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | High | User specified more than 25% of internal nodes | | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 2.7 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++-------------------+-----------+ +| Name | Power (W) | ++-------------------+-----------+ +| example_6_4_1_exe | 11.773 | +| U | 0.092 | ++-------------------+-----------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_power_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_power_routed.rpx" new file mode 100644 index 00000000..cb97d3b3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_power_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_power_summary_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_power_summary_routed.pb" new file mode 100644 index 00000000..87082e47 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_power_summary_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_route_status.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_route_status.pb" new file mode 100644 index 00000000..e975e2c3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_route_status.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_route_status.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_route_status.rpt" new file mode 100644 index 00000000..c51fd5e2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_route_status.rpt" @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 21 : + # of nets not needing routing.......... : 13 : + # of internally routed nets........ : 13 : + # of routable nets..................... : 8 : + # of fully routed nets............. : 8 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_routed.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_routed.dcp" new file mode 100644 index 00000000..1faf5818 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_routed.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_timing_summary_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_timing_summary_routed.pb" new file mode 100644 index 00000000..4526e931 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_timing_summary_routed.pb" @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_timing_summary_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_timing_summary_routed.rpt" new file mode 100644 index 00000000..5c6d494f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_timing_summary_routed.rpt" @@ -0,0 +1,175 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 19:08:50 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file example_6_4_1_exe_timing_summary_routed.rpt -pb example_6_4_1_exe_timing_summary_routed.pb -rpx example_6_4_1_exe_timing_summary_routed.rpx -warn_on_violation +| Design : example_6_4_1_exe +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 4 register/latch pins with no clock driven by root clock pin: btn_1 (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 4 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 4 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_timing_summary_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_timing_summary_routed.rpx" new file mode 100644 index 00000000..c1e0c8fc Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_timing_summary_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_utilization_placed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_utilization_placed.pb" new file mode 100644 index 00000000..c5e54f06 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_utilization_placed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_utilization_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_utilization_placed.rpt" new file mode 100644 index 00000000..765eba4f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/example_6_4_1_exe_utilization_placed.rpt" @@ -0,0 +1,204 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 19:08:30 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_utilization -file example_6_4_1_exe_utilization_placed.rpt -pb example_6_4_1_exe_utilization_placed.pb +| Design : example_6_4_1_exe +| Device : 7a75tfgg484-1 +| Design State : Fully Placed +------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 2 | 0 | 47200 | <0.01 | +| LUT as Logic | 2 | 0 | 47200 | <0.01 | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| Slice Registers | 4 | 0 | 94400 | <0.01 | +| Register as Flip Flop | 4 | 0 | 94400 | <0.01 | +| Register as Latch | 0 | 0 | 94400 | 0.00 | +| F7 Muxes | 0 | 0 | 31700 | 0.00 | +| F8 Muxes | 0 | 0 | 15850 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 4 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------------------------------------+------+-------+-----------+-------+ +| Slice | 1 | 0 | 15850 | <0.01 | +| SLICEL | 1 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 2 | 0 | 47200 | <0.01 | +| using O5 output only | 0 | | | | +| using O6 output only | 0 | | | | +| using O5 and O6 | 2 | | | | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 4 | 0 | 94400 | <0.01 | +| Register driven from within the Slice | 4 | | | | +| Register driven from outside the Slice | 0 | | | | +| Unique Control Sets | 1 | | 15850 | <0.01 | ++------------------------------------------+------+-------+-----------+-------+ +* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 105 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 105 | 0.00 | +| RAMB18 | 0 | 0 | 210 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 180 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 9 | 9 | 285 | 3.16 | +| IOB Master Pads | 4 | | | | +| IOB Slave Pads | 5 | | | | +| Bonded IPADs | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 6 | 0.00 | +| PHASER_REF | 0 | 0 | 6 | 0.00 | +| OUT_FIFO | 0 | 0 | 24 | 0.00 | +| IN_FIFO | 0 | 0 | 24 | 0.00 | +| IDELAYCTRL | 0 | 0 | 6 | 0.00 | +| IBUFDS | 0 | 0 | 274 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 24 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 24 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 300 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 0 | 0 | 6 | 0.00 | +| PLLE2_ADV | 0 | 0 | 6 | 0.00 | +| BUFMRCE | 0 | 0 | 12 | 0.00 | +| BUFHCE | 0 | 0 | 96 | 0.00 | +| BUFR | 0 | 0 | 24 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUFT | 4 | IO | +| OBUF | 4 | IO | +| FDRE | 4 | Flop & Latch | +| LUT3 | 2 | LUT | +| LUT2 | 1 | LUT | +| LUT1 | 1 | LUT | +| IBUF | 1 | IO | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/gen_run.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/gen_run.xml" new file mode 100644 index 00000000..1e8db1b2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/gen_run.xml" @@ -0,0 +1,125 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/htr.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/htr.txt" new file mode 100644 index 00000000..8dee72e0 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/htr.txt" @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log example_6_4_1_exe.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_6_4_1_exe.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/init_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/init_design.pb" new file mode 100644 index 00000000..f511ff42 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/init_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/opt_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/opt_design.pb" new file mode 100644 index 00000000..fce1350e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/opt_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/phys_opt_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/phys_opt_design.pb" new file mode 100644 index 00000000..d1ead981 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/phys_opt_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/place_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/place_design.pb" new file mode 100644 index 00000000..88bdb773 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/place_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/project.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/project.wdf" new file mode 100644 index 00000000..f19198bb --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/project.wdf" @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6636666666323662333063343464343962346333393461306165653132303464:506172656e742050412070726f6a656374204944:00 +eof:1065212842 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/route_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/route_design.pb" new file mode 100644 index 00000000..5a57a5d3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/route_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/rundef.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/rundef.js" new file mode 100644 index 00000000..b13cb05d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/rundef.js" @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;"; +} else { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log example_6_4_1_exe.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_6_4_1_exe.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/runme.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/runme.bat" new file mode 100644 index 00000000..1760626b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/runme.bat" @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/runme.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/runme.sh" new file mode 100644 index 00000000..b32e3ccd --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/runme.sh" @@ -0,0 +1,47 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin +else + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log example_6_4_1_exe.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_6_4_1_exe.tcl -notrace + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/usage_statistics_webtalk.html" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/usage_statistics_webtalk.html" new file mode 100644 index 00000000..a79ee0b4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/usage_statistics_webtalk.html" @@ -0,0 +1,632 @@ +Device Usage Statistics Report +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click
here.


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2708876
date_generatedMon Nov 27 19:08:58 2023os_platformWIN64
product_versionVivado v2019.2 (64-bit)project_idf6fff26b30c44d49b4c394a0aee1204d
project_iteration1random_id5098e843c55f5f60a14bf92371dc2ce7
registration_id5098e843c55f5f60a14bf92371dc2ce7route_designTRUE
target_devicexc7a75ttarget_familyartix7
target_packagefgg484target_speed-1
tool_flowVivado

+ + + + + + + + +
user_environment
cpu_nameAMD Ryzen 9 7945HX with Radeon Graphics cpu_speed2495 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram16.000 GBtotal_processors1

+ + +
vivado_usage
+ + + + + + + + + + + + +
gui_handlers
addsrcwizard_specify_hdl_netlist_block_design=1basedialog_ok=1basedialog_yes=1constraintschooserpanel_add_files=2
flownavigatortreepanel_flow_navigator_tree=1fpgachooser_fpga_table=2gettingstartedview_create_new_project=1numjobschooser_number_of_jobs=1
pacommandnames_add_sources=2projectnamechooser_project_name=1srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1
+ + + + + +
java_command_handlers
addsources=2newproject=1runbitgen=1
+ + + +
other_data
guimode=1
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
project_data
constraintsetcount=1core_container=falsecurrentimplrun=impl_1currentsynthesisrun=synth_1
default_library=xil_defaultlibdesignmode=RTLexport_simulation_activehdl=0export_simulation_ies=0
export_simulation_modelsim=0export_simulation_questa=0export_simulation_riviera=0export_simulation_vcs=0
export_simulation_xsim=0implstrategy=Vivado Implementation Defaultslaunch_simulation_activehdl=0launch_simulation_ies=0
launch_simulation_modelsim=0launch_simulation_questa=0launch_simulation_riviera=0launch_simulation_vcs=0
launch_simulation_xsim=0simulator_language=Mixedsrcsetcount=1synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilogtarget_simulator=XSimtotalimplruns=1totalsynthesisruns=1
+
+ + + + +
unisim_transformation
+ + + + + + + + + + + + +
post_unisim_transformation
bufg=1fdre=4gnd=2ibuf=1
lut1=1lut2=1lut3=2obuf=4
obuft=4vcc=2
+
+ + + + + + + + + + + + +
pre_unisim_transformation
bufg=1fdre=4gnd=2ibuf=1
lut1=1lut2=1lut3=2obuf=4
obuft=4vcc=2
+

+ + + +
phys_opt_design_post_place
+ + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-aggressive_hold_fix=default::[not_specified]-bram_register_opt=default::[not_specified]-clock_opt=default::[not_specified]-critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified]-directive=default::[not_specified]-dsp_register_opt=default::[not_specified]-effort_level=default::[not_specified]
-fanout_opt=default::[not_specified]-hold_fix=default::[not_specified]-insert_negative_edge_ffs=default::[not_specified]-multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified]-restruct_opt=default::[not_specified]-retime=default::[not_specified]-rewire=default::[not_specified]
-shift_register_opt=default::[not_specified]-uram_register_opt=default::[not_specified]-verbose=default::[not_specified]-vhfn=default::[not_specified]
+

+ + + + +
report_drc
+ + + + + + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-internal=default::[not_specified]-internal_only=default::[not_specified]-messages=default::[not_specified]
-name=default::[not_specified]-no_waivers=default::[not_specified]-return_string=default::[not_specified]-ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified]-waived=default::[not_specified]
+
+ + + + +
results
cfgbvs-1=1plck-12=1
+

+ + + + +
report_methodology
+ + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified]-waived=default::[not_specified]
+
+ + + +
results
timing-17=4
+

+ + + + +
report_power
+ + + + + + + + + + + + + + + + +
command_line_options
-advisory=default::[not_specified]-append=default::[not_specified]-file=[specified]-format=default::text
-hier=default::power-hierarchical_depth=default::4-l=default::[not_specified]-name=default::[not_specified]
-no_propagation=default::[not_specified]-return_string=default::[not_specified]-rpx=[specified]-verbose=default::[not_specified]
-vid=default::[not_specified]-xpe=default::[not_specified]
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
usage
airflow=250 (LFM)ambient_temp=25.0 (C)bi-dir_toggle=12.500000bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers)board_selection=medium (10"x10")confidence_level_clock_activity=Lowconfidence_level_design_state=High
confidence_level_device_models=Highconfidence_level_internal_activity=Highconfidence_level_io_activity=Lowconfidence_level_overall=Low
customer=TBDcustomer_class=TBDdevstatic=0.142988die=xc7a75tfgg484-1
dsp_output_toggle=12.500000dynamic=11.773468effective_thetaja=2.7enable_probability=0.990000
family=artix7ff_toggle=12.500000flow_state=routedheatsink=medium (Medium Profile)
i/o=11.663025input_toggle=12.500000junction_temp=56.9 (C)logic=0.044543
mgtavcc_dynamic_current=0.000000mgtavcc_static_current=0.000000mgtavcc_total_current=0.000000mgtavcc_voltage=1.000000
mgtavtt_dynamic_current=0.000000mgtavtt_static_current=0.000000mgtavtt_total_current=0.000000mgtavtt_voltage=1.200000
netlist_net_matched=NAoff-chip_power=0.000000on-chip_power=11.916456output_enable=1.000000
output_load=5.000000output_toggle=12.500000package=fgg484pct_clock_constrained=1.000000
pct_inputs_defined=0platform=nt64process=typicalram_enable=50.000000
ram_write=50.000000read_saif=Falseset/reset_probability=0.000000signal_rate=False
signals=0.065900simulation_file=Nonespeedgrade=-1static_prob=False
temp_grade=commercialthetajb=6.8 (C/W)thetasa=4.6 (C/W)toggle_rate=False
user_board_temp=25.0 (C)user_effective_thetaja=2.7user_junc_temp=56.9 (C)user_thetajb=6.8 (C/W)
user_thetasa=4.6 (C/W)vccadc_dynamic_current=0.000000vccadc_static_current=0.020000vccadc_total_current=0.020000
vccadc_voltage=1.800000vccaux_dynamic_current=0.427236vccaux_io_dynamic_current=0.000000vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000vccaux_io_voltage=1.800000vccaux_static_current=0.022448vccaux_total_current=0.449685
vccaux_voltage=1.800000vccbram_dynamic_current=0.000000vccbram_static_current=0.001070vccbram_total_current=0.001070
vccbram_voltage=1.000000vccint_dynamic_current=0.114443vccint_static_current=0.052311vccint_total_current=0.166754
vccint_voltage=1.000000vcco12_dynamic_current=0.000000vcco12_static_current=0.000000vcco12_total_current=0.000000
vcco12_voltage=1.200000vcco135_dynamic_current=0.000000vcco135_static_current=0.000000vcco135_total_current=0.000000
vcco135_voltage=1.350000vcco15_dynamic_current=0.000000vcco15_static_current=0.000000vcco15_total_current=0.000000
vcco15_voltage=1.500000vcco18_dynamic_current=0.000000vcco18_static_current=0.000000vcco18_total_current=0.000000
vcco18_voltage=1.800000vcco25_dynamic_current=0.000000vcco25_static_current=0.000000vcco25_total_current=0.000000
vcco25_voltage=2.500000vcco33_dynamic_current=3.300000vcco33_static_current=0.004000vcco33_total_current=3.304000
vcco33_voltage=3.300000version=2019.2
+

+ + + + + + + + + +
report_utilization
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
clocking
bufgctrl_available=32bufgctrl_fixed=0bufgctrl_used=1bufgctrl_util_percentage=3.13
bufhce_available=96bufhce_fixed=0bufhce_used=0bufhce_util_percentage=0.00
bufio_available=24bufio_fixed=0bufio_used=0bufio_util_percentage=0.00
bufmrce_available=12bufmrce_fixed=0bufmrce_used=0bufmrce_util_percentage=0.00
bufr_available=24bufr_fixed=0bufr_used=0bufr_util_percentage=0.00
mmcme2_adv_available=6mmcme2_adv_fixed=0mmcme2_adv_used=0mmcme2_adv_util_percentage=0.00
plle2_adv_available=6plle2_adv_fixed=0plle2_adv_used=0plle2_adv_util_percentage=0.00
+
+ + + + + + +
dsp
dsps_available=180dsps_fixed=0dsps_used=0dsps_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
io_standard
blvds_25=0diff_hstl_i=0diff_hstl_i_18=0diff_hstl_ii=0
diff_hstl_ii_18=0diff_hsul_12=0diff_mobile_ddr=0diff_sstl135=0
diff_sstl135_r=0diff_sstl15=0diff_sstl15_r=0diff_sstl18_i=0
diff_sstl18_ii=0hstl_i=0hstl_i_18=0hstl_ii=0
hstl_ii_18=0hsul_12=0lvcmos12=0lvcmos15=0
lvcmos18=0lvcmos25=0lvcmos33=1lvds_25=0
lvttl=0mini_lvds_25=0mobile_ddr=0pci33_3=0
ppds_25=0rsds_25=0sstl135=0sstl135_r=0
sstl15=0sstl15_r=0sstl18_i=0sstl18_ii=0
tmds_33=0
+
+ + + + + + + + + + + + + + +
memory
block_ram_tile_available=105block_ram_tile_fixed=0block_ram_tile_used=0block_ram_tile_util_percentage=0.00
ramb18_available=210ramb18_fixed=0ramb18_used=0ramb18_util_percentage=0.00
ramb36_fifo_available=105ramb36_fifo_fixed=0ramb36_fifo_used=0ramb36_fifo_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + +
primitives
bufg_functional_category=Clockbufg_used=1fdre_functional_category=Flop & Latchfdre_used=4
ibuf_functional_category=IOibuf_used=1lut1_functional_category=LUTlut1_used=1
lut2_functional_category=LUTlut2_used=1lut3_functional_category=LUTlut3_used=2
obuf_functional_category=IOobuf_used=4obuft_functional_category=IOobuft_used=4
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
slice_logic
f7_muxes_available=31700f7_muxes_fixed=0f7_muxes_used=0f7_muxes_util_percentage=0.00
f8_muxes_available=15850f8_muxes_fixed=0f8_muxes_used=0f8_muxes_util_percentage=0.00
lut_as_logic_available=47200lut_as_logic_fixed=0lut_as_logic_used=2lut_as_logic_util_percentage=<0.01
lut_as_memory_available=19000lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=94400register_as_flip_flop_fixed=0register_as_flip_flop_used=4register_as_flip_flop_util_percentage=<0.01
register_as_latch_available=94400register_as_latch_fixed=0register_as_latch_used=0register_as_latch_util_percentage=0.00
slice_luts_available=47200slice_luts_fixed=0slice_luts_used=2slice_luts_util_percentage=<0.01
slice_registers_available=94400slice_registers_fixed=0slice_registers_used=4slice_registers_util_percentage=<0.01
lut_as_distributed_ram_fixed=0lut_as_distributed_ram_used=0lut_as_logic_available=47200lut_as_logic_fixed=0
lut_as_logic_used=2lut_as_logic_util_percentage=<0.01lut_as_memory_available=19000lut_as_memory_fixed=0
lut_as_memory_used=0lut_as_memory_util_percentage=0.00lut_as_shift_register_fixed=0lut_as_shift_register_used=0
register_driven_from_outside_the_slice_fixed=0register_driven_from_outside_the_slice_used=0register_driven_from_within_the_slice_fixed=0register_driven_from_within_the_slice_used=4
slice_available=15850slice_fixed=0slice_registers_available=94400slice_registers_fixed=0
slice_registers_used=4slice_registers_util_percentage=<0.01slice_used=1slice_util_percentage=<0.01
slicel_fixed=0slicel_used=1slicem_fixed=0slicem_used=0
unique_control_sets_available=15850unique_control_sets_fixed=15850unique_control_sets_used=1unique_control_sets_util_percentage=<0.01
using_o5_and_o6_fixed=<0.01using_o5_and_o6_used=2using_o5_output_only_fixed=2using_o5_output_only_used=0
using_o6_output_only_fixed=0using_o6_output_only_used=0
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
specific_feature
bscane2_available=4bscane2_fixed=0bscane2_used=0bscane2_util_percentage=0.00
capturee2_available=1capturee2_fixed=0capturee2_used=0capturee2_util_percentage=0.00
dna_port_available=1dna_port_fixed=0dna_port_used=0dna_port_util_percentage=0.00
efuse_usr_available=1efuse_usr_fixed=0efuse_usr_used=0efuse_usr_util_percentage=0.00
frame_ecce2_available=1frame_ecce2_fixed=0frame_ecce2_used=0frame_ecce2_util_percentage=0.00
icape2_available=2icape2_fixed=0icape2_used=0icape2_util_percentage=0.00
pcie_2_1_available=1pcie_2_1_fixed=0pcie_2_1_used=0pcie_2_1_util_percentage=0.00
startupe2_available=1startupe2_fixed=0startupe2_used=0startupe2_util_percentage=0.00
xadc_available=1xadc_fixed=0xadc_used=0xadc_util_percentage=0.00
+

+ + + + +
synthesis
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-assert=default::[not_specified]-bufg=default::12-cascade_dsp=default::auto-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto-directive=default::default-fanout_limit=default::10000-flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto-gated_clock_conversion=default::off-generic=default::[not_specified]-include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified]-max_bram=default::-1-max_bram_cascade_height=default::-1-max_dsp=default::-1
-max_uram=default::-1-max_uram_cascade_height=default::-1-mode=default::default-name=default::[not_specified]
-no_lc=default::[not_specified]-no_srlextract=default::[not_specified]-no_timing_driven=default::[not_specified]-part=xc7a75tfgg484-1
-resource_sharing=default::auto-retiming=default::[not_specified]-rtl=default::[not_specified]-rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified]-seu_protect=default::none-sfcu=default::[not_specified]-shreg_min_size=default::3
-top=example_6_4_1_exe-verilog_define=default::[not_specified]
+
+ + + + + + +
usage
elapsed=00:00:18shls_ip=0memory_gain=691.781MBmemory_peak=1023.121MB
+

+ + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/usage_statistics_webtalk.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/usage_statistics_webtalk.xml" new file mode 100644 index 00000000..1e8798ec --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/usage_statistics_webtalk.xml" @@ -0,0 +1,565 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+ + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + +
+
+ + +
+
+
+
+ + + + + + + + + + +
+
+ +
+
+
+
+ + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + +
+
+
+
+ + + + + + + + + + +
+
+ + + + + + + + + + +
+
+
+
+ + + + + + + + + + + +
+
+ + + +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/vivado.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/vivado.jou" new file mode 100644 index 00000000..fe3fdb40 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/vivado.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 27 19:08:13 2023 +# Process ID: 29568 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/impl_1 +# Command line: vivado.exe -log example_6_4_1_exe.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source example_6_4_1_exe.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/impl_1/example_6_4_1_exe.vdi +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source example_6_4_1_exe.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/vivado.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/vivado.pb" new file mode 100644 index 00000000..9ffda911 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/vivado.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/write_bitstream.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/write_bitstream.pb" new file mode 100644 index 00000000..c7ee61b8 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/impl_1/write_bitstream.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/.Vivado_Synthesis.queue.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/.Vivado_Synthesis.queue.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/.Xil/example_6_4_1_exe_propImpl.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/.Xil/example_6_4_1_exe_propImpl.xdc" new file mode 100644 index 00000000..f3254485 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/.Xil/example_6_4_1_exe_propImpl.xdc" @@ -0,0 +1,261 @@ +set_property SRC_FILE_INFO {cfile:D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc rfile:../../../ACE1.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design] +//----------------------------------------------系统时钟------------------------------------ +set_property src_info {type:XDC file:1 line:2 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports sys_clk_50m] +set_property src_info {type:XDC file:1 line:3 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports sys_clk_100m] +set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports sys_clk_3hz] +set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] +//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------ +set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] +set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design] +//---------------------------------------------拨码?关sw0~sw7---------------------------------- +set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] +set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design] +//-----------------------------------------------9个按?-------------------------------------- +set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports btn_4] +set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports btn_5] +set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports btn_6] +set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports btn_7] +set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports btn_8] +set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_0_IBUF] +set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] +set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_2_IBUF] +set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_3_IBUF] +set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_4_IBUF] +set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_5_IBUF] +set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_6_IBUF] +set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_7_IBUF] +set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_8_IBUF] +set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design] +//-----------------------------------6个数码管----------------------------------------------------------- +set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[0]}] +set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[1]}] +set_property src_info {type:XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[2]}] +set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {digitron_out[3]}] +set_property src_info {type:XDC file:1 line:59 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS33} [get_ports {digitron_out[4]}] +set_property src_info {type:XDC file:1 line:60 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[5]}] +set_property src_info {type:XDC file:1 line:61 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[6]}] +set_property src_info {type:XDC file:1 line:62 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[7]}] +set_property src_info {type:XDC file:1 line:64 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[0]}] +set_property src_info {type:XDC file:1 line:65 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[1]}] +set_property src_info {type:XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[2]}] +set_property src_info {type:XDC file:1 line:67 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[3]}] +set_property src_info {type:XDC file:1 line:69 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {digitron_a[0]}] +set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[1]}] +set_property src_info {type:XDC file:1 line:71 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {digitron_a[2]}] +set_property src_info {type:XDC file:1 line:72 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[3]}] +set_property src_info {type:XDC file:1 line:74 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33} [get_ports {digitron_b[0]}] +set_property src_info {type:XDC file:1 line:75 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[1]}] +set_property src_info {type:XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[2]}] +set_property src_info {type:XDC file:1 line:77 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports {digitron_b[3]}] +set_property src_info {type:XDC file:1 line:81 export:INPUT save:INPUT read:READ} [current_design] +//----------------------------------------------串口--------------------------------------------- +set_property src_info {type:XDC file:1 line:82 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports uart_rxd] +set_property src_info {type:XDC file:1 line:83 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports uart_txd] +set_property src_info {type:XDC file:1 line:87 export:INPUT save:INPUT read:READ} [current_design] +//----------------------------------------------蜂鸣?----------------------------------------- +set_property src_info {type:XDC file:1 line:88 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports buzzer] +set_property src_info {type:XDC file:1 line:92 export:INPUT save:INPUT read:READ} [current_design] +//--------------------------------------------------------XADC数模转换------------------- +set_property src_info {type:XDC file:1 line:93 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports ad15p] +set_property src_info {type:XDC file:1 line:94 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports ad15n] +set_property src_info {type:XDC file:1 line:95 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports ad7p] +set_property src_info {type:XDC file:1 line:96 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports ad7n] +set_property src_info {type:XDC file:1 line:97 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports ad14p] +set_property src_info {type:XDC file:1 line:98 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports ad14n] +set_property src_info {type:XDC file:1 line:99 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports ad6p] +set_property src_info {type:XDC file:1 line:100 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports ad6n] +set_property src_info {type:XDC file:1 line:101 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports ad5p] +set_property src_info {type:XDC file:1 line:102 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS33} [get_ports ad5n] +set_property src_info {type:XDC file:1 line:103 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports ad13p] +set_property src_info {type:XDC file:1 line:104 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports ad13n] +set_property src_info {type:XDC file:1 line:105 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports ad4p] +set_property src_info {type:XDC file:1 line:106 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports ad4n] +set_property src_info {type:XDC file:1 line:111 export:INPUT save:INPUT read:READ} [current_design] +//--------------------------------------------------------DDR3L------------------------------------- +set_property src_info {type:XDC file:1 line:112 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_p] +set_property src_info {type:XDC file:1 line:113 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_n] +set_property src_info {type:XDC file:1 line:114 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_p] +set_property src_info {type:XDC file:1 line:115 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_n] +set_property src_info {type:XDC file:1 line:117 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq0] +set_property src_info {type:XDC file:1 line:118 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq1] +set_property src_info {type:XDC file:1 line:119 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq2] +set_property src_info {type:XDC file:1 line:120 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq3] +set_property src_info {type:XDC file:1 line:121 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq4] +set_property src_info {type:XDC file:1 line:122 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq5] +set_property src_info {type:XDC file:1 line:123 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq6] +set_property src_info {type:XDC file:1 line:124 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq7] +set_property src_info {type:XDC file:1 line:125 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq8] +set_property src_info {type:XDC file:1 line:126 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq9] +set_property src_info {type:XDC file:1 line:127 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq10] +set_property src_info {type:XDC file:1 line:128 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq11] +set_property src_info {type:XDC file:1 line:129 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq12] +set_property src_info {type:XDC file:1 line:130 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq13] +set_property src_info {type:XDC file:1 line:131 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq14] +set_property src_info {type:XDC file:1 line:132 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq15] +set_property src_info {type:XDC file:1 line:134 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a0] +set_property src_info {type:XDC file:1 line:135 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a1] +set_property src_info {type:XDC file:1 line:136 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a2] +set_property src_info {type:XDC file:1 line:137 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a3] +set_property src_info {type:XDC file:1 line:138 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a4] +set_property src_info {type:XDC file:1 line:139 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a5] +set_property src_info {type:XDC file:1 line:140 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a6] +set_property src_info {type:XDC file:1 line:141 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a7] +set_property src_info {type:XDC file:1 line:142 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a8] +set_property src_info {type:XDC file:1 line:143 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a9] +set_property src_info {type:XDC file:1 line:144 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a10] +set_property src_info {type:XDC file:1 line:145 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a11] +set_property src_info {type:XDC file:1 line:146 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a12] +set_property src_info {type:XDC file:1 line:148 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba0] +set_property src_info {type:XDC file:1 line:149 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba1] +set_property src_info {type:XDC file:1 line:150 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba2] +set_property src_info {type:XDC file:1 line:152 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm0] +set_property src_info {type:XDC file:1 line:153 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm1] +set_property src_info {type:XDC file:1 line:155 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports ddr3l_odt] +set_property src_info {type:XDC file:1 line:156 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_p] +set_property src_info {type:XDC file:1 line:157 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_n] +set_property src_info {type:XDC file:1 line:158 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cke] +set_property src_info {type:XDC file:1 line:159 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports ddr3l_cs] +set_property src_info {type:XDC file:1 line:160 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ras] +set_property src_info {type:XDC file:1 line:161 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports ddr3l_we] +set_property src_info {type:XDC file:1 line:162 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports ddr3l_reset] +set_property src_info {type:XDC file:1 line:163 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cas] diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/.vivado.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/.vivado.begin.rst" new file mode 100644 index 00000000..49ebbc9b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/.vivado.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/.vivado.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/.vivado.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/ISEWrap.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/ISEWrap.js" new file mode 100644 index 00000000..97a2ecbc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/ISEWrap.js" @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/ISEWrap.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/ISEWrap.sh" new file mode 100644 index 00000000..f679f2e8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/ISEWrap.sh" @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/__synthesis_is_complete__" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/__synthesis_is_complete__" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/example_6_4_1_exe.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/example_6_4_1_exe.dcp" new file mode 100644 index 00000000..6d74d5c1 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/example_6_4_1_exe.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/example_6_4_1_exe.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/example_6_4_1_exe.tcl" new file mode 100644 index 00000000..4c40f31c --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/example_6_4_1_exe.tcl" @@ -0,0 +1,56 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param chipscope.maxJobs 8 +set_param xicom.use_bs_reader 1 +create_project -in_memory -part xc7a75tfgg484-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.cache/wt [current_project] +set_property parent.project_path D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo d:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.v +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc +set_property used_in_implementation false [get_files D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc] + +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +synth_design -top example_6_4_1_exe -part xc7a75tfgg484-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef example_6_4_1_exe.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file example_6_4_1_exe_utilization_synth.rpt -pb example_6_4_1_exe_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/example_6_4_1_exe.vds" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/example_6_4_1_exe.vds" new file mode 100644 index 00000000..6f88ea59 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/example_6_4_1_exe.vds" @@ -0,0 +1,605 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 27 19:07:43 2023 +# Process ID: 20248 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/synth_1 +# Command line: vivado.exe -log example_6_4_1_exe.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_4_1_exe.tcl +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/synth_1/example_6_4_1_exe.vds +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source example_6_4_1_exe.tcl -notrace +Command: synth_design -top example_6_4_1_exe -part xc7a75tfgg484-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a75t' +INFO: [Device 21-403] Loading part xc7a75tfgg484-1 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 20636 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 852.898 ; gain = 235.336 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'example_6_4_1_exe' [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.v:28] +INFO: [Synth 8-6157] synthesizing module 'example_6_4_1' [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.v:6] +INFO: [Synth 8-6155] done synthesizing module 'example_6_4_1' (1#1) [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.v:6] +INFO: [Synth 8-6155] done synthesizing module 'example_6_4_1_exe' (2#1) [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.v:28] +WARNING: [Synth 8-3331] design example_6_4_1_exe has unconnected port led_pin[4] +WARNING: [Synth 8-3331] design example_6_4_1_exe has unconnected port led_pin[3] +WARNING: [Synth 8-3331] design example_6_4_1_exe has unconnected port led_pin[2] +WARNING: [Synth 8-3331] design example_6_4_1_exe has unconnected port led_pin[1] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 924.855 ; gain = 307.293 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 924.855 ; gain = 307.293 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 924.855 ; gain = 307.293 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 924.855 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------系统时钟------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:1] +WARNING: [Vivado 12-584] No ports matched 'sys_clk_50m'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_100m'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:3] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:3] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_3hz'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:4] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:4] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:7] +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------拨码?关sw0~sw7----------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:19] +WARNING: [Vivado 12-584] No ports matched 'sw_pin[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:20] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:20] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:21] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:21] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:22] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:22] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:23] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:23] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[4]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:24] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:24] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[5]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:25] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:25] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[6]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:26] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:26] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[7]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:27] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:27] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------------------9个按?--------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:31] +WARNING: [Vivado 12-584] No ports matched 'btn_0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:32] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:32] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:34] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:34] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:35] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:35] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:36] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:36] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:37] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:37] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:38] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:38] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:39] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:39] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:40] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:40] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_0_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:43] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:43] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_1_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:44] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:44] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_2_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:45] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:45] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_3_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:46] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:46] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_4_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:47] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:47] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_5_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:48] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:48] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_6_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:49] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_7_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:50] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:50] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_8_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:51] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:51] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------6个数码管-----------------------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:54] +WARNING: [Vivado 12-584] No ports matched 'digitron_out[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:55] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:55] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:56] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:56] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:57] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:57] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:58] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:58] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[4]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:59] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:59] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[5]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:60] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:60] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[6]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:61] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:61] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[7]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:62] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:62] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:64] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:64] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:65] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:65] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:66] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:66] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:67] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:67] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:69] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:69] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:70] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:70] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:71] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:71] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:72] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:72] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:74] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:74] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:75] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:75] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:76] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:76] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:77] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:77] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------串口---------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:81] +WARNING: [Vivado 12-584] No ports matched 'uart_rxd'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:82] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:82] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'uart_txd'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:83] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:83] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------蜂鸣?-----------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:87] +WARNING: [Vivado 12-584] No ports matched 'buzzer'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:88] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:88] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------XADC数模转换-------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:92] +WARNING: [Vivado 12-584] No ports matched 'ad15p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:93] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:93] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad15n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:94] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:94] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:95] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:95] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:96] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:96] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:97] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:97] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:98] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:98] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:99] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:99] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:100] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:100] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:101] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:101] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:102] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:102] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:103] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:103] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:104] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:104] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:105] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:105] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:106] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:106] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------DDR3L-------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:111] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:112] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:112] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:113] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:113] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:114] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:114] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:115] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:115] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:117] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:117] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:118] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:118] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:119] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:119] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:120] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:120] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:121] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:121] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:122] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:122] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:123] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:123] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:124] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:124] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:125] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:125] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq9'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:126] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:126] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq10'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:127] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:127] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq11'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:128] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:128] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq12'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:129] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:129] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq13'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:130] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:130] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq14'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:131] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:131] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq15'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:132] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:132] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:134] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:134] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:135] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:135] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:136] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:136] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:137] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:137] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:138] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:138] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:139] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:139] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:140] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:140] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:141] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:141] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:142] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:142] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a9'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:143] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:143] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a10'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:144] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:144] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a11'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:145] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:145] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a12'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:146] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:146] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:148] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:148] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:149] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:149] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:150] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:152] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:153] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_odt'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:155] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:156] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:157] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cke'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:158] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cs'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:159] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ras'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:160] +INFO: [Common 17-14] Message 'Vivado 12-584' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc:160] +Finished Parsing XDC File [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/ACE1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/example_6_4_1_exe_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/example_6_4_1_exe_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 973.188 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 973.188 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 973.188 ; gain = 355.625 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a75tfgg484-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 973.188 ; gain = 355.625 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 973.188 ; gain = 355.625 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 973.188 ; gain = 355.625 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 4 ++---Muxes : + 8 Input 1 Bit Muxes := 4 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module example_6_4_1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 4 ++---Muxes : + 8 Input 1 Bit Muxes := 4 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 180 (col length:80) +BRAMs: 210 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3331] design example_6_4_1_exe has unconnected port led_pin[4] +WARNING: [Synth 8-3331] design example_6_4_1_exe has unconnected port led_pin[3] +WARNING: [Synth 8-3331] design example_6_4_1_exe has unconnected port led_pin[2] +WARNING: [Synth 8-3331] design example_6_4_1_exe has unconnected port led_pin[1] +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 973.188 ; gain = 355.625 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 997.246 ; gain = 379.684 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 997.246 ; gain = 379.684 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1007.328 ; gain = 389.766 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1023.121 ; gain = 405.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1023.121 ; gain = 405.559 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1023.121 ; gain = 405.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1023.121 ; gain = 405.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1023.121 ; gain = 405.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1023.121 ; gain = 405.559 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |BUFG | 1| +|2 |LUT1 | 1| +|3 |LUT2 | 1| +|4 |LUT3 | 2| +|5 |FDRE | 4| +|6 |IBUF | 1| +|7 |OBUF | 4| +|8 |OBUFT | 4| ++------+------+------+ + +Report Instance Areas: ++------+---------+--------------+------+ +| |Instance |Module |Cells | ++------+---------+--------------+------+ +|1 |top | | 18| +|2 | U |example_6_4_1 | 8| ++------+---------+--------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1023.121 ; gain = 405.559 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 4 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1023.121 ; gain = 357.227 +Synthesis Optimization Complete : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1023.121 ; gain = 405.559 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1034.137 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1039.047 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +15 Infos, 117 Warnings, 109 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1039.047 ; gain = 732.277 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1039.047 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/synth_1/example_6_4_1_exe.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file example_6_4_1_exe_utilization_synth.rpt -pb example_6_4_1_exe_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Mon Nov 27 19:08:06 2023... diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/example_6_4_1_exe_utilization_synth.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/example_6_4_1_exe_utilization_synth.pb" new file mode 100644 index 00000000..c5e54f06 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/example_6_4_1_exe_utilization_synth.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/example_6_4_1_exe_utilization_synth.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/example_6_4_1_exe_utilization_synth.rpt" new file mode 100644 index 00000000..9ee90ad4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/example_6_4_1_exe_utilization_synth.rpt" @@ -0,0 +1,178 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 19:08:06 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_utilization -file example_6_4_1_exe_utilization_synth.rpt -pb example_6_4_1_exe_utilization_synth.pb +| Design : example_6_4_1_exe +| Device : 7a75tfgg484-1 +| Design State : Synthesized +----------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 2 | 0 | 47200 | <0.01 | +| LUT as Logic | 2 | 0 | 47200 | <0.01 | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| Slice Registers | 4 | 0 | 94400 | <0.01 | +| Register as Flip Flop | 4 | 0 | 94400 | <0.01 | +| Register as Latch | 0 | 0 | 94400 | 0.00 | +| F7 Muxes | 0 | 0 | 31700 | 0.00 | +| F8 Muxes | 0 | 0 | 15850 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 4 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 105 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 105 | 0.00 | +| RAMB18 | 0 | 0 | 210 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 180 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 9 | 0 | 285 | 3.16 | +| Bonded IPADs | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 6 | 0.00 | +| PHASER_REF | 0 | 0 | 6 | 0.00 | +| OUT_FIFO | 0 | 0 | 24 | 0.00 | +| IN_FIFO | 0 | 0 | 24 | 0.00 | +| IDELAYCTRL | 0 | 0 | 6 | 0.00 | +| IBUFDS | 0 | 0 | 274 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 24 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 24 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 300 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 0 | 0 | 6 | 0.00 | +| PLLE2_ADV | 0 | 0 | 6 | 0.00 | +| BUFMRCE | 0 | 0 | 12 | 0.00 | +| BUFHCE | 0 | 0 | 96 | 0.00 | +| BUFR | 0 | 0 | 24 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUFT | 4 | IO | +| OBUF | 4 | IO | +| FDRE | 4 | Flop & Latch | +| LUT3 | 2 | LUT | +| LUT2 | 1 | LUT | +| LUT1 | 1 | LUT | +| IBUF | 1 | IO | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/gen_run.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/gen_run.xml" new file mode 100644 index 00000000..e7795900 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/gen_run.xml" @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/htr.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/htr.txt" new file mode 100644 index 00000000..b561b527 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/htr.txt" @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log example_6_4_1_exe.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_4_1_exe.tcl diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/rundef.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/rundef.js" new file mode 100644 index 00000000..16832ecf --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/rundef.js" @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;"; +} else { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log example_6_4_1_exe.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_4_1_exe.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/runme.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/runme.bat" new file mode 100644 index 00000000..1760626b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/runme.bat" @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/runme.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/runme.sh" new file mode 100644 index 00000000..f26e5239 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/runme.sh" @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin +else + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log example_6_4_1_exe.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_4_1_exe.tcl diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/vivado.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/vivado.jou" new file mode 100644 index 00000000..68af67b6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/vivado.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 27 19:07:43 2023 +# Process ID: 20248 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/synth_1 +# Command line: vivado.exe -log example_6_4_1_exe.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_4_1_exe.tcl +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/synth_1/example_6_4_1_exe.vds +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_1_ACE1/example_6_4_1_ACE1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source example_6_4_1_exe.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/vivado.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/vivado.pb" new file mode 100644 index 00000000..9e6356ea Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.runs/synth_1/vivado.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.v" new file mode 100644 index 00000000..2552f46b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.v" @@ -0,0 +1,50 @@ +//ΪʽģΪʽʵ6.4ģ81 +//루xΪϵKEY1״̬y3y2y1ZΪߵ3LEDԼұߵ1LEDơ + +`timescale 1ns / 1ps + +module example_6_4_1( + input x, + input y3,y2, y1, + output reg ny3,ny2, ny1, z +); + + always @(negedge x) //Ϊʽ + begin + case({y3,y2, y1}) + 0: begin ny3<=0; ny2 <= 0; ny1 <= 1; z <= 0; end + 1: begin ny3<=0; ny2 <= 1; ny1 <= 0; z <= 0; end + 2: begin ny3<=0; ny2 <= 1; ny1 <= 1; z <= 0; end + 3: begin ny3<=1; ny2 <= 0; ny1 <= 0; z <= 0; end + 4: begin ny3<=1; ny2 <= 0; ny1 <= 1; z <= 0; end + 5: begin ny3<=1; ny2 <= 1; ny1 <= 0; z <= 0; end + 6: begin ny3<=1; ny2 <= 1; ny1 <= 1; z <= 0; end + 7: begin ny3<=0; ny2 <= 0; ny1 <= 0; z <= 1; end + endcase + end + +endmodule + +module example_6_4_1_exe( + input btn_1, //KEY1ť + output [7:0] led_pin //8led +); + + reg y3, y2, y1; + + example_6_4_1 U(.x(btn_1), .y3(y3),.y2(y2), .y1(y1), .ny3(led_pin[7]), .ny2(led_pin[6]), .ny1(led_pin[5]), .z(led_pin[0])); + + initial begin + y3=0; + y2=0; + y1=0; + end + + always @(*) //Ϊʽ + begin + y3 <= led_pin[7]; + y2 <= led_pin[6]; + y1 <= led_pin[5]; + end + +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.xpr" new file mode 100644 index 00000000..7c6f0b1d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO1.xpr" @@ -0,0 +1,184 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..a19e5473 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/gui_handlers.wdf" @@ -0,0 +1,20 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f796573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e756d6a6f627363686f6f7365725f6e756d6265725f6f665f6a6f6273:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 +eof:1311085054 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..5db1d223 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,12 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:31:00:00 +eof:919766343 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/project.wpc" new file mode 100644 index 00000000..3c63dc59 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/project.wpc" @@ -0,0 +1,4 @@ +version:1 +57656254616c6b5472616e736d697373696f6e417474656d70746564:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/synthesis.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/synthesis.wdf" new file mode 100644 index 00000000..fbe7d5d5 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/synthesis.wdf" @@ -0,0 +1,39 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:786337613735746667673438342d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:6578616d706c655f365f345f315f657865:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313873:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313032332e3132314d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3639312e3738314d42:00:00 +eof:855822180 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/synthesis_details.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/synthesis_details.wdf" new file mode 100644 index 00000000..78f8d66e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/synthesis_details.wdf" @@ -0,0 +1,3 @@ +version:1 +73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 +eof:2511430288 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..f7e278a2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.cache/wt/webtalk_pa.xml" @@ -0,0 +1,58 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.hw/example_6_4_1_ACE1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.hw/example_6_4_1_ACE1.lpr" new file mode 100644 index 00000000..b7d45757 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.hw/example_6_4_1_ACE1.lpr" @@ -0,0 +1,8 @@ + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.hw/hw_1/hw.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.hw/hw_1/hw.xml" new file mode 100644 index 00000000..432da473 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.hw/hw_1/hw.xml" @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.hw/webtalk/.xsim_webtallk.info" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.hw/webtalk/.xsim_webtallk.info" new file mode 100644 index 00000000..b980ad75 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.hw/webtalk/.xsim_webtallk.info" @@ -0,0 +1,5 @@ +1701083712 +0 +2 +1 +bc70ebd6-0436-4b91-8bdd-9d2379733a51 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.hw/webtalk/usage_statistics_ext_labtool.html" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.hw/webtalk/usage_statistics_ext_labtool.html" new file mode 100644 index 00000000..01844c5b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.hw/webtalk/usage_statistics_ext_labtool.html" @@ -0,0 +1,45 @@ +Device Usage Statistics Report +

LABTOOL Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2708876
date_generatedMon Nov 27 19:06:13 2023os_platformWIN64
product_versionVivado v2019.2 (64-bit)project_idbc70ebd6-0436-4b91-8bdd-9d2379733a51
project_iteration1random_idd24833b7-4cbd-4f74-b7c7-3cb815d77764
registration_idd24833b7-4cbd-4f74-b7c7-3cb815d77764route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowlabtool

+ + + + + + + + +
user_environment
cpu_nameAMD Ryzen 9 7945HX with Radeon Graphics cpu_speed2495 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram16.000 GBtotal_processors1

+ + +
vivado_usage

+ + + +
labtool
+ + + + + +
usage
cable=XilinxA/TULA/15000000:chain=13632093pgmcnt=01:00:00
+

+ + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.hw/webtalk/usage_statistics_ext_labtool.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.hw/webtalk/usage_statistics_ext_labtool.xml" new file mode 100644 index 00000000..cd93be25 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_1_EGO1/example_6_4_1_EGO11.hw/webtalk/usage_statistics_ext_labtool.xml" @@ -0,0 +1,39 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+ + + +
+
+
+
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/EGO1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/EGO1.xdc" new file mode 100644 index 00000000..620edf74 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/EGO1.xdc" @@ -0,0 +1,199 @@ +//----------------------------------------------系统时钟------------------------------------ +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports sys_clk_50m] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports sys_clk_100m] +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports sys_clk_3hz] + + +//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------ +set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + + + +//---------------------------------------------拨码?关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + + +//-----------------------------------------------9个按?-------------------------------------- +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports btn_4] +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports btn_5] +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports btn_6] +set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports btn_7] +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports btn_8] + + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_0_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_2_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_3_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_4_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_5_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_6_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_7_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_8_IBUF] + + +//-----------------------------------6个数码管----------------------------------------------------------- +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[0]}] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[1]}] +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[2]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {digitron_out[3]}] +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS33} [get_ports {digitron_out[4]}] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[5]}] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[6]}] +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[7]}] + +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[0]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[1]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[2]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[3]}] + +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {digitron_a[0]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {digitron_a[2]}] +set_property -dict {PACKAGE_PIN AB18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[3]}] + +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33} [get_ports {digitron_b[0]}] +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[1]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[2]}] +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports {digitron_b[3]}] + + + +//----------------------------------------------串口--------------------------------------------- +set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports uart_rxd] +set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports uart_txd] + + + +//----------------------------------------------蜂鸣?----------------------------------------- +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports buzzer] + + + +//--------------------------------------------------------XADC数模转换------------------- +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports ad15p] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports ad15n] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports ad7p] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports ad7n] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports ad14p] +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports ad14n] +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports ad6p] +set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports ad6n] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports ad5p] +set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS33} [get_ports ad5n] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports ad13p] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports ad13n] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports ad4p] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports ad4n] + + + + +//--------------------------------------------------------DDR3L------------------------------------- +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_p] +set_property -dict {PACKAGE_PIN AA3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_n] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_p] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_n] + +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq0] +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq1] +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq2] +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq3] +set_property -dict {PACKAGE_PIN AA5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq4] +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq5] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq6] +set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq7] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq8] +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq9] +set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq10] +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq11] +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq12] +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq13] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq14] +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq15] + +set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a0] +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a1] +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a2] +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a3] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a4] +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a5] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a6] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a7] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a8] +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a9] +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a10] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a11] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a12] + +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba0] +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba1] +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba2] + +set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm0] +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm1] + +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports ddr3l_odt] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_p] +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_n] +set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cke] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports ddr3l_cs] +set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ras] +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports ddr3l_we] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports ddr3l_reset] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cas] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..c54a2b88 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,39 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f6f725f6372656174655f636f6e73747261696e745f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f73696d756c6174696f6e5f73706563696669635f68646c5f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:38:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f796573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f70656e5f6d657373616765735f76696577:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3332:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3136:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f696e:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f6f7574:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:3134:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f666c6f77:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746f6f6c73:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f76696577:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d73677472656570616e656c5f6d6573736167655f766965775f74726565:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72657374617274:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72756e:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72756e5f616c6c:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72656c61756e6368:3137:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7372635f7265706c6163655f66696c65:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72646976696577735f77617665666f726d5f766965776572:3136:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e6c69766572756e666f72636f6d705f737065636966795f74696d655f616e645f756e697473:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74636c636f6e736f6c65766965775f74636c5f636f6e736f6c655f636f64655f656469746f72:33:00:00 +eof:3565030441 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..798b0a4d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,14 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:37:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:36:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72656c61756e6368:3136:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72657374617274:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e616c6c:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e666f7274696d65:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757064617465736f7572636566696c6573:33:00:00 +eof:1000600044 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..30d3330f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:4 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/synthesis.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/synthesis.wdf" new file mode 100644 index 00000000..1d2dc3d6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/synthesis.wdf" @@ -0,0 +1,39 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:786337613735746667673438342d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:6578616d706c655f365f345f32:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323073:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313031352e3630324d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3638342e3938304d42:00:00 +eof:2428772054 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/synthesis_details.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/synthesis_details.wdf" new file mode 100644 index 00000000..78f8d66e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/synthesis_details.wdf" @@ -0,0 +1,3 @@ +version:1 +73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 +eof:2511430288 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..e54ea303 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,79 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/xsim.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/xsim.wdf" new file mode 100644 index 00000000..51d5206f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt/xsim.wdf" @@ -0,0 +1,4 @@ +version:1 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 +eof:2427094519 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.hw/example_6_4_2_ACE1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.hw/example_6_4_2_ACE1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.hw/example_6_4_2_ACE1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.hw/example_6_4_2_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.hw/example_6_4_2_EGO1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.hw/example_6_4_2_EGO1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.ip_user_files/README.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.ip_user_files/README.txt" new file mode 100644 index 00000000..023052ca --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.ip_user_files/README.txt" @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/.jobs/vrs_config_1.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/.jobs/vrs_config_1.xml" new file mode 100644 index 00000000..9d31c307 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/.jobs/vrs_config_1.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/.jobs/vrs_config_2.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/.jobs/vrs_config_2.xml" new file mode 100644 index 00000000..9d31c307 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/.jobs/vrs_config_2.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.Vivado_Implementation.queue.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.Vivado_Implementation.queue.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.init_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.init_design.begin.rst" new file mode 100644 index 00000000..ffcb0160 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.init_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.init_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.init_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.opt_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.opt_design.begin.rst" new file mode 100644 index 00000000..ffcb0160 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.opt_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.opt_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.opt_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.phys_opt_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.phys_opt_design.begin.rst" new file mode 100644 index 00000000..ffcb0160 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.phys_opt_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.phys_opt_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.phys_opt_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.place_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.place_design.begin.rst" new file mode 100644 index 00000000..ffcb0160 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.place_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.place_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.place_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.route_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.route_design.begin.rst" new file mode 100644 index 00000000..ffcb0160 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.route_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.route_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.route_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.vivado.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.vivado.begin.rst" new file mode 100644 index 00000000..1cb0d3bb --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.vivado.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.vivado.error.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.vivado.error.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.write_bitstream.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.write_bitstream.begin.rst" new file mode 100644 index 00000000..ffcb0160 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.write_bitstream.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.write_bitstream.error.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/.write_bitstream.error.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/ISEWrap.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/ISEWrap.js" new file mode 100644 index 00000000..97a2ecbc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/ISEWrap.js" @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/ISEWrap.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/ISEWrap.sh" new file mode 100644 index 00000000..f679f2e8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/ISEWrap.sh" @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2.tcl" new file mode 100644 index 00000000..3936ee47 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2.tcl" @@ -0,0 +1,186 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param chipscope.maxJobs 4 + create_project -in_memory -part xc7a75tfgg484-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt [current_project] + set_property parent.project_path C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.xpr [current_project] + set_property ip_output_repo C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2.dcp + read_xdc C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc + link_design -top example_6_4_2 -part xc7a75tfgg484-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force example_6_4_2_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file example_6_4_2_drc_opted.rpt -pb example_6_4_2_drc_opted.pb -rpx example_6_4_2_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force example_6_4_2_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file example_6_4_2_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file example_6_4_2_utilization_placed.rpt -pb example_6_4_2_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file example_6_4_2_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step phys_opt_design +set ACTIVE_STEP phys_opt_design +set rc [catch { + create_msg_db phys_opt_design.pb + phys_opt_design + write_checkpoint -force example_6_4_2_physopt.dcp + close_msg_db -file phys_opt_design.pb +} RESULT] +if {$rc} { + step_failed phys_opt_design + return -code error $RESULT +} else { + end_step phys_opt_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force example_6_4_2_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file example_6_4_2_drc_routed.rpt -pb example_6_4_2_drc_routed.pb -rpx example_6_4_2_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file example_6_4_2_methodology_drc_routed.rpt -pb example_6_4_2_methodology_drc_routed.pb -rpx example_6_4_2_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file example_6_4_2_power_routed.rpt -pb example_6_4_2_power_summary_routed.pb -rpx example_6_4_2_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file example_6_4_2_route_status.rpt -pb example_6_4_2_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file example_6_4_2_timing_summary_routed.rpt -pb example_6_4_2_timing_summary_routed.pb -rpx example_6_4_2_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file example_6_4_2_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file example_6_4_2_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file example_6_4_2_bus_skew_routed.rpt -pb example_6_4_2_bus_skew_routed.pb -rpx example_6_4_2_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force example_6_4_2_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + catch { write_mem_info -force example_6_4_2.mmi } + write_bitstream -force example_6_4_2.bit + catch {write_debug_probes -quiet -force example_6_4_2} + catch {file copy -force example_6_4_2.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2.vdi" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2.vdi" new file mode 100644 index 00000000..cd8affa9 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2.vdi" @@ -0,0 +1,834 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Sun Nov 16 19:47:03 2025 +# Process ID: 4024 +# Current directory: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1 +# Command line: vivado.exe -log example_6_4_2.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source example_6_4_2.tcl -notrace +# Log file: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2.vdi +# Journal file: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source example_6_4_2.tcl -notrace +Command: link_design -top example_6_4_2 -part xc7a75tfgg484-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7a75tfgg484-1 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 620.426 ; gain = 0.000 +INFO: [Project 1-479] Netlist was created with Vivado 2019.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------系统时钟------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:1] +WARNING: [Vivado 12-584] No ports matched 'sys_clk_50m'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_100m'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:3] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:3] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_3hz'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:4] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:4] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:7] +WARNING: [Vivado 12-584] No ports matched 'led_pin[0]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:8] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:8] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[1]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:9] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:9] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[2]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:10] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:10] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[3]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:11] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:11] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[4]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:12] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:12] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[5]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:13] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:13] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[6]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:14] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:14] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[7]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:15] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:15] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------拨码?关sw0~sw7----------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:19] +WARNING: [Vivado 12-584] No ports matched 'sw_pin[0]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:20] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:20] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[1]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:21] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:21] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[2]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:22] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:22] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[3]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:23] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:23] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[4]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:24] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:24] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[5]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:25] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:25] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[6]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:26] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:26] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[7]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:27] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:27] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------------------9个按?--------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:31] +WARNING: [Vivado 12-584] No ports matched 'btn_0'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:32] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:32] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_1'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:33] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:33] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_2'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:34] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:34] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_3'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:35] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:35] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_4'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:36] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:36] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_5'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:37] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:37] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_6'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:38] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:38] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_7'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:39] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:39] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_8'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:40] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:40] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_0_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:43] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:43] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_1_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:44] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:44] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_2_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:45] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:45] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_3_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:46] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:46] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_4_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:47] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:47] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_5_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:48] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:48] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_6_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:49] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_7_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:50] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:50] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_8_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:51] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:51] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------6个数码管-----------------------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:54] +WARNING: [Vivado 12-584] No ports matched 'digitron_out[0]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:55] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:55] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[1]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:56] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:56] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[2]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:57] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:57] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[3]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:58] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:58] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[4]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:59] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:59] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[5]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:60] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:60] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[6]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:61] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:61] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[7]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:62] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:62] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[0]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:64] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:64] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[1]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:65] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:65] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[2]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:66] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:66] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[3]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:67] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:67] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[0]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:69] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:69] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[1]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:70] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:70] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[2]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:71] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:71] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[3]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:72] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:72] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[0]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:74] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:74] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[1]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:75] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:75] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[2]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:76] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:76] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[3]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:77] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:77] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------串口---------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:81] +WARNING: [Vivado 12-584] No ports matched 'uart_rxd'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:82] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:82] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'uart_txd'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:83] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:83] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------蜂鸣?-----------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:87] +WARNING: [Vivado 12-584] No ports matched 'buzzer'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:88] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:88] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------XADC数模转换-------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:92] +WARNING: [Vivado 12-584] No ports matched 'ad15p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:93] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:93] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad15n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:94] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:94] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:95] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:95] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:96] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:96] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:97] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:97] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:98] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:98] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:99] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:99] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:100] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:100] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:101] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:101] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:102] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:102] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:103] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:103] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:104] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:104] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:105] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:105] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:106] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:106] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------DDR3L-------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:111] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:112] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:112] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:113] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:113] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:114] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:114] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:115] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:115] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq0'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:117] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:117] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq1'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:118] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:118] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq2'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:119] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:119] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq3'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:120] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:120] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq4'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:121] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:121] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq5'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:122] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:122] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq6'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:123] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:123] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq7'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:124] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:124] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq8'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:125] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:125] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq9'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:126] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:126] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq10'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:127] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:127] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq11'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:128] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:128] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq12'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:129] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:129] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq13'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:130] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:130] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq14'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:131] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:131] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq15'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:132] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:132] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a0'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:134] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:134] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a1'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:135] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:135] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a2'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:136] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:136] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a3'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:137] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:137] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a4'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:138] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:138] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a5'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:139] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:139] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +INFO: [Common 17-14] Message 'Common 17-55' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:139] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a6'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:140] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a7'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:141] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a8'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:142] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a9'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:143] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a10'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:144] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a11'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:145] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a12'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:146] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba0'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:148] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba1'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:149] +INFO: [Common 17-14] Message 'Vivado 12-584' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:149] +Finished Parsing XDC File [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 729.707 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 109 Warnings, 109 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 733.770 ; gain = 422.973 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 751.809 ; gain = 18.039 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 10db07717 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 1257.512 ; gain = 505.703 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 10db07717 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1455.000 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 10db07717 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1455.000 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 10db07717 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1455.000 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. +INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. +INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). +Phase 4 BUFG optimization | Checksum: 10db07717 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1455.000 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 10db07717 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1455.000 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 10db07717 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1455.000 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1455.000 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 10db07717 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1455.000 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 10db07717 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1455.000 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 10db07717 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1455.000 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1455.000 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 10db07717 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1455.000 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +27 Infos, 109 Warnings, 109 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1455.000 ; gain = 721.230 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1455.000 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +INFO: [Common 17-1381] The checkpoint 'C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file example_6_4_2_drc_opted.rpt -pb example_6_4_2_drc_opted.pb -rpx example_6_4_2_drc_opted.rpx +Command: report_drc -file example_6_4_2_drc_opted.rpt -pb example_6_4_2_drc_opted.pb -rpx example_6_4_2_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Vivado/Download/Vivado/2019.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1455.000 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 76b38a04 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1455.000 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1455.000 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d854b015 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1461.973 ; gain = 6.973 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 11e68cdeb + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1471.047 ; gain = 16.047 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 11e68cdeb + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1471.047 ; gain = 16.047 +Phase 1 Placer Initialization | Checksum: 11e68cdeb + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1471.047 ; gain = 16.047 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 11e68cdeb + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1471.047 ; gain = 16.047 + +Phase 2.2 Global Placement Core +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2.2 Global Placement Core | Checksum: 16c133d3c + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1471.047 ; gain = 16.047 +Phase 2 Global Placement | Checksum: 16c133d3c + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1471.047 ; gain = 16.047 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 16c133d3c + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1471.047 ; gain = 16.047 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b9cc4f04 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1471.047 ; gain = 16.047 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1bf974454 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1471.047 ; gain = 16.047 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1bf974454 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1471.047 ; gain = 16.047 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1214a3ad6 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1471.047 ; gain = 16.047 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1214a3ad6 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1471.047 ; gain = 16.047 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1214a3ad6 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1471.047 ; gain = 16.047 +Phase 3 Detail Placement | Checksum: 1214a3ad6 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1471.047 ; gain = 16.047 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1214a3ad6 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1471.047 ; gain = 16.047 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1214a3ad6 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1471.047 ; gain = 16.047 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 1214a3ad6 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1471.047 ; gain = 16.047 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.047 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: 179bdfdf5 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1471.047 ; gain = 16.047 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 179bdfdf5 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1471.047 ; gain = 16.047 +Ending Placer Task | Checksum: d041188d + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1471.047 ; gain = 16.047 +INFO: [Common 17-83] Releasing license: Implementation +45 Infos, 110 Warnings, 109 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.047 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 1475.188 ; gain = 4.141 +INFO: [Common 17-1381] The checkpoint 'C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file example_6_4_2_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.106 . Memory (MB): peak = 1475.188 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file example_6_4_2_utilization_placed.rpt -pb example_6_4_2_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file example_6_4_2_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1475.188 ; gain = 0.000 +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +53 Infos, 110 Warnings, 109 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1475.516 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 1493.441 ; gain = 17.926 +INFO: [Common 17-1381] The checkpoint 'C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_physopt.dcp' has been generated. +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 598d8e89 ConstDB: 0 ShapeSum: 76b38a04 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: b36cc7f0 + +Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1616.758 ; gain = 114.266 +Post Restoration Checksum: NetGraph: 995773f5 NumContArr: 1a1553fb Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: b36cc7f0 + +Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1622.730 ; gain = 120.238 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: b36cc7f0 + +Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1622.730 ; gain = 120.238 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 1269b66da + +Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1640.305 ; gain = 137.812 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 7 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 6 + Number of Partially Routed Nets = 1 + Number of Node Overlaps = 0 + + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 1019ab41f + +Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1640.305 ; gain = 137.812 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 710693fc + +Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1640.305 ; gain = 137.812 +Phase 4 Rip-up And Reroute | Checksum: 710693fc + +Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1640.305 ; gain = 137.812 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 710693fc + +Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1640.305 ; gain = 137.812 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 710693fc + +Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1640.305 ; gain = 137.812 +Phase 6 Post Hold Fix | Checksum: 710693fc + +Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1640.305 ; gain = 137.812 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.000783392 % + Global Horizontal Routing Utilization = 0.00120773 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 710693fc + +Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1640.305 ; gain = 137.812 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 710693fc + +Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1640.305 ; gain = 137.812 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: c5e76040 + +Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1640.305 ; gain = 137.812 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 1640.305 ; gain = 137.812 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +63 Infos, 110 Warnings, 109 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:21 . Memory (MB): peak = 1640.305 ; gain = 146.863 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1640.305 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 1648.176 ; gain = 7.871 +INFO: [Common 17-1381] The checkpoint 'C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file example_6_4_2_drc_routed.rpt -pb example_6_4_2_drc_routed.pb -rpx example_6_4_2_drc_routed.rpx +Command: report_drc -file example_6_4_2_drc_routed.rpt -pb example_6_4_2_drc_routed.pb -rpx example_6_4_2_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file example_6_4_2_methodology_drc_routed.rpt -pb example_6_4_2_methodology_drc_routed.pb -rpx example_6_4_2_methodology_drc_routed.rpx +Command: report_methodology -file example_6_4_2_methodology_drc_routed.rpt -pb example_6_4_2_methodology_drc_routed.pb -rpx example_6_4_2_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file example_6_4_2_power_routed.rpt -pb example_6_4_2_power_summary_routed.pb -rpx example_6_4_2_power_routed.rpx +Command: report_power -file example_6_4_2_power_routed.rpt -pb example_6_4_2_power_summary_routed.pb -rpx example_6_4_2_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +75 Infos, 111 Warnings, 109 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file example_6_4_2_route_status.rpt -pb example_6_4_2_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file example_6_4_2_timing_summary_routed.rpt -pb example_6_4_2_timing_summary_routed.pb -rpx example_6_4_2_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file example_6_4_2_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file example_6_4_2_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file example_6_4_2_bus_skew_routed.rpt -pb example_6_4_2_bus_skew_routed.pb -rpx example_6_4_2_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force example_6_4_2.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +ERROR: [DRC NSTD-1] Unspecified I/O Standard: 6 out of 6 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: y[2:0], rst_n, x, and z. +ERROR: [DRC UCIO-1] Unconstrained Logical Port: 6 out of 6 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: y[2:0], rst_n, x, and z. +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 2 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. +INFO: [Common 17-83] Releasing license: Implementation +91 Infos, 113 Warnings, 109 Critical Warnings and 3 Errors encountered. +write_bitstream failed +ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors. + +INFO: [Common 17-206] Exiting Vivado at Sun Nov 16 19:48:04 2025... diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_bus_skew_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_bus_skew_routed.pb" new file mode 100644 index 00000000..3390588d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_bus_skew_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_bus_skew_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_bus_skew_routed.rpt" new file mode 100644 index 00000000..27fba78f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_bus_skew_routed.rpt" @@ -0,0 +1,15 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sun Nov 16 19:48:03 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file example_6_4_2_bus_skew_routed.rpt -pb example_6_4_2_bus_skew_routed.pb -rpx example_6_4_2_bus_skew_routed.rpx +| Design : example_6_4_2 +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Bus Skew Report + +No bus skew constraints + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_bus_skew_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_bus_skew_routed.rpx" new file mode 100644 index 00000000..06e3d959 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_bus_skew_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_clock_utilization_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_clock_utilization_routed.rpt" new file mode 100644 index 00000000..b74020b8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_clock_utilization_routed.rpt" @@ -0,0 +1,165 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sun Nov 16 19:48:03 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_clock_utilization -file example_6_4_2_clock_utilization_routed.rpt +| Design : example_6_4_2 +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Local Clock Details +5. Clock Regions: Key Resource Utilization +6. Clock Regions : Global Clock Summary +7. Device Cell Placement Summary for Global Clock g0 +8. Clock Region Cell Placement per Global Clock: Region X0Y0 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 96 | 0 | 0 | 0 | +| BUFIO | 0 | 24 | 0 | 0 | 0 | +| BUFMR | 0 | 12 | 0 | 0 | 0 | +| BUFR | 0 | 24 | 0 | 0 | 0 | +| MMCM | 0 | 6 | 0 | 0 | 0 | +| PLL | 0 | 6 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+--------------------+-------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+--------------------+-------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 1 | 0 | | | x_IBUF_BUFG_inst/O | x_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+--------------------+-------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+---------------+--------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+---------------+--------+ +| src0 | g0 | IBUF/O | None | IOB_X0Y28 | X0Y0 | 1 | 1 | | | x_IBUF_inst/O | x_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+---------------+--------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Local Clock Details +---------------------- + ++----------+-----------------+------------+-----------------+--------------+-------------+-----------------+--------------+-------+------------+--------------+ +| Local Id | Driver Type/Pin | Constraint | Site/BEL | Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++----------+-----------------+------------+-----------------+--------------+-------------+-----------------+--------------+-------+------------+--------------|| +| 0 | FDCE/Q | None | SLICE_X0Y16/AFF | X0Y0 | 1 | 3 | | | U1/y_reg/Q | U1/y_OBUF[0] - Static - +| 1 | FDCE/Q | None | SLICE_X1Y17/AFF | X0Y0 | 1 | 3 | | | U2/y_reg/Q | U2/y_OBUF[0] - Static - ++----------+-----------------+------------+-----------------+--------------+-------------+-----------------+--------------+-------+------------+--------------|| +* Local Clocks in this context represents only clocks driven by non-global buffers +** Clock Loads column represents the clock pin loads (pin count) +*** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +5. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1500 | 0 | 550 | 0 | 40 | 0 | 20 | 0 | 40 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1350 | 0 | 500 | 0 | 30 | 0 | 15 | 0 | 40 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +6. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 1 | 0 | ++----+----+----+ + + +7. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------+ +| g0 | BUFG/O | n/a | | | | 1 | 0 | 0 | 0 | x_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------+ +* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 1 | 0 | ++----+----+----+ + + +8. Clock Region Cell Placement per Global Clock: Region X0Y0 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------+ +| g0 | n/a | BUFG/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | x_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells x_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X0Y28 [get_ports x] + +# Clock net "x_IBUF_BUFG" driven by instance "x_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_x_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_x_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="x_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_x_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0} +#endgroup diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_control_sets_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_control_sets_placed.rpt" new file mode 100644 index 00000000..35939eb3 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_control_sets_placed.rpt" @@ -0,0 +1,81 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sun Nov 16 19:47:39 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file example_6_4_2_control_sets_placed.rpt +| Design : example_6_4_2 +| Device : xc7a75t +------------------------------------------------------------------------------------------ + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Total control sets | 3 | +| Minimum number of control sets | 3 | +| Addition due to synthesis replication | 0 | +| Addition due to physical synthesis replication | 0 | +| Unused register locations in slices containing registers | 21 | ++----------------------------------------------------------+-------+ +* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers +** Run report_qor_suggestions for automated merging and remapping suggestions + + +2. Histogram +------------ + ++--------------------+-------+ +| Fanout | Count | ++--------------------+-------+ +| Total control sets | 3 | +| >= 0 to < 4 | 3 | +| >= 4 to < 6 | 0 | +| >= 6 to < 8 | 0 | +| >= 8 to < 10 | 0 | +| >= 10 to < 12 | 0 | +| >= 12 to < 14 | 0 | +| >= 14 to < 16 | 0 | +| >= 16 | 0 | ++--------------------+-------+ +* Control sets can be remapped at either synth_design or opt_design + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 3 | 3 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++---------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++---------------+---------------+------------------+------------------+----------------+ +| ~U1/y_OBUF[0] | | U1/rst_n | 1 | 1 | +| ~U2/y_OBUF[0] | | U1/rst_n | 1 | 1 | +| ~x_IBUF_BUFG | | U1/rst_n | 1 | 1 | ++---------------+---------------+------------------+------------------+----------------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_opted.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_opted.pb" new file mode 100644 index 00000000..0158a2ad Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_opted.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_opted.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_opted.rpt" new file mode 100644 index 00000000..a18dfe1c --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_opted.rpt" @@ -0,0 +1,61 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sun Nov 16 19:47:35 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_drc -file example_6_4_2_drc_opted.rpt -pb example_6_4_2_drc_opted.pb -rpx example_6_4_2_drc_opted.rpx +| Design : example_6_4_2 +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 3 ++----------+------------------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+------------------+-----------------------------------------------------+------------+ +| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | +| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+------------------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +NSTD-1#1 Critical Warning +Unspecified I/O Standard +6 out of 6 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: y[2:0], rst_n, x, z. +Related violations: + +UCIO-1#1 Critical Warning +Unconstrained Logical Port +6 out of 6 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: y[2:0], rst_n, x, z. +Related violations: + +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_opted.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_opted.rpx" new file mode 100644 index 00000000..c3a3d003 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_opted.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_routed.pb" new file mode 100644 index 00000000..0158a2ad Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_routed.rpt" new file mode 100644 index 00000000..8b61ad6a --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_routed.rpt" @@ -0,0 +1,61 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sun Nov 16 19:48:02 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_drc -file example_6_4_2_drc_routed.rpt -pb example_6_4_2_drc_routed.pb -rpx example_6_4_2_drc_routed.rpx +| Design : example_6_4_2 +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Fully Routed +--------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 3 ++----------+------------------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+------------------+-----------------------------------------------------+------------+ +| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | +| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+------------------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +NSTD-1#1 Critical Warning +Unspecified I/O Standard +6 out of 6 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: y[2:0], rst_n, x, z. +Related violations: + +UCIO-1#1 Critical Warning +Unconstrained Logical Port +6 out of 6 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: y[2:0], rst_n, x, z. +Related violations: + +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_routed.rpx" new file mode 100644 index 00000000..53d673bd Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_drc_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_io_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_io_placed.rpt" new file mode 100644 index 00000000..a073b86b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_io_placed.rpt" @@ -0,0 +1,526 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sun Nov 16 19:47:39 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_io -file example_6_4_2_io_placed.rpt +| Design : example_6_4_2 +| Device : xc7a75t +| Speed File : -1 +| Package : fgg484 +| Package Version : FINAL 2012-11-02 +| Package Pin Delay Version : VERS. 2.0 2012-11-02 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 6 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A4 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A6 | | | MGTPTXN2_216 | Gigabit | | | | | | | | | | | | | | | | +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A8 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A10 | | | MGTPRXN2_216 | Gigabit | | | | | | | | | | | | | | | | +| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A19 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A20 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A21 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA3 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA4 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| AA8 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA9 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA10 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA11 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA13 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA14 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA15 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA16 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| AA18 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| AA19 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| AA20 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| AA21 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB2 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB3 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| AB5 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB8 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB10 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB11 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB12 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB13 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| AB15 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB16 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB17 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB20 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| AB21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| AB22 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B4 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| B5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B6 | | | MGTPTXP2_216 | Gigabit | | | | | | | | | | | | | | | | +| B7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B8 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| B9 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B10 | | | MGTPRXP2_216 | Gigabit | | | | | | | | | | | | | | | | +| B11 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B15 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B16 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B20 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| B21 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| B22 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| C1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| C2 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C4 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C5 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C7 | | | MGTPTXN3_216 | Gigabit | | | | | | | | | | | | | | | | +| C8 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C9 | | | MGTPRXN3_216 | Gigabit | | | | | | | | | | | | | | | | +| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C11 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| C12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| C14 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C18 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C19 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C20 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| C21 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C22 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| D2 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D5 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| D6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| D7 | | | MGTPTXP3_216 | Gigabit | | | | | | | | | | | | | | | | +| D8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D9 | | | MGTPRXP3_216 | Gigabit | | | | | | | | | | | | | | | | +| D10 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| D11 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D14 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D16 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| D17 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| D19 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D20 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D21 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D22 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E6 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | | +| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E8 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | | +| E11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E12 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E14 | | High Range | IO_L4N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E15 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| E16 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L2N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| E19 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E21 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| E22 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| F3 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F6 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | | +| F7 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| F8 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | | +| F9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| F10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| F13 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F15 | | High Range | IO_0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L2P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| F19 | | High Range | IO_L18P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| F20 | | High Range | IO_L18N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| F21 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | | +| F22 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| G1 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G15 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| G16 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G19 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G20 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G21 | | High Range | IO_L24P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| G22 | | High Range | IO_L24N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| H1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H2 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| H4 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| H14 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| H17 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H19 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H20 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H22 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| J1 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J2 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| J4 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J14 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J17 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J19 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J20 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J21 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J22 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| K4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K6 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K16 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| K19 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| K20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K21 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| K22 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| L6 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| L12 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| L13 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| L18 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| L19 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| L20 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| L21 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M1 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| M4 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| M5 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| M6 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| M10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| M14 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| M15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| M16 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| M17 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| M21 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| M22 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| N1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| N2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N3 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| N4 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| N12 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| N13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| N14 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| N19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| N20 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| N21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| N22 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| P1 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P2 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| P5 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| P6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P14 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| P19 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| P20 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| P21 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| P22 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| R2 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| R6 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R13 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| R14 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| R15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| R16 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| R19 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R21 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| R22 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| T3 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| T13 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T15 | z | High Range | IO_L15N_T2_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T16 | y[0] | High Range | IO_L17P_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| T19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T20 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| T21 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| T22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| U1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U5 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U6 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| U9 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| U10 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| U11 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| U12 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| U13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U15 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| U16 | rst_n | High Range | IO_L17N_T2_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | +| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| U19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| U20 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| U21 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| U22 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V2 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| V4 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| V7 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V12 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| V13 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V14 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| V17 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| V19 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| V20 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V22 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| W1 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W2 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| W4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W5 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W6 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W9 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| W10 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| W11 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W12 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W13 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| W14 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| W15 | y[2] | High Range | IO_L16P_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W16 | y[1] | High Range | IO_L16N_T2_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| W17 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| W20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| W21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| W22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| Y1 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y3 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y4 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y7 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y8 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y9 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y10 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| Y11 | x | High Range | IO_L11P_T1_SRCC_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | +| Y12 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y13 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y14 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y16 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y17 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| Y19 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| Y20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| Y21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| Y22 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_methodology_drc_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_methodology_drc_routed.pb" new file mode 100644 index 00000000..f9205a9e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_methodology_drc_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_methodology_drc_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_methodology_drc_routed.rpt" new file mode 100644 index 00000000..d3284598 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_methodology_drc_routed.rpt" @@ -0,0 +1,50 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sun Nov 16 19:48:02 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_methodology -file example_6_4_2_methodology_drc_routed.rpt -pb example_6_4_2_methodology_drc_routed.pb -rpx example_6_4_2_methodology_drc_routed.rpx +| Design : example_6_4_2 +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Fully Routed +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 3 ++-----------+------------------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+------------------+-----------------------------+------------+ +| TIMING-17 | Critical Warning | Non-clocked sequential cell | 3 | ++-----------+------------------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Critical Warning +Non-clocked sequential cell +The clock pin U1/y_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Critical Warning +Non-clocked sequential cell +The clock pin U2/y_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Critical Warning +Non-clocked sequential cell +The clock pin U3/y_reg/C is not reached by a timing clock +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_methodology_drc_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_methodology_drc_routed.rpx" new file mode 100644 index 00000000..8883923a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_methodology_drc_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_opt.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_opt.dcp" new file mode 100644 index 00000000..b46bd048 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_opt.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_physopt.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_physopt.dcp" new file mode 100644 index 00000000..9f65047b Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_physopt.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_placed.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_placed.dcp" new file mode 100644 index 00000000..28812283 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_placed.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_power_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_power_routed.rpt" new file mode 100644 index 00000000..86dd48e9 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_power_routed.rpt" @@ -0,0 +1,147 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sun Nov 16 19:48:03 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_power -file example_6_4_2_power_routed.rpt -pb example_6_4_2_power_summary_routed.pb -rpx example_6_4_2_power_routed.rpx +| Design : example_6_4_2 +| Device : xc7a75tfgg484-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 6.209 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 6.102 | +| Device Static (W) | 0.107 | +| Effective TJA (C/W) | 2.7 | +| Max Ambient (C) | 68.4 | +| Junction Temperature (C) | 41.6 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.046 | 12 | --- | --- | +| LUT as Logic | 0.034 | 5 | 47200 | 0.01 | +| Register | 0.007 | 3 | 94400 | <0.01 | +| BUFG | 0.006 | 1 | 32 | 3.13 | +| Others | 0.000 | 3 | --- | --- | +| Signals | 0.114 | 8 | --- | --- | +| I/O | 5.941 | 6 | 285 | 2.11 | +| Static Power | 0.107 | | | | +| Total | 6.209 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.193 | 0.164 | 0.028 | +| Vccaux | 1.800 | 0.506 | 0.486 | 0.020 | +| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 2.817 | 2.813 | 0.004 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.001 | 0.000 | 0.001 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified more than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 2.7 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++---------------+-----------+ +| Name | Power (W) | ++---------------+-----------+ +| example_6_4_2 | 6.102 | +| U1 | 0.045 | +| U2 | 0.045 | +| U3 | 0.038 | +| U4 | 0.015 | ++---------------+-----------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_power_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_power_routed.rpx" new file mode 100644 index 00000000..186c473f Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_power_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_power_summary_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_power_summary_routed.pb" new file mode 100644 index 00000000..8006ae82 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_power_summary_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_route_status.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_route_status.pb" new file mode 100644 index 00000000..e975e2c3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_route_status.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_route_status.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_route_status.rpt" new file mode 100644 index 00000000..cd95ed1f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_route_status.rpt" @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 18 : + # of nets not needing routing.......... : 10 : + # of internally routed nets........ : 10 : + # of routable nets..................... : 8 : + # of fully routed nets............. : 8 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_routed.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_routed.dcp" new file mode 100644 index 00000000..165ad0f5 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_routed.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_timing_summary_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_timing_summary_routed.pb" new file mode 100644 index 00000000..4526e931 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_timing_summary_routed.pb" @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_timing_summary_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_timing_summary_routed.rpt" new file mode 100644 index 00000000..bcf79245 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_timing_summary_routed.rpt" @@ -0,0 +1,179 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sun Nov 16 19:48:03 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file example_6_4_2_timing_summary_routed.rpt -pb example_6_4_2_timing_summary_routed.pb -rpx example_6_4_2_timing_summary_routed.rpx -warn_on_violation +| Design : example_6_4_2 +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There is 1 register/latch pin with no clock driven by root clock pin: x (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: U1/y_reg/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: U2/y_reg/Q (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 6 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There is 1 input port with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 4 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_timing_summary_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_timing_summary_routed.rpx" new file mode 100644 index 00000000..818c9dd1 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_timing_summary_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_utilization_placed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_utilization_placed.pb" new file mode 100644 index 00000000..d72f9081 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_utilization_placed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_utilization_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_utilization_placed.rpt" new file mode 100644 index 00000000..a539115c --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2_utilization_placed.rpt" @@ -0,0 +1,202 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sun Nov 16 19:47:39 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_utilization -file example_6_4_2_utilization_placed.rpt -pb example_6_4_2_utilization_placed.pb +| Design : example_6_4_2 +| Device : 7a75tfgg484-1 +| Design State : Fully Placed +----------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 5 | 0 | 47200 | 0.01 | +| LUT as Logic | 5 | 0 | 47200 | 0.01 | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| Slice Registers | 3 | 0 | 94400 | <0.01 | +| Register as Flip Flop | 3 | 0 | 94400 | <0.01 | +| Register as Latch | 0 | 0 | 94400 | 0.00 | +| F7 Muxes | 0 | 0 | 31700 | 0.00 | +| F8 Muxes | 0 | 0 | 15850 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 3 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------------------------------------+------+-------+-----------+-------+ +| Slice | 4 | 0 | 15850 | 0.03 | +| SLICEL | 4 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 5 | 0 | 47200 | 0.01 | +| using O5 output only | 0 | | | | +| using O6 output only | 5 | | | | +| using O5 and O6 | 0 | | | | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 3 | 0 | 94400 | <0.01 | +| Register driven from within the Slice | 3 | | | | +| Register driven from outside the Slice | 0 | | | | +| Unique Control Sets | 3 | | 15850 | 0.02 | ++------------------------------------------+------+-------+-----------+-------+ +* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 105 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 105 | 0.00 | +| RAMB18 | 0 | 0 | 210 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 180 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 6 | 0 | 285 | 2.11 | +| IOB Master Pads | 3 | | | | +| IOB Slave Pads | 3 | | | | +| Bonded IPADs | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 6 | 0.00 | +| PHASER_REF | 0 | 0 | 6 | 0.00 | +| OUT_FIFO | 0 | 0 | 24 | 0.00 | +| IN_FIFO | 0 | 0 | 24 | 0.00 | +| IDELAYCTRL | 0 | 0 | 6 | 0.00 | +| IBUFDS | 0 | 0 | 274 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 24 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 24 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 300 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 0 | 0 | 6 | 0.00 | +| PLLE2_ADV | 0 | 0 | 6 | 0.00 | +| BUFMRCE | 0 | 0 | 12 | 0.00 | +| BUFHCE | 0 | 0 | 96 | 0.00 | +| BUFR | 0 | 0 | 24 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 4 | IO | +| LUT1 | 4 | LUT | +| FDCE | 3 | Flop & Latch | +| IBUF | 2 | IO | +| LUT4 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/gen_run.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/gen_run.xml" new file mode 100644 index 00000000..337a78d1 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/gen_run.xml" @@ -0,0 +1,123 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/htr.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/htr.txt" new file mode 100644 index 00000000..d4f22ba1 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/htr.txt" @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log example_6_4_2.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_6_4_2.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/init_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/init_design.pb" new file mode 100644 index 00000000..d3337aa3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/init_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/opt_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/opt_design.pb" new file mode 100644 index 00000000..ab4ab2ca Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/opt_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/phys_opt_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/phys_opt_design.pb" new file mode 100644 index 00000000..bfaab7a4 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/phys_opt_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/place_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/place_design.pb" new file mode 100644 index 00000000..e7209e2f Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/place_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/project.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/project.wdf" new file mode 100644 index 00000000..a7d50312 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/project.wdf" @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3138:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6139633736656338323464323438313362346233623032663563313735613732:506172656e742050412070726f6a656374204944:00 +eof:3431268312 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/route_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/route_design.pb" new file mode 100644 index 00000000..64325ca5 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/route_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/rundef.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/rundef.js" new file mode 100644 index 00000000..d2240bc8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/rundef.js" @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Vivado/Download/Vivado/2019.2/bin;"; +} else { + PathVal = "D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Vivado/Download/Vivado/2019.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log example_6_4_2.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_6_4_2.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/runme.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/runme.bat" new file mode 100644 index 00000000..1760626b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/runme.bat" @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/runme.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/runme.sh" new file mode 100644 index 00000000..f0c9b199 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/runme.sh" @@ -0,0 +1,47 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Vivado/Download/Vivado/2019.2/bin +else + PATH=D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Vivado/Download/Vivado/2019.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log example_6_4_2.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_6_4_2.tcl -notrace + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/vivado.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/vivado.jou" new file mode 100644 index 00000000..3d95b5c1 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/vivado.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Sun Nov 16 19:47:03 2025 +# Process ID: 4024 +# Current directory: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1 +# Command line: vivado.exe -log example_6_4_2.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source example_6_4_2.tcl -notrace +# Log file: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/example_6_4_2.vdi +# Journal file: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source example_6_4_2.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/vivado.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/vivado.pb" new file mode 100644 index 00000000..b155e40f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/vivado.pb" @@ -0,0 +1,4 @@ + + + +End Record \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/write_bitstream.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/write_bitstream.pb" new file mode 100644 index 00000000..1402ce04 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/impl_1/write_bitstream.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/.Vivado_Synthesis.queue.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/.Vivado_Synthesis.queue.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/.vivado.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/.vivado.begin.rst" new file mode 100644 index 00000000..fc721e03 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/.vivado.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/.vivado.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/.vivado.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/ISEWrap.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/ISEWrap.js" new file mode 100644 index 00000000..97a2ecbc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/ISEWrap.js" @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/ISEWrap.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/ISEWrap.sh" new file mode 100644 index 00000000..f679f2e8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/ISEWrap.sh" @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/__synthesis_is_complete__" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/__synthesis_is_complete__" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2.dcp" new file mode 100644 index 00000000..b239ba00 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2.tcl" new file mode 100644 index 00000000..c3f53201 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2.tcl" @@ -0,0 +1,55 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param chipscope.maxJobs 4 +create_project -in_memory -part xc7a75tfgg484-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/wt [current_project] +set_property parent.project_path C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo c:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.v +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc +set_property used_in_implementation false [get_files C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc] + +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +synth_design -top example_6_4_2 -part xc7a75tfgg484-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef example_6_4_2.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file example_6_4_2_utilization_synth.rpt -pb example_6_4_2_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2.vds" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2.vds" new file mode 100644 index 00000000..1756b85c --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2.vds" @@ -0,0 +1,596 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Sun Nov 16 19:46:34 2025 +# Process ID: 7812 +# Current directory: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1 +# Command line: vivado.exe -log example_6_4_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_4_2.tcl +# Log file: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2.vds +# Journal file: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source example_6_4_2.tcl -notrace +Command: synth_design -top example_6_4_2 -part xc7a75tfgg484-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a75t' +INFO: [Device 21-403] Loading part xc7a75tfgg484-1 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 11996 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 851.734 ; gain = 233.473 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'example_6_4_2' [C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.v:37] +INFO: [Synth 8-6157] synthesizing module 't_flip_flop' [C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.v:16] +INFO: [Synth 8-6155] done synthesizing module 't_flip_flop' (1#1) [C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.v:16] +INFO: [Synth 8-6157] synthesizing module 'and_gate' [C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.v:6] +INFO: [Synth 8-6155] done synthesizing module 'and_gate' (2#1) [C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.v:6] +INFO: [Synth 8-6155] done synthesizing module 'example_6_4_2' (3#1) [C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.v:37] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 925.359 ; gain = 307.098 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 925.359 ; gain = 307.098 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 925.359 ; gain = 307.098 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 925.359 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------系统时钟------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:1] +WARNING: [Vivado 12-584] No ports matched 'sys_clk_50m'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_100m'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:3] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:3] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_3hz'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:4] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:4] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:7] +WARNING: [Vivado 12-584] No ports matched 'led_pin[0]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:8] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:8] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[1]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:9] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:9] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[2]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:10] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:10] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[3]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:11] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:11] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[4]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:12] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:12] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[5]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:13] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:13] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[6]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:14] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:14] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'led_pin[7]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:15] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:15] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------拨码?关sw0~sw7----------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:19] +WARNING: [Vivado 12-584] No ports matched 'sw_pin[0]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:20] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:20] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[1]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:21] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:21] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[2]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:22] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:22] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[3]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:23] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:23] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[4]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:24] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:24] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[5]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:25] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:25] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[6]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:26] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:26] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[7]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:27] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:27] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------------------9个按?--------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:31] +WARNING: [Vivado 12-584] No ports matched 'btn_0'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:32] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:32] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_1'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:33] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:33] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_2'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:34] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:34] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_3'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:35] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:35] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_4'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:36] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:36] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_5'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:37] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:37] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_6'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:38] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:38] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_7'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:39] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:39] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_8'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:40] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:40] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_0_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:43] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:43] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_1_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:44] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:44] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_2_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:45] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:45] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_3_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:46] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:46] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_4_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:47] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:47] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_5_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:48] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:48] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_6_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:49] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_7_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:50] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:50] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_8_IBUF'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:51] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:51] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------6个数码管-----------------------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:54] +WARNING: [Vivado 12-584] No ports matched 'digitron_out[0]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:55] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:55] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[1]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:56] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:56] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[2]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:57] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:57] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[3]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:58] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:58] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[4]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:59] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:59] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[5]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:60] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:60] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[6]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:61] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:61] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[7]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:62] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:62] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[0]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:64] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:64] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[1]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:65] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:65] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[2]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:66] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:66] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[3]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:67] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:67] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[0]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:69] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:69] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[1]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:70] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:70] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[2]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:71] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:71] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[3]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:72] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:72] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[0]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:74] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:74] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[1]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:75] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:75] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[2]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:76] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:76] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[3]'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:77] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:77] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------串口---------------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:81] +WARNING: [Vivado 12-584] No ports matched 'uart_rxd'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:82] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:82] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'uart_txd'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:83] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:83] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------蜂鸣?-----------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:87] +WARNING: [Vivado 12-584] No ports matched 'buzzer'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:88] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:88] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------XADC数模转换-------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:92] +WARNING: [Vivado 12-584] No ports matched 'ad15p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:93] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:93] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad15n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:94] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:94] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:95] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:95] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:96] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:96] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:97] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:97] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:98] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:98] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:99] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:99] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:100] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:100] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:101] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:101] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:102] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:102] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:103] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:103] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:104] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:104] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:105] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:105] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:106] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:106] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------DDR3L-------------------------------------' is not supported in the xdc constraint file. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:111] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:112] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:112] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:113] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:113] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_p'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:114] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:114] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_n'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:115] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:115] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq0'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:117] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:117] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq1'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:118] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:118] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq2'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:119] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:119] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq3'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:120] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:120] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq4'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:121] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:121] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq5'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:122] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:122] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq6'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:123] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:123] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq7'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:124] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:124] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq8'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:125] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:125] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq9'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:126] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:126] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq10'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:127] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:127] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq11'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:128] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:128] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq12'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:129] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:129] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq13'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:130] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:130] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq14'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:131] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:131] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq15'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:132] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:132] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a0'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:134] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:134] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a1'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:135] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:135] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a2'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:136] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:136] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a3'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:137] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:137] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a4'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:138] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:138] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a5'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:139] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:139] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a6'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:140] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a7'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:141] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a8'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:142] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a9'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:143] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a10'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:144] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a11'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:145] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a12'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:146] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba0'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:148] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba1'. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:149] +INFO: [Common 17-14] Message 'Vivado 12-584' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc:149] +Finished Parsing XDC File [C:/Users/21211/Desktop/example_6_4_2_EGO1/EGO1.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 963.168 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 969.121 ; gain = 5.953 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 969.121 ; gain = 350.859 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a75tfgg484-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 969.121 ; gain = 350.859 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 969.121 ; gain = 350.859 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 969.121 ; gain = 350.859 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 3 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module t_flip_flop +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 180 (col length:80) +BRAMs: 210 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 969.121 ; gain = 350.859 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 990.250 ; gain = 371.988 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 990.250 ; gain = 371.988 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 999.836 ; gain = 381.574 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1015.602 ; gain = 397.340 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1015.602 ; gain = 397.340 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1015.602 ; gain = 397.340 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1015.602 ; gain = 397.340 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1015.602 ; gain = 397.340 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1015.602 ; gain = 397.340 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |BUFG | 1| +|2 |LUT1 | 4| +|3 |LUT4 | 1| +|4 |FDCE | 3| +|5 |IBUF | 2| +|6 |OBUF | 4| ++------+-----+------+ + +Report Instance Areas: ++------+---------+--------------+------+ +| |Instance |Module |Cells | ++------+---------+--------------+------+ +|1 |top | | 15| +|2 | U1 |t_flip_flop | 3| +|3 | U2 |t_flip_flop_0 | 2| +|4 | U3 |t_flip_flop_1 | 2| +|5 | U4 |and_gate | 1| ++------+---------+--------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1015.602 ; gain = 397.340 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1015.602 ; gain = 353.578 +Synthesis Optimization Complete : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1015.602 ; gain = 397.340 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1015.602 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1026.875 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +16 Infos, 110 Warnings, 109 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1026.875 ; gain = 720.008 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1026.875 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file example_6_4_2_utilization_synth.rpt -pb example_6_4_2_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Sun Nov 16 19:46:56 2025... diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2_utilization_synth.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2_utilization_synth.pb" new file mode 100644 index 00000000..d72f9081 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2_utilization_synth.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2_utilization_synth.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2_utilization_synth.rpt" new file mode 100644 index 00000000..6ff93d90 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2_utilization_synth.rpt" @@ -0,0 +1,176 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Sun Nov 16 19:46:56 2025 +| Host : Mercury running 64-bit major release (build 9200) +| Command : report_utilization -file example_6_4_2_utilization_synth.rpt -pb example_6_4_2_utilization_synth.pb +| Design : example_6_4_2 +| Device : 7a75tfgg484-1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 5 | 0 | 47200 | 0.01 | +| LUT as Logic | 5 | 0 | 47200 | 0.01 | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| Slice Registers | 3 | 0 | 94400 | <0.01 | +| Register as Flip Flop | 3 | 0 | 94400 | <0.01 | +| Register as Latch | 0 | 0 | 94400 | 0.00 | +| F7 Muxes | 0 | 0 | 31700 | 0.00 | +| F8 Muxes | 0 | 0 | 15850 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 3 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 105 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 105 | 0.00 | +| RAMB18 | 0 | 0 | 210 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 180 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 6 | 0 | 285 | 2.11 | +| Bonded IPADs | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 6 | 0.00 | +| PHASER_REF | 0 | 0 | 6 | 0.00 | +| OUT_FIFO | 0 | 0 | 24 | 0.00 | +| IN_FIFO | 0 | 0 | 24 | 0.00 | +| IDELAYCTRL | 0 | 0 | 6 | 0.00 | +| IBUFDS | 0 | 0 | 274 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 24 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 24 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 300 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 0 | 0 | 6 | 0.00 | +| PLLE2_ADV | 0 | 0 | 6 | 0.00 | +| BUFMRCE | 0 | 0 | 12 | 0.00 | +| BUFHCE | 0 | 0 | 96 | 0.00 | +| BUFR | 0 | 0 | 24 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 4 | IO | +| LUT1 | 4 | LUT | +| FDCE | 3 | Flop & Latch | +| IBUF | 2 | IO | +| LUT4 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/gen_run.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/gen_run.xml" new file mode 100644 index 00000000..5bfe44e9 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/gen_run.xml" @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/htr.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/htr.txt" new file mode 100644 index 00000000..7872608f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/htr.txt" @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log example_6_4_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_4_2.tcl diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/rundef.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/rundef.js" new file mode 100644 index 00000000..c069f465 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/rundef.js" @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Vivado/Download/Vivado/2019.2/bin;"; +} else { + PathVal = "D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Vivado/Download/Vivado/2019.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log example_6_4_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_4_2.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/runme.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/runme.bat" new file mode 100644 index 00000000..1760626b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/runme.bat" @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/runme.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/runme.sh" new file mode 100644 index 00000000..4a66a84b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/runme.sh" @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Vivado/Download/Vivado/2019.2/bin +else + PATH=D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Vivado/Download/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Vivado/Download/Vivado/2019.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log example_6_4_2.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_4_2.tcl diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/vivado.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/vivado.jou" new file mode 100644 index 00000000..09b00354 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/vivado.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Sun Nov 16 19:46:34 2025 +# Process ID: 7812 +# Current directory: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1 +# Command line: vivado.exe -log example_6_4_2.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_4_2.tcl +# Log file: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/example_6_4_2.vds +# Journal file: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source example_6_4_2.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/vivado.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/vivado.pb" new file mode 100644 index 00000000..72aeae3c Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.runs/synth_1/vivado.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/compile.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/compile.bat" new file mode 100644 index 00000000..40c64d9d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/compile.bat" @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2019.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Sun Nov 16 20:37:12 +0800 2025 +REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +REM +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvlog --incr --relax -prj example_6_4_2_sim_vlog.prj" +call xvlog --incr --relax -prj example_6_4_2_sim_vlog.prj -log xvlog.log +call type xvlog.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/elaborate.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/elaborate.bat" new file mode 100644 index 00000000..0901c15f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/elaborate.bat" @@ -0,0 +1,24 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2019.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Sun Nov 16 20:37:13 +0800 2025 +REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +REM +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +echo "xelab -wto a9c76ec824d24813b4b3b02f5c175a72 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot example_6_4_2_sim_behav xil_defaultlib.example_6_4_2_sim xil_defaultlib.glbl -log elaborate.log" +call xelab -wto a9c76ec824d24813b4b3b02f5c175a72 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot example_6_4_2_sim_behav xil_defaultlib.example_6_4_2_sim xil_defaultlib.glbl -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_1_exe.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_1_exe.tcl" new file mode 100644 index 00000000..1094e45d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_1_exe.tcl" @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_1_exe_behav.wdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_1_exe_behav.wdb" new file mode 100644 index 00000000..1f9fd4de Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_1_exe_behav.wdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_1_exe_vlog.prj" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_1_exe_vlog.prj" new file mode 100644 index 00000000..491a41fe --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_1_exe_vlog.prj" @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../example_6_4_2_ACE1.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4.tcl" new file mode 100644 index 00000000..1094e45d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4.tcl" @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4_2_sim.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4_2_sim.tcl" new file mode 100644 index 00000000..1094e45d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4_2_sim.tcl" @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4_2_sim_behav.wdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4_2_sim_behav.wdb" new file mode 100644 index 00000000..d26431df Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4_2_sim_behav.wdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4_2_sim_vlog.prj" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4_2_sim_vlog.prj" new file mode 100644 index 00000000..19689c55 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4_2_sim_vlog.prj" @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../example_6_4_2_EGO1.v" \ +"../../../../example_6_4_2_sim_EGO1.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4_behav.wdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4_behav.wdb" new file mode 100644 index 00000000..37015bfa Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4_behav.wdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4_vlog.prj" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4_vlog.prj" new file mode 100644 index 00000000..481674fc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/example_6_4_vlog.prj" @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../example_6_4_2_ACE1.v" \ +"../../../../example_6_4_2_sim_ACE1.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/glbl.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/glbl.v" new file mode 100644 index 00000000..be642335 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/glbl.v" @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/simulate.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/simulate.bat" new file mode 100644 index 00000000..71dde72f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/simulate.bat" @@ -0,0 +1,24 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2019.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Sun Nov 16 19:20:09 +0800 2025 +REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +REM +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +echo "xsim example_6_4_2_sim_behav -key {Behavioral:sim_1:Functional:example_6_4_2_sim} -tclbatch example_6_4_2_sim.tcl -log simulate.log" +call xsim example_6_4_2_sim_behav -key {Behavioral:sim_1:Functional:example_6_4_2_sim} -tclbatch example_6_4_2_sim.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk.jou" new file mode 100644 index 00000000..75c83707 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Sun Nov 16 19:25:16 2025 +# Process ID: 7072 +# Current directory: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/xsim_webtalk.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk_19596.backup.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk_19596.backup.jou" new file mode 100644 index 00000000..57d0c732 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk_19596.backup.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 27 19:21:35 2023 +# Process ID: 19596 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/xsim_webtalk.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk_23508.backup.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk_23508.backup.jou" new file mode 100644 index 00000000..c55c466a --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk_23508.backup.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Sun Nov 16 19:20:07 2025 +# Process ID: 23508 +# Current directory: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/xsim_webtalk.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk_25264.backup.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk_25264.backup.jou" new file mode 100644 index 00000000..3b9a25f9 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk_25264.backup.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 27 19:22:24 2023 +# Process ID: 25264 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/xsim_webtalk.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk_31156.backup.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk_31156.backup.jou" new file mode 100644 index 00000000..4d88cd83 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk_31156.backup.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 27 19:37:24 2023 +# Process ID: 31156 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/xsim_webtalk.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk_9700.backup.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk_9700.backup.jou" new file mode 100644 index 00000000..29beb8a7 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/webtalk_9700.backup.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 27 19:32:27 2023 +# Process ID: 9700 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/xsim_webtalk.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xelab.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xelab.pb" new file mode 100644 index 00000000..1ab137d1 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xelab.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/Compile_Options.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/Compile_Options.txt" new file mode 100644 index 00000000..866c7f81 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/Compile_Options.txt" @@ -0,0 +1 @@ +-wto "a9c76ec824d24813b4b3b02f5c175a72" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "example_6_1_exe_behav" "xil_defaultlib.example_6_1_exe" "xil_defaultlib.glbl" -log "elaborate.log" diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/TempBreakPointFile.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/TempBreakPointFile.txt" new file mode 100644 index 00000000..fdbc612e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/TempBreakPointFile.txt" @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/webtalk/.xsim_webtallk.info" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/webtalk/.xsim_webtallk.info" new file mode 100644 index 00000000..27a23abb --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/webtalk/.xsim_webtallk.info" @@ -0,0 +1,5 @@ +1701083996 +1701084040 +3 +1 +a9c76ec824d24813b4b3b02f5c175a72 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/webtalk/usage_statistics_ext_xsim.html" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/webtalk/usage_statistics_ext_xsim.html" new file mode 100644 index 00000000..a96bd71f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/webtalk/usage_statistics_ext_xsim.html" @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2708876
date_generatedMon Nov 27 19:20:40 2023os_platformWIN64
product_versionXSIM v2019.2 (64-bit)project_ida9c76ec824d24813b4b3b02f5c175a72
project_iteration2random_idd24833b7-4cbd-4f74-b7c7-3cb815d77764
registration_idd24833b7-4cbd-4f74-b7c7-3cb815d77764route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_nameAMD Ryzen 9 7945HX with Radeon Graphics cpu_speed2495 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram16.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=0runtime=150 nssimulation_memory=8504_KBsimulation_time=0.03_sec
trace_waveform=true
+

+ + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/webtalk/usage_statistics_ext_xsim.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/webtalk/usage_statistics_ext_xsim.xml" new file mode 100644 index 00000000..59b7a084 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/webtalk/usage_statistics_ext_xsim.xml" @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + + +
+
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.dbg" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.dbg" new file mode 100644 index 00000000..702fa6ec Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.dbg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.mem" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.mem" new file mode 100644 index 00000000..652261d7 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.mem" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.reloc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.reloc" new file mode 100644 index 00000000..7f2a2ca5 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.reloc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.rlx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.rlx" new file mode 100644 index 00000000..ef97c20f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.rlx" @@ -0,0 +1,12 @@ + +{ + crc : 15824837919456871844 , + ccp_crc : 0 , + cmdline : " -wto a9c76ec824d24813b4b3b02f5c175a72 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot example_6_1_exe_behav xil_defaultlib.example_6_1_exe xil_defaultlib.glbl" , + buildDate : "Nov 6 2019" , + buildTime : "21:57:16" , + linkCmd : "D:\\Xilinx\\Vivado\\2019.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/example_6_1_exe_behav/xsimk.exe\" \"xsim.dir/example_6_1_exe_behav/obj/xsim_0.win64.obj\" \"xsim.dir/example_6_1_exe_behav/obj/xsim_1.win64.obj\" -L\"D:\\Xilinx\\Vivado\\2019.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.rtti" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.rtti" new file mode 100644 index 00000000..4adfd8e7 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.rtti" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.svtype" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.svtype" new file mode 100644 index 00000000..8e651271 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.svtype" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.type" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.type" new file mode 100644 index 00000000..14a09a21 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.type" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.xdbg" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.xdbg" new file mode 100644 index 00000000..2abb48ac Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsim.xdbg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsimSettings.ini" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsimSettings.ini" new file mode 100644 index 00000000..c32014cc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_1_exe_behav/xsimSettings.ini" @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPEPROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +PROTO_DATA_TYPE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/Compile_Options.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/Compile_Options.txt" new file mode 100644 index 00000000..b2acd95f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/Compile_Options.txt" @@ -0,0 +1 @@ +-wto "a9c76ec824d24813b4b3b02f5c175a72" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "example_6_4_2_sim_behav" "xil_defaultlib.example_6_4_2_sim" "xil_defaultlib.glbl" -log "elaborate.log" diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/TempBreakPointFile.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/TempBreakPointFile.txt" new file mode 100644 index 00000000..fdbc612e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/TempBreakPointFile.txt" @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/.xsim_webtallk.info" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/.xsim_webtallk.info" new file mode 100644 index 00000000..0e2d72f3 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/.xsim_webtallk.info" @@ -0,0 +1,5 @@ +1763292006 +1763292316 +27 +1 +a9c76ec824d24813b4b3b02f5c175a72 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/usage_statistics_ext_xsim.html" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/usage_statistics_ext_xsim.html" new file mode 100644 index 00000000..0144cf04 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/usage_statistics_ext_xsim.html" @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2708876
date_generatedSun Nov 16 19:25:16 2025os_platformWIN64
product_versionXSIM v2019.2 (64-bit)project_ida9c76ec824d24813b4b3b02f5c175a72
project_iteration4random_idb9e6c560-e05d-4587-a767-600a361ec29f
registration_idb9e6c560-e05d-4587-a767-600a361ec29froute_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) Ultra 5 125Hcpu_speed2995 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram25.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=0runtime=1 ussimulation_memory=9216_KBsimulation_time=0.31_sec
trace_waveform=true
+

+ + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/usage_statistics_ext_xsim.wdm" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/usage_statistics_ext_xsim.wdm" new file mode 100644 index 00000000..04105306 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/usage_statistics_ext_xsim.wdm" @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + context="xsim\\command_line_options"; + xml_map="xsim\\command_line_options"; + html_map="xsim\\command_line_options"; + html_format="UnisimStatsStyle"; + }, + { + context="xsim\\usage"; + xml_map="xsim\\usage"; + html_map="xsim\\usage"; + html_format="UnisimStatsStyle"; + } + ); + } +); + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/usage_statistics_ext_xsim.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/usage_statistics_ext_xsim.xml" new file mode 100644 index 00000000..f9fb1d9a --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/usage_statistics_ext_xsim.xml" @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + + +
+
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/xsim_webtalk.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/xsim_webtalk.tcl" new file mode 100644 index 00000000..5ea471cb --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/xsim_webtalk.tcl" @@ -0,0 +1,33 @@ +webtalk_init -webtalk_dir C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Sun Nov 16 20:41:38 2025" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2019.2 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2708876" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "b9e6c560-e05d-4587-a767-600a361ec29f" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "a9c76ec824d24813b4b3b02f5c175a72" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "26" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Windows Server 2016 or Windows 10" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) Ultra 5 125H" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2995 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "25.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key runall -value "true" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "1800000016500 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "8448_KB" -context "xsim\\usage" +webtalk_transmit -clientid 3827246232 -regid "" -xml C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.dbg" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.dbg" new file mode 100644 index 00000000..263b7778 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.dbg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.mem" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.mem" new file mode 100644 index 00000000..a457e336 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.mem" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.reloc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.reloc" new file mode 100644 index 00000000..ff6bef3d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.reloc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.rlx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.rlx" new file mode 100644 index 00000000..59c224d6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.rlx" @@ -0,0 +1,12 @@ + +{ + crc : 4850782913792688031 , + ccp_crc : 0 , + cmdline : " -wto a9c76ec824d24813b4b3b02f5c175a72 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot example_6_4_2_sim_behav xil_defaultlib.example_6_4_2_sim xil_defaultlib.glbl" , + buildDate : "Nov 6 2019" , + buildTime : "21:57:16" , + linkCmd : "D:\\Vivado\\Download\\Vivado\\2019.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/example_6_4_2_sim_behav/xsimk.exe\" \"xsim.dir/example_6_4_2_sim_behav/obj/xsim_0.win64.obj\" \"xsim.dir/example_6_4_2_sim_behav/obj/xsim_1.win64.obj\" -L\"D:\\Vivado\\Download\\Vivado\\2019.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.rtti" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.rtti" new file mode 100644 index 00000000..862565d1 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.rtti" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.svtype" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.svtype" new file mode 100644 index 00000000..c4904986 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.svtype" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.type" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.type" new file mode 100644 index 00000000..14a09a21 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.type" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.xdbg" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.xdbg" new file mode 100644 index 00000000..c2594287 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsim.xdbg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsimSettings.ini" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsimSettings.ini" new file mode 100644 index 00000000..0250ab14 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_2_sim_behav/xsimSettings.ini" @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=244 +OBJECT_NAME_COLUMN_WIDTH=193 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=166 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=193 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=166 +LOCAL_DATA_TYPEPROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +PROTO_DATA_TYPE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/Compile_Options.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/Compile_Options.txt" new file mode 100644 index 00000000..a77223c3 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/Compile_Options.txt" @@ -0,0 +1 @@ +-wto "a9c76ec824d24813b4b3b02f5c175a72" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "example_6_4_behav" "xil_defaultlib.example_6_4" "xil_defaultlib.glbl" -log "elaborate.log" diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/TempBreakPointFile.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/TempBreakPointFile.txt" new file mode 100644 index 00000000..fdbc612e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/TempBreakPointFile.txt" @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/.xsim_webtallk.info" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/.xsim_webtallk.info" new file mode 100644 index 00000000..e579d4d2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/.xsim_webtallk.info" @@ -0,0 +1,5 @@ +1701084094 +1701084143 +5 +1 +a9c76ec824d24813b4b3b02f5c175a72 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/usage_statistics_ext_xsim.html" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/usage_statistics_ext_xsim.html" new file mode 100644 index 00000000..dcfce991 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/usage_statistics_ext_xsim.html" @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2708876
date_generatedMon Nov 27 19:22:23 2023os_platformWIN64
product_versionXSIM v2019.2 (64-bit)project_ida9c76ec824d24813b4b3b02f5c175a72
project_iteration2random_idd24833b7-4cbd-4f74-b7c7-3cb815d77764
registration_idd24833b7-4cbd-4f74-b7c7-3cb815d77764route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_nameAMD Ryzen 9 7945HX with Radeon Graphics cpu_speed2495 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram16.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=0runtime=1 ussimulation_memory=8348_KBsimulation_time=0.00_sec
trace_waveform=true
+

+ + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/usage_statistics_ext_xsim.wdm" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/usage_statistics_ext_xsim.wdm" new file mode 100644 index 00000000..04105306 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/usage_statistics_ext_xsim.wdm" @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + context="xsim\\command_line_options"; + xml_map="xsim\\command_line_options"; + html_map="xsim\\command_line_options"; + html_format="UnisimStatsStyle"; + }, + { + context="xsim\\usage"; + xml_map="xsim\\usage"; + html_map="xsim\\usage"; + html_format="UnisimStatsStyle"; + } + ); + } +); + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/usage_statistics_ext_xsim.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/usage_statistics_ext_xsim.xml" new file mode 100644 index 00000000..94474bbd --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/usage_statistics_ext_xsim.xml" @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + + +
+
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/xsim_webtalk.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/xsim_webtalk.tcl" new file mode 100644 index 00000000..3d45402e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/xsim_webtalk.tcl" @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Mon Nov 27 19:32:13 2023" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2019.2 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2708876" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "d24833b7-4cbd-4f74-b7c7-3cb815d77764" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "a9c76ec824d24813b4b3b02f5c175a72" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Windows Server 2016 or Windows 10" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "AMD Ryzen 9 7945HX with Radeon Graphics " -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2495 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "150 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "8076_KB" -context "xsim\\usage" +webtalk_transmit -clientid 1655922501 -regid "" -xml D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/usage_statistics_ext_xsim.xml -html D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/usage_statistics_ext_xsim.html -wdm D:/DigitalLogic/ACE1/Test5_Design/example_6_4_2_ACE1/example_6_4_2_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.dbg" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.dbg" new file mode 100644 index 00000000..59512d49 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.dbg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.mem" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.mem" new file mode 100644 index 00000000..d9824b40 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.mem" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.reloc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.reloc" new file mode 100644 index 00000000..4fa25600 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.reloc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.rlx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.rlx" new file mode 100644 index 00000000..7966ab54 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.rlx" @@ -0,0 +1,12 @@ + +{ + crc : 12172702072006492454 , + ccp_crc : 0 , + cmdline : " -wto a9c76ec824d24813b4b3b02f5c175a72 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot example_6_4_behav xil_defaultlib.example_6_4 xil_defaultlib.glbl" , + buildDate : "Nov 6 2019" , + buildTime : "21:57:16" , + linkCmd : "D:\\Xilinx\\Vivado\\2019.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/example_6_4_behav/xsimk.exe\" \"xsim.dir/example_6_4_behav/obj/xsim_0.win64.obj\" \"xsim.dir/example_6_4_behav/obj/xsim_1.win64.obj\" -L\"D:\\Xilinx\\Vivado\\2019.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.rtti" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.rtti" new file mode 100644 index 00000000..8c9fcdd3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.rtti" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.svtype" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.svtype" new file mode 100644 index 00000000..c4904986 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.svtype" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.type" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.type" new file mode 100644 index 00000000..14a09a21 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.type" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.xdbg" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.xdbg" new file mode 100644 index 00000000..23ceed91 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsim.xdbg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsimSettings.ini" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsimSettings.ini" new file mode 100644 index 00000000..c32014cc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/example_6_4_behav/xsimSettings.ini" @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPEPROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +PROTO_DATA_TYPE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/and_gate.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/and_gate.sdb" new file mode 100644 index 00000000..e44c1421 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/and_gate.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_1_exe.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_1_exe.sdb" new file mode 100644 index 00000000..2b3a836d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_1_exe.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_4.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_4.sdb" new file mode 100644 index 00000000..907da003 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_4.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_4_2.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_4_2.sdb" new file mode 100644 index 00000000..5b74be57 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_4_2.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_4_2_sim.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_4_2_sim.sdb" new file mode 100644 index 00000000..f24d592d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_6_4_2_sim.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb" new file mode 100644 index 00000000..ba7fc272 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/jk_flip_flop.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/jk_flip_flop.sdb" new file mode 100644 index 00000000..91a1ee75 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/jk_flip_flop.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/t_flip_flop.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/t_flip_flop.sdb" new file mode 100644 index 00000000..54e427aa Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/t_flip_flop.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_example_6_4_2.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_example_6_4_2.sdb" new file mode 100644 index 00000000..fd8afec9 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_example_6_4_2.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx" new file mode 100644 index 00000000..326857ba --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx" @@ -0,0 +1,7 @@ +0.6 +2019.2 +Nov 6 2019 +21:57:16 +C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/glbl.v,1573089660,verilog,,,,glbl,,,,,,,, +C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_EGO1.v,1763295634,verilog,,C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_sim_EGO1.v,,and_gate;example_6_4_2;t_flip_flop,,,,,,,, +C:/Users/21211/Desktop/example_6_4_2_EGO1/example_6_4_2_sim_EGO1.v,1763296416,verilog,,,,example_6_4_2_sim,,,,,,,, diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.ini" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.ini" new file mode 100644 index 00000000..e8199b25 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xsim.ini" @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xvlog.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xvlog.pb" new file mode 100644 index 00000000..b155e40f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.sim/sim_1/behav/xsim/xvlog.pb" @@ -0,0 +1,4 @@ + + + +End Record \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.v" new file mode 100644 index 00000000..a5c35248 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.v" @@ -0,0 +1,55 @@ +//루xΪϵKEY1״̬y3y2y1ZΪߵ3LEDԼұߵ1LEDơ + +`timescale 1ns / 1ps + +module and_gate( + input a, + input b, + input c, + input d, + output f +); + reg y; + always @(*) //Ϊʽ + begin + y <= a & b & c & d; + end + assign f = y; +endmodule + +module t_flip_flop( + input t, + input cp, + input reset, + output q, qn +); + reg y; + always @(negedge cp or negedge reset) //Ϊʽ + begin + if (reset==0) + y <= 0; + else + case({t}) + 1: y <= ~y; // t = 1 Y=~Y + endcase + end + assign q= y; + assign qn = ~y; +endmodule + +module example_6_4_2( + input x, + input y3,y2, y1, + input reset, +// output ny3,ny2, ny1, z + + output ny1,ny2,ny3, z +); + wire ny3n,ny2n, ny1n; + + t_flip_flop U1(.t(1),.cp(x),.reset(reset),.q(ny1),.qn(ny1n)); //ṹʽ + t_flip_flop U2(.t(1),.cp(y1),.reset(reset),.q(ny2),.qn(ny2n)); //ṹʽ + t_flip_flop U3(.t(1),.cp(y2),.reset(reset),.q(ny3),.qn(ny3n)); //ṹʽ + and_gate U4(.a(x),.b(y1),.c(y2),.d(y3),.f(z)); //ṹʽ + +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.xpr" new file mode 100644 index 00000000..6371384f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_EGO1.xpr" @@ -0,0 +1,191 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_sim_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_sim_EGO1.v" new file mode 100644 index 00000000..2ee2ebac --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_2_EGO1/example_6_4_2_sim_EGO1.v" @@ -0,0 +1,43 @@ +`timescale 1ns / 1ps + +module example_6_4_2_sim(); + + reg x; + wire y3, y2, y1; // Ϊwire + reg reset; + wire z, ny3, ny2, ny1; + + // ֱӣģڲ״̬ + example_6_4_2 U( + .x(x), + .reset(reset), + .y3(ny3), // ֱ + .y2(ny2), + .y1(ny1), + .ny3(ny3), + .ny2(ny2), + .ny1(ny1), + .z(z) + ); + + // ڲ״̬ⲿ۲ + assign y3 = ny3; + assign y2 = ny2; + assign y1 = ny1; + + initial begin + #0 + x = 0; + reset = 0; + + #500 + reset = 1; + + // ʱ + repeat(16) begin + #500 x=1; + #500 x=0; + end + end + +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/EGO1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/EGO1.xdc" new file mode 100644 index 00000000..18c97a11 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/EGO1.xdc" @@ -0,0 +1,253 @@ +//----------------------------------------------系统时钟和复位------------------------------------ +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports sys_clk_in] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports sys_rst_n] + + +//-----------------------------------------------5个按键--------------------------------------------- +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports btn_4] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_0_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_2_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_3_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_4_IBUF] + + +//---------------------------------------------拨码开关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + +//------------------------------------------拨码开关(DIP开关)sw8~sw15--------------------- +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[0]}] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[1]}] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[2]}] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[3]}] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports {dip_pin[4]}] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[5]}] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[6]}] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[7]}] + + +//---------------------------------------------LED0~LED15---------------------------------------- +set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN G3 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {led_pin[8]}] +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {led_pin[9]}] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led_pin[10]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led_pin[11]}] +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {led_pin[12]}] +set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports {led_pin[13]}] +set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports {led_pin[14]}] +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {led_pin[15]}] + + +//-----------------------------------8个数码管位选信号----------------------------------------------- +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[0]}] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[1]}] +set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[2]}] +set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[3]}] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[4]}] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[5]}] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[6]}] +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[7]}] + +//--------------------------------------------数码管段选信号--------------------------------------------- +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[0]}] +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[1]}] +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[2]}] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[3]}] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[4]}] +set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[5]}] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[6]}] +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[7]}] + +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[0]}] +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[1]}] +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[2]}] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[3]}] +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[4]}] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[5]}] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[6]}] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[7]}] + + +//--------------------------------------VGA行同步场同步信号----------------------------------------------- +set_property -dict {PACKAGE_PIN D7 IOSTANDARD LVCMOS33} [get_ports vga_hs_pin] +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports vga_vs_pin] + + +//--------------------------------------VGA红绿蓝信号------------------------------------------------------ +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[0]}] +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[1]}] +set_property -dict {PACKAGE_PIN C5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[2]}] +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[3]}] +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[4]}] +set_property -dict {PACKAGE_PIN A6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[5]}] +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[6]}] +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[7]}] +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[8]}] +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[9]}] +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[10]}] +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[11]}] + + +//----------------------------------------------串口-------------------------------------------------- +set_property -dict {PACKAGE_PIN N5 IOSTANDARD LVCMOS33} [get_ports PC_Uart_rxd] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports PC_Uart_txd] + + +//---------------------------------------------------PS2接口------------------------------------- +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports ps2_clk] +set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports ps2_data] + + +//------------------------------------------------IIC接口--------------------------------------------- +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports pw_iic_scl_io] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports pw_iic_sda_io] + + +//---------------------------------------------------蓝牙--------------------------------------------- +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports BT_Uart_rxd] +set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports BT_Uart_txd] + +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[0]}] +set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[1]}] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[2]}] +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[3]}] +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[4]}] + +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports bt_mcu_int_i] + + + +//-----------------------------------------------------音频接口--------------------------------------- +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports audio_pwm_o] +set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports audio_sd_o ] + + + +//--------------------------------------------------------XADC模数转换----------------------------------- +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_n] +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_p] +set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_n] +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_p] + + +//--------------------------------------------------------DAC数模转换--------------------------- +set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports dac_ile] +set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports dac_cs_n] +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports dac_wr1_n] +set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports dac_wr2_n] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports dac_xfer_n] + +set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS33} [get_ports {dac_data[0]}] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33} [get_ports {dac_data[1]}] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports {dac_data[2]}] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports {dac_data[3]}] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {dac_data[4]}] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {dac_data[5]}] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports {dac_data[6]}] +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports {dac_data[7]}] + + + +//-------------------------------------------------SDRAM芯片接口------------------------------------- +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[18]}] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[17]}] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[16]}] +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[15]}] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {sram_addr[14]}] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[13]}] +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[12]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[11]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[10]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[9]}] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[8]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[7]}] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[6]}] +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[5]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[4]}] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[3]}] +set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[2]}] +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[1]}] +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[0]}] + +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports sram_ce_n] +set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports sram_lb_n] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports sram_oe_n] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports sram_ub_n] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports sram_we_n] + +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {sram_data[15]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {sram_data[14]}] +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {sram_data[13]}] +set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS33} [get_ports {sram_data[12]}] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {sram_data[11]}] +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {sram_data[10]}] +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {sram_data[9]}] +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {sram_data[8]}] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {sram_data[7]}] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {sram_data[6]}] +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {sram_data[5]}] +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {sram_data[4]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {sram_data[3]}] +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {sram_data[2]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {sram_data[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {sram_data[0]}] + + + + +//--------------------------------------32个pmod接口(扩展接口)------------------------------- +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {exp_io[0]}] +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports {exp_io[1]}] +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports {exp_io[2]}] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS33} [get_ports {exp_io[3]}] +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {exp_io[4]}] +set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports {exp_io[5]}] +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports {exp_io[6]}] +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {exp_io[7]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {exp_io[8]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {exp_io[9]}] +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports {exp_io[10]}] +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {exp_io[11]}] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {exp_io[12]}] +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {exp_io[13]}] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {exp_io[14]}] +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {exp_io[15]}] + +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {exp_io[16]}] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {exp_io[17]}] +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports {exp_io[18]}] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {exp_io[19]}] +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports {exp_io[20]}] +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports {exp_io[21]}] +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports {exp_io[22]}] +set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {exp_io[23]}] +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {exp_io[24]}] +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {exp_io[25]}] +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {exp_io[26]}] +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports {exp_io[27]}] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {exp_io[28]}] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {exp_io[29]}] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {exp_io[30]}] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {exp_io[31]}] + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..3c76a7e3 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,14 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:37:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:646566696e656d6f64756c65736469616c6f675f656e746974795f6e616d65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3236:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:34:00:00 +eof:3264589250 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..2176e591 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,5 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:34:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:32:00:00 +eof:3472370421 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..9b342093 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..e8877830 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,45 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.hw/example_6_4_3_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.hw/example_6_4_3_EGO1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.hw/example_6_4_3_EGO1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.ip_user_files/README.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.ip_user_files/README.txt" new file mode 100644 index 00000000..023052ca --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.ip_user_files/README.txt" @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.srcs/sim_1/new/example_6_4_3_sim_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.srcs/sim_1/new/example_6_4_3_sim_EGO1.v" new file mode 100644 index 00000000..e48dbc75 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.srcs/sim_1/new/example_6_4_3_sim_EGO1.v" @@ -0,0 +1,107 @@ +//ʾ6-4ķ +`timescale 1ns / 1ps + +module example_6_4_2_sim(); + reg y3 , y2, y1; + reg x; + wire z, ny3, ny2, ny1; + example_6_4_2 U(.x(x), .y3(y3), .y2(y2), .y1(y1), .ny3(ny3), .ny2(ny2), .ny1(ny1), .z(z)); + + initial begin + #0 + y3=0; + y2=0; + y1=0; + x=0; + + #10 + x=1; + + #5 + y3 = ny3; + y2 = ny2; + y1 = ny1; + x=0; + + #20 + x=1; + + #5 + y3 = ny3; + y2 = ny2; + y1 = ny1; + x=0; + + #30 + x=1; + + #5 + y3 = ny3; + y2 = ny2; + y1 = ny1; + x=0; + + #20 + x=1; + + #5 + y3 = ny3; + y2 = ny2; + y1 = ny1; + x=0; + + #30 + x=1; + + #5 + y3 = ny3; + y2 = ny2; + y1 = ny1; + x=0; + + #5 + y3 = ny3; + y2 = ny2; + y1 = ny1; + x=0; + + #30 + x=1; + + #5 + y3 = ny3; + y2 = ny2; + y1 = ny1; + x=0; + + #5 + y3 = ny3; + y2 = ny2; + y1 = ny1; + x=0; + + #30 + x=1; + + #5 + y3 = ny3; + y2 = ny2; + y1 = ny1; + x=0; + + #5 + y3 = ny3; + y2 = ny2; + y1 = ny1; + x=0; + + #30 + x=1; + + #5 + y3 = ny3; + y2 = ny2; + y1 = ny1; + x=0; + end +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.srcs/sources_1/new/example_6_4_3_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.srcs/sources_1/new/example_6_4_3_EGO1.v" new file mode 100644 index 00000000..ad7a87a7 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.srcs/sources_1/new/example_6_4_3_EGO1.v" @@ -0,0 +1,26 @@ +//ΪʽģΪʽʵ6.4ģ81 +//루xΪϵKEY1״̬y3y2y1ZΪߵ3LEDԼұߵ1LEDơ + +`timescale 1ns / 1ps + +module example_6_4_3( + input x, + input y3,y2, y1, + output reg ny3,ny2, ny1, z +); + + always @(negedge x) //Ϊʽ + begin + case({y3,y2, y1}) + 0: begin ny3<=0; ny2 <= 0; ny1 <= 1; z <= 0; end + 1: begin ny3<=0; ny2 <= 1; ny1 <= 0; z <= 0; end + 2: begin ny3<=0; ny2 <= 1; ny1 <= 1; z <= 0; end + 3: begin ny3<=1; ny2 <= 0; ny1 <= 0; z <= 0; end + 4: begin ny3<=1; ny2 <= 0; ny1 <= 1; z <= 0; end + 5: begin ny3<=1; ny2 <= 1; ny1 <= 0; z <= 0; end + 6: begin ny3<=1; ny2 <= 1; ny1 <= 1; z <= 0; end + 7: begin ny3<=0; ny2 <= 0; ny1 <= 0; z <= 1; end + endcase + end + +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.srcs/sources_1/new/\344\270\272example_6_4_3_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.srcs/sources_1/new/\344\270\272example_6_4_3_EGO1.v" new file mode 100644 index 00000000..8c0326eb --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.srcs/sources_1/new/\344\270\272example_6_4_3_EGO1.v" @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/11/16 20:50:48 +// Design Name: +// Module Name: example_6_4_3_EGO1 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module example_6_4_3_EGO1( + + ); +endmodule diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.xpr" new file mode 100644 index 00000000..a6d1d1e7 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_3_EGO1/example_6_4_3_EGO1.xpr" @@ -0,0 +1,192 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/EGO1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/EGO1.xdc" new file mode 100644 index 00000000..620edf74 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/EGO1.xdc" @@ -0,0 +1,199 @@ +//----------------------------------------------系统时钟------------------------------------ +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports sys_clk_50m] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports sys_clk_100m] +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports sys_clk_3hz] + + +//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------ +set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + + + +//---------------------------------------------拨码?关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + + +//-----------------------------------------------9个按?-------------------------------------- +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports btn_4] +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports btn_5] +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports btn_6] +set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports btn_7] +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports btn_8] + + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_0_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_2_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_3_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_4_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_5_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_6_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_7_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_8_IBUF] + + +//-----------------------------------6个数码管----------------------------------------------------------- +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[0]}] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[1]}] +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[2]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {digitron_out[3]}] +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS33} [get_ports {digitron_out[4]}] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[5]}] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[6]}] +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[7]}] + +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[0]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[1]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[2]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[3]}] + +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {digitron_a[0]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {digitron_a[2]}] +set_property -dict {PACKAGE_PIN AB18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[3]}] + +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33} [get_ports {digitron_b[0]}] +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[1]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[2]}] +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports {digitron_b[3]}] + + + +//----------------------------------------------串口--------------------------------------------- +set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports uart_rxd] +set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports uart_txd] + + + +//----------------------------------------------蜂鸣?----------------------------------------- +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports buzzer] + + + +//--------------------------------------------------------XADC数模转换------------------- +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports ad15p] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports ad15n] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports ad7p] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports ad7n] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports ad14p] +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports ad14n] +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports ad6p] +set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports ad6n] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports ad5p] +set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS33} [get_ports ad5n] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports ad13p] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports ad13n] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports ad4p] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports ad4n] + + + + +//--------------------------------------------------------DDR3L------------------------------------- +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_p] +set_property -dict {PACKAGE_PIN AA3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_n] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_p] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_n] + +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq0] +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq1] +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq2] +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq3] +set_property -dict {PACKAGE_PIN AA5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq4] +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq5] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq6] +set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq7] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq8] +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq9] +set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq10] +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq11] +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq12] +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq13] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq14] +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq15] + +set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a0] +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a1] +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a2] +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a3] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a4] +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a5] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a6] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a7] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a8] +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a9] +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a10] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a11] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a12] + +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba0] +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba1] +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba2] + +set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm0] +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm1] + +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports ddr3l_odt] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_p] +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_n] +set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cke] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports ddr3l_cs] +set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ras] +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports ddr3l_we] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports ddr3l_reset] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cas] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..4ae913b4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,27 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f6f725f6372656174655f636f6e73747261696e745f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f796573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3134:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7372635f7265706c6163655f66696c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f64617368626f617264:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f6f70656e5f746172676574:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f63686f6f73655f70726f6a6563745f6c6f636174696f6e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f736176655f66696c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 +eof:1795988551 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..7adfdae1 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,13 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757064617465736f7572636566696c6573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:31:00:00 +eof:359264400 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..2a7153ee --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/project.wpc" @@ -0,0 +1,4 @@ +version:1 +57656254616c6b5472616e736d697373696f6e417474656d70746564:1 +6d6f64655f636f756e7465727c4755494d6f6465:2 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/synthesis.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/synthesis.wdf" new file mode 100644 index 00000000..ee91a8e4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/synthesis.wdf" @@ -0,0 +1,39 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:786337613735746667673438342d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:6578616d706c655f365f315f657865:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313773:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313031342e3335394d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3638342e3432364d42:00:00 +eof:2369573289 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/synthesis_details.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/synthesis_details.wdf" new file mode 100644 index 00000000..78f8d66e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/synthesis_details.wdf" @@ -0,0 +1,3 @@ +version:1 +73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 +eof:2511430288 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..bb078371 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,66 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/example_6_4_ACE1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/example_6_4_ACE1.lpr" new file mode 100644 index 00000000..b7d45757 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/example_6_4_ACE1.lpr" @@ -0,0 +1,8 @@ + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/example_6_4_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/example_6_4_EGO1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/example_6_4_EGO1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/hw_1/hw.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/hw_1/hw.xml" new file mode 100644 index 00000000..a0843300 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/hw_1/hw.xml" @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/webtalk/.xsim_webtallk.info" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/webtalk/.xsim_webtallk.info" new file mode 100644 index 00000000..daacde09 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/webtalk/.xsim_webtallk.info" @@ -0,0 +1,5 @@ +1701083173 +0 +2 +0 +bc70ebd6-0436-4b91-8bdd-9d2379733a51 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/webtalk/usage_statistics_ext_labtool.html" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/webtalk/usage_statistics_ext_labtool.html" new file mode 100644 index 00000000..01844c5b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/webtalk/usage_statistics_ext_labtool.html" @@ -0,0 +1,45 @@ +Device Usage Statistics Report +

LABTOOL Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2708876
date_generatedMon Nov 27 19:06:13 2023os_platformWIN64
product_versionVivado v2019.2 (64-bit)project_idbc70ebd6-0436-4b91-8bdd-9d2379733a51
project_iteration1random_idd24833b7-4cbd-4f74-b7c7-3cb815d77764
registration_idd24833b7-4cbd-4f74-b7c7-3cb815d77764route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowlabtool

+ + + + + + + + +
user_environment
cpu_nameAMD Ryzen 9 7945HX with Radeon Graphics cpu_speed2495 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram16.000 GBtotal_processors1

+ + +
vivado_usage

+ + + +
labtool
+ + + + + +
usage
cable=XilinxA/TULA/15000000:chain=13632093pgmcnt=01:00:00
+

+ + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/webtalk/usage_statistics_ext_labtool.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/webtalk/usage_statistics_ext_labtool.xml" new file mode 100644 index 00000000..aec7deab --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.hw/webtalk/usage_statistics_ext_labtool.xml" @@ -0,0 +1,39 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+ + + +
+
+
+
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/.jobs/vrs_config_1.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/.jobs/vrs_config_1.xml" new file mode 100644 index 00000000..f901db79 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/.jobs/vrs_config_1.xml" @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.Vivado_Implementation.queue.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.Vivado_Implementation.queue.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.init_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.init_design.begin.rst" new file mode 100644 index 00000000..9e05f154 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.init_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.init_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.init_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.opt_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.opt_design.begin.rst" new file mode 100644 index 00000000..9e05f154 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.opt_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.opt_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.opt_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.phys_opt_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.phys_opt_design.begin.rst" new file mode 100644 index 00000000..9e05f154 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.phys_opt_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.phys_opt_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.phys_opt_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.place_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.place_design.begin.rst" new file mode 100644 index 00000000..9e05f154 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.place_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.place_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.place_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.route_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.route_design.begin.rst" new file mode 100644 index 00000000..9e05f154 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.route_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.route_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.route_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.vivado.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.vivado.begin.rst" new file mode 100644 index 00000000..950a3cdb --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.vivado.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.vivado.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.vivado.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.write_bitstream.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.write_bitstream.begin.rst" new file mode 100644 index 00000000..9e05f154 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.write_bitstream.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.write_bitstream.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/.write_bitstream.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/ISEWrap.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/ISEWrap.js" new file mode 100644 index 00000000..97a2ecbc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/ISEWrap.js" @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/ISEWrap.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/ISEWrap.sh" new file mode 100644 index 00000000..f679f2e8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/ISEWrap.sh" @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe.bit" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe.bit" new file mode 100644 index 00000000..f1b4409e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe.bit" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe.tcl" new file mode 100644 index 00000000..2aebe9e8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe.tcl" @@ -0,0 +1,186 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param chipscope.maxJobs 8 + create_project -in_memory -part xc7a75tfgg484-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.cache/wt [current_project] + set_property parent.project_path D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.xpr [current_project] + set_property ip_output_repo D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/synth_1/example_6_1_exe.dcp + read_xdc D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc + link_design -top example_6_1_exe -part xc7a75tfgg484-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force example_6_1_exe_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file example_6_1_exe_drc_opted.rpt -pb example_6_1_exe_drc_opted.pb -rpx example_6_1_exe_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force example_6_1_exe_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file example_6_1_exe_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file example_6_1_exe_utilization_placed.rpt -pb example_6_1_exe_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file example_6_1_exe_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step phys_opt_design +set ACTIVE_STEP phys_opt_design +set rc [catch { + create_msg_db phys_opt_design.pb + phys_opt_design + write_checkpoint -force example_6_1_exe_physopt.dcp + close_msg_db -file phys_opt_design.pb +} RESULT] +if {$rc} { + step_failed phys_opt_design + return -code error $RESULT +} else { + end_step phys_opt_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force example_6_1_exe_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file example_6_1_exe_drc_routed.rpt -pb example_6_1_exe_drc_routed.pb -rpx example_6_1_exe_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file example_6_1_exe_methodology_drc_routed.rpt -pb example_6_1_exe_methodology_drc_routed.pb -rpx example_6_1_exe_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file example_6_1_exe_power_routed.rpt -pb example_6_1_exe_power_summary_routed.pb -rpx example_6_1_exe_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file example_6_1_exe_route_status.rpt -pb example_6_1_exe_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file example_6_1_exe_timing_summary_routed.rpt -pb example_6_1_exe_timing_summary_routed.pb -rpx example_6_1_exe_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file example_6_1_exe_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file example_6_1_exe_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file example_6_1_exe_bus_skew_routed.rpt -pb example_6_1_exe_bus_skew_routed.pb -rpx example_6_1_exe_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force example_6_1_exe_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + catch { write_mem_info -force example_6_1_exe.mmi } + write_bitstream -force example_6_1_exe.bit + catch {write_debug_probes -quiet -force example_6_1_exe} + catch {file copy -force example_6_1_exe.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe.vdi" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe.vdi" new file mode 100644 index 00000000..07e9286d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe.vdi" @@ -0,0 +1,854 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 27 18:47:59 2023 +# Process ID: 22840 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/impl_1 +# Command line: vivado.exe -log example_6_1_exe.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source example_6_1_exe.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/impl_1/example_6_1_exe.vdi +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source example_6_1_exe.tcl -notrace +Command: link_design -top example_6_1_exe -part xc7a75tfgg484-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7a75tfgg484-1 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 621.715 ; gain = 0.000 +INFO: [Project 1-479] Netlist was created with Vivado 2019.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------系统时钟------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:1] +WARNING: [Vivado 12-584] No ports matched 'sys_clk_50m'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_100m'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:3] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:3] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_3hz'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:4] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:4] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:7] +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------拨码?关sw0~sw7----------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:19] +WARNING: [Vivado 12-584] No ports matched 'sw_pin[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:20] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:20] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:21] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:21] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:22] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:22] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:23] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:23] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[4]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:24] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:24] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[5]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:25] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:25] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[6]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:26] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:26] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[7]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:27] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:27] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------------------9个按?--------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:31] +WARNING: [Vivado 12-584] No ports matched 'btn_0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:32] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:32] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:34] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:34] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:35] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:35] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:36] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:36] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:37] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:37] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:38] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:38] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:39] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:39] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:40] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:40] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_0_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:43] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:43] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_2_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:45] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:45] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_3_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:46] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:46] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_4_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:47] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:47] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_5_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:48] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:48] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_6_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:49] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_7_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:50] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:50] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_8_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:51] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:51] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------6个数码管-----------------------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:54] +WARNING: [Vivado 12-584] No ports matched 'digitron_out[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:55] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:55] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:56] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:56] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:57] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:57] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:58] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:58] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[4]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:59] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:59] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[5]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:60] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:60] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[6]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:61] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:61] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[7]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:62] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:62] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:64] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:64] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:65] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:65] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:66] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:66] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:67] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:67] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:69] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:69] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:70] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:70] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:71] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:71] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:72] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:72] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:74] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:74] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:75] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:75] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:76] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:76] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:77] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:77] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------串口---------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:81] +WARNING: [Vivado 12-584] No ports matched 'uart_rxd'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:82] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:82] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'uart_txd'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:83] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:83] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------蜂鸣?-----------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:87] +WARNING: [Vivado 12-584] No ports matched 'buzzer'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:88] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:88] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------XADC数模转换-------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:92] +WARNING: [Vivado 12-584] No ports matched 'ad15p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:93] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:93] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad15n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:94] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:94] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:95] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:95] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:96] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:96] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:97] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:97] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:98] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:98] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:99] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:99] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:100] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:100] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:101] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:101] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:102] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:102] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:103] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:103] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:104] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:104] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:105] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:105] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:106] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:106] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------DDR3L-------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:111] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:112] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:112] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:113] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:113] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:114] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:114] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:115] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:115] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:117] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:117] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:118] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:118] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:119] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:119] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:120] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:120] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:121] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:121] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:122] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:122] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:123] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:123] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:124] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:124] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:125] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:125] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq9'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:126] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:126] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq10'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:127] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:127] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq11'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:128] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:128] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq12'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:129] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:129] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq13'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:130] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:130] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq14'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:131] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:131] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq15'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:132] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:132] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:134] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:134] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:135] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:135] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:136] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:136] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:137] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:137] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:138] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:138] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:139] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:139] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:140] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:140] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:141] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:141] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:142] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:142] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a9'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:143] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:143] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a10'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:144] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:144] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a11'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:145] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:145] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a12'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:146] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:146] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:148] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:148] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:149] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:149] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:150] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:150] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +INFO: [Common 17-14] Message 'Common 17-55' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:150] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:152] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:153] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_odt'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:155] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:156] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:157] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cke'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:158] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cs'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:159] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ras'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:160] +INFO: [Common 17-14] Message 'Vivado 12-584' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:160] +Finished Parsing XDC File [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 729.621 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +7 Infos, 108 Warnings, 109 Critical Warnings and 0 Errors encountered. +link_design completed successfully +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.406 . Memory (MB): peak = 754.574 ; gain = 20.910 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 25b878aab + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1276.094 ; gain = 521.520 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 25b878aab + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1468.523 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 25b878aab + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1468.523 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 25b878aab + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1468.523 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. +INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. +INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). +Phase 4 BUFG optimization | Checksum: 25b878aab + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1468.523 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 25b878aab + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1468.523 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 25b878aab + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1468.523 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1468.523 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 25b878aab + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 25b878aab + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 25b878aab + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1468.523 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 25b878aab + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1468.523 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +27 Infos, 108 Warnings, 109 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1468.523 ; gain = 734.859 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1468.523 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1468.523 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/impl_1/example_6_1_exe_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file example_6_1_exe_drc_opted.rpt -pb example_6_1_exe_drc_opted.pb -rpx example_6_1_exe_drc_opted.rpx +Command: report_drc -file example_6_1_exe_drc_opted.rpt -pb example_6_1_exe_drc_opted.pb -rpx example_6_1_exe_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/impl_1/example_6_1_exe_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1468.523 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e854ef16 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1468.523 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. + + btn_1_IBUF_inst (IBUF.O) is locked to IOB_X1Y146 + btn_1_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 +Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 9d31d158 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.407 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 133036db2 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.434 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 133036db2 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.437 . Memory (MB): peak = 1468.523 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 133036db2 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.442 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 133036db2 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.448 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Phase 2.2 Global Placement Core +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2.2 Global Placement Core | Checksum: 13e972379 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.668 . Memory (MB): peak = 1468.523 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 13e972379 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.671 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 13e972379 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.673 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 106311caa + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.677 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: ebbad192 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.682 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: ebbad192 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.683 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 2431cac08 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.787 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 2431cac08 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.788 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 2431cac08 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.789 . Memory (MB): peak = 1468.523 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 2431cac08 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.789 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 2431cac08 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.790 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 2431cac08 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.795 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 2431cac08 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.795 . Memory (MB): peak = 1468.523 ; gain = 0.000 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1468.523 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: 2b172382a + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.796 . Memory (MB): peak = 1468.523 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2b172382a + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.796 . Memory (MB): peak = 1468.523 ; gain = 0.000 +Ending Placer Task | Checksum: 1b50e08cf + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.797 . Memory (MB): peak = 1468.523 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +45 Infos, 110 Warnings, 109 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1468.523 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1479.398 ; gain = 10.875 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/impl_1/example_6_1_exe_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file example_6_1_exe_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1479.398 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file example_6_1_exe_utilization_placed.rpt -pb example_6_1_exe_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file example_6_1_exe_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1479.398 ; gain = 0.000 +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +53 Infos, 110 Warnings, 109 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1486.809 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1504.637 ; gain = 17.828 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/impl_1/example_6_1_exe_physopt.dcp' has been generated. +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. +Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. + This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. + + btn_1_IBUF_inst (IBUF.O) is locked to IOB_X1Y146 + btn_1_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: c09ee0a0 ConstDB: 0 ShapeSum: f46f282f RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 10ecf9468 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1630.066 ; gain = 113.320 +Post Restoration Checksum: NetGraph: e0c60aac NumContArr: 2e0989bc Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 10ecf9468 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1636.324 ; gain = 119.578 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 10ecf9468 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1636.324 ; gain = 119.578 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 104bb2b7b + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1642.301 ; gain = 125.555 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 5 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 5 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: b9e316a9 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1644.215 ; gain = 127.469 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 1901e4999 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1644.215 ; gain = 127.469 +Phase 4 Rip-up And Reroute | Checksum: 1901e4999 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1644.215 ; gain = 127.469 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 1901e4999 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1644.215 ; gain = 127.469 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 1901e4999 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1644.215 ; gain = 127.469 +Phase 6 Post Hold Fix | Checksum: 1901e4999 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1644.215 ; gain = 127.469 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.00295948 % + Global Horizontal Routing Utilization = 0.00404945 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 1901e4999 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1644.215 ; gain = 127.469 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 1901e4999 + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1646.277 ; gain = 129.531 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 17877cc0e + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1646.277 ; gain = 129.531 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 1646.277 ; gain = 129.531 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +63 Infos, 111 Warnings, 109 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 1646.277 ; gain = 141.641 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1646.277 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1656.160 ; gain = 9.883 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/impl_1/example_6_1_exe_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file example_6_1_exe_drc_routed.rpt -pb example_6_1_exe_drc_routed.pb -rpx example_6_1_exe_drc_routed.rpx +Command: report_drc -file example_6_1_exe_drc_routed.rpt -pb example_6_1_exe_drc_routed.pb -rpx example_6_1_exe_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/impl_1/example_6_1_exe_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file example_6_1_exe_methodology_drc_routed.rpt -pb example_6_1_exe_methodology_drc_routed.pb -rpx example_6_1_exe_methodology_drc_routed.rpx +Command: report_methodology -file example_6_1_exe_methodology_drc_routed.rpt -pb example_6_1_exe_methodology_drc_routed.pb -rpx example_6_1_exe_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/impl_1/example_6_1_exe_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file example_6_1_exe_power_routed.rpt -pb example_6_1_exe_power_summary_routed.pb -rpx example_6_1_exe_power_routed.rpx +Command: report_power -file example_6_1_exe_power_routed.rpt -pb example_6_1_exe_power_summary_routed.pb -rpx example_6_1_exe_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +75 Infos, 112 Warnings, 109 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file example_6_1_exe_route_status.rpt -pb example_6_1_exe_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file example_6_1_exe_timing_summary_routed.rpt -pb example_6_1_exe_timing_summary_routed.pb -rpx example_6_1_exe_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file example_6_1_exe_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file example_6_1_exe_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file example_6_1_exe_bus_skew_routed.rpt -pb example_6_1_exe_bus_skew_routed.pb -rpx example_6_1_exe_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force example_6_1_exe.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./example_6_1_exe.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +94 Infos, 114 Warnings, 109 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2144.906 ; gain = 457.449 +INFO: [Common 17-206] Exiting Vivado at Mon Nov 27 18:48:46 2023... diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_bus_skew_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_bus_skew_routed.pb" new file mode 100644 index 00000000..3390588d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_bus_skew_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_bus_skew_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_bus_skew_routed.rpt" new file mode 100644 index 00000000..56be555f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_bus_skew_routed.rpt" @@ -0,0 +1,15 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 18:48:37 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file example_6_1_exe_bus_skew_routed.rpt -pb example_6_1_exe_bus_skew_routed.pb -rpx example_6_1_exe_bus_skew_routed.rpx +| Design : example_6_1_exe +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Bus Skew Report + +No bus skew constraints + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_bus_skew_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_bus_skew_routed.rpx" new file mode 100644 index 00000000..f05b2e65 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_bus_skew_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_clock_utilization_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_clock_utilization_routed.rpt" new file mode 100644 index 00000000..2589e103 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_clock_utilization_routed.rpt" @@ -0,0 +1,165 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 18:48:37 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_clock_utilization -file example_6_1_exe_clock_utilization_routed.rpt +| Design : example_6_1_exe +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Local Clock Details +5. Clock Regions: Key Resource Utilization +6. Clock Regions : Global Clock Summary +7. Device Cell Placement Summary for Global Clock g0 +8. Clock Region Cell Placement per Global Clock: Region X0Y1 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 96 | 0 | 0 | 0 | +| BUFIO | 0 | 24 | 0 | 0 | 0 | +| BUFMR | 0 | 12 | 0 | 0 | 0 | +| BUFR | 0 | 24 | 0 | 0 | 0 | +| MMCM | 0 | 6 | 0 | 0 | 0 | +| PLL | 0 | 6 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+------------------------+-----------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+------------------------+-----------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 1 | 0 | | | btn_1_IBUF_BUFG_inst/O | btn_1_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+------------------------+-----------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-------------------+------------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-------------------+------------+ +| src0 | g0 | IBUF/O | IOB_X1Y146 | IOB_X1Y146 | X1Y2 | 1 | 1 | | | btn_1_IBUF_inst/O | btn_1_IBUF | ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-------------------+------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Local Clock Details +---------------------- + ++----------+-----------------+------------+-----------------+--------------+-------------+-----------------+--------------+-------+--------------+----------+ +| Local Id | Driver Type/Pin | Constraint | Site/BEL | Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++----------+-----------------+------------+-----------------+--------------+-------------+-----------------+--------------+-------+--------------+----------|| +| 0 | FDRE/Q | None | SLICE_X1Y91/AFF | X0Y1 | 1 | 3 | | | U/U1/y_reg/Q | U/U1/ny1 - Static - +| 1 | FDRE/Q | None | SLICE_X0Y89/AFF | X0Y1 | 1 | 3 | | | U/U2/y_reg/Q | U/U2/ny2 - Static - ++----------+-----------------+------------+-----------------+--------------+-------------+-----------------+--------------+-------+--------------+----------|| +* Local Clocks in this context represents only clocks driven by non-global buffers +** Clock Loads column represents the clock pin loads (pin count) +*** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +5. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1500 | 0 | 550 | 0 | 40 | 0 | 20 | 0 | 40 | +| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1350 | 0 | 500 | 0 | 30 | 0 | 15 | 0 | 40 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +6. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 1 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + +7. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------+ +| g0 | BUFG/O | n/a | | | | 1 | 0 | 0 | 0 | btn_1_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------+ +* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 1 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + +8. Clock Region Cell Placement per Global Clock: Region X0Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-----------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-----------------+ +| g0 | n/a | BUFG/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | btn_1_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-----------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells btn_1_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X1Y146 [get_ports btn_1] + +# Clock net "btn_1_IBUF_BUFG" driven by instance "btn_1_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_btn_1_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_btn_1_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="btn_1_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_btn_1_IBUF_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1} +#endgroup diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_control_sets_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_control_sets_placed.rpt" new file mode 100644 index 00000000..bdff4a06 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_control_sets_placed.rpt" @@ -0,0 +1,81 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 18:48:16 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file example_6_1_exe_control_sets_placed.rpt +| Design : example_6_1_exe +| Device : xc7a75t +-------------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Total control sets | 3 | +| Minimum number of control sets | 3 | +| Addition due to synthesis replication | 0 | +| Addition due to physical synthesis replication | 0 | +| Unused register locations in slices containing registers | 21 | ++----------------------------------------------------------+-------+ +* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers +** Run report_qor_suggestions for automated merging and remapping suggestions + + +2. Histogram +------------ + ++--------------------+-------+ +| Fanout | Count | ++--------------------+-------+ +| Total control sets | 3 | +| >= 0 to < 4 | 3 | +| >= 4 to < 6 | 0 | +| >= 6 to < 8 | 0 | +| >= 8 to < 10 | 0 | +| >= 10 to < 12 | 0 | +| >= 12 to < 14 | 0 | +| >= 14 to < 16 | 0 | +| >= 16 | 0 | ++--------------------+-------+ +* Control sets can be remapped at either synth_design or opt_design + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 3 | 3 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++------------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++------------------+---------------+------------------+------------------+----------------+ +| ~U/U2/ny2 | | | 1 | 1 | +| ~U/U1/ny1 | | | 1 | 1 | +| ~btn_1_IBUF_BUFG | | | 1 | 1 | ++------------------+---------------+------------------+------------------+----------------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_opted.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_opted.pb" new file mode 100644 index 00000000..5aa0de05 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_opted.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_opted.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_opted.rpt" new file mode 100644 index 00000000..caf43751 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_opted.rpt" @@ -0,0 +1,61 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 18:48:15 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_drc -file example_6_1_exe_drc_opted.rpt -pb example_6_1_exe_drc_opted.pb -rpx example_6_1_exe_drc_opted.rpx +| Design : example_6_1_exe +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 2 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| PLCK-12 | Warning | Clock Placer Checks | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +PLCK-12#1 Warning +Clock Placer Checks +Poor placement for routing between an IO pin and BUFG. +Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. + This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. + + btn_1_IBUF_inst (IBUF.O) is locked to C2 + btn_1_IBUF_BUFG_inst (BUFG.I) cannot be placed + +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_opted.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_opted.rpx" new file mode 100644 index 00000000..9b788b9e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_opted.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_routed.pb" new file mode 100644 index 00000000..5aa0de05 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_routed.rpt" new file mode 100644 index 00000000..36ff6692 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_routed.rpt" @@ -0,0 +1,61 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 18:48:36 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_drc -file example_6_1_exe_drc_routed.rpt -pb example_6_1_exe_drc_routed.pb -rpx example_6_1_exe_drc_routed.rpx +| Design : example_6_1_exe +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Fully Routed +--------------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 2 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| PLCK-12 | Warning | Clock Placer Checks | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +PLCK-12#1 Warning +Clock Placer Checks +Poor placement for routing between an IO pin and BUFG. +Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. + This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. + + btn_1_IBUF_inst (IBUF.O) is locked to C2 + btn_1_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 + +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_routed.rpx" new file mode 100644 index 00000000..d9abd7ba Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_drc_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_io_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_io_placed.rpt" new file mode 100644 index 00000000..e7b26b7e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_io_placed.rpt" @@ -0,0 +1,526 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 18:48:16 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_io -file example_6_1_exe_io_placed.rpt +| Design : example_6_1_exe +| Device : xc7a75t +| Speed File : -1 +| Package : fgg484 +| Package Version : FINAL 2012-11-02 +| Package Pin Delay Version : VERS. 2.0 2012-11-02 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 9 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A4 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A6 | | | MGTPTXN2_216 | Gigabit | | | | | | | | | | | | | | | | +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A8 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A10 | | | MGTPRXN2_216 | Gigabit | | | | | | | | | | | | | | | | +| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A19 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A20 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A21 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA3 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA4 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| AA8 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA9 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA10 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA11 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA13 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA14 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA15 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA16 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| AA18 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| AA19 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| AA20 | led_pin[1] | High Range | IO_L8P_T1_D11_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| AA21 | led_pin[0] | High Range | IO_L8N_T1_D12_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB2 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB3 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| AB5 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB8 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB10 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB11 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB12 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB13 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| AB15 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB16 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB17 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB20 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| AB21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| AB22 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B4 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| B5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B6 | | | MGTPTXP2_216 | Gigabit | | | | | | | | | | | | | | | | +| B7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B8 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| B9 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B10 | | | MGTPRXP2_216 | Gigabit | | | | | | | | | | | | | | | | +| B11 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B15 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B16 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B20 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| B21 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| B22 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| C1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C2 | btn_1 | High Range | IO_L2P_T0_AD12P_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | | +| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C4 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C5 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C7 | | | MGTPTXN3_216 | Gigabit | | | | | | | | | | | | | | | | +| C8 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C9 | | | MGTPRXN3_216 | Gigabit | | | | | | | | | | | | | | | | +| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C11 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| C12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| C14 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C18 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C19 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C20 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| C21 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C22 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| D2 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D5 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| D6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| D7 | | | MGTPTXP3_216 | Gigabit | | | | | | | | | | | | | | | | +| D8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D9 | | | MGTPRXP3_216 | Gigabit | | | | | | | | | | | | | | | | +| D10 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| D11 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D14 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D16 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| D17 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| D19 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D20 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D21 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D22 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E6 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | | +| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E8 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | | +| E11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E12 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E14 | | High Range | IO_L4N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E15 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| E16 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L2N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| E19 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E21 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| E22 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F6 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | | +| F7 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| F8 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | | +| F9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| F10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| F13 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F15 | | High Range | IO_0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L2P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| F19 | | High Range | IO_L18P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| F20 | | High Range | IO_L18N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| F21 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | | +| F22 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| G1 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G15 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| G16 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G19 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G20 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G21 | | High Range | IO_L24P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| G22 | | High Range | IO_L24N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| H1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H2 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| H4 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| H14 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| H17 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H19 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H20 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H22 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| J1 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J2 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J4 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J14 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J17 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J19 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J20 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J21 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J22 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| K4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K6 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K16 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| K19 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| K20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K21 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| K22 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| L6 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| L12 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| L13 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| L18 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| L19 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| L20 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| L21 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M1 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| M4 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| M5 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| M6 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| M10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| M14 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| M15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| M16 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| M17 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| M21 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| M22 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| N1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| N2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N3 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| N4 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| N12 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| N13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| N14 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| N19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| N20 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| N21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| N22 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| P1 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P2 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| P5 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| P6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P14 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| P19 | led_pin[6] | High Range | IO_L5P_T0_D06_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P20 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| P21 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| P22 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| R2 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| R6 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R13 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| R14 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| R15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| R16 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| R19 | led_pin[5] | High Range | IO_L5N_T0_D07_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R21 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| R22 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| T3 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| T13 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| T19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T20 | led_pin[4] | High Range | IO_L6N_T0_D08_VREF_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T21 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| T22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U5 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U6 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| U9 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| U10 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| U11 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| U12 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| U13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U15 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| U16 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| U19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U20 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| U21 | led_pin[7] | High Range | IO_L4N_T0_D05_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U22 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V2 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| V4 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| V7 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V12 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| V13 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V14 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| V17 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| V19 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| V20 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V22 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| W1 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W2 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| W4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W5 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W6 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W9 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| W10 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| W11 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W12 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W13 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| W14 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| W15 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| W16 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| W17 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| W20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| W21 | led_pin[3] | High Range | IO_L7P_T1_D09_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| W22 | led_pin[2] | High Range | IO_L7N_T1_D10_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| Y1 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y3 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y4 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y7 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y8 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y9 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y10 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| Y11 | | High Range | IO_L11P_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y12 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y13 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y14 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y16 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y17 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| Y19 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| Y20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| Y21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| Y22 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_methodology_drc_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_methodology_drc_routed.pb" new file mode 100644 index 00000000..f9205a9e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_methodology_drc_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_methodology_drc_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_methodology_drc_routed.rpt" new file mode 100644 index 00000000..8867dda2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_methodology_drc_routed.rpt" @@ -0,0 +1,50 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 18:48:37 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_methodology -file example_6_1_exe_methodology_drc_routed.rpt -pb example_6_1_exe_methodology_drc_routed.pb -rpx example_6_1_exe_methodology_drc_routed.rpx +| Design : example_6_1_exe +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Fully Routed +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 3 ++-----------+------------------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+------------------+-----------------------------+------------+ +| TIMING-17 | Critical Warning | Non-clocked sequential cell | 3 | ++-----------+------------------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Critical Warning +Non-clocked sequential cell +The clock pin U/U1/y_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Critical Warning +Non-clocked sequential cell +The clock pin U/U2/y_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Critical Warning +Non-clocked sequential cell +The clock pin U/U3/y_reg/C is not reached by a timing clock +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_methodology_drc_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_methodology_drc_routed.rpx" new file mode 100644 index 00000000..d5342778 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_methodology_drc_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_opt.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_opt.dcp" new file mode 100644 index 00000000..18ef92eb Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_opt.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_physopt.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_physopt.dcp" new file mode 100644 index 00000000..fc0793e1 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_physopt.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_placed.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_placed.dcp" new file mode 100644 index 00000000..990bb156 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_placed.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_power_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_power_routed.rpt" new file mode 100644 index 00000000..40c00653 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_power_routed.rpt" @@ -0,0 +1,148 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 18:48:37 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_power -file example_6_1_exe_power_routed.rpt -pb example_6_1_exe_power_summary_routed.pb -rpx example_6_1_exe_power_routed.rpx +| Design : example_6_1_exe +| Device : xc7a75tfgg484-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 18.600 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 18.390 | +| Device Static (W) | 0.210 | +| Effective TJA (C/W) | 2.7 | +| Max Ambient (C) | 35.2 | +| Junction Temperature (C) | 74.8 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.049 | 16 | --- | --- | +| LUT as Logic | 0.037 | 4 | 47200 | <0.01 | +| Register | 0.007 | 3 | 94400 | <0.01 | +| BUFG | 0.006 | 1 | 32 | 3.13 | +| Others | 0.000 | 8 | --- | --- | +| Signals | 0.119 | 6 | --- | --- | +| I/O | 18.221 | 9 | 285 | 3.16 | +| Static Power | 0.210 | | | | +| Total | 18.600 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.278 | 0.172 | 0.105 | +| Vccaux | 1.800 | 0.697 | 0.668 | 0.029 | +| Vcco33 | 3.300 | 5.160 | 5.156 | 0.004 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.003 | 0.000 | 0.003 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | High | User specified more than 25% of internal nodes | | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 2.7 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++-----------------+-----------+ +| Name | Power (W) | ++-----------------+-----------+ +| example_6_1_exe | 18.390 | +| U | 0.145 | +| U1 | 0.044 | +| U2 | 0.045 | +| U3 | 0.035 | +| U4 | 0.022 | ++-----------------+-----------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_power_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_power_routed.rpx" new file mode 100644 index 00000000..7e0677ed Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_power_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_power_summary_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_power_summary_routed.pb" new file mode 100644 index 00000000..f22f08b6 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_power_summary_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_route_status.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_route_status.pb" new file mode 100644 index 00000000..e975e2c3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_route_status.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_route_status.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_route_status.rpt" new file mode 100644 index 00000000..b9ee7fa4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_route_status.rpt" @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 20 : + # of nets not needing routing.......... : 12 : + # of internally routed nets........ : 12 : + # of routable nets..................... : 8 : + # of fully routed nets............. : 8 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_routed.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_routed.dcp" new file mode 100644 index 00000000..ae61f991 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_routed.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_timing_summary_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_timing_summary_routed.pb" new file mode 100644 index 00000000..4526e931 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_timing_summary_routed.pb" @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_timing_summary_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_timing_summary_routed.rpt" new file mode 100644 index 00000000..99e29405 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_timing_summary_routed.rpt" @@ -0,0 +1,179 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 18:48:37 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file example_6_1_exe_timing_summary_routed.rpt -pb example_6_1_exe_timing_summary_routed.pb -rpx example_6_1_exe_timing_summary_routed.rpx -warn_on_violation +| Design : example_6_1_exe +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There is 1 register/latch pin with no clock driven by root clock pin: btn_1 (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: U/U1/y_reg/Q (HIGH) + + There is 1 register/latch pin with no clock driven by root clock pin: U/U2/y_reg/Q (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 3 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 4 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_timing_summary_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_timing_summary_routed.rpx" new file mode 100644 index 00000000..9fcfebf2 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_timing_summary_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_utilization_placed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_utilization_placed.pb" new file mode 100644 index 00000000..2d6be84b Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_utilization_placed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_utilization_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_utilization_placed.rpt" new file mode 100644 index 00000000..d6c057b8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/example_6_1_exe_utilization_placed.rpt" @@ -0,0 +1,203 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 18:48:16 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_utilization -file example_6_1_exe_utilization_placed.rpt -pb example_6_1_exe_utilization_placed.pb +| Design : example_6_1_exe +| Device : 7a75tfgg484-1 +| Design State : Fully Placed +--------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 4 | 0 | 47200 | <0.01 | +| LUT as Logic | 4 | 0 | 47200 | <0.01 | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| Slice Registers | 3 | 0 | 94400 | <0.01 | +| Register as Flip Flop | 3 | 0 | 94400 | <0.01 | +| Register as Latch | 0 | 0 | 94400 | 0.00 | +| F7 Muxes | 0 | 0 | 31700 | 0.00 | +| F8 Muxes | 0 | 0 | 15850 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 3 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------------------------------------+------+-------+-----------+-------+ +| Slice | 3 | 0 | 15850 | 0.02 | +| SLICEL | 3 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 4 | 0 | 47200 | <0.01 | +| using O5 output only | 0 | | | | +| using O6 output only | 4 | | | | +| using O5 and O6 | 0 | | | | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 3 | 0 | 94400 | <0.01 | +| Register driven from within the Slice | 3 | | | | +| Register driven from outside the Slice | 0 | | | | +| Unique Control Sets | 3 | | 15850 | 0.02 | ++------------------------------------------+------+-------+-----------+-------+ +* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 105 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 105 | 0.00 | +| RAMB18 | 0 | 0 | 210 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 180 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 9 | 9 | 285 | 3.16 | +| IOB Master Pads | 4 | | | | +| IOB Slave Pads | 5 | | | | +| Bonded IPADs | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 6 | 0.00 | +| PHASER_REF | 0 | 0 | 6 | 0.00 | +| OUT_FIFO | 0 | 0 | 24 | 0.00 | +| IN_FIFO | 0 | 0 | 24 | 0.00 | +| IDELAYCTRL | 0 | 0 | 6 | 0.00 | +| IBUFDS | 0 | 0 | 274 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 24 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 24 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 300 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 0 | 0 | 6 | 0.00 | +| PLLE2_ADV | 0 | 0 | 6 | 0.00 | +| BUFMRCE | 0 | 0 | 12 | 0.00 | +| BUFHCE | 0 | 0 | 96 | 0.00 | +| BUFR | 0 | 0 | 24 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUFT | 4 | IO | +| OBUF | 4 | IO | +| LUT1 | 3 | LUT | +| FDRE | 3 | Flop & Latch | +| LUT4 | 1 | LUT | +| IBUF | 1 | IO | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/gen_run.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/gen_run.xml" new file mode 100644 index 00000000..345c561d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/gen_run.xml" @@ -0,0 +1,125 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/htr.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/htr.txt" new file mode 100644 index 00000000..3acaa945 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/htr.txt" @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log example_6_1_exe.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_6_1_exe.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/init_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/init_design.pb" new file mode 100644 index 00000000..7b9057dc Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/init_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/opt_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/opt_design.pb" new file mode 100644 index 00000000..3d192a2e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/opt_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/phys_opt_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/phys_opt_design.pb" new file mode 100644 index 00000000..745b665f Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/phys_opt_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/place_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/place_design.pb" new file mode 100644 index 00000000..0c4f5b5a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/place_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/project.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/project.wdf" new file mode 100644 index 00000000..0f2b286f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/project.wdf" @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6261663738623436323538663432613262303533346662663930393262633566:506172656e742050412070726f6a656374204944:00 +eof:3982300751 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/route_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/route_design.pb" new file mode 100644 index 00000000..a96a3dd6 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/route_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/rundef.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/rundef.js" new file mode 100644 index 00000000..b0cc5b63 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/rundef.js" @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;"; +} else { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log example_6_1_exe.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_6_1_exe.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/runme.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/runme.bat" new file mode 100644 index 00000000..1760626b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/runme.bat" @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/runme.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/runme.sh" new file mode 100644 index 00000000..423450a6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/runme.sh" @@ -0,0 +1,47 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin +else + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log example_6_1_exe.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_6_1_exe.tcl -notrace + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/usage_statistics_webtalk.html" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/usage_statistics_webtalk.html" new file mode 100644 index 00000000..bd7c14ee --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/usage_statistics_webtalk.html" @@ -0,0 +1,630 @@ +Device Usage Statistics Report +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2708876
date_generatedMon Nov 27 18:48:45 2023os_platformWIN64
product_versionVivado v2019.2 (64-bit)project_idbaf78b46258f42a2b0534fbf9092bc5f
project_iteration1random_id5098e843c55f5f60a14bf92371dc2ce7
registration_id5098e843c55f5f60a14bf92371dc2ce7route_designTRUE
target_devicexc7a75ttarget_familyartix7
target_packagefgg484target_speed-1
tool_flowVivado

+ + + + + + + + +
user_environment
cpu_nameAMD Ryzen 9 7945HX with Radeon Graphics cpu_speed2495 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram16.000 GBtotal_processors1

+ + +
vivado_usage
+ + + + + + + + + + + + + + +
gui_handlers
addsrcwizard_specify_or_create_constraint_files=1basedialog_ok=1basedialog_yes=1constraintschooserpanel_add_files=1
filesetpanel_file_set_panel_tree=4flownavigatortreepanel_flow_navigator_tree=1fpgachooser_fpga_table=2gettingstartedview_create_new_project=1
pacommandnames_add_sources=2projectnamechooser_choose_project_location=1projectnamechooser_project_name=1rdicommands_save_file=2
srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1
+ + + + + +
java_command_handlers
addsources=2newproject=1runbitgen=1
+ + + +
other_data
guimode=1
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
project_data
constraintsetcount=1core_container=falsecurrentimplrun=impl_1currentsynthesisrun=synth_1
default_library=xil_defaultlibdesignmode=RTLexport_simulation_activehdl=0export_simulation_ies=0
export_simulation_modelsim=0export_simulation_questa=0export_simulation_riviera=0export_simulation_vcs=0
export_simulation_xsim=0implstrategy=Vivado Implementation Defaultslaunch_simulation_activehdl=0launch_simulation_ies=0
launch_simulation_modelsim=0launch_simulation_questa=0launch_simulation_riviera=0launch_simulation_vcs=0
launch_simulation_xsim=0simulator_language=Mixedsrcsetcount=1synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilogtarget_simulator=XSimtotalimplruns=1totalsynthesisruns=1
+
+ + + + +
unisim_transformation
+ + + + + + + + + + + +
post_unisim_transformation
bufg=1fdre=3gnd=4ibuf=1
lut1=3lut4=1obuf=4obuft=4
vcc=4
+
+ + + + + + + + + + + +
pre_unisim_transformation
bufg=1fdre=3gnd=4ibuf=1
lut1=3lut4=1obuf=4obuft=4
vcc=4
+

+ + + +
phys_opt_design_post_place
+ + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-aggressive_hold_fix=default::[not_specified]-bram_register_opt=default::[not_specified]-clock_opt=default::[not_specified]-critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified]-directive=default::[not_specified]-dsp_register_opt=default::[not_specified]-effort_level=default::[not_specified]
-fanout_opt=default::[not_specified]-hold_fix=default::[not_specified]-insert_negative_edge_ffs=default::[not_specified]-multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified]-restruct_opt=default::[not_specified]-retime=default::[not_specified]-rewire=default::[not_specified]
-shift_register_opt=default::[not_specified]-uram_register_opt=default::[not_specified]-verbose=default::[not_specified]-vhfn=default::[not_specified]
+

+ + + + +
report_drc
+ + + + + + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-internal=default::[not_specified]-internal_only=default::[not_specified]-messages=default::[not_specified]
-name=default::[not_specified]-no_waivers=default::[not_specified]-return_string=default::[not_specified]-ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified]-waived=default::[not_specified]
+
+ + + + +
results
cfgbvs-1=1plck-12=1
+

+ + + + +
report_methodology
+ + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified]-waived=default::[not_specified]
+
+ + + +
results
timing-17=3
+

+ + + + +
report_power
+ + + + + + + + + + + + + + + + +
command_line_options
-advisory=default::[not_specified]-append=default::[not_specified]-file=[specified]-format=default::text
-hier=default::power-hierarchical_depth=default::4-l=default::[not_specified]-name=default::[not_specified]
-no_propagation=default::[not_specified]-return_string=default::[not_specified]-rpx=[specified]-verbose=default::[not_specified]
-vid=default::[not_specified]-xpe=default::[not_specified]
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
usage
airflow=250 (LFM)ambient_temp=25.0 (C)bi-dir_toggle=12.500000bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers)board_selection=medium (10"x10")confidence_level_clock_activity=Lowconfidence_level_design_state=High
confidence_level_device_models=Highconfidence_level_internal_activity=Highconfidence_level_io_activity=Lowconfidence_level_overall=Low
customer=TBDcustomer_class=TBDdevstatic=0.210238die=xc7a75tfgg484-1
dsp_output_toggle=12.500000dynamic=18.389568effective_thetaja=2.7enable_probability=0.990000
family=artix7ff_toggle=12.500000flow_state=routedheatsink=medium (Medium Profile)
i/o=18.221227input_toggle=12.500000junction_temp=74.8 (C)logic=0.049196
mgtavcc_dynamic_current=0.000000mgtavcc_static_current=0.000000mgtavcc_total_current=0.000000mgtavcc_voltage=1.000000
mgtavtt_dynamic_current=0.000000mgtavtt_static_current=0.000000mgtavtt_total_current=0.000000mgtavtt_voltage=1.200000
netlist_net_matched=NAoff-chip_power=0.000000on-chip_power=18.599806output_enable=1.000000
output_load=5.000000output_toggle=12.500000package=fgg484pct_clock_constrained=0.000000
pct_inputs_defined=0platform=nt64process=typicalram_enable=50.000000
ram_write=50.000000read_saif=Falseset/reset_probability=0.000000signal_rate=False
signals=0.119145simulation_file=Nonespeedgrade=-1static_prob=False
temp_grade=commercialthetajb=6.8 (C/W)thetasa=4.6 (C/W)toggle_rate=False
user_board_temp=25.0 (C)user_effective_thetaja=2.7user_junc_temp=74.8 (C)user_thetajb=6.8 (C/W)
user_thetasa=4.6 (C/W)vccadc_dynamic_current=0.000000vccadc_static_current=0.020000vccadc_total_current=0.020000
vccadc_voltage=1.800000vccaux_dynamic_current=0.667557vccaux_io_dynamic_current=0.000000vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000vccaux_io_voltage=1.800000vccaux_static_current=0.029476vccaux_total_current=0.697033
vccaux_voltage=1.800000vccbram_dynamic_current=0.000000vccbram_static_current=0.002557vccbram_total_current=0.002557
vccbram_voltage=1.000000vccint_dynamic_current=0.172342vccint_static_current=0.105423vccint_total_current=0.277765
vccint_voltage=1.000000vcco12_dynamic_current=0.000000vcco12_static_current=0.000000vcco12_total_current=0.000000
vcco12_voltage=1.200000vcco135_dynamic_current=0.000000vcco135_static_current=0.000000vcco135_total_current=0.000000
vcco135_voltage=1.350000vcco15_dynamic_current=0.000000vcco15_static_current=0.000000vcco15_total_current=0.000000
vcco15_voltage=1.500000vcco18_dynamic_current=0.000000vcco18_static_current=0.000000vcco18_total_current=0.000000
vcco18_voltage=1.800000vcco25_dynamic_current=0.000000vcco25_static_current=0.000000vcco25_total_current=0.000000
vcco25_voltage=2.500000vcco33_dynamic_current=5.156250vcco33_static_current=0.004000vcco33_total_current=5.160250
vcco33_voltage=3.300000version=2019.2
+

+ + + + + + + + + +
report_utilization
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
clocking
bufgctrl_available=32bufgctrl_fixed=0bufgctrl_used=1bufgctrl_util_percentage=3.13
bufhce_available=96bufhce_fixed=0bufhce_used=0bufhce_util_percentage=0.00
bufio_available=24bufio_fixed=0bufio_used=0bufio_util_percentage=0.00
bufmrce_available=12bufmrce_fixed=0bufmrce_used=0bufmrce_util_percentage=0.00
bufr_available=24bufr_fixed=0bufr_used=0bufr_util_percentage=0.00
mmcme2_adv_available=6mmcme2_adv_fixed=0mmcme2_adv_used=0mmcme2_adv_util_percentage=0.00
plle2_adv_available=6plle2_adv_fixed=0plle2_adv_used=0plle2_adv_util_percentage=0.00
+
+ + + + + + +
dsp
dsps_available=180dsps_fixed=0dsps_used=0dsps_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
io_standard
blvds_25=0diff_hstl_i=0diff_hstl_i_18=0diff_hstl_ii=0
diff_hstl_ii_18=0diff_hsul_12=0diff_mobile_ddr=0diff_sstl135=0
diff_sstl135_r=0diff_sstl15=0diff_sstl15_r=0diff_sstl18_i=0
diff_sstl18_ii=0hstl_i=0hstl_i_18=0hstl_ii=0
hstl_ii_18=0hsul_12=0lvcmos12=0lvcmos15=0
lvcmos18=0lvcmos25=0lvcmos33=1lvds_25=0
lvttl=0mini_lvds_25=0mobile_ddr=0pci33_3=0
ppds_25=0rsds_25=0sstl135=0sstl135_r=0
sstl15=0sstl15_r=0sstl18_i=0sstl18_ii=0
tmds_33=0
+
+ + + + + + + + + + + + + + +
memory
block_ram_tile_available=105block_ram_tile_fixed=0block_ram_tile_used=0block_ram_tile_util_percentage=0.00
ramb18_available=210ramb18_fixed=0ramb18_used=0ramb18_util_percentage=0.00
ramb36_fifo_available=105ramb36_fifo_fixed=0ramb36_fifo_used=0ramb36_fifo_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + +
primitives
bufg_functional_category=Clockbufg_used=1fdre_functional_category=Flop & Latchfdre_used=3
ibuf_functional_category=IOibuf_used=1lut1_functional_category=LUTlut1_used=3
lut4_functional_category=LUTlut4_used=1obuf_functional_category=IOobuf_used=4
obuft_functional_category=IOobuft_used=4
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
slice_logic
f7_muxes_available=31700f7_muxes_fixed=0f7_muxes_used=0f7_muxes_util_percentage=0.00
f8_muxes_available=15850f8_muxes_fixed=0f8_muxes_used=0f8_muxes_util_percentage=0.00
lut_as_logic_available=47200lut_as_logic_fixed=0lut_as_logic_used=4lut_as_logic_util_percentage=<0.01
lut_as_memory_available=19000lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=94400register_as_flip_flop_fixed=0register_as_flip_flop_used=3register_as_flip_flop_util_percentage=<0.01
register_as_latch_available=94400register_as_latch_fixed=0register_as_latch_used=0register_as_latch_util_percentage=0.00
slice_luts_available=47200slice_luts_fixed=0slice_luts_used=4slice_luts_util_percentage=<0.01
slice_registers_available=94400slice_registers_fixed=0slice_registers_used=3slice_registers_util_percentage=<0.01
lut_as_distributed_ram_fixed=0lut_as_distributed_ram_used=0lut_as_logic_available=47200lut_as_logic_fixed=0
lut_as_logic_used=4lut_as_logic_util_percentage=<0.01lut_as_memory_available=19000lut_as_memory_fixed=0
lut_as_memory_used=0lut_as_memory_util_percentage=0.00lut_as_shift_register_fixed=0lut_as_shift_register_used=0
register_driven_from_outside_the_slice_fixed=0register_driven_from_outside_the_slice_used=0register_driven_from_within_the_slice_fixed=0register_driven_from_within_the_slice_used=3
slice_available=15850slice_fixed=0slice_registers_available=94400slice_registers_fixed=0
slice_registers_used=3slice_registers_util_percentage=<0.01slice_used=3slice_util_percentage=0.02
slicel_fixed=0slicel_used=3slicem_fixed=0slicem_used=0
unique_control_sets_available=15850unique_control_sets_fixed=15850unique_control_sets_used=3unique_control_sets_util_percentage=0.02
using_o5_and_o6_fixed=0.02using_o5_and_o6_used=0using_o5_output_only_fixed=0using_o5_output_only_used=0
using_o6_output_only_fixed=0using_o6_output_only_used=4
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
specific_feature
bscane2_available=4bscane2_fixed=0bscane2_used=0bscane2_util_percentage=0.00
capturee2_available=1capturee2_fixed=0capturee2_used=0capturee2_util_percentage=0.00
dna_port_available=1dna_port_fixed=0dna_port_used=0dna_port_util_percentage=0.00
efuse_usr_available=1efuse_usr_fixed=0efuse_usr_used=0efuse_usr_util_percentage=0.00
frame_ecce2_available=1frame_ecce2_fixed=0frame_ecce2_used=0frame_ecce2_util_percentage=0.00
icape2_available=2icape2_fixed=0icape2_used=0icape2_util_percentage=0.00
pcie_2_1_available=1pcie_2_1_fixed=0pcie_2_1_used=0pcie_2_1_util_percentage=0.00
startupe2_available=1startupe2_fixed=0startupe2_used=0startupe2_util_percentage=0.00
xadc_available=1xadc_fixed=0xadc_used=0xadc_util_percentage=0.00
+

+ + + + +
synthesis
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-assert=default::[not_specified]-bufg=default::12-cascade_dsp=default::auto-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto-directive=default::default-fanout_limit=default::10000-flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto-gated_clock_conversion=default::off-generic=default::[not_specified]-include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified]-max_bram=default::-1-max_bram_cascade_height=default::-1-max_dsp=default::-1
-max_uram=default::-1-max_uram_cascade_height=default::-1-mode=default::default-name=default::[not_specified]
-no_lc=default::[not_specified]-no_srlextract=default::[not_specified]-no_timing_driven=default::[not_specified]-part=xc7a75tfgg484-1
-resource_sharing=default::auto-retiming=default::[not_specified]-rtl=default::[not_specified]-rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified]-seu_protect=default::none-sfcu=default::[not_specified]-shreg_min_size=default::3
-top=example_6_1_exe-verilog_define=default::[not_specified]
+
+ + + + + + +
usage
elapsed=00:00:17shls_ip=0memory_gain=684.426MBmemory_peak=1014.359MB
+

+ + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/usage_statistics_webtalk.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/usage_statistics_webtalk.xml" new file mode 100644 index 00000000..26dfe221 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/usage_statistics_webtalk.xml" @@ -0,0 +1,563 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+ + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + +
+
+ + +
+
+
+
+ + + + + + + + + + +
+
+ +
+
+
+
+ + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + +
+
+
+
+ + + + + + + + + +
+
+ + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + +
+
+ + + +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/vivado.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/vivado.jou" new file mode 100644 index 00000000..5b2cef19 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/vivado.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 27 18:47:59 2023 +# Process ID: 22840 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/impl_1 +# Command line: vivado.exe -log example_6_1_exe.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source example_6_1_exe.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/impl_1/example_6_1_exe.vdi +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source example_6_1_exe.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/vivado.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/vivado.pb" new file mode 100644 index 00000000..36c545ce Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/vivado.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/write_bitstream.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/write_bitstream.pb" new file mode 100644 index 00000000..9f5c4611 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/impl_1/write_bitstream.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/.Vivado_Synthesis.queue.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/.Vivado_Synthesis.queue.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/.Xil/example_6_1_exe_propImpl.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/.Xil/example_6_1_exe_propImpl.xdc" new file mode 100644 index 00000000..27c45191 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/.Xil/example_6_1_exe_propImpl.xdc" @@ -0,0 +1,261 @@ +set_property SRC_FILE_INFO {cfile:D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc rfile:../../../ACE1.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design] +//----------------------------------------------系统时钟------------------------------------ +set_property src_info {type:XDC file:1 line:2 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports sys_clk_50m] +set_property src_info {type:XDC file:1 line:3 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports sys_clk_100m] +set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports sys_clk_3hz] +set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] +//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------ +set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] +set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design] +//---------------------------------------------拨码?关sw0~sw7---------------------------------- +set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] +set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design] +//-----------------------------------------------9个按?-------------------------------------- +set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property src_info {type:XDC file:1 line:36 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports btn_4] +set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports btn_5] +set_property src_info {type:XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports btn_6] +set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports btn_7] +set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports btn_8] +set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_0_IBUF] +set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] +set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_2_IBUF] +set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_3_IBUF] +set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_4_IBUF] +set_property src_info {type:XDC file:1 line:48 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_5_IBUF] +set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_6_IBUF] +set_property src_info {type:XDC file:1 line:50 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_7_IBUF] +set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_8_IBUF] +set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design] +//-----------------------------------6个数码管----------------------------------------------------------- +set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[0]}] +set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[1]}] +set_property src_info {type:XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[2]}] +set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {digitron_out[3]}] +set_property src_info {type:XDC file:1 line:59 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS33} [get_ports {digitron_out[4]}] +set_property src_info {type:XDC file:1 line:60 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[5]}] +set_property src_info {type:XDC file:1 line:61 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[6]}] +set_property src_info {type:XDC file:1 line:62 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[7]}] +set_property src_info {type:XDC file:1 line:64 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[0]}] +set_property src_info {type:XDC file:1 line:65 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[1]}] +set_property src_info {type:XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[2]}] +set_property src_info {type:XDC file:1 line:67 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[3]}] +set_property src_info {type:XDC file:1 line:69 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {digitron_a[0]}] +set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[1]}] +set_property src_info {type:XDC file:1 line:71 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {digitron_a[2]}] +set_property src_info {type:XDC file:1 line:72 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[3]}] +set_property src_info {type:XDC file:1 line:74 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33} [get_ports {digitron_b[0]}] +set_property src_info {type:XDC file:1 line:75 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[1]}] +set_property src_info {type:XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[2]}] +set_property src_info {type:XDC file:1 line:77 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports {digitron_b[3]}] +set_property src_info {type:XDC file:1 line:81 export:INPUT save:INPUT read:READ} [current_design] +//----------------------------------------------串口--------------------------------------------- +set_property src_info {type:XDC file:1 line:82 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports uart_rxd] +set_property src_info {type:XDC file:1 line:83 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports uart_txd] +set_property src_info {type:XDC file:1 line:87 export:INPUT save:INPUT read:READ} [current_design] +//----------------------------------------------蜂鸣?----------------------------------------- +set_property src_info {type:XDC file:1 line:88 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports buzzer] +set_property src_info {type:XDC file:1 line:92 export:INPUT save:INPUT read:READ} [current_design] +//--------------------------------------------------------XADC数模转换------------------- +set_property src_info {type:XDC file:1 line:93 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports ad15p] +set_property src_info {type:XDC file:1 line:94 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports ad15n] +set_property src_info {type:XDC file:1 line:95 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports ad7p] +set_property src_info {type:XDC file:1 line:96 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports ad7n] +set_property src_info {type:XDC file:1 line:97 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports ad14p] +set_property src_info {type:XDC file:1 line:98 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports ad14n] +set_property src_info {type:XDC file:1 line:99 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports ad6p] +set_property src_info {type:XDC file:1 line:100 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports ad6n] +set_property src_info {type:XDC file:1 line:101 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports ad5p] +set_property src_info {type:XDC file:1 line:102 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS33} [get_ports ad5n] +set_property src_info {type:XDC file:1 line:103 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports ad13p] +set_property src_info {type:XDC file:1 line:104 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports ad13n] +set_property src_info {type:XDC file:1 line:105 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports ad4p] +set_property src_info {type:XDC file:1 line:106 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports ad4n] +set_property src_info {type:XDC file:1 line:111 export:INPUT save:INPUT read:READ} [current_design] +//--------------------------------------------------------DDR3L------------------------------------- +set_property src_info {type:XDC file:1 line:112 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_p] +set_property src_info {type:XDC file:1 line:113 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_n] +set_property src_info {type:XDC file:1 line:114 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_p] +set_property src_info {type:XDC file:1 line:115 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_n] +set_property src_info {type:XDC file:1 line:117 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq0] +set_property src_info {type:XDC file:1 line:118 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq1] +set_property src_info {type:XDC file:1 line:119 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq2] +set_property src_info {type:XDC file:1 line:120 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq3] +set_property src_info {type:XDC file:1 line:121 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq4] +set_property src_info {type:XDC file:1 line:122 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq5] +set_property src_info {type:XDC file:1 line:123 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq6] +set_property src_info {type:XDC file:1 line:124 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq7] +set_property src_info {type:XDC file:1 line:125 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq8] +set_property src_info {type:XDC file:1 line:126 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq9] +set_property src_info {type:XDC file:1 line:127 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq10] +set_property src_info {type:XDC file:1 line:128 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq11] +set_property src_info {type:XDC file:1 line:129 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq12] +set_property src_info {type:XDC file:1 line:130 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq13] +set_property src_info {type:XDC file:1 line:131 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq14] +set_property src_info {type:XDC file:1 line:132 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq15] +set_property src_info {type:XDC file:1 line:134 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a0] +set_property src_info {type:XDC file:1 line:135 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a1] +set_property src_info {type:XDC file:1 line:136 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a2] +set_property src_info {type:XDC file:1 line:137 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a3] +set_property src_info {type:XDC file:1 line:138 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a4] +set_property src_info {type:XDC file:1 line:139 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a5] +set_property src_info {type:XDC file:1 line:140 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a6] +set_property src_info {type:XDC file:1 line:141 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a7] +set_property src_info {type:XDC file:1 line:142 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a8] +set_property src_info {type:XDC file:1 line:143 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a9] +set_property src_info {type:XDC file:1 line:144 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a10] +set_property src_info {type:XDC file:1 line:145 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a11] +set_property src_info {type:XDC file:1 line:146 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a12] +set_property src_info {type:XDC file:1 line:148 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba0] +set_property src_info {type:XDC file:1 line:149 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba1] +set_property src_info {type:XDC file:1 line:150 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba2] +set_property src_info {type:XDC file:1 line:152 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm0] +set_property src_info {type:XDC file:1 line:153 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm1] +set_property src_info {type:XDC file:1 line:155 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports ddr3l_odt] +set_property src_info {type:XDC file:1 line:156 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_p] +set_property src_info {type:XDC file:1 line:157 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_n] +set_property src_info {type:XDC file:1 line:158 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cke] +set_property src_info {type:XDC file:1 line:159 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports ddr3l_cs] +set_property src_info {type:XDC file:1 line:160 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ras] +set_property src_info {type:XDC file:1 line:161 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports ddr3l_we] +set_property src_info {type:XDC file:1 line:162 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports ddr3l_reset] +set_property src_info {type:XDC file:1 line:163 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cas] diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/.vivado.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/.vivado.begin.rst" new file mode 100644 index 00000000..20f650e1 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/.vivado.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/.vivado.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/.vivado.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/ISEWrap.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/ISEWrap.js" new file mode 100644 index 00000000..97a2ecbc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/ISEWrap.js" @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/ISEWrap.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/ISEWrap.sh" new file mode 100644 index 00000000..f679f2e8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/ISEWrap.sh" @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/__synthesis_is_complete__" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/__synthesis_is_complete__" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/example_6_1_exe.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/example_6_1_exe.dcp" new file mode 100644 index 00000000..60d5f002 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/example_6_1_exe.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/example_6_1_exe.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/example_6_1_exe.tcl" new file mode 100644 index 00000000..91886bdd --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/example_6_1_exe.tcl" @@ -0,0 +1,54 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +create_project -in_memory -part xc7a75tfgg484-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.cache/wt [current_project] +set_property parent.project_path D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo d:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.v +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc +set_property used_in_implementation false [get_files D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc] + +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +synth_design -top example_6_1_exe -part xc7a75tfgg484-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef example_6_1_exe.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file example_6_1_exe_utilization_synth.rpt -pb example_6_1_exe_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/example_6_1_exe.vds" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/example_6_1_exe.vds" new file mode 100644 index 00000000..b18d9104 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/example_6_1_exe.vds" @@ -0,0 +1,609 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 27 18:47:32 2023 +# Process ID: 19780 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/synth_1 +# Command line: vivado.exe -log example_6_1_exe.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_1_exe.tcl +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/synth_1/example_6_1_exe.vds +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source example_6_1_exe.tcl -notrace +Command: synth_design -top example_6_1_exe -part xc7a75tfgg484-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a75t' +INFO: [Device 21-403] Loading part xc7a75tfgg484-1 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 19400 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 852.434 ; gain = 234.930 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'example_6_1_exe' [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.v:51] +INFO: [Synth 8-6157] synthesizing module 'example_6_4' [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.v:37] +INFO: [Synth 8-6157] synthesizing module 'jk_flip_flop' [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.v:21] +INFO: [Synth 8-155] case statement is not full and has no default [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.v:29] +INFO: [Synth 8-6155] done synthesizing module 'jk_flip_flop' (1#1) [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.v:21] +INFO: [Synth 8-6157] synthesizing module 'and_gate' [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.v:6] +INFO: [Synth 8-6155] done synthesizing module 'and_gate' (2#1) [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.v:6] +INFO: [Synth 8-6155] done synthesizing module 'example_6_4' (3#1) [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.v:37] +INFO: [Synth 8-6155] done synthesizing module 'example_6_1_exe' (4#1) [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.v:51] +WARNING: [Synth 8-3331] design example_6_1_exe has unconnected port led_pin[4] +WARNING: [Synth 8-3331] design example_6_1_exe has unconnected port led_pin[3] +WARNING: [Synth 8-3331] design example_6_1_exe has unconnected port led_pin[2] +WARNING: [Synth 8-3331] design example_6_1_exe has unconnected port led_pin[1] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 924.773 ; gain = 307.270 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 924.773 ; gain = 307.270 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 924.773 ; gain = 307.270 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 924.773 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------系统时钟------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:1] +WARNING: [Vivado 12-584] No ports matched 'sys_clk_50m'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_100m'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:3] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:3] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_3hz'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:4] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:4] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:7] +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------拨码?关sw0~sw7----------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:19] +WARNING: [Vivado 12-584] No ports matched 'sw_pin[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:20] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:20] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:21] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:21] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:22] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:22] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:23] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:23] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[4]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:24] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:24] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[5]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:25] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:25] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[6]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:26] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:26] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sw_pin[7]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:27] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:27] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------------------9个按?--------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:31] +WARNING: [Vivado 12-584] No ports matched 'btn_0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:32] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:32] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:34] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:34] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:35] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:35] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:36] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:36] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:37] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:37] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:38] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:38] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:39] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:39] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:40] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:40] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_0_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:43] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:43] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_1_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:44] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:44] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_2_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:45] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:45] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_3_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:46] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:46] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_4_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:47] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:47] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_5_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:48] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:48] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_6_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:49] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_7_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:50] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:50] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_8_IBUF'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:51] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:51] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------6个数码管-----------------------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:54] +WARNING: [Vivado 12-584] No ports matched 'digitron_out[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:55] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:55] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:56] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:56] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:57] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:57] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:58] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:58] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[4]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:59] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:59] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[5]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:60] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:60] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[6]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:61] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:61] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[7]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:62] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:62] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:64] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:64] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:65] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:65] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:66] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:66] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:67] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:67] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:69] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:69] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:70] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:70] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:71] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:71] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:72] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:72] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[0]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:74] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:74] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[1]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:75] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:75] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[2]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:76] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:76] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[3]'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:77] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:77] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------串口---------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:81] +WARNING: [Vivado 12-584] No ports matched 'uart_rxd'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:82] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:82] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'uart_txd'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:83] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:83] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------蜂鸣?-----------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:87] +WARNING: [Vivado 12-584] No ports matched 'buzzer'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:88] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:88] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------XADC数模转换-------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:92] +WARNING: [Vivado 12-584] No ports matched 'ad15p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:93] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:93] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad15n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:94] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:94] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:95] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:95] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:96] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:96] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:97] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:97] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:98] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:98] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:99] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:99] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:100] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:100] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:101] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:101] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:102] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:102] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:103] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:103] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:104] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:104] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:105] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:105] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:106] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:106] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------DDR3L-------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:111] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:112] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:112] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:113] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:113] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:114] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:114] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:115] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:115] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:117] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:117] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:118] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:118] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:119] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:119] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:120] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:120] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:121] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:121] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:122] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:122] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:123] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:123] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:124] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:124] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:125] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:125] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq9'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:126] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:126] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq10'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:127] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:127] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq11'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:128] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:128] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq12'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:129] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:129] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq13'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:130] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:130] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq14'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:131] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:131] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq15'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:132] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:132] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:134] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:134] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:135] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:135] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:136] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:136] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a3'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:137] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:137] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a4'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:138] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:138] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a5'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:139] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:139] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a6'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:140] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:140] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a7'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:141] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:141] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a8'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:142] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:142] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a9'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:143] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:143] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a10'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:144] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:144] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a11'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:145] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:145] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a12'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:146] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:146] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:148] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:148] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:149] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:149] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba2'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:150] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm0'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:152] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm1'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:153] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_odt'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:155] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_p'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:156] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_n'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:157] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cke'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:158] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cs'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:159] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ras'. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:160] +INFO: [Common 17-14] Message 'Vivado 12-584' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc:160] +Finished Parsing XDC File [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/ACE1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/example_6_1_exe_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/example_6_1_exe_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 962.434 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 962.434 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 962.434 ; gain = 344.930 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a75tfgg484-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 962.434 ; gain = 344.930 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 962.434 ; gain = 344.930 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 962.434 ; gain = 344.930 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 3 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module jk_flip_flop +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 180 (col length:80) +BRAMs: 210 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3331] design example_6_1_exe has unconnected port led_pin[4] +WARNING: [Synth 8-3331] design example_6_1_exe has unconnected port led_pin[3] +WARNING: [Synth 8-3331] design example_6_1_exe has unconnected port led_pin[2] +WARNING: [Synth 8-3331] design example_6_1_exe has unconnected port led_pin[1] +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 962.434 ; gain = 344.930 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 989.012 ; gain = 371.508 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 989.012 ; gain = 371.508 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 998.594 ; gain = 381.090 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1014.359 ; gain = 396.855 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1014.359 ; gain = 396.855 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1014.359 ; gain = 396.855 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1014.359 ; gain = 396.855 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1014.359 ; gain = 396.855 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1014.359 ; gain = 396.855 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |BUFG | 1| +|2 |LUT1 | 3| +|3 |LUT4 | 1| +|4 |FDRE | 3| +|5 |IBUF | 1| +|6 |OBUF | 4| +|7 |OBUFT | 4| ++------+------+------+ + +Report Instance Areas: ++------+---------+---------------+------+ +| |Instance |Module |Cells | ++------+---------+---------------+------+ +|1 |top | | 17| +|2 | U |example_6_4 | 7| +|3 | U1 |jk_flip_flop | 2| +|4 | U2 |jk_flip_flop_0 | 2| +|5 | U3 |jk_flip_flop_1 | 2| +|6 | U4 |and_gate | 1| ++------+---------+---------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1014.359 ; gain = 396.855 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 4 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1014.359 ; gain = 359.195 +Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1014.359 ; gain = 396.855 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1026.344 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1032.355 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +20 Infos, 117 Warnings, 109 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1032.355 ; gain = 727.297 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1032.355 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/synth_1/example_6_1_exe.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file example_6_1_exe_utilization_synth.rpt -pb example_6_1_exe_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Mon Nov 27 18:47:53 2023... diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/example_6_1_exe_utilization_synth.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/example_6_1_exe_utilization_synth.pb" new file mode 100644 index 00000000..2d6be84b Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/example_6_1_exe_utilization_synth.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/example_6_1_exe_utilization_synth.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/example_6_1_exe_utilization_synth.rpt" new file mode 100644 index 00000000..7d84fed6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/example_6_1_exe_utilization_synth.rpt" @@ -0,0 +1,177 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 27 18:47:53 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_utilization -file example_6_1_exe_utilization_synth.rpt -pb example_6_1_exe_utilization_synth.pb +| Design : example_6_1_exe +| Device : 7a75tfgg484-1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 4 | 0 | 47200 | <0.01 | +| LUT as Logic | 4 | 0 | 47200 | <0.01 | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| Slice Registers | 3 | 0 | 94400 | <0.01 | +| Register as Flip Flop | 3 | 0 | 94400 | <0.01 | +| Register as Latch | 0 | 0 | 94400 | 0.00 | +| F7 Muxes | 0 | 0 | 31700 | 0.00 | +| F8 Muxes | 0 | 0 | 15850 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 3 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 105 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 105 | 0.00 | +| RAMB18 | 0 | 0 | 210 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 180 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 9 | 0 | 285 | 3.16 | +| Bonded IPADs | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 6 | 0.00 | +| PHASER_REF | 0 | 0 | 6 | 0.00 | +| OUT_FIFO | 0 | 0 | 24 | 0.00 | +| IN_FIFO | 0 | 0 | 24 | 0.00 | +| IDELAYCTRL | 0 | 0 | 6 | 0.00 | +| IBUFDS | 0 | 0 | 274 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 24 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 24 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 300 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 0 | 0 | 6 | 0.00 | +| PLLE2_ADV | 0 | 0 | 6 | 0.00 | +| BUFMRCE | 0 | 0 | 12 | 0.00 | +| BUFHCE | 0 | 0 | 96 | 0.00 | +| BUFR | 0 | 0 | 24 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUFT | 4 | IO | +| OBUF | 4 | IO | +| LUT1 | 3 | LUT | +| FDRE | 3 | Flop & Latch | +| LUT4 | 1 | LUT | +| IBUF | 1 | IO | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/gen_run.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/gen_run.xml" new file mode 100644 index 00000000..3cab2465 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/gen_run.xml" @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/htr.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/htr.txt" new file mode 100644 index 00000000..fe1f1254 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/htr.txt" @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log example_6_1_exe.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_1_exe.tcl diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/rundef.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/rundef.js" new file mode 100644 index 00000000..89bdc290 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/rundef.js" @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;"; +} else { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log example_6_1_exe.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_1_exe.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/runme.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/runme.bat" new file mode 100644 index 00000000..1760626b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/runme.bat" @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/runme.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/runme.sh" new file mode 100644 index 00000000..23f740c4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/runme.sh" @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin +else + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log example_6_1_exe.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_1_exe.tcl diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/vivado.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/vivado.jou" new file mode 100644 index 00000000..0b69928e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/vivado.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 27 18:47:32 2023 +# Process ID: 19780 +# Current directory: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/synth_1 +# Command line: vivado.exe -log example_6_1_exe.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_6_1_exe.tcl +# Log file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/synth_1/example_6_1_exe.vds +# Journal file: D:/DigitalLogic/ACE1/Test5_Design/example_6_4_ACE1/example_6_4_ACE1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source example_6_1_exe.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/vivado.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/vivado.pb" new file mode 100644 index 00000000..1f0b4eaa Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.runs/synth_1/vivado.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.v" new file mode 100644 index 00000000..a3941c5d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.v" @@ -0,0 +1,68 @@ +//ṹʽģΪʽʵ6.4ģ81 +//루xΪϵKEY1״̬y3y2y1ZΪߵ3LEDԼұߵ1LEDơ + +`timescale 1ns / 1ps + +module and_gate( + input a, + input b, + input c, + input d, + output f +); + reg y; + always @(*) //Ϊʽ + begin + y <= a & b & c & d; + end + assign f = y; +endmodule + +module t_flip_flop( + input t, + input cp, + output q, qn +); + reg y; + always @(negedge cp) //Ϊʽ + begin + case({t}) + 1: y <= ~y; // t = 1 Y=~Y + endcase + end + assign q= y; + assign qn = ~y; +endmodule + +module example_6_4( + input x, + input y3,y2, y1, + output ny3,ny2, ny1, z +); + wire ny3n,ny2n, ny1n; + + t_flip_flop U1(.t(1),.cp(x),.q(ny1),.qn(ny1n)); //ṹʽ + t_flip_flop U2(.t(1),.cp(y1),.q(ny2),.qn(ny2n)); //ṹʽ + t_flip_flop U3(.t(1),.cp(y2),.q(ny3),.qn(ny3n)); //ṹʽ + and_gate U4(.a(x),.b(y1),.c(y2),.d(y3),.f(z)); //ṹʽ + +endmodule + +module example_6_1_exe( + input btn_1, //KEY1ť + output [7:0] led_pin //8led +); + reg y3, y2, y1; + example_6_4 U(.x(btn_1),.y3(y3), .y2(y2), .y1(y1),.ny3(led_pin[7]), .ny2(led_pin[6]), .ny1(led_pin[5]), .z(led_pin[0])); + initial begin + y3=0; + y2=0; + y1=0; + end + always @(*) //Ϊʽ + begin + y3 <= led_pin[7]; + y2 <= led_pin[6]; + y1 <= led_pin[5]; + end +endmodule diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.xpr" new file mode 100644 index 00000000..6460113d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/example_6_4_EGO1/example_6_4_EGO1.xpr" @@ -0,0 +1,184 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/\347\254\2545\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/\347\254\2545\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" new file mode 100644 index 00000000..a2c29d72 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/\347\254\2545\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:69c853c30368e526b7d964c6ba3015ddb294485afc2ad3a9ff96e2fa471b37b8 +size 3537935 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/\347\254\2546\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260.circ" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/\347\254\2546\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260.circ" new file mode 100644 index 00000000..49a75e86 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\344\272\224/\347\254\2546\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260.circ" @@ -0,0 +1,2652 @@ + + +This file is intended to be loaded by Logisim http://logisim.altervista.org + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + addr/data: 8 8 +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1.v" new file mode 100644 index 00000000..4ed3028d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1.v" @@ -0,0 +1,20 @@ + +`timescale 1ns / 1ps + +module ttl74153( + input [7:0] sw_pin, //8 + output [15:0] led_pin +); + reg y; + always @(*) //Ϊʽ + begin + case({sw_pin[0],sw_pin[1],sw_pin[2]}) + 0: y <= sw_pin[7]; + 1: y <= sw_pin[6]; + 2: y <= sw_pin[5]; + 3: y <= sw_pin[4]; + default: y <= 0; // ߵ4ȫ + endcase + end + assign led_pin[0]=y; + endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..70f01b5d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,11 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f63686f6f73655f70726f6a6563745f6c6f636174696f6e:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 +eof:3470976879 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..37728e9e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,4 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +eof:2411667182 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..9b342093 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..3899c8c3 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,41 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.hw/74153_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.hw/74153_EGO1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.hw/74153_EGO1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.xpr" new file mode 100644 index 00000000..f342e876 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/74153_EGO1/74153_EGO1.xpr" @@ -0,0 +1,185 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/EGO1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/EGO1.xdc" new file mode 100644 index 00000000..18c97a11 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/EGO1.xdc" @@ -0,0 +1,253 @@ +//----------------------------------------------系统时钟和复位------------------------------------ +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports sys_clk_in] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports sys_rst_n] + + +//-----------------------------------------------5个按键--------------------------------------------- +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports btn_4] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_0_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_2_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_3_IBUF] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_4_IBUF] + + +//---------------------------------------------拨码开关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + +//------------------------------------------拨码开关(DIP开关)sw8~sw15--------------------- +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[0]}] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[1]}] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {dip_pin[2]}] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[3]}] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports {dip_pin[4]}] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[5]}] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {dip_pin[6]}] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dip_pin[7]}] + + +//---------------------------------------------LED0~LED15---------------------------------------- +set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN G3 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {led_pin[8]}] +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {led_pin[9]}] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led_pin[10]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led_pin[11]}] +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {led_pin[12]}] +set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports {led_pin[13]}] +set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports {led_pin[14]}] +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {led_pin[15]}] + + +//-----------------------------------8个数码管位选信号----------------------------------------------- +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[0]}] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[1]}] +set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[2]}] +set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[3]}] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[4]}] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[5]}] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[6]}] +set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports {seg_cs_pin[7]}] + +//--------------------------------------------数码管段选信号--------------------------------------------- +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[0]}] +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[1]}] +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[2]}] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[3]}] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[4]}] +set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[5]}] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[6]}] +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports {seg_data_0_pin[7]}] + +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[0]}] +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[1]}] +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[2]}] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[3]}] +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[4]}] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[5]}] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[6]}] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports {seg_data_1_pin[7]}] + + +//--------------------------------------VGA行同步场同步信号----------------------------------------------- +set_property -dict {PACKAGE_PIN D7 IOSTANDARD LVCMOS33} [get_ports vga_hs_pin] +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports vga_vs_pin] + + +//--------------------------------------VGA红绿蓝信号------------------------------------------------------ +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[0]}] +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[1]}] +set_property -dict {PACKAGE_PIN C5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[2]}] +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[3]}] +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[4]}] +set_property -dict {PACKAGE_PIN A6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[5]}] +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[6]}] +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[7]}] +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[8]}] +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[9]}] +set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[10]}] +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS33} [get_ports {vga_data_pin[11]}] + + +//----------------------------------------------串口-------------------------------------------------- +set_property -dict {PACKAGE_PIN N5 IOSTANDARD LVCMOS33} [get_ports PC_Uart_rxd] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports PC_Uart_txd] + + +//---------------------------------------------------PS2接口------------------------------------- +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports ps2_clk] +set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports ps2_data] + + +//------------------------------------------------IIC接口--------------------------------------------- +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports pw_iic_scl_io] +set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS33} [get_ports pw_iic_sda_io] + + +//---------------------------------------------------蓝牙--------------------------------------------- +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports BT_Uart_rxd] +set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports BT_Uart_txd] + +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[0]}] +set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[1]}] +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[2]}] +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[3]}] +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {bt_ctrl_o[4]}] + +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports bt_mcu_int_i] + + + +//-----------------------------------------------------音频接口--------------------------------------- +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports audio_pwm_o] +set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports audio_sd_o ] + + + +//--------------------------------------------------------XADC模数转换----------------------------------- +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_n] +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports XADC_AUX_v_p] +set_property -dict {PACKAGE_PIN K9 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_n] +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports XADC_VP_VN_v_p] + + +//--------------------------------------------------------DAC数模转换--------------------------- +set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports dac_ile] +set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports dac_cs_n] +set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports dac_wr1_n] +set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports dac_wr2_n] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports dac_xfer_n] + +set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS33} [get_ports {dac_data[0]}] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33} [get_ports {dac_data[1]}] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports {dac_data[2]}] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports {dac_data[3]}] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {dac_data[4]}] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {dac_data[5]}] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports {dac_data[6]}] +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports {dac_data[7]}] + + + +//-------------------------------------------------SDRAM芯片接口------------------------------------- +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[18]}] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[17]}] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[16]}] +set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[15]}] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {sram_addr[14]}] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[13]}] +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {sram_addr[12]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[11]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[10]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[9]}] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[8]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[7]}] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {sram_addr[6]}] +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[5]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {sram_addr[4]}] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[3]}] +set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {sram_addr[2]}] +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {sram_addr[1]}] +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {sram_addr[0]}] + +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports sram_ce_n] +set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports sram_lb_n] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports sram_oe_n] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports sram_ub_n] +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports sram_we_n] + +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {sram_data[15]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {sram_data[14]}] +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {sram_data[13]}] +set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS33} [get_ports {sram_data[12]}] +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {sram_data[11]}] +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {sram_data[10]}] +set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {sram_data[9]}] +set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {sram_data[8]}] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {sram_data[7]}] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {sram_data[6]}] +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {sram_data[5]}] +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {sram_data[4]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {sram_data[3]}] +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {sram_data[2]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {sram_data[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {sram_data[0]}] + + + + +//--------------------------------------32个pmod接口(扩展接口)------------------------------- +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {exp_io[0]}] +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports {exp_io[1]}] +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports {exp_io[2]}] +set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS33} [get_ports {exp_io[3]}] +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {exp_io[4]}] +set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports {exp_io[5]}] +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports {exp_io[6]}] +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {exp_io[7]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {exp_io[8]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {exp_io[9]}] +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports {exp_io[10]}] +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports {exp_io[11]}] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {exp_io[12]}] +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS33} [get_ports {exp_io[13]}] +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {exp_io[14]}] +set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {exp_io[15]}] + +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {exp_io[16]}] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {exp_io[17]}] +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports {exp_io[18]}] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {exp_io[19]}] +set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports {exp_io[20]}] +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports {exp_io[21]}] +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports {exp_io[22]}] +set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {exp_io[23]}] +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {exp_io[24]}] +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports {exp_io[25]}] +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS33} [get_ports {exp_io[26]}] +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports {exp_io[27]}] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {exp_io[28]}] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {exp_io[29]}] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {exp_io[30]}] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports {exp_io[31]}] + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1.v" new file mode 100644 index 00000000..70ddc69d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1.v" @@ -0,0 +1,111 @@ +//ýṹʽʵ4λƳ˷ +`timescale 1ns / 1ps +module full_adder( + input a, + input b, + input cin, + output f, + output cout +); + reg y1, y2; + + always @(*) //Ϊʽ + begin + {y2,y1} <= a+b+cin; + end + + assign f = y1; + assign cout = y2; + +endmodule + +module ttl74283( + input a4,a3,a2,a1,b4,b3,b2,b1,c0, + output f4,f3,f2,f1,fc4 +); + wire c1, c2, c3; + + // Full adder for bit 1 + full_adder fa1 ( + .a(a1), + .b(b1), + .cin(c0), + .f(f1), + .cout(c1) + ); + + + // Full adder for bit 2 + full_adder fa2 ( + .a(a2), + .b(b2), + .cin(c1), + .f(f2), + .cout(c2) + ); + + // Full adder for bit 3 + full_adder fa3 ( + .a(a3), + .b(b3), + .cin(c2), + .f(f3), + .cout(c3) + ); + + // Full adder for bit 4 + full_adder fa4 ( + .a(a4), + .b(b4), + .cin(c3), + .f(f4), + .cout(fc4) + ); +endmodule + +module and_gate( + input a, + input b, + output reg f +); + always @(*) //Ϊʽ + begin + f <= a & b; + end +endmodule + + +module multiplier( + input y3,y2,y1,y0,x3,x2,x1,x0, + output z7,z6,z5,z4,z3,z2,z1,z0 +); + wire a14,a13,a12,a11,b13,b12,b11,a24,a23,a22,a21,b34,b33,b32,b31; + wire f14,f13,f12,fc41; + wire f24,f23,f22,fc42; + and_gate U1(.a(y1),.b(x3),.f(a14)); + and_gate U2(.a(y1),.b(x2),.f(a13)); + and_gate U3(.a(y1),.b(x1),.f(a12)); + and_gate U4(.a(y1),.b(x0),.f(a11)); + and_gate U5(.a(y0),.b(x3),.f(b13)); + and_gate U6(.a(y0),.b(x2),.f(b12)); + and_gate U7(.a(y0),.b(x1),.f(b11)); + and_gate U8(.a(y0),.b(x0),.f(z0)); + ttl74283 U9(.a4(a14),.a3(a13),.a2(a12),.a1(a11),.b4(0),.b3(b13),.b2(b12),.b1(b11),.c0(0),.f4(f14),.f3(f13),.f2(f12),.f1(z1),.fc4(fc41)); + and_gate U10(.a(y2),.b(x3),.f(a24)); + and_gate U11(.a(y2),.b(x2),.f(a23)); + and_gate U12(.a(y2),.b(x1),.f(a22)); + and_gate U13(.a(y2),.b(x0),.f(a21)); + ttl74283 U14(.a4(a24),.a3(a23),.a2(a22),.a1(a21),.b4(fc41),.b3(f14),.b2(f13),.b1(f12),.c0(0),.f4(f24),.f3(f23),.f2(f22),.f1(z2),.fc4(fc42)); + and_gate U15(.a(y3),.b(x3),.f(b34)); + and_gate U16(.a(y3),.b(x2),.f(b33)); + and_gate U17(.a(y3),.b(x1),.f(b32)); + and_gate U18(.a(y3),.b(x0),.f(b31)); + ttl74283 U19(.a4(fc42),.a3(f24),.a2(f23),.a1(f22),.b4(b34),.b3(b33),.b2(b32),.b1(b31),.c0(0),.f4(z6),.f3(z5),.f2(z4),.f1(z3),.fc4(z7)); +endmodule + +module multiplier_exe( + input sw_pin[7:0], + output led_pin[15:0] +); + multiplier U(.y3(sw_pin[0]),.y2(sw_pin[1]),.y1(sw_pin[2]),.y0(sw_pin[3]),.x3(sw_pin[4]),.x2(sw_pin[5]),.x1(sw_pin[6]),.x0(sw_pin[7]),.z7(led_pin[0]),.z6(led_pin[1]),.z5(led_pin[2]),.z4(led_pin[3]),.z3(led_pin[4]),.z2(led_pin[5]),.z1(led_pin[6]),.z0(led_pin[7])); +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..060bdb9f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,14 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3130:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f63686f6f73655f70726f6a6563745f6c6f636174696f6e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 +eof:392333363 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..9a006883 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,5 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +eof:2791156663 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.cache/wt/project.wpc" new file mode 100644 index 00000000..9b342093 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..d4aa2dab --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,45 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.hw/multiplier_EGO1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.hw/multiplier_EGO1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.hw/multiplier_EGO1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.xpr" new file mode 100644 index 00000000..87018fd2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/multiplier_EGO1/multiplier_EGO1.xpr" @@ -0,0 +1,185 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/\347\254\2546\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/\347\254\2546\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" new file mode 100644 index 00000000..4f27213f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/\347\254\2546\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:344a77e02407c22f4f1f52c967ab55c5d2b01a4ab72c828b102c8a5a239f9353 +size 5183678 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/\347\254\2547\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260\357\274\210\347\254\2541\351\203\250\345\210\206\357\274\211.circ" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/\347\254\2547\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260\357\274\210\347\254\2541\351\203\250\345\210\206\357\274\211.circ" new file mode 100644 index 00000000..1cca526d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\205\255/\347\254\2547\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260\357\274\210\347\254\2541\351\203\250\345\210\206\357\274\211.circ" @@ -0,0 +1,3481 @@ + + +This file is intended to be loaded by Logisim http://logisim.altervista.org + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + addr/data: 8 8 +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/ACE1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/ACE1.xdc" new file mode 100644 index 00000000..6347de5e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/ACE1.xdc" @@ -0,0 +1,191 @@ +//----------------------------------------------系统时钟------------------------------------ +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports sys_clk_50m] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports sys_clk_100m] +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports sys_clk_3hz] + + +//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------ +set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + + + +//---------------------------------------------拨码?关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + + +//-----------------------------------------------9个按?-------------------------------------- +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports btn_4] +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports btn_5] +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports btn_6] +set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports btn_7] +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports btn_8] + + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] + + +//-----------------------------------6个数码管----------------------------------------------------------- +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[0]}] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[1]}] +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[2]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {digitron_out[3]}] +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS33} [get_ports {digitron_out[4]}] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[5]}] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[6]}] +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[7]}] + +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[0]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[1]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[2]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[3]}] + +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {digitron_a[0]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {digitron_a[2]}] +set_property -dict {PACKAGE_PIN AB18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[3]}] + +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33} [get_ports {digitron_b[0]}] +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[1]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[2]}] +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports {digitron_b[3]}] + + + +//----------------------------------------------串口--------------------------------------------- +set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports uart_rxd] +set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports uart_txd] + + + +//----------------------------------------------蜂鸣?----------------------------------------- +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports buzzer] + + + +//--------------------------------------------------------XADC数模转换------------------- +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports ad15p] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports ad15n] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports ad7p] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports ad7n] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports ad14p] +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports ad14n] +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports ad6p] +set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports ad6n] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports ad5p] +set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS33} [get_ports ad5n] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports ad13p] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports ad13n] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports ad4p] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports ad4n] + + + + +//--------------------------------------------------------DDR3L------------------------------------- +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_p] +set_property -dict {PACKAGE_PIN AA3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_n] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_p] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_n] + +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq0] +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq1] +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq2] +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq3] +set_property -dict {PACKAGE_PIN AA5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq4] +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq5] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq6] +set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq7] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq8] +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq9] +set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq10] +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq11] +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq12] +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq13] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq14] +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq15] + +set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a0] +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a1] +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a2] +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a3] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a4] +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a5] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a6] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a7] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a8] +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a9] +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a10] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a11] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a12] + +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba0] +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba1] +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba2] + +set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm0] +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm1] + +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports ddr3l_odt] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_p] +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_n] +set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cke] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports ddr3l_cs] +set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ras] +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports ddr3l_we] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports ddr3l_reset] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cas] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..1a7e9ab0 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,26 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f6f725f6372656174655f636f6e73747261696e745f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6d65737361676573:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f73696d756c6174696f6e5f77617665666f726d:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72657374617274:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72756e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72646976696577735f77617665666f726d5f766965776572:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:31:00:00 +eof:863519628 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..1f082065 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,9 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72657374617274:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:35:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e666f7274696d65:31:00:00 +eof:1959047579 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.cache/wt/project.wpc" new file mode 100644 index 00000000..6888edec --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:2 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..0742564c --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,61 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.cache/wt/xsim.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.cache/wt/xsim.wdf" new file mode 100644 index 00000000..50afb2c7 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.cache/wt/xsim.wdf" @@ -0,0 +1,4 @@ +version:1 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 +eof:241934075 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.hw/example_5_3_1_ACE1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.hw/example_5_3_1_ACE1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.hw/example_5_3_1_ACE1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.ip_user_files/README.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.ip_user_files/README.txt" new file mode 100644 index 00000000..023052ca --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.ip_user_files/README.txt" @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/compile.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/compile.bat" new file mode 100644 index 00000000..74bb8b73 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/compile.bat" @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2019.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Mon Nov 13 19:26:38 +0800 2023 +REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +REM +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvlog --incr --relax -prj example_5_3_1_sim_vlog.prj" +call xvlog --incr --relax -prj example_5_3_1_sim_vlog.prj -log xvlog.log +call type xvlog.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/elaborate.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/elaborate.bat" new file mode 100644 index 00000000..a04c465d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/elaborate.bat" @@ -0,0 +1,24 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2019.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Mon Nov 13 19:26:39 +0800 2023 +REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +REM +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +echo "xelab -wto a4420beb07e945d5876eda592b6ba751 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot example_5_3_1_sim_behav xil_defaultlib.example_5_3_1_sim xil_defaultlib.glbl -log elaborate.log" +call xelab -wto a4420beb07e945d5876eda592b6ba751 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot example_5_3_1_sim_behav xil_defaultlib.example_5_3_1_sim xil_defaultlib.glbl -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/example_5_3_1_sim.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/example_5_3_1_sim.tcl" new file mode 100644 index 00000000..1094e45d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/example_5_3_1_sim.tcl" @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/example_5_3_1_sim_behav.wdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/example_5_3_1_sim_behav.wdb" new file mode 100644 index 00000000..e0e2c305 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/example_5_3_1_sim_behav.wdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/example_5_3_1_sim_vlog.prj" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/example_5_3_1_sim_vlog.prj" new file mode 100644 index 00000000..124b093b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/example_5_3_1_sim_vlog.prj" @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../example_5_3_1_ACE1.v" \ +"../../../../example_5_3_1_sim_ACE1.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/glbl.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/glbl.v" new file mode 100644 index 00000000..be642335 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/glbl.v" @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/simulate.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/simulate.bat" new file mode 100644 index 00000000..12ba42c8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/simulate.bat" @@ -0,0 +1,24 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2019.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Mon Nov 13 19:26:41 +0800 2023 +REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +REM +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +echo "xsim example_5_3_1_sim_behav -key {Behavioral:sim_1:Functional:example_5_3_1_sim} -tclbatch example_5_3_1_sim.tcl -log simulate.log" +call xsim example_5_3_1_sim_behav -key {Behavioral:sim_1:Functional:example_5_3_1_sim} -tclbatch example_5_3_1_sim.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/webtalk.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/webtalk.jou" new file mode 100644 index 00000000..097b0356 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/webtalk.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 13 19:57:00 2023 +# Process ID: 7608 +# Current directory: D:/DigitalLogic/ACE1/Test4_Design/example_5_3_1_ACE1/example_5_3_1_ACE1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/DigitalLogic/ACE1/Test4_Design/example_5_3_1_ACE1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test4_Design/example_5_3_1_ACE1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/DigitalLogic/ACE1/Test4_Design/example_5_3_1_ACE1/example_5_3_1_ACE1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/DigitalLogic/ACE1/Test4_Design/example_5_3_1_ACE1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/webtalk/xsim_webtalk.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/webtalk_3704.backup.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/webtalk_3704.backup.jou" new file mode 100644 index 00000000..3870a291 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/webtalk_3704.backup.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 13 19:26:40 2023 +# Process ID: 3704 +# Current directory: D:/DigitalLogic/ACE1/Test4_Design/example_5_3_1_ACE1/example_5_3_1_ACE1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/DigitalLogic/ACE1/Test4_Design/example_5_3_1_ACE1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test4_Design/example_5_3_1_ACE1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/DigitalLogic/ACE1/Test4_Design/example_5_3_1_ACE1/example_5_3_1_ACE1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/DigitalLogic/ACE1/Test4_Design/example_5_3_1_ACE1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/webtalk/xsim_webtalk.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xelab.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xelab.pb" new file mode 100644 index 00000000..62ed22e9 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xelab.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/Compile_Options.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/Compile_Options.txt" new file mode 100644 index 00000000..5f701c83 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/Compile_Options.txt" @@ -0,0 +1 @@ +-wto "a4420beb07e945d5876eda592b6ba751" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "example_5_3_1_sim_behav" "xil_defaultlib.example_5_3_1_sim" "xil_defaultlib.glbl" -log "elaborate.log" diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/TempBreakPointFile.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/TempBreakPointFile.txt" new file mode 100644 index 00000000..fdbc612e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/TempBreakPointFile.txt" @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/webtalk/.xsim_webtallk.info" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/webtalk/.xsim_webtallk.info" new file mode 100644 index 00000000..faa9835c --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/webtalk/.xsim_webtallk.info" @@ -0,0 +1,5 @@ +1699874800 +1699876619 +3 +1 +a4420beb07e945d5876eda592b6ba751 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/webtalk/usage_statistics_ext_xsim.html" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/webtalk/usage_statistics_ext_xsim.html" new file mode 100644 index 00000000..4fc609df --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/webtalk/usage_statistics_ext_xsim.html" @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2708876
date_generatedMon Nov 13 19:56:59 2023os_platformWIN64
product_versionXSIM v2019.2 (64-bit)project_ida4420beb07e945d5876eda592b6ba751
project_iteration2random_idd24833b7-4cbd-4f74-b7c7-3cb815d77764
registration_idd24833b7-4cbd-4f74-b7c7-3cb815d77764route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_nameAMD Ryzen 9 7945HX with Radeon Graphics cpu_speed2495 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram16.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=1runtime=160 nssimulation_memory=8464_KBsimulation_time=0.03_sec
trace_waveform=true
+

+ + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/webtalk/usage_statistics_ext_xsim.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/webtalk/usage_statistics_ext_xsim.xml" new file mode 100644 index 00000000..917a65e3 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/webtalk/usage_statistics_ext_xsim.xml" @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + + +
+
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.dbg" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.dbg" new file mode 100644 index 00000000..6210a65c Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.dbg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.mem" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.mem" new file mode 100644 index 00000000..a256f637 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.mem" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.reloc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.reloc" new file mode 100644 index 00000000..20ba8d90 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.reloc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.rlx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.rlx" new file mode 100644 index 00000000..f1b2820d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.rlx" @@ -0,0 +1,12 @@ + +{ + crc : 14326878044582699144 , + ccp_crc : 0 , + cmdline : " -wto a4420beb07e945d5876eda592b6ba751 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot example_5_3_1_sim_behav xil_defaultlib.example_5_3_1_sim xil_defaultlib.glbl" , + buildDate : "Nov 6 2019" , + buildTime : "21:57:16" , + linkCmd : "D:\\Xilinx\\Vivado\\2019.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/example_5_3_1_sim_behav/xsimk.exe\" \"xsim.dir/example_5_3_1_sim_behav/obj/xsim_0.win64.obj\" \"xsim.dir/example_5_3_1_sim_behav/obj/xsim_1.win64.obj\" -L\"D:\\Xilinx\\Vivado\\2019.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.rtti" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.rtti" new file mode 100644 index 00000000..50a391b9 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.rtti" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.svtype" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.svtype" new file mode 100644 index 00000000..55847a84 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.svtype" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.type" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.type" new file mode 100644 index 00000000..14a09a21 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.type" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.xdbg" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.xdbg" new file mode 100644 index 00000000..e9de1bdc Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsim.xdbg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsimSettings.ini" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsimSettings.ini" new file mode 100644 index 00000000..c32014cc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_1_sim_behav/xsimSettings.ini" @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPEPROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +PROTO_DATA_TYPE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_5_3_1.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_5_3_1.sdb" new file mode 100644 index 00000000..fcd3bcf9 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_5_3_1.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_5_3_1_sim.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_5_3_1_sim.sdb" new file mode 100644 index 00000000..f2b3f74f Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_5_3_1_sim.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb" new file mode 100644 index 00000000..71583edc Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx" new file mode 100644 index 00000000..37756070 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx" @@ -0,0 +1,7 @@ +0.6 +2019.2 +Nov 6 2019 +21:57:16 +D:/DigitalLogic/ACE1/Test4_Design/example_5_3_1_ACE1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/glbl.v,1573089660,verilog,,,,glbl,,,,,,,, +D:/DigitalLogic/ACE1/Test4_Design/example_5_3_1_ACE1/example_5_3_1_ACE1.v,1699874360,verilog,,D:/DigitalLogic/ACE1/Test4_Design/example_5_3_1_ACE1/example_5_3_1_sim_ACE1.v,,example_5_3_1,,,,,,,, +D:/DigitalLogic/ACE1/Test4_Design/example_5_3_1_ACE1/example_5_3_1_sim_ACE1.v,1699874794,verilog,,,,example_5_3_1_sim,,,,,,,, diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.ini" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.ini" new file mode 100644 index 00000000..e8199b25 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xsim.ini" @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xvlog.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xvlog.pb" new file mode 100644 index 00000000..117dbb77 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.sim/sim_1/behav/xsim/xvlog.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.v" new file mode 100644 index 00000000..87ad7c38 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.v" @@ -0,0 +1,28 @@ +//Ϊʽʵ5.3Ĵмӷ +//õ·Ϊx1x2״̬ΪyΪZCPΪʱźš + +`timescale 1ns / 1ps + +module example_5_3_1( + input cp, + input x1,x2, + input y1, + output reg ny1, z +); + + always @(negedge cp) //Ϊʽ + + begin + case({y1, x1, x2}) + 0: begin ny1 <= 0; z=0; end // y1 x1 x2 = 000 y1n+1 = 0 z=0 + 1: begin ny1 <= 0; z=1; end // y1 x1 x2 = 001 y1n+1 = 0 z=1 + 2: begin ny1 <= 0; z=1; end // y1 x1 x2 = 010 y1n+1 = 0 z=1 + 3: begin ny1 <= 1; z=0; end // y1 x1 x2 = 011 y1n+1 = 1 z=0 + 4: begin ny1 <= 0; z=1; end // y1 x1 x2 = 100 y1n+1 = 0 z=1 + 5: begin ny1 <= 1; z=0; end // y1 x1 x2 = 101 y1n+1 = 1 z=0 + 6: begin ny1 <= 1; z=0; end // y1 x1 x2 = 110 y1n+1 = 1 z=0 + 7: begin ny1 <= 1; z=1; end // y1 x1 x2 = 111 y1n+1 = 1 z=1 + endcase + end + +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.xpr" new file mode 100644 index 00000000..16532a45 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_ACE1.xpr" @@ -0,0 +1,192 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_sim_ACE1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_sim_ACE1.v" new file mode 100644 index 00000000..4d440950 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_1_EGO1/example_5_3_1_sim_ACE1.v" @@ -0,0 +1,40 @@ +//5.3ķ + +`timescale 1ns / 1ps + +module example_5_3_1_sim(); + + reg cp, x1,x2; + wire ny1, z; + reg y1; + + example_5_3_1 U(.cp(cp), .x1(x1), .x2(x2), .y1(y1), .ny1(ny1), .z(z)); + + initial begin + #0 + y1=0; + cp=1; + x1=0; + x2=0; + #20 + x2=1; + #20 + x1=1; + x2=0; + #20 + x2=1; + #20 + x1=0; + #20 + x1=1; + #20 + x2=0; + #20 + x1=0; + end + + always #10 cp <= ~cp; + + always #20 begin y1 <= ny1; end + +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/ACE1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/ACE1.xdc" new file mode 100644 index 00000000..6347de5e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/ACE1.xdc" @@ -0,0 +1,191 @@ +//----------------------------------------------系统时钟------------------------------------ +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports sys_clk_50m] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports sys_clk_100m] +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports sys_clk_3hz] + + +//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------ +set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + + + +//---------------------------------------------拨码?关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + + +//-----------------------------------------------9个按?-------------------------------------- +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports btn_4] +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports btn_5] +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports btn_6] +set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports btn_7] +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports btn_8] + + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] + + +//-----------------------------------6个数码管----------------------------------------------------------- +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[0]}] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[1]}] +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[2]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {digitron_out[3]}] +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS33} [get_ports {digitron_out[4]}] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[5]}] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[6]}] +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[7]}] + +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[0]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[1]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[2]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[3]}] + +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {digitron_a[0]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {digitron_a[2]}] +set_property -dict {PACKAGE_PIN AB18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[3]}] + +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33} [get_ports {digitron_b[0]}] +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[1]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[2]}] +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports {digitron_b[3]}] + + + +//----------------------------------------------串口--------------------------------------------- +set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports uart_rxd] +set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports uart_txd] + + + +//----------------------------------------------蜂鸣?----------------------------------------- +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports buzzer] + + + +//--------------------------------------------------------XADC数模转换------------------- +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports ad15p] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports ad15n] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports ad7p] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports ad7n] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports ad14p] +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports ad14n] +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports ad6p] +set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports ad6n] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports ad5p] +set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS33} [get_ports ad5n] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports ad13p] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports ad13n] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports ad4p] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports ad4n] + + + + +//--------------------------------------------------------DDR3L------------------------------------- +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_p] +set_property -dict {PACKAGE_PIN AA3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_n] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_p] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_n] + +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq0] +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq1] +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq2] +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq3] +set_property -dict {PACKAGE_PIN AA5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq4] +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq5] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq6] +set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq7] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq8] +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq9] +set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq10] +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq11] +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq12] +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq13] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq14] +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq15] + +set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a0] +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a1] +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a2] +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a3] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a4] +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a5] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a6] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a7] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a8] +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a9] +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a10] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a11] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a12] + +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba0] +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba1] +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba2] + +set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm0] +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm1] + +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports ddr3l_odt] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_p] +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_n] +set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cke] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports ddr3l_cs] +set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ras] +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports ddr3l_we] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports ddr3l_reset] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cas] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..58d03bd2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,30 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6d65737361676573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3232:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f65646974:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f73696d756c6174696f6e5f77617665666f726d:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f7570646174655f68696572:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72657374617274:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f6c6976655f72756e:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f63686f6f73655f70726f6a6563745f6c6f636174696f6e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f736176655f66696c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72646976696577735f77617665666f726d5f766965776572:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e6c69766572756e666f72636f6d705f737065636966795f74696d655f616e645f756e697473:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:32:00:00 +eof:938727919 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..01170a7a --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,9 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72657374617274:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:35:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e666f7274696d65:32:00:00 +eof:977532587 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.cache/wt/project.wpc" new file mode 100644 index 00000000..de67d9ce --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.cache/wt/project.wpc" @@ -0,0 +1,3 @@ +version:1 +6d6f64655f636f756e7465727c4755494d6f6465:3 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..1b03c26e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,65 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.cache/wt/xsim.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.cache/wt/xsim.wdf" new file mode 100644 index 00000000..50afb2c7 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.cache/wt/xsim.wdf" @@ -0,0 +1,4 @@ +version:1 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 +eof:241934075 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.hw/example_5_3_ACE1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.hw/example_5_3_ACE1.lpr" new file mode 100644 index 00000000..c0c4ca27 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.hw/example_5_3_ACE1.lpr" @@ -0,0 +1,6 @@ + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.ip_user_files/README.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.ip_user_files/README.txt" new file mode 100644 index 00000000..023052ca --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.ip_user_files/README.txt" @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/compile.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/compile.bat" new file mode 100644 index 00000000..9b78fb9e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/compile.bat" @@ -0,0 +1,25 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2019.2 (64-bit) +REM +REM Filename : compile.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for compiling the simulation design source files +REM +REM Generated by Vivado on Mon Nov 13 18:57:56 +0800 2023 +REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +REM +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM +REM usage: compile.bat +REM +REM **************************************************************************** +echo "xvlog --incr --relax -prj example_5_3_sim_vlog.prj" +call xvlog --incr --relax -prj example_5_3_sim_vlog.prj -log xvlog.log +call type xvlog.log > compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/elaborate.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/elaborate.bat" new file mode 100644 index 00000000..6d7ccf35 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/elaborate.bat" @@ -0,0 +1,24 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2019.2 (64-bit) +REM +REM Filename : elaborate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for elaborating the compiled design +REM +REM Generated by Vivado on Mon Nov 13 18:57:57 +0800 2023 +REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +REM +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM +REM usage: elaborate.bat +REM +REM **************************************************************************** +echo "xelab -wto 7a8bb9c3d2b44966a060b4eef07ce763 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot example_5_3_sim_behav xil_defaultlib.example_5_3_sim xil_defaultlib.glbl -log elaborate.log" +call xelab -wto 7a8bb9c3d2b44966a060b4eef07ce763 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot example_5_3_sim_behav xil_defaultlib.example_5_3_sim xil_defaultlib.glbl -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/example_5_3_sim.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/example_5_3_sim.tcl" new file mode 100644 index 00000000..1094e45d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/example_5_3_sim.tcl" @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/example_5_3_sim_behav.wdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/example_5_3_sim_behav.wdb" new file mode 100644 index 00000000..89c06540 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/example_5_3_sim_behav.wdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/example_5_3_sim_vlog.prj" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/example_5_3_sim_vlog.prj" new file mode 100644 index 00000000..606cf73e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/example_5_3_sim_vlog.prj" @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../example_5_3_ACE1.v" \ +"../../../../example_5_3_sim_ACE1.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/glbl.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/glbl.v" new file mode 100644 index 00000000..be642335 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/glbl.v" @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/simulate.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/simulate.bat" new file mode 100644 index 00000000..1eef6441 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/simulate.bat" @@ -0,0 +1,24 @@ +@echo off +REM **************************************************************************** +REM Vivado (TM) v2019.2 (64-bit) +REM +REM Filename : simulate.bat +REM Simulator : Xilinx Vivado Simulator +REM Description : Script for simulating the design by launching the simulator +REM +REM Generated by Vivado on Mon Nov 13 18:57:58 +0800 2023 +REM SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +REM +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM +REM usage: simulate.bat +REM +REM **************************************************************************** +echo "xsim example_5_3_sim_behav -key {Behavioral:sim_1:Functional:example_5_3_sim} -tclbatch example_5_3_sim.tcl -log simulate.log" +call xsim example_5_3_sim_behav -key {Behavioral:sim_1:Functional:example_5_3_sim} -tclbatch example_5_3_sim.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/webtalk.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/webtalk.jou" new file mode 100644 index 00000000..86ffbb7c --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/webtalk.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 13 18:57:54 2023 +# Process ID: 3092 +# Current directory: D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_ACE1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_ACE1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_ACE1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/xsim_webtalk.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/webtalk_15228.backup.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/webtalk_15228.backup.jou" new file mode 100644 index 00000000..fdbc35a5 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/webtalk_15228.backup.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 13 18:50:08 2023 +# Process ID: 15228 +# Current directory: D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_ACE1.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_ACE1.sim/sim_1/behav/xsim/webtalk.log +# Journal file: D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_ACE1.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/xsim_webtalk.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xelab.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xelab.pb" new file mode 100644 index 00000000..b5700135 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xelab.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/Compile_Options.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/Compile_Options.txt" new file mode 100644 index 00000000..90507d6d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/Compile_Options.txt" @@ -0,0 +1 @@ +-wto "7a8bb9c3d2b44966a060b4eef07ce763" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "example_5_3_sim_behav" "xil_defaultlib.example_5_3_sim" "xil_defaultlib.glbl" -log "elaborate.log" diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/TempBreakPointFile.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/TempBreakPointFile.txt" new file mode 100644 index 00000000..fdbc612e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/TempBreakPointFile.txt" @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/.xsim_webtallk.info" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/.xsim_webtallk.info" new file mode 100644 index 00000000..bfe00c19 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/.xsim_webtallk.info" @@ -0,0 +1,5 @@ +1699872607 +1699873074 +5 +1 +7a8bb9c3d2b44966a060b4eef07ce763 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/usage_statistics_ext_xsim.html" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/usage_statistics_ext_xsim.html" new file mode 100644 index 00000000..4f7f2ec4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/usage_statistics_ext_xsim.html" @@ -0,0 +1,53 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2708876
date_generatedMon Nov 13 18:57:54 2023os_platformWIN64
product_versionXSIM v2019.2 (64-bit)project_id7a8bb9c3d2b44966a060b4eef07ce763
project_iteration2random_idd24833b7-4cbd-4f74-b7c7-3cb815d77764
registration_idd24833b7-4cbd-4f74-b7c7-3cb815d77764route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

+ + + + + + + + +
user_environment
cpu_nameAMD Ryzen 9 7945HX with Radeon Graphics cpu_speed2495 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram16.000 GBtotal_processors1

+ + +
vivado_usage

+ + + + +
xsim
+ + + +
command_line_options
command=xsim
+
+ + + + + + + +
usage
iteration=1runtime=160 nssimulation_memory=8452_KBsimulation_time=0.01_sec
trace_waveform=true
+

+ + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/usage_statistics_ext_xsim.wdm" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/usage_statistics_ext_xsim.wdm" new file mode 100644 index 00000000..04105306 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/usage_statistics_ext_xsim.wdm" @@ -0,0 +1,38 @@ +version = "1.0"; +clients = +( + { client_name = "project"; + rules = ( + { + context="software_version_and_target_device"; + xml_map="software_version_and_target_device"; + html_map="software_version_and_target_device"; + html_format="UserEnvStyle"; + }, + { + context="user_environment"; + xml_map="user_environment"; + html_map="user_environment"; + html_format="UserEnvStyle"; + } + ); + }, + + { client_name = "xsim"; + rules = ( + { + context="xsim\\command_line_options"; + xml_map="xsim\\command_line_options"; + html_map="xsim\\command_line_options"; + html_format="UnisimStatsStyle"; + }, + { + context="xsim\\usage"; + xml_map="xsim\\usage"; + html_map="xsim\\usage"; + html_format="UnisimStatsStyle"; + } + ); + } +); + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/usage_statistics_ext_xsim.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/usage_statistics_ext_xsim.xml" new file mode 100644 index 00000000..368a31a2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/usage_statistics_ext_xsim.xml" @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + + +
+
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/xsim_webtalk.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/xsim_webtalk.tcl" new file mode 100644 index 00000000..3a93c185 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/xsim_webtalk.tcl" @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Mon Nov 13 19:19:35 2023" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2019.2 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2708876" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "d24833b7-4cbd-4f74-b7c7-3cb815d77764" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "7a8bb9c3d2b44966a060b4eef07ce763" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Windows Server 2016 or Windows 10" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "AMD Ryzen 9 7945HX with Radeon Graphics " -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2495 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "160 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "1" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.00_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "8064_KB" -context "xsim\\usage" +webtalk_transmit -clientid 2826541465 -regid "" -xml D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/usage_statistics_ext_xsim.xml -html D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/usage_statistics_ext_xsim.html -wdm D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.dbg" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.dbg" new file mode 100644 index 00000000..fca2aa23 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.dbg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.mem" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.mem" new file mode 100644 index 00000000..07bdb48b Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.mem" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.reloc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.reloc" new file mode 100644 index 00000000..1e472470 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.reloc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.rlx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.rlx" new file mode 100644 index 00000000..aef9f968 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.rlx" @@ -0,0 +1,12 @@ + +{ + crc : 7723581887301344514 , + ccp_crc : 0 , + cmdline : " -wto 7a8bb9c3d2b44966a060b4eef07ce763 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot example_5_3_sim_behav xil_defaultlib.example_5_3_sim xil_defaultlib.glbl" , + buildDate : "Nov 6 2019" , + buildTime : "21:57:16" , + linkCmd : "D:\\Xilinx\\Vivado\\2019.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/example_5_3_sim_behav/xsimk.exe\" \"xsim.dir/example_5_3_sim_behav/obj/xsim_0.win64.obj\" \"xsim.dir/example_5_3_sim_behav/obj/xsim_1.win64.obj\" -L\"D:\\Xilinx\\Vivado\\2019.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.rtti" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.rtti" new file mode 100644 index 00000000..a2740d8b Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.rtti" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.svtype" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.svtype" new file mode 100644 index 00000000..55847a84 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.svtype" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.type" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.type" new file mode 100644 index 00000000..14a09a21 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.type" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.xdbg" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.xdbg" new file mode 100644 index 00000000..443de2a5 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsim.xdbg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsimSettings.ini" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsimSettings.ini" new file mode 100644 index 00000000..c32014cc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/example_5_3_sim_behav/xsimSettings.ini" @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=1024 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=65536 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=75 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 +OBJECT_NAME_COLUMN_WIDTH=75 +OBJECT_VALUE_COLUMN_WIDTH=75 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPEPROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +PROTO_DATA_TYPE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/d_flip_flop.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/d_flip_flop.sdb" new file mode 100644 index 00000000..c40be605 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/d_flip_flop.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_5_3.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_5_3.sdb" new file mode 100644 index 00000000..2ed3e90e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_5_3.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_5_3_sim.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_5_3_sim.sdb" new file mode 100644 index 00000000..dd5f7d04 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/example_5_3_sim.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb" new file mode 100644 index 00000000..7971414c Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/nand_gate.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/nand_gate.sdb" new file mode 100644 index 00000000..c1dc93e9 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/nand_gate.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx" new file mode 100644 index 00000000..4ae1756e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx" @@ -0,0 +1,7 @@ +0.6 +2019.2 +Nov 6 2019 +21:57:16 +D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_ACE1.sim/sim_1/behav/xsim/glbl.v,1573089660,verilog,,,,glbl,,,,,,,, +D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_ACE1.v,1699873066,verilog,,D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_sim_ACE1.v,,d_flip_flop;example_5_3;nand_gate;xor_gate,,,,,,,, +D:/DigitalLogic/ACE1/Test4_Design/example_5_3_ACE1/example_5_3_sim_ACE1.v,1699872595,verilog,,,,example_5_3_sim,,,,,,,, diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xor_gate.sdb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xor_gate.sdb" new file mode 100644 index 00000000..0361e2c6 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xor_gate.sdb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.ini" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.ini" new file mode 100644 index 00000000..e8199b25 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xsim.ini" @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xvlog.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xvlog.pb" new file mode 100644 index 00000000..68dd8670 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.sim/sim_1/behav/xsim/xvlog.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.v" new file mode 100644 index 00000000..379a9ca0 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.v" @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps + +module nand_gate(input a,input b,output f); + reg y; + always @(*) //Ϊʽ + begin + y <= ~(a & b); + end + assign f = y; +endmodule + +module xor_gate(input a,input b,output f); + reg y; + always @(*) //Ϊʽ + begin + y <= (a ^ b); + end + assign f = y; +endmodule + +module d_flip_flop(input d,input cp,output q, qn); + reg y; + always @(negedge cp) //Ϊʽ + begin + case(d) + 0: y <= 0; // D = 0 Y=0 + 1: y <= 1; // D = 1 Y=1 + endcase + end + assign q= y; + assign qn = ~y; +endmodule + +module example_5_3( + input cp, + input x1,x2, + input y1, y1n, + output ny1, ny1n, z +); + wire f1,f2,f3,d1; + xor_gate U1(.a(x1),.b(x2),.f(f1)); //ṹʽ + nand_gate U2(.a(x1),.b(x2),.f(f2)); //ṹʽ + d_flip_flop U3(.d(d1),.cp(cp),.q(ny1),.qn(ny1n)); //ṹʽ + nand_gate U4(.a(ny1),.b(f1),.f(f3)); //ṹʽ + nand_gate U5(.a(f2),.b(f3),.f(d1)); //ṹʽ + xor_gate U6(.a(f1),.b(ny1),.f(z)); //ṹʽ +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.xpr" new file mode 100644 index 00000000..36a321a2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_ACE1.xpr" @@ -0,0 +1,192 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_sim_ACE1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_sim_ACE1.v" new file mode 100644 index 00000000..736481ac --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_3_EGO1/example_5_3_sim_ACE1.v" @@ -0,0 +1,42 @@ +//5.3ķ + +`timescale 1ns / 1ps + +module example_5_3_sim(); + + reg cp, x1,x2; + wire ny1, z; + wire ny1n; + reg y1, y1n; + + example_5_3 U(.cp(cp), .x1(x1), .x2(x2), .y1(y1), .y1n(y1n), .ny1(ny1), .ny1n(ny1n), .z(z)); + + initial begin + #0 + y1=0; + y1n=1; + cp=1; + x1=0; + x2=0; + #20 + x2=1; + #20 + x1=1; + x2=0; + #20 + x2=1; + #20 + x1=0; + #20 + x1=1; + #20 + x2=0; + #20 + x1=0; + end + + always #10 cp <= ~cp; + + always #20 begin y1 <= ny1; y1n <= ny1n; end + +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/ACE1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/ACE1.xdc" new file mode 100644 index 00000000..6347de5e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/ACE1.xdc" @@ -0,0 +1,191 @@ +//----------------------------------------------系统时钟------------------------------------ +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports sys_clk_50m] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports sys_clk_100m] +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports sys_clk_3hz] + + +//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------ +set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + + + +//---------------------------------------------拨码?关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + + +//-----------------------------------------------9个按?-------------------------------------- +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports btn_4] +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports btn_5] +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports btn_6] +set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports btn_7] +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports btn_8] + + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] + + +//-----------------------------------6个数码管----------------------------------------------------------- +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[0]}] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[1]}] +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[2]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {digitron_out[3]}] +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS33} [get_ports {digitron_out[4]}] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[5]}] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[6]}] +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[7]}] + +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[0]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[1]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[2]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[3]}] + +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {digitron_a[0]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {digitron_a[2]}] +set_property -dict {PACKAGE_PIN AB18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[3]}] + +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33} [get_ports {digitron_b[0]}] +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[1]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[2]}] +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports {digitron_b[3]}] + + + +//----------------------------------------------串口--------------------------------------------- +set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports uart_rxd] +set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports uart_txd] + + + +//----------------------------------------------蜂鸣?----------------------------------------- +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports buzzer] + + + +//--------------------------------------------------------XADC数模转换------------------- +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports ad15p] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports ad15n] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports ad7p] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports ad7n] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports ad14p] +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports ad14n] +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports ad6p] +set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports ad6n] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports ad5p] +set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS33} [get_ports ad5n] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports ad13p] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports ad13n] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports ad4p] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports ad4n] + + + + +//--------------------------------------------------------DDR3L------------------------------------- +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_p] +set_property -dict {PACKAGE_PIN AA3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_n] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_p] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_n] + +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq0] +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq1] +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq2] +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq3] +set_property -dict {PACKAGE_PIN AA5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq4] +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq5] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq6] +set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq7] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq8] +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq9] +set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq10] +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq11] +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq12] +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq13] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq14] +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq15] + +set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a0] +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a1] +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a2] +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a3] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a4] +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a5] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a6] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a7] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a8] +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a9] +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a10] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a11] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a12] + +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba0] +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba1] +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba2] + +set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm0] +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm1] + +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports ddr3l_odt] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_p] +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_n] +set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cke] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports ddr3l_cs] +set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ras] +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports ddr3l_we] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports ddr3l_reset] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cas] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..8581cc71 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,21 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f796573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:38:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7372635f7265706c6163655f66696c65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f6f70656e5f746172676574:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 +eof:1740952025 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..02a84e6d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,13 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757064617465736f7572636566696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:31:00:00 +eof:749309662 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/project.wpc" new file mode 100644 index 00000000..2a7153ee --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/project.wpc" @@ -0,0 +1,4 @@ +version:1 +57656254616c6b5472616e736d697373696f6e417474656d70746564:1 +6d6f64655f636f756e7465727c4755494d6f6465:2 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/synthesis.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/synthesis.wdf" new file mode 100644 index 00000000..4ce911a9 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/synthesis.wdf" @@ -0,0 +1,39 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:786337613735746667673438342d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:6578616d706c655f355f345f31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313573:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313032342e3231314d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3639332e3933344d42:00:00 +eof:3757614083 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/synthesis_details.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/synthesis_details.wdf" new file mode 100644 index 00000000..78f8d66e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/synthesis_details.wdf" @@ -0,0 +1,3 @@ +version:1 +73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 +eof:2511430288 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..db74baf2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,60 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.hw/example_5_4_1_ACE1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.hw/example_5_4_1_ACE1.lpr" new file mode 100644 index 00000000..b7d45757 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.hw/example_5_4_1_ACE1.lpr" @@ -0,0 +1,8 @@ + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.hw/hw_1/hw.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.hw/hw_1/hw.xml" new file mode 100644 index 00000000..629ce3c3 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.hw/hw_1/hw.xml" @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.hw/webtalk/.xsim_webtallk.info" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.hw/webtalk/.xsim_webtallk.info" new file mode 100644 index 00000000..8d319a35 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.hw/webtalk/.xsim_webtallk.info" @@ -0,0 +1,5 @@ +1699879196 +0 +2 +1 +1471ffd8-bb23-4806-96b9-c88dcf13e9ff diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.hw/webtalk/usage_statistics_ext_labtool.html" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.hw/webtalk/usage_statistics_ext_labtool.html" new file mode 100644 index 00000000..42ad78f2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.hw/webtalk/usage_statistics_ext_labtool.html" @@ -0,0 +1,45 @@ +Device Usage Statistics Report +

LABTOOL Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2708876
date_generatedMon Nov 13 20:12:05 2023os_platformWIN64
product_versionVivado v2019.2 (64-bit)project_id1471ffd8-bb23-4806-96b9-c88dcf13e9ff
project_iteration1random_idd24833b7-4cbd-4f74-b7c7-3cb815d77764
registration_idd24833b7-4cbd-4f74-b7c7-3cb815d77764route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowlabtool

+ + + + + + + + +
user_environment
cpu_nameAMD Ryzen 9 7945HX with Radeon Graphics cpu_speed2495 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram16.000 GBtotal_processors1

+ + +
vivado_usage

+ + + +
labtool
+ + + + + +
usage
cable=XilinxA/TULA/15000000:chain=13632093pgmcnt=01:00:00
+

+ + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.hw/webtalk/usage_statistics_ext_labtool.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.hw/webtalk/usage_statistics_ext_labtool.xml" new file mode 100644 index 00000000..ea61d912 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.hw/webtalk/usage_statistics_ext_labtool.xml" @@ -0,0 +1,39 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+ + + +
+
+
+
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.Vivado_Implementation.queue.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.Vivado_Implementation.queue.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.init_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.init_design.begin.rst" new file mode 100644 index 00000000..c2e08bae --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.init_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.init_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.init_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.opt_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.opt_design.begin.rst" new file mode 100644 index 00000000..c2e08bae --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.opt_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.opt_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.opt_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.phys_opt_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.phys_opt_design.begin.rst" new file mode 100644 index 00000000..c2e08bae --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.phys_opt_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.phys_opt_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.phys_opt_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.place_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.place_design.begin.rst" new file mode 100644 index 00000000..c2e08bae --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.place_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.place_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.place_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.route_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.route_design.begin.rst" new file mode 100644 index 00000000..c2e08bae --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.route_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.route_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.route_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.vivado.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.vivado.begin.rst" new file mode 100644 index 00000000..4de800e0 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.vivado.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.vivado.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.vivado.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.write_bitstream.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.write_bitstream.begin.rst" new file mode 100644 index 00000000..c2e08bae --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.write_bitstream.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.write_bitstream.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/.write_bitstream.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/ISEWrap.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/ISEWrap.js" new file mode 100644 index 00000000..97a2ecbc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/ISEWrap.js" @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/ISEWrap.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/ISEWrap.sh" new file mode 100644 index 00000000..f679f2e8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/ISEWrap.sh" @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1.bit" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1.bit" new file mode 100644 index 00000000..818a3308 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1.bit" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1.tcl" new file mode 100644 index 00000000..32a505af --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1.tcl" @@ -0,0 +1,187 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param chipscope.maxJobs 8 + set_param xicom.use_bs_reader 1 + create_project -in_memory -part xc7a75tfgg484-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.cache/wt [current_project] + set_property parent.project_path D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.xpr [current_project] + set_property ip_output_repo D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1.dcp + read_xdc D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc + link_design -top example_5_4_1 -part xc7a75tfgg484-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force example_5_4_1_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file example_5_4_1_drc_opted.rpt -pb example_5_4_1_drc_opted.pb -rpx example_5_4_1_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force example_5_4_1_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file example_5_4_1_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file example_5_4_1_utilization_placed.rpt -pb example_5_4_1_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file example_5_4_1_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step phys_opt_design +set ACTIVE_STEP phys_opt_design +set rc [catch { + create_msg_db phys_opt_design.pb + phys_opt_design + write_checkpoint -force example_5_4_1_physopt.dcp + close_msg_db -file phys_opt_design.pb +} RESULT] +if {$rc} { + step_failed phys_opt_design + return -code error $RESULT +} else { + end_step phys_opt_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force example_5_4_1_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file example_5_4_1_drc_routed.rpt -pb example_5_4_1_drc_routed.pb -rpx example_5_4_1_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file example_5_4_1_methodology_drc_routed.rpt -pb example_5_4_1_methodology_drc_routed.pb -rpx example_5_4_1_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file example_5_4_1_power_routed.rpt -pb example_5_4_1_power_summary_routed.pb -rpx example_5_4_1_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file example_5_4_1_route_status.rpt -pb example_5_4_1_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file example_5_4_1_timing_summary_routed.rpt -pb example_5_4_1_timing_summary_routed.pb -rpx example_5_4_1_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file example_5_4_1_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file example_5_4_1_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file example_5_4_1_bus_skew_routed.rpt -pb example_5_4_1_bus_skew_routed.pb -rpx example_5_4_1_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force example_5_4_1_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + catch { write_mem_info -force example_5_4_1.mmi } + write_bitstream -force example_5_4_1.bit + catch {write_debug_probes -quiet -force example_5_4_1} + catch {file copy -force example_5_4_1.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1.vdi" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1.vdi" new file mode 100644 index 00000000..4901a8ef --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1.vdi" @@ -0,0 +1,829 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 13 20:23:58 2023 +# Process ID: 17340 +# Current directory: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/impl_1 +# Command line: vivado.exe -log example_5_4_1.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source example_5_4_1.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1.vdi +# Journal file: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source example_5_4_1.tcl -notrace +Command: link_design -top example_5_4_1 -part xc7a75tfgg484-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7a75tfgg484-1 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 621.027 ; gain = 0.000 +INFO: [Project 1-479] Netlist was created with Vivado 2019.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------系统时钟------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:1] +WARNING: [Vivado 12-584] No ports matched 'sys_clk_50m'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_100m'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:3] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:3] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_3hz'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:4] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:4] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:7] +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------拨码?关sw0~sw7----------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:19] +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------------------9个按?--------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:31] +WARNING: [Vivado 12-584] No ports matched 'btn_0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:32] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:32] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_2'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:34] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:34] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_3'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:35] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:35] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_4'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:36] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:36] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_5'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:37] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:37] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_6'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:38] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:38] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_7'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:39] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:39] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_8'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:40] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:40] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------6个数码管-----------------------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:46] +WARNING: [Vivado 12-584] No ports matched 'digitron_out[0]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:47] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:47] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[1]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:48] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:48] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[2]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:49] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[3]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:50] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:50] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[4]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:51] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:51] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[5]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:52] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:52] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[6]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:53] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:53] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[7]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:54] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:54] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[0]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:56] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:56] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[1]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:57] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:57] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[2]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:58] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:58] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[3]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:59] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:59] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[0]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:61] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:61] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[1]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:62] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:62] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[2]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:63] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:63] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[3]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:64] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:64] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[0]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:66] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:66] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[1]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:67] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:67] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[2]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:68] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:68] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[3]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:69] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:69] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------串口---------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:73] +WARNING: [Vivado 12-584] No ports matched 'uart_rxd'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:74] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:74] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'uart_txd'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:75] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:75] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------蜂鸣?-----------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:79] +WARNING: [Vivado 12-584] No ports matched 'buzzer'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:80] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:80] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------XADC数模转换-------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:84] +WARNING: [Vivado 12-584] No ports matched 'ad15p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:85] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:85] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad15n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:86] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:86] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:87] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:87] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:88] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:88] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:89] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:89] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:90] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:90] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:91] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:91] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:92] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:92] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:93] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:93] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:94] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:94] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:95] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:95] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:96] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:96] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:97] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:97] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:98] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:98] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------DDR3L-------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:103] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:104] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:104] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:105] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:105] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:106] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:106] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:107] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:107] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:109] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:109] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq1'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:110] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:110] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq2'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:111] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:111] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq3'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:112] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:112] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq4'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:113] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:113] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq5'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:114] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:114] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq6'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:115] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:115] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq7'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:116] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:116] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq8'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:117] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:117] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq9'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:118] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:118] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq10'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:119] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:119] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq11'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:120] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:120] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq12'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:121] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:121] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq13'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:122] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:122] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq14'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:123] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:123] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq15'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:124] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:124] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:126] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:126] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a1'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:127] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:127] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a2'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:128] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:128] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a3'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:129] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:129] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a4'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:130] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:130] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a5'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:131] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:131] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a6'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:132] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:132] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a7'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:133] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:133] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a8'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:134] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:134] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a9'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:135] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:135] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a10'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:136] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:136] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a11'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:137] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:137] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a12'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:138] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:138] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:140] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:140] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba1'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:141] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:141] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba2'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:142] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:142] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:144] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:144] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm1'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:145] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:145] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_odt'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:147] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:147] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:148] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:148] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:149] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:149] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cke'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:150] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:150] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cs'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:151] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:151] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ras'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:152] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:152] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_we'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:153] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:153] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_reset'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:154] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:154] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cas'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:155] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:155] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 729.168 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +5 Infos, 95 Warnings, 104 Critical Warnings and 0 Errors encountered. +link_design completed successfully +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.283 . Memory (MB): peak = 754.219 ; gain = 21.047 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 2691394e1 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1263.332 ; gain = 509.113 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 2691394e1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1459.355 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 2691394e1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1459.355 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 22bb29a7a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1459.355 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 2 cells and removed 0 cells + +Phase 4 BUFG optimization +INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. +INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. +INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). +Phase 4 BUFG optimization | Checksum: 22bb29a7a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1459.355 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 22bb29a7a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1459.355 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 22bb29a7a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1459.355 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 2 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1459.355 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1b3be4e25 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1459.355 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1b3be4e25 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1459.355 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 1b3be4e25 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1459.355 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1459.355 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 1b3be4e25 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1459.355 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +25 Infos, 95 Warnings, 104 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1459.355 ; gain = 726.184 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1459.355 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1459.355 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file example_5_4_1_drc_opted.rpt -pb example_5_4_1_drc_opted.pb -rpx example_5_4_1_drc_opted.rpx +Command: report_drc -file example_5_4_1_drc_opted.rpt -pb example_5_4_1_drc_opted.pb -rpx example_5_4_1_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1459.355 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1990d83b6 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1459.355 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1459.355 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. + + btn_1_IBUF_inst (IBUF.O) is locked to IOB_X1Y146 + btn_1_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 +Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 176ee0cfd + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.328 . Memory (MB): peak = 1466.234 ; gain = 6.879 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 26aabda31 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.334 . Memory (MB): peak = 1466.234 ; gain = 6.879 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 26aabda31 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.335 . Memory (MB): peak = 1466.234 ; gain = 6.879 +Phase 1 Placer Initialization | Checksum: 26aabda31 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.336 . Memory (MB): peak = 1466.234 ; gain = 6.879 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 26aabda31 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.337 . Memory (MB): peak = 1466.234 ; gain = 6.879 + +Phase 2.2 Global Placement Core +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2.2 Global Placement Core | Checksum: 1b926582f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.504 . Memory (MB): peak = 1466.234 ; gain = 6.879 +Phase 2 Global Placement | Checksum: 1b926582f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.506 . Memory (MB): peak = 1466.234 ; gain = 6.879 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1b926582f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.507 . Memory (MB): peak = 1466.234 ; gain = 6.879 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 23a47ea6b + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.510 . Memory (MB): peak = 1466.234 ; gain = 6.879 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 215b4b679 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.514 . Memory (MB): peak = 1466.234 ; gain = 6.879 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 215b4b679 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.514 . Memory (MB): peak = 1466.234 ; gain = 6.879 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 2850b4e9f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.587 . Memory (MB): peak = 1466.234 ; gain = 6.879 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 2850b4e9f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.587 . Memory (MB): peak = 1466.234 ; gain = 6.879 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 2850b4e9f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.588 . Memory (MB): peak = 1466.234 ; gain = 6.879 +Phase 3 Detail Placement | Checksum: 2850b4e9f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.588 . Memory (MB): peak = 1466.234 ; gain = 6.879 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 2850b4e9f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.589 . Memory (MB): peak = 1466.234 ; gain = 6.879 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 2850b4e9f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.590 . Memory (MB): peak = 1466.234 ; gain = 6.879 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: 2850b4e9f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.591 . Memory (MB): peak = 1466.234 ; gain = 6.879 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1466.234 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: 24c52c5ab + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.591 . Memory (MB): peak = 1466.234 ; gain = 6.879 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 24c52c5ab + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.591 . Memory (MB): peak = 1466.234 ; gain = 6.879 +Ending Placer Task | Checksum: 14f2cb09f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.591 . Memory (MB): peak = 1466.234 ; gain = 6.879 +INFO: [Common 17-83] Releasing license: Implementation +43 Infos, 97 Warnings, 104 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1466.234 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1481.254 ; gain = 15.020 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file example_5_4_1_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1481.254 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file example_5_4_1_utilization_placed.rpt -pb example_5_4_1_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file example_5_4_1_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1481.254 ; gain = 0.000 +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +51 Infos, 97 Warnings, 104 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1487.070 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1504.992 ; gain = 17.922 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_physopt.dcp' has been generated. +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. +Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. + This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. + + btn_1_IBUF_inst (IBUF.O) is locked to IOB_X1Y146 + btn_1_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 96e03ea4 ConstDB: 0 ShapeSum: b84c71fb RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: d94877e5 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1626.449 ; gain = 112.371 +Post Restoration Checksum: NetGraph: d79fff27 NumContArr: 1a878be Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: d94877e5 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1632.496 ; gain = 118.418 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: d94877e5 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1632.496 ; gain = 118.418 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 55a39b4d + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1639.539 ; gain = 125.461 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 8 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 8 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 19038f583 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1640.242 ; gain = 126.164 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 70b12d46 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1640.242 ; gain = 126.164 +Phase 4 Rip-up And Reroute | Checksum: 70b12d46 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1640.242 ; gain = 126.164 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 70b12d46 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1640.242 ; gain = 126.164 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 70b12d46 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1640.242 ; gain = 126.164 +Phase 6 Post Hold Fix | Checksum: 70b12d46 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1640.242 ; gain = 126.164 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.00309005 % + Global Horizontal Routing Utilization = 0.00262859 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 70b12d46 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1640.242 ; gain = 126.164 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 70b12d46 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1642.289 ; gain = 128.211 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: cde0956c + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1642.289 ; gain = 128.211 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1642.289 ; gain = 128.211 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +61 Infos, 98 Warnings, 104 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1642.289 ; gain = 137.297 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1642.289 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1652.176 ; gain = 9.887 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file example_5_4_1_drc_routed.rpt -pb example_5_4_1_drc_routed.pb -rpx example_5_4_1_drc_routed.rpx +Command: report_drc -file example_5_4_1_drc_routed.rpt -pb example_5_4_1_drc_routed.pb -rpx example_5_4_1_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file example_5_4_1_methodology_drc_routed.rpt -pb example_5_4_1_methodology_drc_routed.pb -rpx example_5_4_1_methodology_drc_routed.rpx +Command: report_methodology -file example_5_4_1_methodology_drc_routed.rpt -pb example_5_4_1_methodology_drc_routed.pb -rpx example_5_4_1_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file example_5_4_1_power_routed.rpt -pb example_5_4_1_power_summary_routed.pb -rpx example_5_4_1_power_routed.rpx +Command: report_power -file example_5_4_1_power_routed.rpt -pb example_5_4_1_power_summary_routed.pb -rpx example_5_4_1_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +73 Infos, 99 Warnings, 104 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file example_5_4_1_route_status.rpt -pb example_5_4_1_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file example_5_4_1_timing_summary_routed.rpt -pb example_5_4_1_timing_summary_routed.pb -rpx example_5_4_1_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file example_5_4_1_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file example_5_4_1_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file example_5_4_1_bus_skew_routed.rpt -pb example_5_4_1_bus_skew_routed.pb -rpx example_5_4_1_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force example_5_4_1.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./example_5_4_1.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +92 Infos, 101 Warnings, 104 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2127.602 ; gain = 446.941 +INFO: [Common 17-206] Exiting Vivado at Mon Nov 13 20:24:35 2023... diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_bus_skew_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_bus_skew_routed.pb" new file mode 100644 index 00000000..3390588d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_bus_skew_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_bus_skew_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_bus_skew_routed.rpt" new file mode 100644 index 00000000..f9781871 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_bus_skew_routed.rpt" @@ -0,0 +1,15 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:24:27 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file example_5_4_1_bus_skew_routed.rpt -pb example_5_4_1_bus_skew_routed.pb -rpx example_5_4_1_bus_skew_routed.rpx +| Design : example_5_4_1 +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Bus Skew Report + +No bus skew constraints + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_bus_skew_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_bus_skew_routed.rpx" new file mode 100644 index 00000000..5b4f6535 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_bus_skew_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_clock_utilization_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_clock_utilization_routed.rpt" new file mode 100644 index 00000000..9756c1d4 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_clock_utilization_routed.rpt" @@ -0,0 +1,150 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:24:27 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_clock_utilization -file example_5_4_1_clock_utilization_routed.rpt +| Design : example_5_4_1 +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X0Y1 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 96 | 0 | 0 | 0 | +| BUFIO | 0 | 24 | 0 | 0 | 0 | +| BUFMR | 0 | 12 | 0 | 0 | 0 | +| BUFR | 0 | 24 | 0 | 0 | 0 | +| MMCM | 0 | 6 | 0 | 0 | 0 | +| PLL | 0 | 6 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+------------------------+-----------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+------------------------+-----------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 6 | 0 | | | btn_1_IBUF_BUFG_inst/O | btn_1_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+------------------------+-----------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-------------------+------------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-------------------+------------+ +| src0 | g0 | IBUF/O | IOB_X1Y146 | IOB_X1Y146 | X1Y2 | 1 | 0 | | | btn_1_IBUF_inst/O | btn_1_IBUF | ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-------------------+------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1500 | 0 | 550 | 0 | 40 | 0 | 20 | 0 | 40 | +| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 6 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1350 | 0 | 500 | 0 | 30 | 0 | 15 | 0 | 40 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 1 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------+ +| g0 | BUFG/O | n/a | | | | 6 | 0 | 0 | 0 | btn_1_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------+ +* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 6 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + +7. Clock Region Cell Placement per Global Clock: Region X0Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-----------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-----------------+ +| g0 | n/a | BUFG/O | None | 6 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | btn_1_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-----------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells btn_1_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X1Y146 [get_ports btn_1] + +# Clock net "btn_1_IBUF_BUFG" driven by instance "btn_1_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_btn_1_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_btn_1_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="btn_1_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_btn_1_IBUF_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1} +#endgroup diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_control_sets_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_control_sets_placed.rpt" new file mode 100644 index 00000000..ba5df54f --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_control_sets_placed.rpt" @@ -0,0 +1,79 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:24:11 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file example_5_4_1_control_sets_placed.rpt +| Design : example_5_4_1 +| Device : xc7a75t +------------------------------------------------------------------------------------------ + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Total control sets | 1 | +| Minimum number of control sets | 1 | +| Addition due to synthesis replication | 0 | +| Addition due to physical synthesis replication | 0 | +| Unused register locations in slices containing registers | 2 | ++----------------------------------------------------------+-------+ +* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers +** Run report_qor_suggestions for automated merging and remapping suggestions + + +2. Histogram +------------ + ++--------------------+-------+ +| Fanout | Count | ++--------------------+-------+ +| Total control sets | 1 | +| >= 0 to < 4 | 0 | +| >= 4 to < 6 | 0 | +| >= 6 to < 8 | 1 | +| >= 8 to < 10 | 0 | +| >= 10 to < 12 | 0 | +| >= 12 to < 14 | 0 | +| >= 14 to < 16 | 0 | +| >= 16 | 0 | ++--------------------+-------+ +* Control sets can be remapped at either synth_design or opt_design + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 6 | 5 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++------------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++------------------+---------------+------------------+------------------+----------------+ +| ~btn_1_IBUF_BUFG | | | 5 | 6 | ++------------------+---------------+------------------+------------------+----------------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_opted.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_opted.pb" new file mode 100644 index 00000000..5aa0de05 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_opted.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_opted.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_opted.rpt" new file mode 100644 index 00000000..a3599090 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_opted.rpt" @@ -0,0 +1,61 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:24:10 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_drc -file example_5_4_1_drc_opted.rpt -pb example_5_4_1_drc_opted.pb -rpx example_5_4_1_drc_opted.rpx +| Design : example_5_4_1 +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 2 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| PLCK-12 | Warning | Clock Placer Checks | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +PLCK-12#1 Warning +Clock Placer Checks +Poor placement for routing between an IO pin and BUFG. +Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. + This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. + + btn_1_IBUF_inst (IBUF.O) is locked to C2 + btn_1_IBUF_BUFG_inst (BUFG.I) cannot be placed + +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_opted.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_opted.rpx" new file mode 100644 index 00000000..e8d431f5 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_opted.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_routed.pb" new file mode 100644 index 00000000..5aa0de05 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_routed.rpt" new file mode 100644 index 00000000..df269f46 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_routed.rpt" @@ -0,0 +1,61 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:24:27 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_drc -file example_5_4_1_drc_routed.rpt -pb example_5_4_1_drc_routed.pb -rpx example_5_4_1_drc_routed.rpx +| Design : example_5_4_1 +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Fully Routed +--------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 2 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| PLCK-12 | Warning | Clock Placer Checks | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +PLCK-12#1 Warning +Clock Placer Checks +Poor placement for routing between an IO pin and BUFG. +Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. + This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. + + btn_1_IBUF_inst (IBUF.O) is locked to C2 + btn_1_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 + +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_routed.rpx" new file mode 100644 index 00000000..ab3f6830 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_drc_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_io_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_io_placed.rpt" new file mode 100644 index 00000000..7a0ae05d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_io_placed.rpt" @@ -0,0 +1,526 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:24:11 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_io -file example_5_4_1_io_placed.rpt +| Design : example_5_4_1 +| Device : xc7a75t +| Speed File : -1 +| Package : fgg484 +| Package Version : FINAL 2012-11-02 +| Package Pin Delay Version : VERS. 2.0 2012-11-02 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 17 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A4 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A6 | | | MGTPTXN2_216 | Gigabit | | | | | | | | | | | | | | | | +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A8 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A10 | | | MGTPRXN2_216 | Gigabit | | | | | | | | | | | | | | | | +| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A19 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A20 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A21 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA3 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA4 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| AA8 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA9 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA10 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA11 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA13 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA14 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA15 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA16 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| AA18 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| AA19 | sw_pin[0] | High Range | IO_L15P_T2_DQS_RDWR_B_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| AA20 | led_pin[1] | High Range | IO_L8P_T1_D11_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| AA21 | led_pin[0] | High Range | IO_L8N_T1_D12_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB2 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB3 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| AB5 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB8 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB10 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB11 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB12 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB13 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| AB15 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB16 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB17 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB20 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| AB21 | sw_pin[7] | High Range | IO_L10P_T1_D14_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| AB22 | sw_pin[6] | High Range | IO_L10N_T1_D15_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| B1 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B4 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| B5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B6 | | | MGTPTXP2_216 | Gigabit | | | | | | | | | | | | | | | | +| B7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B8 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| B9 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B10 | | | MGTPRXP2_216 | Gigabit | | | | | | | | | | | | | | | | +| B11 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B15 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B16 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B20 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| B21 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| B22 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| C1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C2 | btn_1 | High Range | IO_L2P_T0_AD12P_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | | +| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C4 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C5 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C7 | | | MGTPTXN3_216 | Gigabit | | | | | | | | | | | | | | | | +| C8 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C9 | | | MGTPRXN3_216 | Gigabit | | | | | | | | | | | | | | | | +| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C11 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| C12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| C14 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C18 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C19 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C20 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| C21 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C22 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| D2 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D5 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| D6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| D7 | | | MGTPTXP3_216 | Gigabit | | | | | | | | | | | | | | | | +| D8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D9 | | | MGTPRXP3_216 | Gigabit | | | | | | | | | | | | | | | | +| D10 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| D11 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D14 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D16 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| D17 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| D19 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D20 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D21 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D22 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E6 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | | +| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E8 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | | +| E11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E12 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E14 | | High Range | IO_L4N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E15 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| E16 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L2N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| E19 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E21 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| E22 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F6 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | | +| F7 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| F8 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | | +| F9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| F10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| F13 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F15 | | High Range | IO_0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L2P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| F19 | | High Range | IO_L18P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| F20 | | High Range | IO_L18N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| F21 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | | +| F22 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| G1 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G15 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| G16 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G19 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G20 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G21 | | High Range | IO_L24P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| G22 | | High Range | IO_L24N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| H1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H2 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| H4 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| H14 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| H17 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H19 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H20 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H22 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| J1 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J2 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J4 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J14 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J17 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J19 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J20 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J21 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J22 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| K4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K6 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K16 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| K19 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| K20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K21 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| K22 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| L6 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| L12 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| L13 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| L18 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| L19 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| L20 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| L21 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M1 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| M4 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| M5 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| M6 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| M10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| M14 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| M15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| M16 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| M17 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| M21 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| M22 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| N1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| N2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N3 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| N4 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| N12 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| N13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| N14 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| N19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| N20 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| N21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| N22 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| P1 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P2 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| P5 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| P6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P14 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| P19 | led_pin[6] | High Range | IO_L5P_T0_D06_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P20 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| P21 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| P22 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| R2 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| R6 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R13 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| R14 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| R15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| R16 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| R19 | led_pin[5] | High Range | IO_L5N_T0_D07_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R21 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| R22 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| T3 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| T13 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| T19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T20 | led_pin[4] | High Range | IO_L6N_T0_D08_VREF_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T21 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| T22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U5 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U6 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| U9 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| U10 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| U11 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| U12 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| U13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U15 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| U16 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| U19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U20 | sw_pin[5] | High Range | IO_L11P_T1_SRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| U21 | led_pin[7] | High Range | IO_L4N_T0_D05_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U22 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V2 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| V4 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| V7 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V12 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| V13 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V14 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| V17 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | sw_pin[2] | High Range | IO_L14P_T2_SRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| V19 | sw_pin[1] | High Range | IO_L14N_T2_SRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| V20 | sw_pin[4] | High Range | IO_L11N_T1_SRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V22 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| W1 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W2 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| W4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W5 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W6 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W9 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| W10 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| W11 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W12 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W13 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| W14 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| W15 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| W16 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| W17 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| W20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| W21 | led_pin[3] | High Range | IO_L7P_T1_D09_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| W22 | led_pin[2] | High Range | IO_L7N_T1_D10_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| Y1 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y3 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y4 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y7 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y8 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y9 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y10 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| Y11 | | High Range | IO_L11P_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y12 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y13 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y14 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y16 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y17 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| Y19 | sw_pin[3] | High Range | IO_L13N_T2_MRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| Y20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| Y21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| Y22 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_methodology_drc_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_methodology_drc_routed.pb" new file mode 100644 index 00000000..ebdc7f8c Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_methodology_drc_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_methodology_drc_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_methodology_drc_routed.rpt" new file mode 100644 index 00000000..bf0a4b98 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_methodology_drc_routed.rpt" @@ -0,0 +1,65 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:24:27 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_methodology -file example_5_4_1_methodology_drc_routed.rpt -pb example_5_4_1_methodology_drc_routed.pb -rpx example_5_4_1_methodology_drc_routed.rpx +| Design : example_5_4_1 +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Fully Routed +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 6 ++-----------+------------------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+------------------+-----------------------------+------------+ +| TIMING-17 | Critical Warning | Non-clocked sequential cell | 6 | ++-----------+------------------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Critical Warning +Non-clocked sequential cell +The clock pin led_pin_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Critical Warning +Non-clocked sequential cell +The clock pin led_pin_reg[5]/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Critical Warning +Non-clocked sequential cell +The clock pin led_pin_reg[6]/C is not reached by a timing clock +Related violations: + +TIMING-17#4 Critical Warning +Non-clocked sequential cell +The clock pin led_pin_reg[6]_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#5 Critical Warning +Non-clocked sequential cell +The clock pin led_pin_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#6 Critical Warning +Non-clocked sequential cell +The clock pin led_pin_reg[7]_lopt_replica/C is not reached by a timing clock +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_methodology_drc_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_methodology_drc_routed.rpx" new file mode 100644 index 00000000..9aee619b Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_methodology_drc_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_opt.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_opt.dcp" new file mode 100644 index 00000000..f666e29e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_opt.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_physopt.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_physopt.dcp" new file mode 100644 index 00000000..9bcea8b3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_physopt.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_placed.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_placed.dcp" new file mode 100644 index 00000000..c6674fa2 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_placed.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_power_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_power_routed.rpt" new file mode 100644 index 00000000..0c474a39 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_power_routed.rpt" @@ -0,0 +1,143 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:24:27 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_power -file example_5_4_1_power_routed.rpt -pb example_5_4_1_power_summary_routed.pb -rpx example_5_4_1_power_routed.rpx +| Design : example_5_4_1 +| Device : xc7a75tfgg484-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 4.033 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 3.927 | +| Device Static (W) | 0.106 | +| Effective TJA (C/W) | 2.7 | +| Max Ambient (C) | 74.2 | +| Junction Temperature (C) | 35.8 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.011 | 10 | --- | --- | +| BUFG | 0.006 | 1 | 32 | 3.13 | +| LUT as Logic | 0.003 | 1 | 47200 | <0.01 | +| Register | 0.002 | 6 | 94400 | <0.01 | +| Others | 0.000 | 2 | --- | --- | +| Signals | 0.037 | 9 | --- | --- | +| I/O | 3.879 | 10 | 285 | 3.51 | +| Static Power | 0.106 | | | | +| Total | 4.033 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.079 | 0.056 | 0.023 | +| Vccaux | 1.800 | 0.161 | 0.142 | 0.019 | +| Vcco33 | 3.300 | 1.100 | 1.096 | 0.004 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 2.7 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++---------------+-----------+ +| Name | Power (W) | ++---------------+-----------+ +| example_5_4_1 | 3.927 | ++---------------+-----------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_power_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_power_routed.rpx" new file mode 100644 index 00000000..29769785 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_power_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_power_summary_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_power_summary_routed.pb" new file mode 100644 index 00000000..c2bc1834 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_power_summary_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_route_status.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_route_status.pb" new file mode 100644 index 00000000..cac3c427 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_route_status.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_route_status.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_route_status.rpt" new file mode 100644 index 00000000..7edf7a84 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_route_status.rpt" @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 22 : + # of nets not needing routing.......... : 11 : + # of internally routed nets........ : 11 : + # of routable nets..................... : 11 : + # of fully routed nets............. : 11 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_routed.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_routed.dcp" new file mode 100644 index 00000000..e63b5ddc Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_routed.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_timing_summary_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_timing_summary_routed.pb" new file mode 100644 index 00000000..4526e931 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_timing_summary_routed.pb" @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_timing_summary_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_timing_summary_routed.rpt" new file mode 100644 index 00000000..9c39a7c0 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_timing_summary_routed.rpt" @@ -0,0 +1,175 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:24:27 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file example_5_4_1_timing_summary_routed.rpt -pb example_5_4_1_timing_summary_routed.pb -rpx example_5_4_1_timing_summary_routed.rpx -warn_on_violation +| Design : example_5_4_1 +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 6 register/latch pins with no clock driven by root clock pin: btn_1 (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 6 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There is 1 input port with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 4 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_timing_summary_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_timing_summary_routed.rpx" new file mode 100644 index 00000000..f27625cd Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_timing_summary_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_utilization_placed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_utilization_placed.pb" new file mode 100644 index 00000000..306d1d29 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_utilization_placed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_utilization_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_utilization_placed.rpt" new file mode 100644 index 00000000..c210164e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1_utilization_placed.rpt" @@ -0,0 +1,204 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:24:11 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_utilization -file example_5_4_1_utilization_placed.rpt -pb example_5_4_1_utilization_placed.pb +| Design : example_5_4_1 +| Device : 7a75tfgg484-1 +| Design State : Fully Placed +----------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 1 | 0 | 47200 | <0.01 | +| LUT as Logic | 1 | 0 | 47200 | <0.01 | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| Slice Registers | 6 | 0 | 94400 | <0.01 | +| Register as Flip Flop | 6 | 0 | 94400 | <0.01 | +| Register as Latch | 0 | 0 | 94400 | 0.00 | +| F7 Muxes | 0 | 0 | 31700 | 0.00 | +| F8 Muxes | 0 | 0 | 15850 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 6 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++--------------------------------------------+------+-------+-----------+-------+ +| Slice | 5 | 0 | 15850 | 0.03 | +| SLICEL | 5 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 1 | 0 | 47200 | <0.01 | +| using O5 output only | 0 | | | | +| using O6 output only | 1 | | | | +| using O5 and O6 | 0 | | | | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 6 | 0 | 94400 | <0.01 | +| Register driven from within the Slice | 1 | | | | +| Register driven from outside the Slice | 5 | | | | +| LUT in front of the register is unused | 4 | | | | +| LUT in front of the register is used | 1 | | | | +| Unique Control Sets | 1 | | 15850 | <0.01 | ++--------------------------------------------+------+-------+-----------+-------+ +* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 105 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 105 | 0.00 | +| RAMB18 | 0 | 0 | 210 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 180 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 10 | 10 | 285 | 3.51 | +| IOB Master Pads | 5 | | | | +| IOB Slave Pads | 5 | | | | +| Bonded IPADs | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 6 | 0.00 | +| PHASER_REF | 0 | 0 | 6 | 0.00 | +| OUT_FIFO | 0 | 0 | 24 | 0.00 | +| IN_FIFO | 0 | 0 | 24 | 0.00 | +| IDELAYCTRL | 0 | 0 | 6 | 0.00 | +| IBUFDS | 0 | 0 | 274 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 24 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 24 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 300 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 0 | 0 | 6 | 0.00 | +| PLLE2_ADV | 0 | 0 | 6 | 0.00 | +| BUFMRCE | 0 | 0 | 12 | 0.00 | +| BUFHCE | 0 | 0 | 96 | 0.00 | +| BUFR | 0 | 0 | 24 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 6 | Flop & Latch | +| OBUFT | 4 | IO | +| OBUF | 4 | IO | +| IBUF | 2 | IO | +| LUT3 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/gen_run.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/gen_run.xml" new file mode 100644 index 00000000..17600c4b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/gen_run.xml" @@ -0,0 +1,125 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/htr.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/htr.txt" new file mode 100644 index 00000000..5be6c91e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/htr.txt" @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log example_5_4_1.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_5_4_1.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/init_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/init_design.pb" new file mode 100644 index 00000000..fc7cb879 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/init_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/opt_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/opt_design.pb" new file mode 100644 index 00000000..8e379fb0 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/opt_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/phys_opt_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/phys_opt_design.pb" new file mode 100644 index 00000000..14a337b1 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/phys_opt_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/place_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/place_design.pb" new file mode 100644 index 00000000..ce7c1b9b Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/place_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/project.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/project.wdf" new file mode 100644 index 00000000..ed68e16c --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/project.wdf" @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3363353532323366646238343434343139306437366535303163303766656332:506172656e742050412070726f6a656374204944:00 +eof:2664062467 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/route_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/route_design.pb" new file mode 100644 index 00000000..c27880b2 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/route_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/rundef.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/rundef.js" new file mode 100644 index 00000000..3abcdef3 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/rundef.js" @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;"; +} else { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log example_5_4_1.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_5_4_1.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/runme.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/runme.bat" new file mode 100644 index 00000000..1760626b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/runme.bat" @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/runme.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/runme.sh" new file mode 100644 index 00000000..057949ab --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/runme.sh" @@ -0,0 +1,47 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin +else + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log example_5_4_1.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_5_4_1.tcl -notrace + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/usage_statistics_webtalk.html" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/usage_statistics_webtalk.html" new file mode 100644 index 00000000..195d0637 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/usage_statistics_webtalk.html" @@ -0,0 +1,630 @@ +Device Usage Statistics Report +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click
here.


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2708876
date_generatedMon Nov 13 20:24:34 2023os_platformWIN64
product_versionVivado v2019.2 (64-bit)project_id3c55223fdb84444190d76e501c07fec2
project_iteration1random_id5098e843c55f5f60a14bf92371dc2ce7
registration_id5098e843c55f5f60a14bf92371dc2ce7route_designTRUE
target_devicexc7a75ttarget_familyartix7
target_packagefgg484target_speed-1
tool_flowVivado

+ + + + + + + + +
user_environment
cpu_nameAMD Ryzen 9 7945HX with Radeon Graphics cpu_speed2495 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram16.000 GBtotal_processors1

+ + +
vivado_usage
+ + + + + + + + + + + + + +
gui_handlers
addsrcwizard_specify_hdl_netlist_block_design=1basedialog_ok=1basedialog_yes=1constraintschooserpanel_add_files=1
filesetpanel_file_set_panel_tree=6flownavigatortreepanel_flow_navigator_tree=1fpgachooser_fpga_table=2gettingstartedview_create_new_project=1
pacommandnames_add_sources=2pacommandnames_src_replace_file=1projectnamechooser_project_name=1srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1
+ + + + + + +
java_command_handlers
addsources=2newproject=1runbitgen=1updatesourcefiles=1
+ + + +
other_data
guimode=1
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
project_data
constraintsetcount=1core_container=falsecurrentimplrun=impl_1currentsynthesisrun=synth_1
default_library=xil_defaultlibdesignmode=RTLexport_simulation_activehdl=0export_simulation_ies=0
export_simulation_modelsim=0export_simulation_questa=0export_simulation_riviera=0export_simulation_vcs=0
export_simulation_xsim=0implstrategy=Vivado Implementation Defaultslaunch_simulation_activehdl=0launch_simulation_ies=0
launch_simulation_modelsim=0launch_simulation_questa=0launch_simulation_riviera=0launch_simulation_vcs=0
launch_simulation_xsim=0simulator_language=Mixedsrcsetcount=1synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilogtarget_simulator=XSimtotalimplruns=1totalsynthesisruns=1
+
+ + + + +
unisim_transformation
+ + + + + + + + + + +
post_unisim_transformation
bufg=1fdre=4gnd=1ibuf=2
lut3=1obuf=4obuft=4vcc=1
+
+ + + + + + + + + + +
pre_unisim_transformation
bufg=1fdre=4gnd=1ibuf=2
lut3=1obuf=4obuft=4vcc=1
+

+ + + +
phys_opt_design_post_place
+ + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-aggressive_hold_fix=default::[not_specified]-bram_register_opt=default::[not_specified]-clock_opt=default::[not_specified]-critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified]-directive=default::[not_specified]-dsp_register_opt=default::[not_specified]-effort_level=default::[not_specified]
-fanout_opt=default::[not_specified]-hold_fix=default::[not_specified]-insert_negative_edge_ffs=default::[not_specified]-multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified]-restruct_opt=default::[not_specified]-retime=default::[not_specified]-rewire=default::[not_specified]
-shift_register_opt=default::[not_specified]-uram_register_opt=default::[not_specified]-verbose=default::[not_specified]-vhfn=default::[not_specified]
+

+ + + + +
report_drc
+ + + + + + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-internal=default::[not_specified]-internal_only=default::[not_specified]-messages=default::[not_specified]
-name=default::[not_specified]-no_waivers=default::[not_specified]-return_string=default::[not_specified]-ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified]-waived=default::[not_specified]
+
+ + + + +
results
cfgbvs-1=1plck-12=1
+

+ + + + +
report_methodology
+ + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified]-waived=default::[not_specified]
+
+ + + +
results
timing-17=6
+

+ + + + +
report_power
+ + + + + + + + + + + + + + + + +
command_line_options
-advisory=default::[not_specified]-append=default::[not_specified]-file=[specified]-format=default::text
-hier=default::power-hierarchical_depth=default::4-l=default::[not_specified]-name=default::[not_specified]
-no_propagation=default::[not_specified]-return_string=default::[not_specified]-rpx=[specified]-verbose=default::[not_specified]
-vid=default::[not_specified]-xpe=default::[not_specified]
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
usage
airflow=250 (LFM)ambient_temp=25.0 (C)bi-dir_toggle=12.500000bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers)board_selection=medium (10"x10")confidence_level_clock_activity=Lowconfidence_level_design_state=High
confidence_level_device_models=Highconfidence_level_internal_activity=Mediumconfidence_level_io_activity=Lowconfidence_level_overall=Low
customer=TBDcustomer_class=TBDdevstatic=0.106052die=xc7a75tfgg484-1
dsp_output_toggle=12.500000dynamic=3.927300effective_thetaja=2.7enable_probability=0.990000
family=artix7ff_toggle=12.500000flow_state=routedheatsink=medium (Medium Profile)
i/o=3.879161input_toggle=12.500000junction_temp=35.8 (C)logic=0.010793
mgtavcc_dynamic_current=0.000000mgtavcc_static_current=0.000000mgtavcc_total_current=0.000000mgtavcc_voltage=1.000000
mgtavtt_dynamic_current=0.000000mgtavtt_static_current=0.000000mgtavtt_total_current=0.000000mgtavtt_voltage=1.200000
netlist_net_matched=NAoff-chip_power=0.000000on-chip_power=4.033351output_enable=1.000000
output_load=5.000000output_toggle=12.500000package=fgg484pct_clock_constrained=0.000000
pct_inputs_defined=0platform=nt64process=typicalram_enable=50.000000
ram_write=50.000000read_saif=Falseset/reset_probability=0.000000signal_rate=False
signals=0.037346simulation_file=Nonespeedgrade=-1static_prob=False
temp_grade=commercialthetajb=6.8 (C/W)thetasa=4.6 (C/W)toggle_rate=False
user_board_temp=25.0 (C)user_effective_thetaja=2.7user_junc_temp=35.8 (C)user_thetajb=6.8 (C/W)
user_thetasa=4.6 (C/W)vccadc_dynamic_current=0.000000vccadc_static_current=0.020000vccadc_total_current=0.020000
vccadc_voltage=1.800000vccaux_dynamic_current=0.141856vccaux_io_dynamic_current=0.000000vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000vccaux_io_voltage=1.800000vccaux_static_current=0.018857vccaux_total_current=0.160712
vccaux_voltage=1.800000vccbram_dynamic_current=0.000000vccbram_static_current=0.000383vccbram_total_current=0.000383
vccbram_voltage=1.000000vccint_dynamic_current=0.056139vccint_static_current=0.022527vccint_total_current=0.078665
vccint_voltage=1.000000vcco12_dynamic_current=0.000000vcco12_static_current=0.000000vcco12_total_current=0.000000
vcco12_voltage=1.200000vcco135_dynamic_current=0.000000vcco135_static_current=0.000000vcco135_total_current=0.000000
vcco135_voltage=1.350000vcco15_dynamic_current=0.000000vcco15_static_current=0.000000vcco15_total_current=0.000000
vcco15_voltage=1.500000vcco18_dynamic_current=0.000000vcco18_static_current=0.000000vcco18_total_current=0.000000
vcco18_voltage=1.800000vcco25_dynamic_current=0.000000vcco25_static_current=0.000000vcco25_total_current=0.000000
vcco25_voltage=2.500000vcco33_dynamic_current=1.095703vcco33_static_current=0.004000vcco33_total_current=1.099703
vcco33_voltage=3.300000version=2019.2
+

+ + + + + + + + + +
report_utilization
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
clocking
bufgctrl_available=32bufgctrl_fixed=0bufgctrl_used=1bufgctrl_util_percentage=3.13
bufhce_available=96bufhce_fixed=0bufhce_used=0bufhce_util_percentage=0.00
bufio_available=24bufio_fixed=0bufio_used=0bufio_util_percentage=0.00
bufmrce_available=12bufmrce_fixed=0bufmrce_used=0bufmrce_util_percentage=0.00
bufr_available=24bufr_fixed=0bufr_used=0bufr_util_percentage=0.00
mmcme2_adv_available=6mmcme2_adv_fixed=0mmcme2_adv_used=0mmcme2_adv_util_percentage=0.00
plle2_adv_available=6plle2_adv_fixed=0plle2_adv_used=0plle2_adv_util_percentage=0.00
+
+ + + + + + +
dsp
dsps_available=180dsps_fixed=0dsps_used=0dsps_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
io_standard
blvds_25=0diff_hstl_i=0diff_hstl_i_18=0diff_hstl_ii=0
diff_hstl_ii_18=0diff_hsul_12=0diff_mobile_ddr=0diff_sstl135=0
diff_sstl135_r=0diff_sstl15=0diff_sstl15_r=0diff_sstl18_i=0
diff_sstl18_ii=0hstl_i=0hstl_i_18=0hstl_ii=0
hstl_ii_18=0hsul_12=0lvcmos12=0lvcmos15=0
lvcmos18=0lvcmos25=0lvcmos33=1lvds_25=0
lvttl=0mini_lvds_25=0mobile_ddr=0pci33_3=0
ppds_25=0rsds_25=0sstl135=0sstl135_r=0
sstl15=0sstl15_r=0sstl18_i=0sstl18_ii=0
tmds_33=0
+
+ + + + + + + + + + + + + + +
memory
block_ram_tile_available=105block_ram_tile_fixed=0block_ram_tile_used=0block_ram_tile_util_percentage=0.00
ramb18_available=210ramb18_fixed=0ramb18_used=0ramb18_util_percentage=0.00
ramb36_fifo_available=105ramb36_fifo_fixed=0ramb36_fifo_used=0ramb36_fifo_util_percentage=0.00
+
+ + + + + + + + + + + + + + +
primitives
bufg_functional_category=Clockbufg_used=1fdre_functional_category=Flop & Latchfdre_used=6
ibuf_functional_category=IOibuf_used=2lut3_functional_category=LUTlut3_used=1
obuf_functional_category=IOobuf_used=4obuft_functional_category=IOobuft_used=4
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
slice_logic
f7_muxes_available=31700f7_muxes_fixed=0f7_muxes_used=0f7_muxes_util_percentage=0.00
f8_muxes_available=15850f8_muxes_fixed=0f8_muxes_used=0f8_muxes_util_percentage=0.00
lut_as_logic_available=47200lut_as_logic_fixed=0lut_as_logic_used=1lut_as_logic_util_percentage=<0.01
lut_as_memory_available=19000lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=94400register_as_flip_flop_fixed=0register_as_flip_flop_used=6register_as_flip_flop_util_percentage=<0.01
register_as_latch_available=94400register_as_latch_fixed=0register_as_latch_used=0register_as_latch_util_percentage=0.00
slice_luts_available=47200slice_luts_fixed=0slice_luts_used=1slice_luts_util_percentage=<0.01
slice_registers_available=94400slice_registers_fixed=0slice_registers_used=6slice_registers_util_percentage=<0.01
lut_as_distributed_ram_fixed=0lut_as_distributed_ram_used=0lut_as_logic_available=47200lut_as_logic_fixed=0
lut_as_logic_used=1lut_as_logic_util_percentage=<0.01lut_as_memory_available=19000lut_as_memory_fixed=0
lut_as_memory_used=0lut_as_memory_util_percentage=0.00lut_as_shift_register_fixed=0lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0lut_in_front_of_the_register_is_unused_used=4lut_in_front_of_the_register_is_used_fixed=4lut_in_front_of_the_register_is_used_used=1
register_driven_from_outside_the_slice_fixed=1register_driven_from_outside_the_slice_used=5register_driven_from_within_the_slice_fixed=5register_driven_from_within_the_slice_used=1
slice_available=15850slice_fixed=0slice_registers_available=94400slice_registers_fixed=0
slice_registers_used=6slice_registers_util_percentage=<0.01slice_used=5slice_util_percentage=0.03
slicel_fixed=0slicel_used=5slicem_fixed=0slicem_used=0
unique_control_sets_available=15850unique_control_sets_fixed=15850unique_control_sets_used=1unique_control_sets_util_percentage=<0.01
using_o5_and_o6_fixed=<0.01using_o5_and_o6_used=0using_o5_output_only_fixed=0using_o5_output_only_used=0
using_o6_output_only_fixed=0using_o6_output_only_used=1
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
specific_feature
bscane2_available=4bscane2_fixed=0bscane2_used=0bscane2_util_percentage=0.00
capturee2_available=1capturee2_fixed=0capturee2_used=0capturee2_util_percentage=0.00
dna_port_available=1dna_port_fixed=0dna_port_used=0dna_port_util_percentage=0.00
efuse_usr_available=1efuse_usr_fixed=0efuse_usr_used=0efuse_usr_util_percentage=0.00
frame_ecce2_available=1frame_ecce2_fixed=0frame_ecce2_used=0frame_ecce2_util_percentage=0.00
icape2_available=2icape2_fixed=0icape2_used=0icape2_util_percentage=0.00
pcie_2_1_available=1pcie_2_1_fixed=0pcie_2_1_used=0pcie_2_1_util_percentage=0.00
startupe2_available=1startupe2_fixed=0startupe2_used=0startupe2_util_percentage=0.00
xadc_available=1xadc_fixed=0xadc_used=0xadc_util_percentage=0.00
+

+ + + + +
synthesis
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-assert=default::[not_specified]-bufg=default::12-cascade_dsp=default::auto-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto-directive=default::default-fanout_limit=default::10000-flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto-gated_clock_conversion=default::off-generic=default::[not_specified]-include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified]-max_bram=default::-1-max_bram_cascade_height=default::-1-max_dsp=default::-1
-max_uram=default::-1-max_uram_cascade_height=default::-1-mode=default::default-name=default::[not_specified]
-no_lc=default::[not_specified]-no_srlextract=default::[not_specified]-no_timing_driven=default::[not_specified]-part=xc7a75tfgg484-1
-resource_sharing=default::auto-retiming=default::[not_specified]-rtl=default::[not_specified]-rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified]-seu_protect=default::none-sfcu=default::[not_specified]-shreg_min_size=default::3
-top=example_5_4_1-verilog_define=default::[not_specified]
+
+ + + + + + +
usage
elapsed=00:00:15shls_ip=0memory_gain=693.934MBmemory_peak=1024.211MB
+

+ + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/usage_statistics_webtalk.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/usage_statistics_webtalk.xml" new file mode 100644 index 00000000..f56f330c --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/usage_statistics_webtalk.xml" @@ -0,0 +1,563 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+ + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + +
+
+ + +
+
+
+
+ + + + + + + + + + +
+
+ +
+
+
+
+ + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + +
+
+ + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + +
+
+
+
+ + + + + + + + +
+
+ + + + + + + + +
+
+
+
+ + + + + + + + + + + + +
+
+ + + + +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/vivado.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/vivado.jou" new file mode 100644 index 00000000..b871242a --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/vivado.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 13 20:23:58 2023 +# Process ID: 17340 +# Current directory: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/impl_1 +# Command line: vivado.exe -log example_5_4_1.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source example_5_4_1.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/impl_1/example_5_4_1.vdi +# Journal file: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source example_5_4_1.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/vivado.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/vivado.pb" new file mode 100644 index 00000000..1fe8ab76 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/vivado.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/write_bitstream.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/write_bitstream.pb" new file mode 100644 index 00000000..3da818b9 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/impl_1/write_bitstream.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/.Vivado_Synthesis.queue.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/.Vivado_Synthesis.queue.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/.vivado.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/.vivado.begin.rst" new file mode 100644 index 00000000..59fc9593 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/.vivado.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/.vivado.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/.vivado.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/ISEWrap.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/ISEWrap.js" new file mode 100644 index 00000000..97a2ecbc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/ISEWrap.js" @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/ISEWrap.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/ISEWrap.sh" new file mode 100644 index 00000000..f679f2e8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/ISEWrap.sh" @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/__synthesis_is_complete__" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/__synthesis_is_complete__" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1.dcp" new file mode 100644 index 00000000..ff4b86a5 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1.tcl" new file mode 100644 index 00000000..3bd1d08e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1.tcl" @@ -0,0 +1,56 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param chipscope.maxJobs 8 +set_param xicom.use_bs_reader 1 +create_project -in_memory -part xc7a75tfgg484-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.cache/wt [current_project] +set_property parent.project_path D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo d:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.v +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc +set_property used_in_implementation false [get_files D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc] + +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +synth_design -top example_5_4_1 -part xc7a75tfgg484-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef example_5_4_1.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file example_5_4_1_utilization_synth.rpt -pb example_5_4_1_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1.vds" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1.vds" new file mode 100644 index 00000000..34bc2ade --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1.vds" @@ -0,0 +1,585 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 13 20:23:34 2023 +# Process ID: 12788 +# Current directory: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/synth_1 +# Command line: vivado.exe -log example_5_4_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_5_4_1.tcl +# Log file: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1.vds +# Journal file: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source example_5_4_1.tcl -notrace +Command: synth_design -top example_5_4_1 -part xc7a75tfgg484-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a75t' +INFO: [Device 21-403] Loading part xc7a75tfgg484-1 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 13504 +WARNING: [Synth 8-2539] port sw_pin must not be declared to be an array [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.v:7] +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 857.664 ; gain = 239.641 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'example_5_4_1' [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.v:6] +INFO: [Synth 8-6155] done synthesizing module 'example_5_4_1' (1#1) [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.v:6] +WARNING: [Synth 8-3331] design example_5_4_1 has unconnected port sw_pin[6] +WARNING: [Synth 8-3331] design example_5_4_1 has unconnected port sw_pin[5] +WARNING: [Synth 8-3331] design example_5_4_1 has unconnected port sw_pin[4] +WARNING: [Synth 8-3331] design example_5_4_1 has unconnected port sw_pin[3] +WARNING: [Synth 8-3331] design example_5_4_1 has unconnected port sw_pin[2] +WARNING: [Synth 8-3331] design example_5_4_1 has unconnected port sw_pin[1] +WARNING: [Synth 8-3331] design example_5_4_1 has unconnected port sw_pin[0] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 904.277 ; gain = 286.254 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 904.277 ; gain = 286.254 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 904.277 ; gain = 286.254 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 904.277 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------系统时钟------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:1] +WARNING: [Vivado 12-584] No ports matched 'sys_clk_50m'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_100m'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:3] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:3] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_3hz'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:4] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:4] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:7] +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------拨码?关sw0~sw7----------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:19] +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------------------9个按?--------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:31] +WARNING: [Vivado 12-584] No ports matched 'btn_0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:32] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:32] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_2'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:34] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:34] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_3'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:35] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:35] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_4'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:36] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:36] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_5'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:37] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:37] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_6'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:38] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:38] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_7'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:39] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:39] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_8'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:40] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:40] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_1_IBUF'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:43] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:43] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------6个数码管-----------------------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:46] +WARNING: [Vivado 12-584] No ports matched 'digitron_out[0]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:47] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:47] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[1]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:48] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:48] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[2]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:49] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[3]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:50] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:50] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[4]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:51] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:51] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[5]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:52] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:52] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[6]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:53] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:53] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[7]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:54] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:54] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[0]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:56] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:56] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[1]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:57] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:57] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[2]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:58] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:58] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[3]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:59] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:59] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[0]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:61] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:61] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[1]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:62] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:62] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[2]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:63] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:63] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[3]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:64] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:64] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[0]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:66] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:66] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[1]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:67] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:67] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[2]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:68] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:68] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[3]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:69] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:69] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------串口---------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:73] +WARNING: [Vivado 12-584] No ports matched 'uart_rxd'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:74] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:74] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'uart_txd'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:75] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:75] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------蜂鸣?-----------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:79] +WARNING: [Vivado 12-584] No ports matched 'buzzer'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:80] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:80] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------XADC数模转换-------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:84] +WARNING: [Vivado 12-584] No ports matched 'ad15p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:85] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:85] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad15n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:86] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:86] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:87] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:87] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:88] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:88] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:89] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:89] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:90] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:90] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:91] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:91] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:92] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:92] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:93] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:93] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:94] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:94] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:95] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:95] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:96] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:96] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:97] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:97] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:98] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:98] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------DDR3L-------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:103] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:104] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:104] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:105] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:105] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:106] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:106] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:107] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:107] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:109] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:109] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq1'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:110] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:110] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq2'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:111] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:111] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq3'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:112] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:112] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq4'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:113] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:113] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq5'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:114] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:114] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq6'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:115] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:115] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq7'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:116] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:116] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq8'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:117] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:117] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq9'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:118] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:118] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq10'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:119] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:119] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq11'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:120] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:120] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq12'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:121] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:121] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq13'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:122] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:122] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq14'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:123] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:123] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq15'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:124] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:124] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:126] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:126] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a1'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:127] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:127] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a2'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:128] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:128] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a3'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:129] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:129] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a4'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:130] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:130] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a5'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:131] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:131] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a6'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:132] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:132] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a7'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:133] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:133] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a8'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:134] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:134] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a9'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:135] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:135] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a10'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:136] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:136] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a11'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:137] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:137] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a12'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:138] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:138] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:140] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:140] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba1'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:141] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:141] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba2'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:142] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:142] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:144] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:144] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm1'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:145] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:145] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_odt'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:147] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:147] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:148] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:148] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:149] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:149] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cke'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:150] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:150] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cs'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:151] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:151] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ras'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:152] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:152] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_we'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:153] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:153] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_reset'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:154] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:154] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cas'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:155] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc:155] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/ACE1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/example_5_4_1_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/example_5_4_1_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 947.652 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 947.652 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 947.652 ; gain = 329.629 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a75tfgg484-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 947.652 ; gain = 329.629 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 947.652 ; gain = 329.629 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 947.652 ; gain = 329.629 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 1 ++---Muxes : + 16 Input 8 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module example_5_4_1 +Detailed RTL Component Info : ++---Registers : + 8 Bit Registers := 1 ++---Muxes : + 16 Input 8 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 180 (col length:80) +BRAMs: 210 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3331] design example_5_4_1 has unconnected port sw_pin[6] +WARNING: [Synth 8-3331] design example_5_4_1 has unconnected port sw_pin[5] +WARNING: [Synth 8-3331] design example_5_4_1 has unconnected port sw_pin[4] +WARNING: [Synth 8-3331] design example_5_4_1 has unconnected port sw_pin[3] +WARNING: [Synth 8-3331] design example_5_4_1 has unconnected port sw_pin[2] +WARNING: [Synth 8-3331] design example_5_4_1 has unconnected port sw_pin[1] +WARNING: [Synth 8-3331] design example_5_4_1 has unconnected port sw_pin[0] +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 947.652 ; gain = 329.629 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 998.848 ; gain = 380.824 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 998.848 ; gain = 380.824 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1008.445 ; gain = 390.422 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1024.211 ; gain = 406.188 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1024.211 ; gain = 406.188 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1024.211 ; gain = 406.188 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1024.211 ; gain = 406.188 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1024.211 ; gain = 406.188 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1024.211 ; gain = 406.188 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |BUFG | 1| +|2 |LUT3 | 1| +|3 |FDRE | 4| +|4 |IBUF | 2| +|5 |OBUF | 4| +|6 |OBUFT | 4| ++------+------+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 16| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1024.211 ; gain = 406.188 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 7 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1024.211 ; gain = 362.812 +Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1024.211 ; gain = 406.188 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1024.211 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1035.699 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +12 Infos, 111 Warnings, 105 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1035.699 ; gain = 728.711 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1035.699 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file example_5_4_1_utilization_synth.rpt -pb example_5_4_1_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Mon Nov 13 20:23:51 2023... diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1_utilization_synth.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1_utilization_synth.pb" new file mode 100644 index 00000000..63b0e6b3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1_utilization_synth.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1_utilization_synth.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1_utilization_synth.rpt" new file mode 100644 index 00000000..dce086e9 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1_utilization_synth.rpt" @@ -0,0 +1,176 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:23:51 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_utilization -file example_5_4_1_utilization_synth.rpt -pb example_5_4_1_utilization_synth.pb +| Design : example_5_4_1 +| Device : 7a75tfgg484-1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 1 | 0 | 47200 | <0.01 | +| LUT as Logic | 1 | 0 | 47200 | <0.01 | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| Slice Registers | 4 | 0 | 94400 | <0.01 | +| Register as Flip Flop | 4 | 0 | 94400 | <0.01 | +| Register as Latch | 0 | 0 | 94400 | 0.00 | +| F7 Muxes | 0 | 0 | 31700 | 0.00 | +| F8 Muxes | 0 | 0 | 15850 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 4 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 105 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 105 | 0.00 | +| RAMB18 | 0 | 0 | 210 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 180 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 10 | 0 | 285 | 3.51 | +| Bonded IPADs | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 6 | 0.00 | +| PHASER_REF | 0 | 0 | 6 | 0.00 | +| OUT_FIFO | 0 | 0 | 24 | 0.00 | +| IN_FIFO | 0 | 0 | 24 | 0.00 | +| IDELAYCTRL | 0 | 0 | 6 | 0.00 | +| IBUFDS | 0 | 0 | 274 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 24 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 24 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 300 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 0 | 0 | 6 | 0.00 | +| PLLE2_ADV | 0 | 0 | 6 | 0.00 | +| BUFMRCE | 0 | 0 | 12 | 0.00 | +| BUFHCE | 0 | 0 | 96 | 0.00 | +| BUFR | 0 | 0 | 24 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUFT | 4 | IO | +| OBUF | 4 | IO | +| FDRE | 4 | Flop & Latch | +| IBUF | 2 | IO | +| LUT3 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/gen_run.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/gen_run.xml" new file mode 100644 index 00000000..43080cf2 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/gen_run.xml" @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/htr.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/htr.txt" new file mode 100644 index 00000000..be0752ae --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/htr.txt" @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log example_5_4_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_5_4_1.tcl diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/rundef.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/rundef.js" new file mode 100644 index 00000000..252a859d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/rundef.js" @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;"; +} else { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log example_5_4_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_5_4_1.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/runme.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/runme.bat" new file mode 100644 index 00000000..1760626b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/runme.bat" @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/runme.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/runme.sh" new file mode 100644 index 00000000..959ac1e7 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/runme.sh" @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin +else + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log example_5_4_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_5_4_1.tcl diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/vivado.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/vivado.jou" new file mode 100644 index 00000000..7a52b1a5 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/vivado.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 13 20:23:34 2023 +# Process ID: 12788 +# Current directory: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/synth_1 +# Command line: vivado.exe -log example_5_4_1.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_5_4_1.tcl +# Log file: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/synth_1/example_5_4_1.vds +# Journal file: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_1_ACE1/example_5_4_1_ACE1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source example_5_4_1.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/vivado.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/vivado.pb" new file mode 100644 index 00000000..ace8de80 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.runs/synth_1/vivado.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.v" new file mode 100644 index 00000000..a5edf5fa --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.v" @@ -0,0 +1,35 @@ +//Ϊʽʵ5.43λλĴ +//õ·Ϊx״̬Ϊy3y2y1ΪZCPΪʱźš + +`timescale 1ns / 1ps + +module example_5_4_1( + input sw_pin[7:0], //8 + input btn_1, //1ť + output reg [7:0] led_pin //8led +); + + always @(negedge btn_1) //Ϊʽ + + begin + case({sw_pin[7], led_pin[7], led_pin[6], led_pin[5]}) + 0: begin led_pin[7] <= 0; led_pin[6] <= 0; led_pin[5] <= 0;led_pin[0] <= 0;end + 1: begin led_pin[7] <= 0; led_pin[6] <= 1; led_pin[5] <= 0;led_pin[0] <= 1;end + 2: begin led_pin[7] <= 1; led_pin[6] <= 0; led_pin[5] <= 0;led_pin[0] <= 1;end + 3: begin led_pin[7] <= 1; led_pin[6] <= 1; led_pin[5] <= 0;led_pin[0] <= 0;end + 4: begin led_pin[7] <= 0; led_pin[6] <= 0; led_pin[5] <= 0;led_pin[0] <= 1;end + 5: begin led_pin[7] <= 0; led_pin[6] <= 1; led_pin[5] <= 0;led_pin[0] <= 0;end + 6: begin led_pin[7] <= 1; led_pin[6] <= 0; led_pin[5] <= 0;led_pin[0] <= 0;end + 7: begin led_pin[7] <= 1; led_pin[6] <= 1; led_pin[5] <= 0;led_pin[0] <= 1;end + 8: begin led_pin[7] <= 0; led_pin[6] <= 0; led_pin[5] <= 1;led_pin[0] <= 0;end + 9: begin led_pin[7] <= 0; led_pin[6] <= 1; led_pin[5] <= 1;led_pin[0] <= 1;end + 10: begin led_pin[7] <= 1; led_pin[6] <= 0; led_pin[5] <= 1;led_pin[0] <= 1;end + 11: begin led_pin[7] <= 1; led_pin[6] <= 1; led_pin[5] <= 1;led_pin[0] <= 0;end + 12: begin led_pin[7] <= 0; led_pin[6] <= 0; led_pin[5] <= 1;led_pin[0] <= 1;end + 13: begin led_pin[7] <= 0; led_pin[6] <= 1; led_pin[5] <= 1;led_pin[0] <= 0;end + 14: begin led_pin[7] <= 1; led_pin[6] <= 0; led_pin[5] <= 1;led_pin[0] <= 0;end + 15: begin led_pin[7] <= 1; led_pin[6] <= 1; led_pin[5] <= 1;led_pin[0] <= 1;end + endcase + end + +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.xpr" new file mode 100644 index 00000000..5a7a57d7 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_1_EGO1/example_5_4_1_ACE1.xpr" @@ -0,0 +1,187 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/ACE1.xdc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/ACE1.xdc" new file mode 100644 index 00000000..6347de5e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/ACE1.xdc" @@ -0,0 +1,191 @@ +//----------------------------------------------系统时钟------------------------------------ +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports sys_clk_50m] +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports sys_clk_100m] +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports sys_clk_3hz] + + +//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------ +set_property -dict {PACKAGE_PIN AA21 IOSTANDARD LVCMOS33} [get_ports {led_pin[0]}] +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports {led_pin[1]}] +set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports {led_pin[2]}] +set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports {led_pin[3]}] +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports {led_pin[4]}] +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports {led_pin[5]}] +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {led_pin[6]}] +set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {led_pin[7]}] + + + +//---------------------------------------------拨码?关sw0~sw7---------------------------------- +set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[0]}] +set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[1]}] +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {sw_pin[2]}] +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {sw_pin[3]}] +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[4]}] +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports {sw_pin[5]}] +set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports {sw_pin[6]}] +set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS33} [get_ports {sw_pin[7]}] + + + +//-----------------------------------------------9个按?-------------------------------------- +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports btn_0] +set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports btn_1] +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports btn_2] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports btn_3] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33} [get_ports btn_4] +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports btn_5] +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports btn_6] +set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports btn_7] +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports btn_8] + + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_1_IBUF] + + +//-----------------------------------6个数码管----------------------------------------------------------- +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[0]}] +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[1]}] +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[2]}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {digitron_out[3]}] +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS33} [get_ports {digitron_out[4]}] +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {digitron_out[5]}] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {digitron_out[6]}] +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {digitron_out[7]}] + +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[0]}] +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[1]}] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[2]}] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {digitroncs_out[3]}] + +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {digitron_a[0]}] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[1]}] +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {digitron_a[2]}] +set_property -dict {PACKAGE_PIN AB18 IOSTANDARD LVCMOS33} [get_ports {digitron_a[3]}] + +set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33} [get_ports {digitron_b[0]}] +set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[1]}] +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {digitron_b[2]}] +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports {digitron_b[3]}] + + + +//----------------------------------------------串口--------------------------------------------- +set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports uart_rxd] +set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports uart_txd] + + + +//----------------------------------------------蜂鸣?----------------------------------------- +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports buzzer] + + + +//--------------------------------------------------------XADC数模转换------------------- +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports ad15p] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports ad15n] +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports ad7p] +set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports ad7n] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports ad14p] +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports ad14n] +set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports ad6p] +set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports ad6n] +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports ad5p] +set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS33} [get_ports ad5n] +set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports ad13p] +set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports ad13n] +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports ad4p] +set_property -dict {PACKAGE_PIN A1 IOSTANDARD LVCMOS33} [get_ports ad4n] + + + + +//--------------------------------------------------------DDR3L------------------------------------- +set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_p] +set_property -dict {PACKAGE_PIN AA3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs0_n] +set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_p] +set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dqs1_n] + +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq0] +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq1] +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq2] +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq3] +set_property -dict {PACKAGE_PIN AA5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq4] +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq5] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq6] +set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq7] +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq8] +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq9] +set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq10] +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq11] +set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq12] +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq13] +set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq14] +set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports ddr3l_dq15] + +set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a0] +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a1] +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a2] +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports ddr3l_a3] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a4] +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a5] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a6] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS33} [get_ports ddr3l_a7] +set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports ddr3l_a8] +set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports ddr3l_a9] +set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a10] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a11] +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports ddr3l_a12] + +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba0] +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba1] +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ba2] + +set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm0] +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS33} [get_ports ddr3l_dm1] + +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports ddr3l_odt] +set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_p] +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS33} [get_ports ddr3l_clk_n] +set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cke] +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports ddr3l_cs] +set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports ddr3l_ras] +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS33} [get_ports ddr3l_we] +set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports ddr3l_reset] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports ddr3l_cas] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/gui_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/gui_handlers.wdf" new file mode 100644 index 00000000..d7558a40 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/gui_handlers.wdf" @@ -0,0 +1,25 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f6f725f6372656174655f636f6e73747261696e745f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f796573:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6e73747261696e747363686f6f73657270616e656c5f6164645f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:3131:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6372656174655f6e65775f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:34:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6175746f5f636f6e6e6563745f746172676574:32:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f70726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f64617368626f617264:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:33:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d64656275677461625f6f70656e5f746172676574:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6772616d667067616469616c6f675f70726f6772616d:35:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f68646c5f616e645f6e65746c6973745f66696c65735f746f5f796f75725f70726f6a656374:31:00:00 +eof:3956430967 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/java_command_handlers.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/java_command_handlers.wdf" new file mode 100644 index 00000000..8df56fa7 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/java_command_handlers.wdf" @@ -0,0 +1,14 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6175746f636f6e6e656374746172676574:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6c61756e636870726f6772616d66706761:35:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e68617264776172656d616e61676572:38:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e726563656e74746172676574:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:70726f6772616d646576696365:35:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e62697467656e:33:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:32:00:00 +eof:2672888466 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/project.wpc" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/project.wpc" new file mode 100644 index 00000000..01202261 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/project.wpc" @@ -0,0 +1,4 @@ +version:1 +57656254616c6b5472616e736d697373696f6e417474656d70746564:2 +6d6f64655f636f756e7465727c4755494d6f6465:3 +eof: diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/synthesis.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/synthesis.wdf" new file mode 100644 index 00000000..b8c7ed66 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/synthesis.wdf" @@ -0,0 +1,39 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:786337613735746667673438342d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:6578616d706c655f355f34:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f6970:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c5f736b69705f636f6e73747261696e7473:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f6c63:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f647370:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f6272616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d61785f7572616d5f636173636164655f686569676874:64656661756c743a3a2d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d726574696d696e67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f73726c65787472616374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313473:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313032342e3135324d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3639332e3530384d42:00:00 +eof:4034082574 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/synthesis_details.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/synthesis_details.wdf" new file mode 100644 index 00000000..78f8d66e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/synthesis_details.wdf" @@ -0,0 +1,3 @@ +version:1 +73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 +eof:2511430288 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/webtalk_pa.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/webtalk_pa.xml" new file mode 100644 index 00000000..00af0765 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.cache/wt/webtalk_pa.xml" @@ -0,0 +1,65 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.hw/example_5_4_ACE1.lpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.hw/example_5_4_ACE1.lpr" new file mode 100644 index 00000000..b7d45757 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.hw/example_5_4_ACE1.lpr" @@ -0,0 +1,8 @@ + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.hw/hw_1/hw.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.hw/hw_1/hw.xml" new file mode 100644 index 00000000..5ff558da --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.hw/hw_1/hw.xml" @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.hw/webtalk/.xsim_webtallk.info" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.hw/webtalk/.xsim_webtallk.info" new file mode 100644 index 00000000..4804dbb1 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.hw/webtalk/.xsim_webtallk.info" @@ -0,0 +1,5 @@ +1699877525 +0 +2 +0 +1471ffd8-bb23-4806-96b9-c88dcf13e9ff diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.hw/webtalk/usage_statistics_ext_labtool.html" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.hw/webtalk/usage_statistics_ext_labtool.html" new file mode 100644 index 00000000..05c0c867 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.hw/webtalk/usage_statistics_ext_labtool.html" @@ -0,0 +1,45 @@ +Device Usage Statistics Report +

LABTOOL Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2708876
date_generatedMon Nov 13 20:12:05 2023os_platformWIN64
product_versionVivado v2019.2 (64-bit)project_id1471ffd8-bb23-4806-96b9-c88dcf13e9ff
project_iteration1random_idd24833b7-4cbd-4f74-b7c7-3cb815d77764
registration_idd24833b7-4cbd-4f74-b7c7-3cb815d77764route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowlabtool

+ + + + + + + + +
user_environment
cpu_nameAMD Ryzen 9 7945HX with Radeon Graphics cpu_speed2495 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram16.000 GBtotal_processors1

+ + +
vivado_usage

+ + + +
labtool
+ + + + + +
usage
cable=XilinxA/TULA/15000000:chain=13632093pgmcnt=03:00:00
+

+ + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.hw/webtalk/usage_statistics_ext_labtool.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.hw/webtalk/usage_statistics_ext_labtool.xml" new file mode 100644 index 00000000..06020cb5 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.hw/webtalk/usage_statistics_ext_labtool.xml" @@ -0,0 +1,39 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+ + + +
+
+
+
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.Vivado_Implementation.queue.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.Vivado_Implementation.queue.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.init_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.init_design.begin.rst" new file mode 100644 index 00000000..3a53b864 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.init_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.init_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.init_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.opt_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.opt_design.begin.rst" new file mode 100644 index 00000000..3a53b864 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.opt_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.opt_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.opt_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.phys_opt_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.phys_opt_design.begin.rst" new file mode 100644 index 00000000..3a53b864 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.phys_opt_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.phys_opt_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.phys_opt_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.place_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.place_design.begin.rst" new file mode 100644 index 00000000..3a53b864 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.place_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.place_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.place_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.route_design.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.route_design.begin.rst" new file mode 100644 index 00000000..3a53b864 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.route_design.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.route_design.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.route_design.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.vivado.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.vivado.begin.rst" new file mode 100644 index 00000000..98e398d0 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.vivado.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.vivado.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.vivado.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.write_bitstream.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.write_bitstream.begin.rst" new file mode 100644 index 00000000..3a53b864 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.write_bitstream.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.write_bitstream.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/.write_bitstream.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/ISEWrap.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/ISEWrap.js" new file mode 100644 index 00000000..97a2ecbc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/ISEWrap.js" @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/ISEWrap.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/ISEWrap.sh" new file mode 100644 index 00000000..f679f2e8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/ISEWrap.sh" @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4.bit" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4.bit" new file mode 100644 index 00000000..be9898aa Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4.bit" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4.tcl" new file mode 100644 index 00000000..8e486c1a --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4.tcl" @@ -0,0 +1,187 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param chipscope.maxJobs 8 + set_param xicom.use_bs_reader 1 + create_project -in_memory -part xc7a75tfgg484-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.cache/wt [current_project] + set_property parent.project_path D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.xpr [current_project] + set_property ip_output_repo D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/synth_1/example_5_4.dcp + read_xdc D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc + link_design -top example_5_4 -part xc7a75tfgg484-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force example_5_4_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file example_5_4_drc_opted.rpt -pb example_5_4_drc_opted.pb -rpx example_5_4_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force example_5_4_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file example_5_4_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file example_5_4_utilization_placed.rpt -pb example_5_4_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file example_5_4_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step phys_opt_design +set ACTIVE_STEP phys_opt_design +set rc [catch { + create_msg_db phys_opt_design.pb + phys_opt_design + write_checkpoint -force example_5_4_physopt.dcp + close_msg_db -file phys_opt_design.pb +} RESULT] +if {$rc} { + step_failed phys_opt_design + return -code error $RESULT +} else { + end_step phys_opt_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force example_5_4_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file example_5_4_drc_routed.rpt -pb example_5_4_drc_routed.pb -rpx example_5_4_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file example_5_4_methodology_drc_routed.rpt -pb example_5_4_methodology_drc_routed.pb -rpx example_5_4_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file example_5_4_power_routed.rpt -pb example_5_4_power_summary_routed.pb -rpx example_5_4_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file example_5_4_route_status.rpt -pb example_5_4_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file example_5_4_timing_summary_routed.rpt -pb example_5_4_timing_summary_routed.pb -rpx example_5_4_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file example_5_4_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file example_5_4_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file example_5_4_bus_skew_routed.rpt -pb example_5_4_bus_skew_routed.pb -rpx example_5_4_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force example_5_4_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + catch { write_mem_info -force example_5_4.mmi } + write_bitstream -force example_5_4.bit + catch {write_debug_probes -quiet -force example_5_4} + catch {file copy -force example_5_4.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4.vdi" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4.vdi" new file mode 100644 index 00000000..43582949 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4.vdi" @@ -0,0 +1,829 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 13 20:43:14 2023 +# Process ID: 14652 +# Current directory: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/impl_1 +# Command line: vivado.exe -log example_5_4.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source example_5_4.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/impl_1/example_5_4.vdi +# Journal file: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source example_5_4.tcl -notrace +Command: link_design -top example_5_4 -part xc7a75tfgg484-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7a75tfgg484-1 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 620.969 ; gain = 0.000 +INFO: [Project 1-479] Netlist was created with Vivado 2019.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------系统时钟------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:1] +WARNING: [Vivado 12-584] No ports matched 'sys_clk_50m'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_100m'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:3] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:3] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_3hz'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:4] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:4] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:7] +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------拨码?关sw0~sw7----------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:19] +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------------------9个按?--------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:31] +WARNING: [Vivado 12-584] No ports matched 'btn_0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:32] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:32] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_2'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:34] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:34] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_3'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:35] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:35] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_4'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:36] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:36] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_5'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:37] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:37] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_6'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:38] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:38] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_7'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:39] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:39] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_8'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:40] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:40] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------6个数码管-----------------------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:46] +WARNING: [Vivado 12-584] No ports matched 'digitron_out[0]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:47] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:47] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[1]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:48] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:48] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[2]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:49] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[3]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:50] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:50] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[4]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:51] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:51] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[5]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:52] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:52] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[6]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:53] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:53] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[7]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:54] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:54] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[0]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:56] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:56] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[1]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:57] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:57] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[2]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:58] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:58] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[3]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:59] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:59] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[0]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:61] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:61] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[1]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:62] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:62] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[2]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:63] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:63] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[3]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:64] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:64] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[0]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:66] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:66] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[1]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:67] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:67] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[2]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:68] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:68] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[3]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:69] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:69] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------串口---------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:73] +WARNING: [Vivado 12-584] No ports matched 'uart_rxd'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:74] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:74] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'uart_txd'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:75] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:75] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------蜂鸣?-----------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:79] +WARNING: [Vivado 12-584] No ports matched 'buzzer'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:80] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:80] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------XADC数模转换-------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:84] +WARNING: [Vivado 12-584] No ports matched 'ad15p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:85] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:85] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad15n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:86] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:86] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:87] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:87] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:88] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:88] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:89] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:89] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:90] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:90] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:91] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:91] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:92] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:92] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:93] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:93] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:94] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:94] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:95] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:95] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:96] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:96] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:97] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:97] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:98] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:98] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------DDR3L-------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:103] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:104] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:104] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:105] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:105] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:106] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:106] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:107] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:107] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:109] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:109] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq1'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:110] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:110] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq2'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:111] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:111] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq3'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:112] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:112] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq4'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:113] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:113] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq5'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:114] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:114] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq6'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:115] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:115] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq7'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:116] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:116] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq8'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:117] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:117] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq9'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:118] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:118] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq10'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:119] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:119] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq11'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:120] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:120] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq12'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:121] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:121] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq13'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:122] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:122] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq14'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:123] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:123] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq15'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:124] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:124] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:126] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:126] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a1'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:127] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:127] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a2'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:128] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:128] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a3'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:129] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:129] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a4'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:130] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:130] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a5'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:131] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:131] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a6'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:132] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:132] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a7'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:133] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:133] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a8'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:134] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:134] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a9'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:135] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:135] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a10'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:136] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:136] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a11'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:137] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:137] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a12'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:138] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:138] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:140] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:140] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba1'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:141] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:141] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba2'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:142] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:142] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:144] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:144] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm1'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:145] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:145] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_odt'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:147] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:147] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:148] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:148] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:149] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:149] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cke'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:150] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:150] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cs'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:151] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:151] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ras'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:152] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:152] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_we'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:153] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:153] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_reset'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:154] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:154] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cas'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:155] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:155] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 729.750 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +5 Infos, 95 Warnings, 104 Critical Warnings and 0 Errors encountered. +link_design completed successfully +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.300 . Memory (MB): peak = 754.434 ; gain = 20.715 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 190b3f7ad + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1281.371 ; gain = 526.938 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 190b3f7ad + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1474.922 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 190b3f7ad + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1474.922 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 22b7d5054 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1474.922 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 2 cells and removed 0 cells + +Phase 4 BUFG optimization +INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common MMCM/DPLL/XPLL driver. +INFO: [Opt 31-1112] Starts optimizing BUFG(s) with a common driver. +INFO: [Opt 31-1092] Phase BUFG optimization transformed 0 BUFG(s) to MBUFG(s). +Phase 4 BUFG optimization | Checksum: 22b7d5054 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1474.922 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 22b7d5054 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1474.922 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 22b7d5054 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1474.922 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 2 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1474.922 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 26cf29f00 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 26cf29f00 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 26cf29f00 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1474.922 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 26cf29f00 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1474.922 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +25 Infos, 95 Warnings, 104 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1474.922 ; gain = 741.203 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1474.922 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1474.922 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/impl_1/example_5_4_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file example_5_4_drc_opted.rpt -pb example_5_4_drc_opted.pb -rpx example_5_4_drc_opted.rpx +Command: report_drc -file example_5_4_drc_opted.rpt -pb example_5_4_drc_opted.pb -rpx example_5_4_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1474.922 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 18af9f078 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1474.922 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. + + btn_1_IBUF_inst (IBUF.O) is locked to IOB_X1Y146 + btn_1_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 +Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: c05128f9 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.323 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 10d12f6d2 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.329 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 10d12f6d2 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.329 . Memory (MB): peak = 1474.922 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 10d12f6d2 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.331 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 10d12f6d2 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.331 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Phase 2.2 Global Placement Core +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2.2 Global Placement Core | Checksum: 113693a0c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.493 . Memory (MB): peak = 1474.922 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 113693a0c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.495 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 113693a0c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.496 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 16a8b6a35 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.499 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 108eeed79 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.503 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 108eeed79 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.503 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: f0c43822 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.577 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: f0c43822 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.578 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: f0c43822 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.578 . Memory (MB): peak = 1474.922 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: f0c43822 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.578 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: f0c43822 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.579 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: f0c43822 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.581 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: f0c43822 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.581 . Memory (MB): peak = 1474.922 ; gain = 0.000 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1474.922 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: f0c43822 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.581 . Memory (MB): peak = 1474.922 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: f0c43822 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.581 . Memory (MB): peak = 1474.922 ; gain = 0.000 +Ending Placer Task | Checksum: bc8aa41d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.581 . Memory (MB): peak = 1474.922 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +43 Infos, 97 Warnings, 104 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1474.922 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1477.852 ; gain = 2.930 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/impl_1/example_5_4_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file example_5_4_io_placed.rpt +report_io: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1477.852 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file example_5_4_utilization_placed.rpt -pb example_5_4_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file example_5_4_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1477.852 ; gain = 0.000 +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +51 Infos, 97 Warnings, 104 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1483.195 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1501.062 ; gain = 17.867 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/impl_1/example_5_4_physopt.dcp' has been generated. +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. +Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. + This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. + + btn_1_IBUF_inst (IBUF.O) is locked to IOB_X1Y146 + btn_1_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: 43e3222 ConstDB: 0 ShapeSum: b84c71fb RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 12138289b + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1626.289 ; gain = 115.117 +Post Restoration Checksum: NetGraph: 722ab909 NumContArr: af0d6f92 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 12138289b + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1632.250 ; gain = 121.078 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 12138289b + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 1632.250 ; gain = 121.078 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: f46798d3 + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1639.254 ; gain = 128.082 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 8 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 8 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 1f7ffb18e + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1641.125 ; gain = 129.953 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: 2af18b3f + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1641.125 ; gain = 129.953 +Phase 4 Rip-up And Reroute | Checksum: 2af18b3f + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1641.125 ; gain = 129.953 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: 2af18b3f + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1641.125 ; gain = 129.953 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: 2af18b3f + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1641.125 ; gain = 129.953 +Phase 6 Post Hold Fix | Checksum: 2af18b3f + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1641.125 ; gain = 129.953 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.00313357 % + Global Horizontal Routing Utilization = 0.00262859 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: 2af18b3f + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1641.125 ; gain = 129.953 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 2af18b3f + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1643.168 ; gain = 131.996 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 43a3231d + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1643.168 ; gain = 131.996 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 1643.168 ; gain = 131.996 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +61 Infos, 98 Warnings, 104 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:15 . Memory (MB): peak = 1643.168 ; gain = 142.105 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1643.168 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1653.078 ; gain = 9.910 +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/impl_1/example_5_4_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file example_5_4_drc_routed.rpt -pb example_5_4_drc_routed.pb -rpx example_5_4_drc_routed.rpx +Command: report_drc -file example_5_4_drc_routed.rpt -pb example_5_4_drc_routed.pb -rpx example_5_4_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file example_5_4_methodology_drc_routed.rpt -pb example_5_4_methodology_drc_routed.pb -rpx example_5_4_methodology_drc_routed.rpx +Command: report_methodology -file example_5_4_methodology_drc_routed.rpt -pb example_5_4_methodology_drc_routed.pb -rpx example_5_4_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/impl_1/example_5_4_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file example_5_4_power_routed.rpt -pb example_5_4_power_summary_routed.pb -rpx example_5_4_power_routed.rpx +Command: report_power -file example_5_4_power_routed.rpt -pb example_5_4_power_summary_routed.pb -rpx example_5_4_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +73 Infos, 99 Warnings, 104 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file example_5_4_route_status.rpt -pb example_5_4_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file example_5_4_timing_summary_routed.rpt -pb example_5_4_timing_summary_routed.pb -rpx example_5_4_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file example_5_4_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file example_5_4_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file example_5_4_bus_skew_routed.rpt -pb example_5_4_bus_skew_routed.pb -rpx example_5_4_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force example_5_4.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a75t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./example_5_4.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +92 Infos, 101 Warnings, 104 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2137.172 ; gain = 455.586 +INFO: [Common 17-206] Exiting Vivado at Mon Nov 13 20:43:51 2023... diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_bus_skew_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_bus_skew_routed.pb" new file mode 100644 index 00000000..3390588d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_bus_skew_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_bus_skew_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_bus_skew_routed.rpt" new file mode 100644 index 00000000..ba506356 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_bus_skew_routed.rpt" @@ -0,0 +1,15 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:43:43 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file example_5_4_bus_skew_routed.rpt -pb example_5_4_bus_skew_routed.pb -rpx example_5_4_bus_skew_routed.rpx +| Design : example_5_4 +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +------------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Bus Skew Report + +No bus skew constraints + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_bus_skew_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_bus_skew_routed.rpx" new file mode 100644 index 00000000..1fc46f45 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_bus_skew_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_clock_utilization_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_clock_utilization_routed.rpt" new file mode 100644 index 00000000..e84f0f0c --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_clock_utilization_routed.rpt" @@ -0,0 +1,150 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:43:43 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_clock_utilization -file example_5_4_clock_utilization_routed.rpt +| Design : example_5_4 +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +----------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X0Y1 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 96 | 0 | 0 | 0 | +| BUFIO | 0 | 24 | 0 | 0 | 0 | +| BUFMR | 0 | 12 | 0 | 0 | 0 | +| BUFR | 0 | 24 | 0 | 0 | 0 | +| MMCM | 0 | 6 | 0 | 0 | 0 | +| PLL | 0 | 6 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+------------------------+-----------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+------------------------+-----------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 5 | 0 | | | btn_1_IBUF_BUFG_inst/O | btn_1_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+------------------------+-----------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-------------------+------------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-------------------+------------+ +| src0 | g0 | IBUF/O | IOB_X1Y146 | IOB_X1Y146 | X1Y2 | 1 | 0 | | | btn_1_IBUF_inst/O | btn_1_IBUF | ++-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-------------------+------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1500 | 0 | 550 | 0 | 40 | 0 | 20 | 0 | 40 | +| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 5 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1350 | 0 | 500 | 0 | 30 | 0 | 15 | 0 | 40 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 1 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------+ +| g0 | BUFG/O | n/a | | | | 5 | 0 | 0 | 0 | btn_1_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------+ +* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 5 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + +7. Clock Region Cell Placement per Global Clock: Region X0Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-----------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-----------------+ +| g0 | n/a | BUFG/O | None | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | btn_1_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-----------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells btn_1_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X1Y146 [get_ports btn_1] + +# Clock net "btn_1_IBUF_BUFG" driven by instance "btn_1_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_btn_1_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_btn_1_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="btn_1_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_btn_1_IBUF_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1} +#endgroup diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_control_sets_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_control_sets_placed.rpt" new file mode 100644 index 00000000..a7e6dfc3 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_control_sets_placed.rpt" @@ -0,0 +1,79 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:43:27 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file example_5_4_control_sets_placed.rpt +| Design : example_5_4 +| Device : xc7a75t +---------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Total control sets | 1 | +| Minimum number of control sets | 1 | +| Addition due to synthesis replication | 0 | +| Addition due to physical synthesis replication | 0 | +| Unused register locations in slices containing registers | 3 | ++----------------------------------------------------------+-------+ +* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers +** Run report_qor_suggestions for automated merging and remapping suggestions + + +2. Histogram +------------ + ++--------------------+-------+ +| Fanout | Count | ++--------------------+-------+ +| Total control sets | 1 | +| >= 0 to < 4 | 0 | +| >= 4 to < 6 | 1 | +| >= 6 to < 8 | 0 | +| >= 8 to < 10 | 0 | +| >= 10 to < 12 | 0 | +| >= 12 to < 14 | 0 | +| >= 14 to < 16 | 0 | +| >= 16 | 0 | ++--------------------+-------+ +* Control sets can be remapped at either synth_design or opt_design + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 5 | 5 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++------------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++------------------+---------------+------------------+------------------+----------------+ +| ~btn_1_IBUF_BUFG | | | 5 | 5 | ++------------------+---------------+------------------+------------------+----------------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_opted.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_opted.pb" new file mode 100644 index 00000000..5aa0de05 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_opted.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_opted.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_opted.rpt" new file mode 100644 index 00000000..13ffa6ef --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_opted.rpt" @@ -0,0 +1,61 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:43:26 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_drc -file example_5_4_drc_opted.rpt -pb example_5_4_drc_opted.pb -rpx example_5_4_drc_opted.rpx +| Design : example_5_4 +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 2 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| PLCK-12 | Warning | Clock Placer Checks | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +PLCK-12#1 Warning +Clock Placer Checks +Poor placement for routing between an IO pin and BUFG. +Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. + This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. + + btn_1_IBUF_inst (IBUF.O) is locked to C2 + btn_1_IBUF_BUFG_inst (BUFG.I) cannot be placed + +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_opted.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_opted.rpx" new file mode 100644 index 00000000..4c365cb4 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_opted.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_routed.pb" new file mode 100644 index 00000000..5aa0de05 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_routed.rpt" new file mode 100644 index 00000000..ca1df90e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_routed.rpt" @@ -0,0 +1,61 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:43:43 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_drc -file example_5_4_drc_routed.rpt -pb example_5_4_drc_routed.pb -rpx example_5_4_drc_routed.rpx +| Design : example_5_4 +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Fully Routed +--------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 2 ++----------+----------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+----------+-----------------------------------------------------+------------+ +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | +| PLCK-12 | Warning | Clock Placer Checks | 1 | ++----------+----------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +PLCK-12#1 Warning +Clock Placer Checks +Poor placement for routing between an IO pin and BUFG. +Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. + This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. + + btn_1_IBUF_inst (IBUF.O) is locked to C2 + btn_1_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 + +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_routed.rpx" new file mode 100644 index 00000000..5540ed36 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_drc_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_io_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_io_placed.rpt" new file mode 100644 index 00000000..3deed7f3 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_io_placed.rpt" @@ -0,0 +1,526 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:43:27 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_io -file example_5_4_io_placed.rpt +| Design : example_5_4 +| Device : xc7a75t +| Speed File : -1 +| Package : fgg484 +| Package Version : FINAL 2012-11-02 +| Package Pin Delay Version : VERS. 2.0 2012-11-02 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 17 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A4 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A6 | | | MGTPTXN2_216 | Gigabit | | | | | | | | | | | | | | | | +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A8 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A10 | | | MGTPRXN2_216 | Gigabit | | | | | | | | | | | | | | | | +| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A19 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A20 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| A21 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA3 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA4 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| AA8 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA9 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA10 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA11 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA13 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA14 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA15 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA16 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| AA18 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| AA19 | sw_pin[0] | High Range | IO_L15P_T2_DQS_RDWR_B_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| AA20 | led_pin[1] | High Range | IO_L8P_T1_D11_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| AA21 | led_pin[0] | High Range | IO_L8N_T1_D12_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB2 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB3 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| AB5 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB8 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB10 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB11 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB12 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB13 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| AB15 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB16 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB17 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB20 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| AB21 | sw_pin[7] | High Range | IO_L10P_T1_D14_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| AB22 | sw_pin[6] | High Range | IO_L10N_T1_D15_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| B1 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B4 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| B5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B6 | | | MGTPTXP2_216 | Gigabit | | | | | | | | | | | | | | | | +| B7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B8 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| B9 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B10 | | | MGTPRXP2_216 | Gigabit | | | | | | | | | | | | | | | | +| B11 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| B15 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B16 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B20 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| B21 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| B22 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| C1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C2 | btn_1 | High Range | IO_L2P_T0_AD12P_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | | +| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C4 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C5 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C7 | | | MGTPTXN3_216 | Gigabit | | | | | | | | | | | | | | | | +| C8 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C9 | | | MGTPRXN3_216 | Gigabit | | | | | | | | | | | | | | | | +| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C11 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| C12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| C14 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C18 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C19 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C20 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| C21 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C22 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| D2 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D5 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| D6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| D7 | | | MGTPTXP3_216 | Gigabit | | | | | | | | | | | | | | | | +| D8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D9 | | | MGTPRXP3_216 | Gigabit | | | | | | | | | | | | | | | | +| D10 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| D11 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D14 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| D16 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| D17 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| D19 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D20 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D21 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D22 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E6 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | | +| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E8 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | | +| E11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E12 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E14 | | High Range | IO_L4N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E15 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| E16 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L2N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| E19 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E21 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| E22 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F6 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | | +| F7 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| F8 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | | +| F9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| F10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| F13 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F15 | | High Range | IO_0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L2P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| F19 | | High Range | IO_L18P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| F20 | | High Range | IO_L18N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| F21 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | | +| F22 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| G1 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G15 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| G16 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G19 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G20 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G21 | | High Range | IO_L24P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| G22 | | High Range | IO_L24N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| H1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H2 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| H4 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| H6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| H14 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| H17 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H19 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H20 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H22 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| J1 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J2 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J4 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| J6 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J14 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J17 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J19 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J20 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J21 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| J22 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| K4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K6 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K16 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| K19 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| K20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K21 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| K22 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| L4 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| L5 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| L6 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| L12 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| L13 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| L18 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| L19 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| L20 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| L21 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M1 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| M4 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| M5 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| M6 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| M10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| M14 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| M15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| M16 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| M17 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| M21 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| M22 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| N1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| N2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N3 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| N4 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| N12 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| N13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| N14 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| N19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| N20 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| N21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| N22 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| P1 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P2 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| P5 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| P6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P14 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| P19 | led_pin[6] | High Range | IO_L5P_T0_D06_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P20 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| P21 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| P22 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| R2 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| R6 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| R7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R13 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| R14 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| R15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| R16 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| R19 | led_pin[5] | High Range | IO_L5N_T0_D07_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R21 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| R22 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| T3 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| T13 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| T19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T20 | led_pin[4] | High Range | IO_L6N_T0_D08_VREF_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T21 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| T22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U5 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U6 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| U7 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| U9 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| U10 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| U11 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| U12 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| U13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U15 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| U16 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| U19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U20 | sw_pin[5] | High Range | IO_L11P_T1_SRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| U21 | led_pin[7] | High Range | IO_L4N_T0_D05_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U22 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V2 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| V4 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| V7 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V10 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V12 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| V13 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V14 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| V17 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | sw_pin[2] | High Range | IO_L14P_T2_SRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| V19 | sw_pin[1] | High Range | IO_L14N_T2_SRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| V20 | sw_pin[4] | High Range | IO_L11N_T1_SRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V22 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| W1 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W2 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| W4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W5 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W6 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| W7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W9 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| W10 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| W11 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W12 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W13 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| W14 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| W15 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| W16 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| W17 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| W20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| W21 | led_pin[3] | High Range | IO_L7P_T1_D09_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| W22 | led_pin[2] | High Range | IO_L7N_T1_D10_14 | TRISTATE | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| Y1 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y3 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y4 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y7 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y8 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y9 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y10 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | | +| Y11 | | High Range | IO_L11P_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y12 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y13 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y14 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y16 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y17 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| Y19 | sw_pin[3] | High Range | IO_L13N_T2_MRCC_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| Y20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| Y21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| Y22 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_methodology_drc_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_methodology_drc_routed.pb" new file mode 100644 index 00000000..5f8a2d9e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_methodology_drc_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_methodology_drc_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_methodology_drc_routed.rpt" new file mode 100644 index 00000000..eae652dd --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_methodology_drc_routed.rpt" @@ -0,0 +1,60 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:43:43 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_methodology -file example_5_4_methodology_drc_routed.rpt -pb example_5_4_methodology_drc_routed.pb -rpx example_5_4_methodology_drc_routed.rpx +| Design : example_5_4 +| Device : xc7a75tfgg484-1 +| Speed File : -1 +| Design State : Fully Routed +----------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 5 ++-----------+------------------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+------------------+-----------------------------+------------+ +| TIMING-17 | Critical Warning | Non-clocked sequential cell | 5 | ++-----------+------------------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Critical Warning +Non-clocked sequential cell +The clock pin U2/y_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Critical Warning +Non-clocked sequential cell +The clock pin U4/y_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Critical Warning +Non-clocked sequential cell +The clock pin U4/y_reg_lopt_replica/C is not reached by a timing clock +Related violations: + +TIMING-17#4 Critical Warning +Non-clocked sequential cell +The clock pin U6/y_reg/C is not reached by a timing clock +Related violations: + +TIMING-17#5 Critical Warning +Non-clocked sequential cell +The clock pin U6/y_reg_lopt_replica/C is not reached by a timing clock +Related violations: + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_methodology_drc_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_methodology_drc_routed.rpx" new file mode 100644 index 00000000..cdbd4c77 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_methodology_drc_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_opt.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_opt.dcp" new file mode 100644 index 00000000..5ac1932a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_opt.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_physopt.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_physopt.dcp" new file mode 100644 index 00000000..bef263aa Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_physopt.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_placed.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_placed.dcp" new file mode 100644 index 00000000..d8bb9102 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_placed.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_power_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_power_routed.rpt" new file mode 100644 index 00000000..765f4fda --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_power_routed.rpt" @@ -0,0 +1,146 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:43:43 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_power -file example_5_4_power_routed.rpt -pb example_5_4_power_summary_routed.pb -rpx example_5_4_power_routed.rpx +| Design : example_5_4 +| Device : xc7a75tfgg484-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 4.033 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 3.927 | +| Device Static (W) | 0.106 | +| Effective TJA (C/W) | 2.7 | +| Max Ambient (C) | 74.2 | +| Junction Temperature (C) | 35.8 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.010 | 15 | --- | --- | +| BUFG | 0.006 | 1 | 32 | 3.13 | +| LUT as Logic | 0.003 | 1 | 47200 | <0.01 | +| Register | 0.001 | 5 | 94400 | <0.01 | +| Others | 0.000 | 8 | --- | --- | +| Signals | 0.037 | 9 | --- | --- | +| I/O | 3.879 | 10 | 285 | 3.51 | +| Static Power | 0.106 | | | | +| Total | 4.033 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.078 | 0.055 | 0.023 | +| Vccaux | 1.800 | 0.161 | 0.142 | 0.019 | +| Vcco33 | 3.300 | 1.100 | 1.096 | 0.004 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | High | User specified more than 25% of internal nodes | | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 2.7 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++-------------+-----------+ +| Name | Power (W) | ++-------------+-----------+ +| example_5_4 | 3.927 | +| U2 | 0.006 | +| U4 | 0.017 | +| U6 | 0.004 | ++-------------+-----------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_power_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_power_routed.rpx" new file mode 100644 index 00000000..afeb0675 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_power_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_power_summary_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_power_summary_routed.pb" new file mode 100644 index 00000000..1f12c62c Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_power_summary_routed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_route_status.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_route_status.pb" new file mode 100644 index 00000000..cac3c427 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_route_status.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_route_status.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_route_status.rpt" new file mode 100644 index 00000000..24d7117e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_route_status.rpt" @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 21 : + # of nets not needing routing.......... : 10 : + # of internally routed nets........ : 10 : + # of routable nets..................... : 11 : + # of fully routed nets............. : 11 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_routed.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_routed.dcp" new file mode 100644 index 00000000..b87f37ca Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_routed.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_timing_summary_routed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_timing_summary_routed.pb" new file mode 100644 index 00000000..4526e931 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_timing_summary_routed.pb" @@ -0,0 +1,2 @@ + +2012.4)Timing analysis from Implemented netlist. \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_timing_summary_routed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_timing_summary_routed.rpt" new file mode 100644 index 00000000..814915dc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_timing_summary_routed.rpt" @@ -0,0 +1,175 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:43:43 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file example_5_4_timing_summary_routed.rpt -pb example_5_4_timing_summary_routed.pb -rpx example_5_4_timing_summary_routed.rpx -warn_on_violation +| Design : example_5_4 +| Device : 7a75t-fgg484 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 5 register/latch pins with no clock driven by root clock pin: btn_1 (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 5 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There is 1 input port with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 4 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_timing_summary_routed.rpx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_timing_summary_routed.rpx" new file mode 100644 index 00000000..3d03d768 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_timing_summary_routed.rpx" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_utilization_placed.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_utilization_placed.pb" new file mode 100644 index 00000000..ee778674 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_utilization_placed.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_utilization_placed.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_utilization_placed.rpt" new file mode 100644 index 00000000..a289aeba --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/example_5_4_utilization_placed.rpt" @@ -0,0 +1,204 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:43:27 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_utilization -file example_5_4_utilization_placed.rpt -pb example_5_4_utilization_placed.pb +| Design : example_5_4 +| Device : 7a75tfgg484-1 +| Design State : Fully Placed +------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 1 | 0 | 47200 | <0.01 | +| LUT as Logic | 1 | 0 | 47200 | <0.01 | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| Slice Registers | 5 | 0 | 94400 | <0.01 | +| Register as Flip Flop | 5 | 0 | 94400 | <0.01 | +| Register as Latch | 0 | 0 | 94400 | 0.00 | +| F7 Muxes | 0 | 0 | 31700 | 0.00 | +| F8 Muxes | 0 | 0 | 15850 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 5 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++--------------------------------------------+------+-------+-----------+-------+ +| Slice | 5 | 0 | 15850 | 0.03 | +| SLICEL | 5 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 1 | 0 | 47200 | <0.01 | +| using O5 output only | 0 | | | | +| using O6 output only | 1 | | | | +| using O5 and O6 | 0 | | | | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 5 | 0 | 94400 | <0.01 | +| Register driven from within the Slice | 0 | | | | +| Register driven from outside the Slice | 5 | | | | +| LUT in front of the register is unused | 4 | | | | +| LUT in front of the register is used | 1 | | | | +| Unique Control Sets | 1 | | 15850 | <0.01 | ++--------------------------------------------+------+-------+-----------+-------+ +* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 105 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 105 | 0.00 | +| RAMB18 | 0 | 0 | 210 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 180 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 10 | 10 | 285 | 3.51 | +| IOB Master Pads | 5 | | | | +| IOB Slave Pads | 5 | | | | +| Bonded IPADs | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 6 | 0.00 | +| PHASER_REF | 0 | 0 | 6 | 0.00 | +| OUT_FIFO | 0 | 0 | 24 | 0.00 | +| IN_FIFO | 0 | 0 | 24 | 0.00 | +| IDELAYCTRL | 0 | 0 | 6 | 0.00 | +| IBUFDS | 0 | 0 | 274 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 24 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 24 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 300 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 0 | 0 | 6 | 0.00 | +| PLLE2_ADV | 0 | 0 | 6 | 0.00 | +| BUFMRCE | 0 | 0 | 12 | 0.00 | +| BUFHCE | 0 | 0 | 96 | 0.00 | +| BUFR | 0 | 0 | 24 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 5 | Flop & Latch | +| OBUFT | 4 | IO | +| OBUF | 4 | IO | +| IBUF | 2 | IO | +| LUT3 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/gen_run.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/gen_run.xml" new file mode 100644 index 00000000..bc26bc3c --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/gen_run.xml" @@ -0,0 +1,123 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/htr.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/htr.txt" new file mode 100644 index 00000000..4d930b1b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/htr.txt" @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log example_5_4.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_5_4.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/init_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/init_design.pb" new file mode 100644 index 00000000..443d05d8 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/init_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/opt_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/opt_design.pb" new file mode 100644 index 00000000..06b9b121 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/opt_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/phys_opt_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/phys_opt_design.pb" new file mode 100644 index 00000000..903ff13d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/phys_opt_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/place_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/place_design.pb" new file mode 100644 index 00000000..ef7a4419 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/place_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/project.wdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/project.wdf" new file mode 100644 index 00000000..63b8df5d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/project.wdf" @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3738633566343465613761363464613138623934646431313366623430343666:506172656e742050412070726f6a656374204944:00 +eof:4131815232 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/route_design.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/route_design.pb" new file mode 100644 index 00000000..85ea9d87 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/route_design.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/rundef.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/rundef.js" new file mode 100644 index 00000000..e598ad15 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/rundef.js" @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;"; +} else { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log example_5_4.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_5_4.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/runme.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/runme.bat" new file mode 100644 index 00000000..1760626b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/runme.bat" @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/runme.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/runme.sh" new file mode 100644 index 00000000..68b5df94 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/runme.sh" @@ -0,0 +1,47 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin +else + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log example_5_4.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source example_5_4.tcl -notrace + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/usage_statistics_webtalk.html" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/usage_statistics_webtalk.html" new file mode 100644 index 00000000..98990473 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/usage_statistics_webtalk.html" @@ -0,0 +1,647 @@ +Device Usage Statistics Report +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
betaFALSEbuild_version2708876
date_generatedMon Nov 13 20:43:50 2023os_platformWIN64
product_versionVivado v2019.2 (64-bit)project_id78c5f44ea7a64da18b94dd113fb4046f
project_iteration2random_id5098e843c55f5f60a14bf92371dc2ce7
registration_id5098e843c55f5f60a14bf92371dc2ce7route_designTRUE
target_devicexc7a75ttarget_familyartix7
target_packagefgg484target_speed-1
tool_flowVivado

+ + + + + + + + +
user_environment
cpu_nameAMD Ryzen 9 7945HX with Radeon Graphics cpu_speed2495 MHz
os_nameWindows Server 2016 or Windows 10os_releasemajor release (build 9200)
system_ram16.000 GBtotal_processors1

+ + +
vivado_usage
+ + + + + + + + + + + + + + + + + + + + + + +
gui_handlers
addsrcwizard_specify_hdl_netlist_block_design=1addsrcwizard_specify_or_create_constraint_files=1basedialog_ok=5basedialog_yes=3
cmdmsgdialog_ok=3constraintschooserpanel_add_files=1flownavigatortreepanel_flow_navigator_tree=10fpgachooser_fpga_table=2
gettingstartedview_create_new_project=1gettingstartedview_open_project=1mainmenumgr_file=2mainmenumgr_project=1
pacommandnames_add_sources=2pacommandnames_auto_connect_target=2pacommandnames_close_project=1paviews_dashboard=1
paviews_project_summary=2programdebugtab_open_target=1programfpgadialog_program=4projectnamechooser_project_name=1
srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1
+ + + + + + + + + + + + + + +
java_command_handlers
addsources=2autoconnecttarget=2closeproject=1launchprogramfpga=4
newproject=1openhardwaremanager=7openproject=1openrecenttarget=1
programdevice=4runbitgen=3showview=1viewtaskimplementation=1
+ + + +
other_data
guimode=2
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
project_data
constraintsetcount=1core_container=falsecurrentimplrun=impl_1currentsynthesisrun=synth_1
default_library=xil_defaultlibdesignmode=RTLexport_simulation_activehdl=0export_simulation_ies=0
export_simulation_modelsim=0export_simulation_questa=0export_simulation_riviera=0export_simulation_vcs=0
export_simulation_xsim=0implstrategy=Vivado Implementation Defaultslaunch_simulation_activehdl=0launch_simulation_ies=0
launch_simulation_modelsim=0launch_simulation_questa=0launch_simulation_riviera=0launch_simulation_vcs=0
launch_simulation_xsim=0simulator_language=Mixedsrcsetcount=1synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilogtarget_simulator=XSimtotalimplruns=1totalsynthesisruns=1
+
+ + + + +
unisim_transformation
+ + + + + + + + + + +
post_unisim_transformation
bufg=1fdre=3gnd=4ibuf=2
lut3=1obuf=4obuft=4vcc=4
+
+ + + + + + + + + + +
pre_unisim_transformation
bufg=1fdre=3gnd=4ibuf=2
lut3=1obuf=4obuft=4vcc=4
+

+ + + +
phys_opt_design_post_place
+ + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-aggressive_hold_fix=default::[not_specified]-bram_register_opt=default::[not_specified]-clock_opt=default::[not_specified]-critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified]-directive=default::[not_specified]-dsp_register_opt=default::[not_specified]-effort_level=default::[not_specified]
-fanout_opt=default::[not_specified]-hold_fix=default::[not_specified]-insert_negative_edge_ffs=default::[not_specified]-multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified]-restruct_opt=default::[not_specified]-retime=default::[not_specified]-rewire=default::[not_specified]
-shift_register_opt=default::[not_specified]-uram_register_opt=default::[not_specified]-verbose=default::[not_specified]-vhfn=default::[not_specified]
+

+ + + + +
report_drc
+ + + + + + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-internal=default::[not_specified]-internal_only=default::[not_specified]-messages=default::[not_specified]
-name=default::[not_specified]-no_waivers=default::[not_specified]-return_string=default::[not_specified]-ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified]-waived=default::[not_specified]
+
+ + + + +
results
cfgbvs-1=1plck-12=1
+

+ + + + +
report_methodology
+ + + + + + + + + + + + +
command_line_options
-append=default::[not_specified]-checks=default::[not_specified]-fail_on=default::[not_specified]-force=default::[not_specified]
-format=default::[not_specified]-messages=default::[not_specified]-name=default::[not_specified]-return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified]-waived=default::[not_specified]
+
+ + + +
results
timing-17=5
+

+ + + + +
report_power
+ + + + + + + + + + + + + + + + +
command_line_options
-advisory=default::[not_specified]-append=default::[not_specified]-file=[specified]-format=default::text
-hier=default::power-hierarchical_depth=default::4-l=default::[not_specified]-name=default::[not_specified]
-no_propagation=default::[not_specified]-return_string=default::[not_specified]-rpx=[specified]-verbose=default::[not_specified]
-vid=default::[not_specified]-xpe=default::[not_specified]
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
usage
airflow=250 (LFM)ambient_temp=25.0 (C)bi-dir_toggle=12.500000bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers)board_selection=medium (10"x10")confidence_level_clock_activity=Lowconfidence_level_design_state=High
confidence_level_device_models=Highconfidence_level_internal_activity=Highconfidence_level_io_activity=Lowconfidence_level_overall=Low
customer=TBDcustomer_class=TBDdevstatic=0.106049die=xc7a75tfgg484-1
dsp_output_toggle=12.500000dynamic=3.926536effective_thetaja=2.7enable_probability=0.990000
family=artix7ff_toggle=12.500000flow_state=routedheatsink=medium (Medium Profile)
i/o=3.879161input_toggle=12.500000junction_temp=35.8 (C)logic=0.010036
mgtavcc_dynamic_current=0.000000mgtavcc_static_current=0.000000mgtavcc_total_current=0.000000mgtavcc_voltage=1.000000
mgtavtt_dynamic_current=0.000000mgtavtt_static_current=0.000000mgtavtt_total_current=0.000000mgtavtt_voltage=1.200000
netlist_net_matched=NAoff-chip_power=0.000000on-chip_power=4.032586output_enable=1.000000
output_load=5.000000output_toggle=12.500000package=fgg484pct_clock_constrained=0.000000
pct_inputs_defined=0platform=nt64process=typicalram_enable=50.000000
ram_write=50.000000read_saif=Falseset/reset_probability=0.000000signal_rate=False
signals=0.037340simulation_file=Nonespeedgrade=-1static_prob=False
temp_grade=commercialthetajb=6.8 (C/W)thetasa=4.6 (C/W)toggle_rate=False
user_board_temp=25.0 (C)user_effective_thetaja=2.7user_junc_temp=35.8 (C)user_thetajb=6.8 (C/W)
user_thetasa=4.6 (C/W)vccadc_dynamic_current=0.000000vccadc_static_current=0.020000vccadc_total_current=0.020000
vccadc_voltage=1.800000vccaux_dynamic_current=0.141856vccaux_io_dynamic_current=0.000000vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000vccaux_io_voltage=1.800000vccaux_static_current=0.018857vccaux_total_current=0.160712
vccaux_voltage=1.800000vccbram_dynamic_current=0.000000vccbram_static_current=0.000383vccbram_total_current=0.000383
vccbram_voltage=1.000000vccint_dynamic_current=0.055376vccint_static_current=0.022525vccint_total_current=0.077900
vccint_voltage=1.000000vcco12_dynamic_current=0.000000vcco12_static_current=0.000000vcco12_total_current=0.000000
vcco12_voltage=1.200000vcco135_dynamic_current=0.000000vcco135_static_current=0.000000vcco135_total_current=0.000000
vcco135_voltage=1.350000vcco15_dynamic_current=0.000000vcco15_static_current=0.000000vcco15_total_current=0.000000
vcco15_voltage=1.500000vcco18_dynamic_current=0.000000vcco18_static_current=0.000000vcco18_total_current=0.000000
vcco18_voltage=1.800000vcco25_dynamic_current=0.000000vcco25_static_current=0.000000vcco25_total_current=0.000000
vcco25_voltage=2.500000vcco33_dynamic_current=1.095703vcco33_static_current=0.004000vcco33_total_current=1.099703
vcco33_voltage=3.300000version=2019.2
+

+ + + + + + + + + +
report_utilization
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
clocking
bufgctrl_available=32bufgctrl_fixed=0bufgctrl_used=1bufgctrl_util_percentage=3.13
bufhce_available=96bufhce_fixed=0bufhce_used=0bufhce_util_percentage=0.00
bufio_available=24bufio_fixed=0bufio_used=0bufio_util_percentage=0.00
bufmrce_available=12bufmrce_fixed=0bufmrce_used=0bufmrce_util_percentage=0.00
bufr_available=24bufr_fixed=0bufr_used=0bufr_util_percentage=0.00
mmcme2_adv_available=6mmcme2_adv_fixed=0mmcme2_adv_used=0mmcme2_adv_util_percentage=0.00
plle2_adv_available=6plle2_adv_fixed=0plle2_adv_used=0plle2_adv_util_percentage=0.00
+
+ + + + + + +
dsp
dsps_available=180dsps_fixed=0dsps_used=0dsps_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
io_standard
blvds_25=0diff_hstl_i=0diff_hstl_i_18=0diff_hstl_ii=0
diff_hstl_ii_18=0diff_hsul_12=0diff_mobile_ddr=0diff_sstl135=0
diff_sstl135_r=0diff_sstl15=0diff_sstl15_r=0diff_sstl18_i=0
diff_sstl18_ii=0hstl_i=0hstl_i_18=0hstl_ii=0
hstl_ii_18=0hsul_12=0lvcmos12=0lvcmos15=0
lvcmos18=0lvcmos25=0lvcmos33=1lvds_25=0
lvttl=0mini_lvds_25=0mobile_ddr=0pci33_3=0
ppds_25=0rsds_25=0sstl135=0sstl135_r=0
sstl15=0sstl15_r=0sstl18_i=0sstl18_ii=0
tmds_33=0
+
+ + + + + + + + + + + + + + +
memory
block_ram_tile_available=105block_ram_tile_fixed=0block_ram_tile_used=0block_ram_tile_util_percentage=0.00
ramb18_available=210ramb18_fixed=0ramb18_used=0ramb18_util_percentage=0.00
ramb36_fifo_available=105ramb36_fifo_fixed=0ramb36_fifo_used=0ramb36_fifo_util_percentage=0.00
+
+ + + + + + + + + + + + + + +
primitives
bufg_functional_category=Clockbufg_used=1fdre_functional_category=Flop & Latchfdre_used=5
ibuf_functional_category=IOibuf_used=2lut3_functional_category=LUTlut3_used=1
obuf_functional_category=IOobuf_used=4obuft_functional_category=IOobuft_used=4
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
slice_logic
f7_muxes_available=31700f7_muxes_fixed=0f7_muxes_used=0f7_muxes_util_percentage=0.00
f8_muxes_available=15850f8_muxes_fixed=0f8_muxes_used=0f8_muxes_util_percentage=0.00
lut_as_logic_available=47200lut_as_logic_fixed=0lut_as_logic_used=1lut_as_logic_util_percentage=<0.01
lut_as_memory_available=19000lut_as_memory_fixed=0lut_as_memory_used=0lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=94400register_as_flip_flop_fixed=0register_as_flip_flop_used=5register_as_flip_flop_util_percentage=<0.01
register_as_latch_available=94400register_as_latch_fixed=0register_as_latch_used=0register_as_latch_util_percentage=0.00
slice_luts_available=47200slice_luts_fixed=0slice_luts_used=1slice_luts_util_percentage=<0.01
slice_registers_available=94400slice_registers_fixed=0slice_registers_used=5slice_registers_util_percentage=<0.01
lut_as_distributed_ram_fixed=0lut_as_distributed_ram_used=0lut_as_logic_available=47200lut_as_logic_fixed=0
lut_as_logic_used=1lut_as_logic_util_percentage=<0.01lut_as_memory_available=19000lut_as_memory_fixed=0
lut_as_memory_used=0lut_as_memory_util_percentage=0.00lut_as_shift_register_fixed=0lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0lut_in_front_of_the_register_is_unused_used=4lut_in_front_of_the_register_is_used_fixed=4lut_in_front_of_the_register_is_used_used=1
register_driven_from_outside_the_slice_fixed=1register_driven_from_outside_the_slice_used=5register_driven_from_within_the_slice_fixed=5register_driven_from_within_the_slice_used=0
slice_available=15850slice_fixed=0slice_registers_available=94400slice_registers_fixed=0
slice_registers_used=5slice_registers_util_percentage=<0.01slice_used=5slice_util_percentage=0.03
slicel_fixed=0slicel_used=5slicem_fixed=0slicem_used=0
unique_control_sets_available=15850unique_control_sets_fixed=15850unique_control_sets_used=1unique_control_sets_util_percentage=<0.01
using_o5_and_o6_fixed=<0.01using_o5_and_o6_used=0using_o5_output_only_fixed=0using_o5_output_only_used=0
using_o6_output_only_fixed=0using_o6_output_only_used=1
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
specific_feature
bscane2_available=4bscane2_fixed=0bscane2_used=0bscane2_util_percentage=0.00
capturee2_available=1capturee2_fixed=0capturee2_used=0capturee2_util_percentage=0.00
dna_port_available=1dna_port_fixed=0dna_port_used=0dna_port_util_percentage=0.00
efuse_usr_available=1efuse_usr_fixed=0efuse_usr_used=0efuse_usr_util_percentage=0.00
frame_ecce2_available=1frame_ecce2_fixed=0frame_ecce2_used=0frame_ecce2_util_percentage=0.00
icape2_available=2icape2_fixed=0icape2_used=0icape2_util_percentage=0.00
pcie_2_1_available=1pcie_2_1_fixed=0pcie_2_1_used=0pcie_2_1_util_percentage=0.00
startupe2_available=1startupe2_fixed=0startupe2_used=0startupe2_util_percentage=0.00
xadc_available=1xadc_fixed=0xadc_used=0xadc_util_percentage=0.00
+

+ + + + +
synthesis
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-assert=default::[not_specified]-bufg=default::12-cascade_dsp=default::auto-constrset=default::[not_specified]
-control_set_opt_threshold=default::auto-directive=default::default-fanout_limit=default::10000-flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto-gated_clock_conversion=default::off-generic=default::[not_specified]-include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified]-max_bram=default::-1-max_bram_cascade_height=default::-1-max_dsp=default::-1
-max_uram=default::-1-max_uram_cascade_height=default::-1-mode=default::default-name=default::[not_specified]
-no_lc=default::[not_specified]-no_srlextract=default::[not_specified]-no_timing_driven=default::[not_specified]-part=xc7a75tfgg484-1
-resource_sharing=default::auto-retiming=default::[not_specified]-rtl=default::[not_specified]-rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified]-seu_protect=default::none-sfcu=default::[not_specified]-shreg_min_size=default::3
-top=example_5_4-verilog_define=default::[not_specified]
+
+ + + + + + +
usage
elapsed=00:00:14shls_ip=0memory_gain=693.508MBmemory_peak=1024.152MB
+

+ + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/usage_statistics_webtalk.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/usage_statistics_webtalk.xml" new file mode 100644 index 00000000..8ba0d5e6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/usage_statistics_webtalk.xml" @@ -0,0 +1,580 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+ + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + +
+
+ + +
+
+
+
+ + + + + + + + + + +
+
+ +
+
+
+
+ + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + +
+
+ + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + +
+
+
+
+ + + + + + + + +
+
+ + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + +
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/vivado.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/vivado.jou" new file mode 100644 index 00000000..0ba5d4be --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/vivado.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 13 20:43:14 2023 +# Process ID: 14652 +# Current directory: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/impl_1 +# Command line: vivado.exe -log example_5_4.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source example_5_4.tcl -notrace +# Log file: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/impl_1/example_5_4.vdi +# Journal file: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source example_5_4.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/vivado.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/vivado.pb" new file mode 100644 index 00000000..96e01954 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/vivado.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/write_bitstream.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/write_bitstream.pb" new file mode 100644 index 00000000..c21309da Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/impl_1/write_bitstream.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/.Vivado_Synthesis.queue.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/.Vivado_Synthesis.queue.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/.vivado.begin.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/.vivado.begin.rst" new file mode 100644 index 00000000..32d8af38 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/.vivado.begin.rst" @@ -0,0 +1,5 @@ + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/.vivado.end.rst" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/.vivado.end.rst" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/ISEWrap.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/ISEWrap.js" new file mode 100644 index 00000000..97a2ecbc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/ISEWrap.js" @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/ISEWrap.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/ISEWrap.sh" new file mode 100644 index 00000000..f679f2e8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/ISEWrap.sh" @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/__synthesis_is_complete__" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/__synthesis_is_complete__" new file mode 100644 index 00000000..e69de29b diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/example_5_4.dcp" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/example_5_4.dcp" new file mode 100644 index 00000000..e77f2e5e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/example_5_4.dcp" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/example_5_4.tcl" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/example_5_4.tcl" new file mode 100644 index 00000000..0730ecbc --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/example_5_4.tcl" @@ -0,0 +1,56 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param chipscope.maxJobs 8 +set_param xicom.use_bs_reader 1 +create_project -in_memory -part xc7a75tfgg484-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.cache/wt [current_project] +set_property parent.project_path D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo d:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.v +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc +set_property used_in_implementation false [get_files D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc] + +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +synth_design -top example_5_4 -part xc7a75tfgg484-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef example_5_4.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file example_5_4_utilization_synth.rpt -pb example_5_4_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/example_5_4.vds" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/example_5_4.vds" new file mode 100644 index 00000000..f08e65ec --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/example_5_4.vds" @@ -0,0 +1,604 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 13 20:42:49 2023 +# Process ID: 9536 +# Current directory: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/synth_1 +# Command line: vivado.exe -log example_5_4.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_5_4.tcl +# Log file: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/synth_1/example_5_4.vds +# Journal file: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source example_5_4.tcl -notrace +Command: synth_design -top example_5_4 -part xc7a75tfgg484-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a75t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a75t' +INFO: [Device 21-403] Loading part xc7a75tfgg484-1 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 3980 +WARNING: [Synth 8-2539] port sw_pin must not be declared to be an array [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.v:28] +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 857.426 ; gain = 238.430 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'example_5_4' [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.v:27] +INFO: [Synth 8-6157] synthesizing module 'xor_gate' [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.v:6] +INFO: [Synth 8-6155] done synthesizing module 'xor_gate' (1#1) [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.v:6] +INFO: [Synth 8-6157] synthesizing module 't_flip_flop' [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.v:15] +INFO: [Synth 8-155] case statement is not full and has no default [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.v:19] +INFO: [Synth 8-6155] done synthesizing module 't_flip_flop' (2#1) [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.v:15] +INFO: [Synth 8-6155] done synthesizing module 'example_5_4' (3#1) [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.v:27] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port led_pin[4] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port led_pin[3] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port led_pin[2] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port led_pin[1] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port sw_pin[6] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port sw_pin[5] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port sw_pin[4] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port sw_pin[3] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port sw_pin[2] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port sw_pin[1] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port sw_pin[0] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 903.406 ; gain = 284.410 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 903.406 ; gain = 284.410 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 903.406 ; gain = 284.410 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 903.406 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------系统时钟------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:1] +WARNING: [Vivado 12-584] No ports matched 'sys_clk_50m'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_100m'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:3] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:3] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'sys_clk_3hz'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:4] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:4] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------LED0~LED7(DAC_D0~DAC_D7?------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:7] +CRITICAL WARNING: [Designutils 20-1307] Command '//---------------------------------------------拨码?关sw0~sw7----------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:19] +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------------------9个按?--------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:31] +WARNING: [Vivado 12-584] No ports matched 'btn_0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:32] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:32] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_2'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:34] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:34] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_3'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:35] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:35] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_4'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:36] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:36] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_5'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:37] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:37] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_6'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:38] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:38] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_7'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:39] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:39] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'btn_8'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:40] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:40] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-507] No nets matched 'btn_1_IBUF'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:43] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:43] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//-----------------------------------6个数码管-----------------------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:46] +WARNING: [Vivado 12-584] No ports matched 'digitron_out[0]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:47] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:47] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[1]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:48] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:48] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[2]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:49] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[3]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:50] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:50] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[4]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:51] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:51] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[5]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:52] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:52] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[6]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:53] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:53] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_out[7]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:54] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:54] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[0]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:56] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:56] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[1]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:57] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:57] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[2]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:58] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:58] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitroncs_out[3]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:59] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:59] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[0]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:61] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:61] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[1]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:62] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:62] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[2]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:63] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:63] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_a[3]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:64] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:64] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[0]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:66] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:66] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[1]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:67] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:67] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[2]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:68] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:68] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'digitron_b[3]'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:69] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:69] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------串口---------------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:73] +WARNING: [Vivado 12-584] No ports matched 'uart_rxd'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:74] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:74] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'uart_txd'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:75] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:75] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//----------------------------------------------蜂鸣?-----------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:79] +WARNING: [Vivado 12-584] No ports matched 'buzzer'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:80] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:80] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------XADC数模转换-------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:84] +WARNING: [Vivado 12-584] No ports matched 'ad15p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:85] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:85] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad15n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:86] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:86] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:87] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:87] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad7n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:88] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:88] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:89] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:89] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad14n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:90] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:90] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:91] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:91] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad6n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:92] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:92] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:93] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:93] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad5n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:94] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:94] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:95] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:95] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad13n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:96] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:96] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:97] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:97] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ad4n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:98] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:98] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +CRITICAL WARNING: [Designutils 20-1307] Command '//--------------------------------------------------------DDR3L-------------------------------------' is not supported in the xdc constraint file. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:103] +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:104] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:104] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs0_n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:105] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:105] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:106] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:106] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dqs1_n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:107] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:107] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:109] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:109] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq1'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:110] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:110] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq2'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:111] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:111] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq3'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:112] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:112] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq4'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:113] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:113] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq5'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:114] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:114] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq6'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:115] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:115] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq7'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:116] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:116] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq8'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:117] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:117] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq9'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:118] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:118] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq10'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:119] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:119] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq11'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:120] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:120] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq12'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:121] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:121] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq13'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:122] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:122] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq14'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:123] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:123] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dq15'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:124] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:124] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:126] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:126] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a1'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:127] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:127] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a2'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:128] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:128] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a3'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:129] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:129] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a4'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:130] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:130] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a5'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:131] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:131] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a6'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:132] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:132] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a7'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:133] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:133] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a8'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:134] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:134] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a9'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:135] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:135] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a10'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:136] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:136] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a11'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:137] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:137] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_a12'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:138] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:138] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:140] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:140] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba1'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:141] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:141] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ba2'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:142] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:142] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm0'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:144] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:144] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_dm1'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:145] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:145] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_odt'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:147] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:147] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_p'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:148] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:148] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_clk_n'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:149] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:149] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cke'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:150] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:150] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cs'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:151] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:151] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_ras'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:152] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:152] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_we'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:153] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:153] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_reset'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:154] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:154] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'ddr3l_cas'. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:155] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc:155] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/ACE1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/example_5_4_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/example_5_4_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 973.840 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 973.840 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 973.840 ; gain = 354.844 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a75tfgg484-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 973.840 ; gain = 354.844 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 973.840 ; gain = 354.844 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 973.840 ; gain = 354.844 +--------------------------------------------------------------------------------- +INFO: [Synth 8-223] decloning instance 'U5' (xor_gate) to 'U7' + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 4 ++---Registers : + 1 Bit Registers := 3 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module xor_gate +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 +Module t_flip_flop +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 180 (col length:80) +BRAMs: 210 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3331] design example_5_4 has unconnected port led_pin[4] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port led_pin[3] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port led_pin[2] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port led_pin[1] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port sw_pin[6] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port sw_pin[5] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port sw_pin[4] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port sw_pin[3] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port sw_pin[2] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port sw_pin[1] +WARNING: [Synth 8-3331] design example_5_4 has unconnected port sw_pin[0] +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 973.840 ; gain = 354.844 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 999.801 ; gain = 380.805 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 999.801 ; gain = 380.805 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1009.391 ; gain = 390.395 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1024.152 ; gain = 405.156 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1024.152 ; gain = 405.156 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1024.152 ; gain = 405.156 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1024.152 ; gain = 405.156 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1024.152 ; gain = 405.156 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1024.152 ; gain = 405.156 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |BUFG | 1| +|2 |LUT3 | 1| +|3 |FDRE | 3| +|4 |IBUF | 2| +|5 |OBUF | 4| +|6 |OBUFT | 4| ++------+------+------+ + +Report Instance Areas: ++------+---------+--------------+------+ +| |Instance |Module |Cells | ++------+---------+--------------+------+ +|1 |top | | 15| +|2 | U2 |t_flip_flop | 1| +|3 | U4 |t_flip_flop_0 | 2| +|4 | U6 |t_flip_flop_1 | 1| ++------+---------+--------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1024.152 ; gain = 405.156 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 11 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1024.152 ; gain = 334.723 +Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1024.152 ; gain = 405.156 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1037.215 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1041.766 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +18 Infos, 119 Warnings, 105 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1041.766 ; gain = 734.535 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1041.766 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/synth_1/example_5_4.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file example_5_4_utilization_synth.rpt -pb example_5_4_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Mon Nov 13 20:43:06 2023... diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/example_5_4_utilization_synth.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/example_5_4_utilization_synth.pb" new file mode 100644 index 00000000..8b58e1d5 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/example_5_4_utilization_synth.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/example_5_4_utilization_synth.rpt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/example_5_4_utilization_synth.rpt" new file mode 100644 index 00000000..4cf54d31 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/example_5_4_utilization_synth.rpt" @@ -0,0 +1,176 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019 +| Date : Mon Nov 13 20:43:06 2023 +| Host : X-BELIEVER running 64-bit major release (build 9200) +| Command : report_utilization -file example_5_4_utilization_synth.rpt -pb example_5_4_utilization_synth.pb +| Design : example_5_4 +| Device : 7a75tfgg484-1 +| Design State : Synthesized +----------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 1 | 0 | 47200 | <0.01 | +| LUT as Logic | 1 | 0 | 47200 | <0.01 | +| LUT as Memory | 0 | 0 | 19000 | 0.00 | +| Slice Registers | 3 | 0 | 94400 | <0.01 | +| Register as Flip Flop | 3 | 0 | 94400 | <0.01 | +| Register as Latch | 0 | 0 | 94400 | 0.00 | +| F7 Muxes | 0 | 0 | 31700 | 0.00 | +| F8 Muxes | 0 | 0 | 15850 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 3 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 105 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 105 | 0.00 | +| RAMB18 | 0 | 0 | 210 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 180 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 10 | 0 | 285 | 3.51 | +| Bonded IPADs | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 6 | 0.00 | +| PHASER_REF | 0 | 0 | 6 | 0.00 | +| OUT_FIFO | 0 | 0 | 24 | 0.00 | +| IN_FIFO | 0 | 0 | 24 | 0.00 | +| IDELAYCTRL | 0 | 0 | 6 | 0.00 | +| IBUFDS | 0 | 0 | 274 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 24 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 24 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 300 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 0 | 0 | 6 | 0.00 | +| PLLE2_ADV | 0 | 0 | 6 | 0.00 | +| BUFMRCE | 0 | 0 | 12 | 0.00 | +| BUFHCE | 0 | 0 | 96 | 0.00 | +| BUFR | 0 | 0 | 24 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUFT | 4 | IO | +| OBUF | 4 | IO | +| FDRE | 3 | Flop & Latch | +| IBUF | 2 | IO | +| LUT3 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/gen_run.xml" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/gen_run.xml" new file mode 100644 index 00000000..70062c19 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/gen_run.xml" @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/htr.txt" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/htr.txt" new file mode 100644 index 00000000..355ece81 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/htr.txt" @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log example_5_4.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_5_4.tcl diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/rundef.js" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/rundef.js" new file mode 100644 index 00000000..9e1d1cc3 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/rundef.js" @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;"; +} else { + PathVal = "D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2019.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log example_5_4.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_5_4.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/runme.bat" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/runme.bat" new file mode 100644 index 00000000..1760626b --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/runme.bat" @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/runme.sh" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/runme.sh" new file mode 100644 index 00000000..b734624c --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/runme.sh" @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin +else + PATH=D:/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2019.2/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2019.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log example_5_4.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_5_4.tcl diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/vivado.jou" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/vivado.jou" new file mode 100644 index 00000000..1341153e --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/vivado.jou" @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.2 (64-bit) +# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019 +# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 +# Start of session at: Mon Nov 13 20:42:49 2023 +# Process ID: 9536 +# Current directory: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/synth_1 +# Command line: vivado.exe -log example_5_4.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source example_5_4.tcl +# Log file: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/synth_1/example_5_4.vds +# Journal file: D:/DigitalLogic/ACE1/Test4_Design/example_5_4_ACE1/example_5_4_ACE1.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source example_5_4.tcl -notrace diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/vivado.pb" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/vivado.pb" new file mode 100644 index 00000000..fd6b7e62 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.runs/synth_1/vivado.pb" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.v" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.v" new file mode 100644 index 00000000..bdb64c55 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.v" @@ -0,0 +1,45 @@ +//ṹʽģΪʽʵ5.43λλĴ +//õ·Ϊx״̬Ϊy3y2y1ΪZCPΪʱźš + +`timescale 1ns / 1ps + +module xor_gate(input a,input b,output f); + reg y; + always @(*) //Ϊʽ + begin + y <= a ^ b; + end + assign f = y; +endmodule + +module t_flip_flop(input t,input cp,output q, qn); + reg y; + always @(negedge cp) //Ϊʽ + begin + case({t}) + 1: y <= ~y; // t = 1 Y=~Y + endcase + end + assign q= y; + assign qn = ~y; +endmodule + +module example_5_4( + input sw_pin[7:0], //8 + input btn_1, //1ť + output [7:0] led_pin //8led +); + wire y1, y1n, y2, y2n, y3, y3n, t1,t2,t3,f1,z; + xor_gate U1(.a(sw_pin[7]),.b(y1),.f(t1)); //ṹʽ + t_flip_flop U2(.t(t1),.cp(btn_1),.q(y1),.qn(y1n)); //ṹʽ + xor_gate U3(.a(y1),.b(y2),.f(t2)); //ṹʽ + t_flip_flop U4(.t(t2),.cp(btn_1),.q(y2),.qn(y2n)); //ṹʽ + xor_gate U5(.a(y2),.b(y3),.f(t3)); //ṹʽ + t_flip_flop U6(.t(t3),.cp(btn_1),.q(y3),.qn(y3n)); //ṹʽ + xor_gate U7(.a(y2),.b(y3),.f(f1)); //ṹʽ + xor_gate U8(.a(y1),.b(f1),.f(z)); //ṹʽ + assign led_pin[7] = y3; + assign led_pin[6] = y2; + assign led_pin[5] = y1; + assign led_pin[0] = z; +endmodule \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.xpr" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.xpr" new file mode 100644 index 00000000..041cfcb8 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/example_5_4_EGO1/example_5_4_ACE1.xpr" @@ -0,0 +1,184 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/\347\254\2544\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/\347\254\2544\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" new file mode 100644 index 00000000..3f34cf0d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/\347\254\2544\346\254\241\345\256\236\351\252\214\346\212\245\345\221\212.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:dd4e607754ee2e13dc1adc2f18e17b9ef39d8a624c951ba95a5c18f2412b1695 +size 2471749 diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/\347\254\2545\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260.circ" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/\347\254\2545\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260.circ" new file mode 100644 index 00000000..142ac0e6 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\345\256\236\351\252\214/\345\256\236\351\252\214\345\217\202\350\200\203/\345\256\236\351\252\214\345\233\233/\347\254\2545\347\253\240\344\271\240\351\242\230\347\224\265\350\267\257\347\232\204\345\256\236\347\216\260.circ" @@ -0,0 +1,2266 @@ + + +This file is intended to be loaded by Logisim http://logisim.altervista.org + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + addr/data: 8 8 +0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\346\234\237\344\270\255/2023\346\225\260\345\255\227\351\200\273\350\276\221\346\234\237\344\270\255.pdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\346\234\237\344\270\255/2023\346\225\260\345\255\227\351\200\273\350\276\221\346\234\237\344\270\255.pdf" new file mode 100644 index 00000000..f8e2df65 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\346\234\237\344\270\255/2023\346\225\260\345\255\227\351\200\273\350\276\221\346\234\237\344\270\255.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\346\234\237\344\270\255/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\346\234\237\344\270\255\350\200\203\350\257\225\350\200\203\345\215\267\357\274\2102023\345\271\26411\346\234\2104\346\227\245\357\274\211.pdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\346\234\237\344\270\255/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\346\234\237\344\270\255\350\200\203\350\257\225\350\200\203\345\215\267\357\274\2102023\345\271\26411\346\234\2104\346\227\245\357\274\211.pdf" new file mode 100644 index 00000000..1f9d2ecf Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\346\234\237\344\270\255/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\346\234\237\344\270\255\350\200\203\350\257\225\350\200\203\345\215\267\357\274\2102023\345\271\26411\346\234\2104\346\227\245\357\274\211.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\346\234\237\344\270\255/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\346\234\237\344\270\255\350\200\203\350\257\225\350\200\203\345\215\267\357\274\2102025\345\271\26411\346\234\2101\346\227\245\357\274\211.pdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\346\234\237\344\270\255/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\346\234\237\344\270\255\350\200\203\350\257\225\350\200\203\345\215\267\357\274\2102025\345\271\26411\346\234\2101\346\227\245\357\274\211.pdf" new file mode 100644 index 00000000..16ce38d4 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\346\234\237\344\270\255/\343\200\212\346\225\260\345\255\227\351\200\273\350\276\221\343\200\213\346\234\237\344\270\255\350\200\203\350\257\225\350\200\203\345\215\267\357\274\2102025\345\271\26411\346\234\2101\346\227\245\357\274\211.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\346\234\237\344\270\255/\346\234\237\344\270\255\350\200\203\350\257\225\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\346\234\237\344\270\255/\346\234\237\344\270\255\350\200\203\350\257\225\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..92d3896a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\346\234\237\344\270\255/\346\234\237\344\270\255\350\200\203\350\257\225\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\346\234\237\346\234\253/24\347\272\247\346\225\260\345\255\227\351\200\273\350\276\221\346\234\237\346\234\253\350\200\203.md" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\346\234\237\346\234\253/24\347\272\247\346\225\260\345\255\227\351\200\273\350\276\221\346\234\237\346\234\253\350\200\203.md" new file mode 100644 index 00000000..49799e57 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\346\234\237\346\234\253/24\347\272\247\346\225\260\345\255\227\351\200\273\350\276\221\346\234\237\346\234\253\350\200\203.md" @@ -0,0 +1,26 @@ +### 24级数字逻辑期末考 + +* 跟之前几届或者本届的期中试卷重叠度较高,尤其是填空 +* 不是完全出自总复习PPT的习题 +* 无但不表示不会有:进制转换 + +#### 填空 + +* OC,单项总线传输、双向总线传输 + +#### 简答 + +* 描述取反函数的规则,并求反函数 +* 描述PROM、EPROM、$E ^2 PROM$的区别 +* 最简与-或,或-与表达式 +* 描述那4个触发器的功能表,应该是$Q \rightarrow Q^{n+1}$的图 +* 描述异步脉冲时序电路和同步时序电路的区别 +* 余三码转换为2421码,无关项组合逻辑电路原题 +* 给出或-与表达式,用代数法和卡诺图法判断险象,并用冗余法消除(就24期中原题) +* 是PPT里模6异步计数器原题 + +#### 设计 **(PPT上)** + +* 给出同步计数器,设计模100计数器原题 +* 给出串行寄存器,设计那个11001(8个数字)的序列发生器原题 + diff --git "a/\345\244\247\344\272\214\344\270\212/DigitalLogic/\350\257\276\347\250\213\347\256\200\344\273\213.md" "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\350\257\276\347\250\213\347\256\200\344\273\213.md" new file mode 100644 index 00000000..7bc9e2c5 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/DigitalLogic/\350\257\276\347\250\213\347\256\200\344\273\213.md" @@ -0,0 +1,10 @@ +### 同学1: + +* 作业和实验部分参考了往届学长学姐的成果(感谢!),并修改了一部分认为不太正确的部分 +* zwh老师提供的参考答案的有些过程似乎不太正确(但忘了在哪XD +* 作业部分一定要先看总复习PPT,时序电路的设计是不考的(24级),但后面几个单元容易考一些比较杂的内容 +* 给分不行,敢信全勤平时分才给90%,作业和实验需要写一下午才90% +* 注意期末考必须按照复习PPT上记忆,批卷只有唯一答案,等价思路不给分,就算PPT上错了也按照上面的来记,比如与-或卡诺图化简是会破坏险象的,但PPT上却化简而非取反 +* 建议除非选修只选上这一门,或者想早点修完,否则不要选 + +> 建议作业部分还是自己做为主,实验部分就随意了。。。 \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/\344\272\244\344\272\222\350\256\276\350\256\241/\350\257\276\347\250\213\347\256\200\344\273\213.md" "b/\345\244\247\344\272\214\344\270\212/\344\272\244\344\272\222\350\256\276\350\256\241/\350\257\276\347\250\213\347\256\200\344\273\213.md" new file mode 100644 index 00000000..9de2fd48 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/\344\272\244\344\272\222\350\256\276\350\256\241/\350\257\276\347\250\213\347\256\200\344\273\213.md" @@ -0,0 +1,18 @@ +### 同学1: + +#### 考查形式 + +* 24级做的是包括前后端+云端(至少需要一个作为存储数据的中转)的`保研加分小助手`,类似于`七彩信息`小程序(可自行选择框架) + * 做鸿蒙版本有加分+5,但是比较难,因为不够成熟、不够广泛,不方便找资料,做成浏览器套壳或许挺简单 + * 有人做邮箱验证登录、简单的LLM加分材料分类等等创新功能 + * 推荐Vibe Coding✅ + +* 青蓝计划(介绍HCI相关知识,制作PPT,并录制视频) +* 论文分享(读ACM HCI2025论文并分享,制作PPT,录制视频) + +#### 课堂评价 + +* gsh理论课不怎么在,主要是项目展示/打分的时候在场 +* 讨论课上会对项目提出新的要求,也有很多插曲任务,比如看自编教材提建议等等 +* 不会教前后端+云端怎么写,需自学 +* 其他时间还是挺自由的(有很多线上课,不打卡;线下课代签会严重扣分),项目在阶段性展示前冲刺一下还是能做得很不错的 \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\210\232\344\275\223\347\232\204\345\256\232\350\275\264\350\275\254\345\212\2501\347\255\224\346\241\210(1).pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\210\232\344\275\223\347\232\204\345\256\232\350\275\264\350\275\254\345\212\2501\347\255\224\346\241\210(1).pdf" new file mode 100644 index 00000000..16bd81f5 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\210\232\344\275\223\347\232\204\345\256\232\350\275\264\350\275\254\345\212\2501\347\255\224\346\241\210(1).pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\210\232\344\275\223\347\232\204\345\256\232\350\275\264\350\275\254\345\212\2502\347\255\224\346\241\210(1).pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\210\232\344\275\223\347\232\204\345\256\232\350\275\264\350\275\254\345\212\2502\347\255\224\346\241\210(1).pdf" new file mode 100644 index 00000000..19b1f062 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\210\232\344\275\223\347\232\204\345\256\232\350\275\264\350\275\254\345\212\2502\347\255\224\346\241\210(1).pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\345\207\240\344\275\225\345\205\211\345\255\246\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\345\207\240\344\275\225\345\205\211\345\255\246\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..556335c4 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\345\207\240\344\275\225\345\205\211\345\255\246\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\345\217\230\345\214\226\347\232\204\347\224\265\347\243\201\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\345\217\230\345\214\226\347\232\204\347\224\265\347\243\201\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..eafa5fc3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\345\217\230\345\214\226\347\232\204\347\224\265\347\243\201\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\201\222\345\256\232\347\243\201\345\234\2721\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\201\222\345\256\232\347\243\201\345\234\2721\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..de3826d4 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\201\222\345\256\232\347\243\201\345\234\2721\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\201\222\345\256\232\347\243\201\345\234\2722\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\201\222\345\256\232\347\243\201\345\234\2722\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..9a6c6fcf Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\201\222\345\256\232\347\243\201\345\234\2722\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\214\257\345\212\250\344\270\216\346\263\242\345\212\2501\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\214\257\345\212\250\344\270\216\346\263\242\345\212\2501\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..013b84af Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\214\257\345\212\250\344\270\216\346\263\242\345\212\2501\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\214\257\345\212\250\344\270\216\346\263\242\345\212\2502\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\214\257\345\212\250\344\270\216\346\263\242\345\212\2502\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..3743349f Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\214\257\345\212\250\344\270\216\346\263\242\345\212\2502\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\263\242\345\212\250\345\205\211\345\255\2461\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\263\242\345\212\250\345\205\211\345\255\2461\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..5efde3b3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\263\242\345\212\250\345\205\211\345\255\2461\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\263\242\345\212\250\345\205\211\345\255\2462\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\263\242\345\212\250\345\205\211\345\255\2462\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..07a3c65f Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\346\263\242\345\212\250\345\205\211\345\255\2462\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\351\235\231\347\224\265\345\234\2721\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\351\235\231\347\224\265\345\234\2721\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..cdd45443 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\351\235\231\347\224\265\345\234\2721\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\351\235\231\347\224\265\345\234\2722\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\351\235\231\347\224\265\345\234\2722\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..db9e8efe Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\351\235\231\347\224\265\345\234\2722\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\351\235\231\347\224\265\345\234\272\344\270\255\347\232\204\345\257\274\344\275\223\344\270\216\347\224\265\344\273\213\350\264\2501\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\351\235\231\347\224\265\345\234\272\344\270\255\347\232\204\345\257\274\344\275\223\344\270\216\347\224\265\344\273\213\350\264\2501\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..21f27946 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\351\235\231\347\224\265\345\234\272\344\270\255\347\232\204\345\257\274\344\275\223\344\270\216\347\224\265\344\273\213\350\264\2501\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\351\235\231\347\224\265\345\234\272\344\270\255\347\232\204\345\257\274\344\275\223\344\270\216\347\224\265\344\273\213\350\264\2502\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\351\235\231\347\224\265\345\234\272\344\270\255\347\232\204\345\257\274\344\275\223\344\270\216\347\224\265\344\273\213\350\264\2502\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..19c74620 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\345\244\247\351\233\276\347\255\224\346\241\210/\351\235\231\347\224\265\345\234\272\344\270\255\347\232\204\345\257\274\344\275\223\344\270\216\347\224\265\344\273\213\350\264\2502\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\346\260\224\344\275\223\345\212\250\347\220\206\350\256\2722.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\346\260\224\344\275\223\345\212\250\347\220\206\350\256\2722.pdf" new file mode 100644 index 00000000..1ccd2d54 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\346\260\224\344\275\223\345\212\250\347\220\206\350\256\2722.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\346\260\224\344\275\223\350\277\220\347\220\206\350\256\2721.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\346\260\224\344\275\223\350\277\220\347\220\206\350\256\2721.pdf" new file mode 100644 index 00000000..25d2815c Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\346\260\224\344\275\223\350\277\220\347\220\206\350\256\2721.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\347\203\255\345\212\233\345\255\246\345\237\272\347\241\2001-\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\347\203\255\345\212\233\345\255\246\345\237\272\347\241\2001-\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..071462c6 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\347\203\255\345\212\233\345\255\246\345\237\272\347\241\2001-\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\347\203\255\345\212\233\345\255\246\345\237\272\347\241\2002-\347\255\224\346\241\210(1).pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\347\203\255\345\212\233\345\255\246\345\237\272\347\241\2002-\347\255\224\346\241\210(1).pdf" new file mode 100644 index 00000000..e33bc34d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\347\203\255\345\212\233\345\255\246\345\237\272\347\241\2002-\347\255\224\346\241\210(1).pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\347\213\255\344\271\211\347\233\270\345\257\271\350\256\272 \347\255\224\346\241\210.JPG" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\347\213\255\344\271\211\347\233\270\345\257\271\350\256\272 \347\255\224\346\241\210.JPG" new file mode 100644 index 00000000..df15184c Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\347\213\255\344\271\211\347\233\270\345\257\271\350\256\272 \347\255\224\346\241\210.JPG" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\347\213\255\344\271\211\347\233\270\345\257\271\350\256\2720.JPG" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\347\213\255\344\271\211\347\233\270\345\257\271\350\256\2720.JPG" new file mode 100644 index 00000000..66c19b5f Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\347\213\255\344\271\211\347\233\270\345\257\271\350\256\2720.JPG" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\350\264\250\347\202\271\345\212\250\345\212\233\345\255\2461\347\255\224\346\241\210(1).pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\350\264\250\347\202\271\345\212\250\345\212\233\345\255\2461\347\255\224\346\241\210(1).pdf" new file mode 100644 index 00000000..bd68bb2a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\350\264\250\347\202\271\345\212\250\345\212\233\345\255\2461\347\255\224\346\241\210(1).pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\350\264\250\347\202\271\345\212\250\345\212\233\345\255\2462\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\350\264\250\347\202\271\345\212\250\345\212\233\345\255\2462\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..e9064e7e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\350\264\250\347\202\271\345\212\250\345\212\233\345\255\2462\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\350\264\250\347\202\271\350\277\220\345\212\250\345\255\2461\347\255\224\346\241\210(1).pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\350\264\250\347\202\271\350\277\220\345\212\250\345\255\2461\347\255\224\346\241\210(1).pdf" new file mode 100644 index 00000000..c5ba533b Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\350\264\250\347\202\271\350\277\220\345\212\250\345\255\2461\347\255\224\346\241\210(1).pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\350\264\250\347\202\271\350\277\220\345\212\250\345\255\2462\347\255\224\346\241\210(1).pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\350\264\250\347\202\271\350\277\220\345\212\250\345\255\2462\347\255\224\346\241\210(1).pdf" new file mode 100644 index 00000000..75383e97 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\344\275\234\344\270\232\345\217\202\350\200\203\347\255\224\346\241\210 \345\244\247\347\211\251\344\270\212\346\234\252\350\277\207\346\227\266/\350\264\250\347\202\271\350\277\220\345\212\250\345\255\2462\347\255\224\346\241\210(1).pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\345\207\240\344\275\225\345\205\211\345\255\246\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\345\207\240\344\275\225\345\205\211\345\255\246\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..556335c4 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\345\207\240\344\275\225\345\205\211\345\255\246\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\345\217\230\345\214\226\347\232\204\347\224\265\347\243\201\345\234\272 .pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\345\217\230\345\214\226\347\232\204\347\224\265\347\243\201\345\234\272 .pdf" new file mode 100644 index 00000000..8f4f7a55 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\345\217\230\345\214\226\347\232\204\347\224\265\347\243\201\345\234\272 .pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\201\222\345\256\232\347\243\201\345\234\2721 .pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\201\222\345\256\232\347\243\201\345\234\2721 .pdf" new file mode 100644 index 00000000..337df797 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\201\222\345\256\232\347\243\201\345\234\2721 .pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\201\222\345\256\232\347\243\201\345\234\2722 .pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\201\222\345\256\232\347\243\201\345\234\2722 .pdf" new file mode 100644 index 00000000..b8e4f525 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\201\222\345\256\232\347\243\201\345\234\2722 .pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\214\257\345\212\250\344\270\216\346\263\242\345\212\2501 .pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\214\257\345\212\250\344\270\216\346\263\242\345\212\2501 .pdf" new file mode 100644 index 00000000..013b84af Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\214\257\345\212\250\344\270\216\346\263\242\345\212\2501 .pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\214\257\345\212\250\344\270\216\346\263\242\345\212\2502.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\214\257\345\212\250\344\270\216\346\263\242\345\212\2502.pdf" new file mode 100644 index 00000000..3743349f Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\214\257\345\212\250\344\270\216\346\263\242\345\212\2502.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\263\242\345\212\250\345\205\211\345\255\2461 .pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\263\242\345\212\250\345\205\211\345\255\2461 .pdf" new file mode 100644 index 00000000..16334e39 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\263\242\345\212\250\345\205\211\345\255\2461 .pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\263\242\345\212\250\345\205\211\345\255\2462 .pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\263\242\345\212\250\345\205\211\345\255\2462 .pdf" new file mode 100644 index 00000000..803268b4 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\346\263\242\345\212\250\345\205\211\345\255\2462 .pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\351\235\231\347\224\265\345\234\2721 .pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\351\235\231\347\224\265\345\234\2721 .pdf" new file mode 100644 index 00000000..5202b0ab Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\351\235\231\347\224\265\345\234\2721 .pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\351\235\231\347\224\265\345\234\2722 .pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\351\235\231\347\224\265\345\234\2722 .pdf" new file mode 100644 index 00000000..d20ef0f1 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\351\235\231\347\224\265\345\234\2722 .pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\351\235\231\347\224\265\345\234\272\344\270\255\347\232\204\345\257\274\344\275\223\344\270\216\347\224\265\344\273\213\350\264\2501 .pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\351\235\231\347\224\265\345\234\272\344\270\255\347\232\204\345\257\274\344\275\223\344\270\216\347\224\265\344\273\213\350\264\2501 .pdf" new file mode 100644 index 00000000..35efb9bd Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\351\235\231\347\224\265\345\234\272\344\270\255\347\232\204\345\257\274\344\275\223\344\270\216\347\224\265\344\273\213\350\264\2501 .pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\351\235\231\347\224\265\345\234\272\344\270\255\347\232\204\345\257\274\344\275\223\344\270\216\347\224\265\344\273\213\350\264\2502 .pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\351\235\231\347\224\265\345\234\272\344\270\255\347\232\204\345\257\274\344\275\223\344\270\216\347\224\265\344\273\213\350\264\2502 .pdf" new file mode 100644 index 00000000..7ba29db3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\217\202\350\200\203\347\255\224\346\241\210/\345\244\247\347\211\251\344\270\213\344\275\234\344\270\232\347\255\224\346\241\210 \346\226\260/\351\235\231\347\224\265\345\234\272\344\270\255\347\232\204\345\257\274\344\275\223\344\270\216\347\224\265\344\273\213\350\264\2502 .pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/1C69F90DA7B751CAC45C440C5DB08763.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/1C69F90DA7B751CAC45C440C5DB08763.jpg" new file mode 100644 index 00000000..bbaefdbf Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/1C69F90DA7B751CAC45C440C5DB08763.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/47F1C44257079F466530F973F02655D0.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/47F1C44257079F466530F973F02655D0.jpg" new file mode 100644 index 00000000..c436719f Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/47F1C44257079F466530F973F02655D0.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/5E4406FFA5B02C432C0E5E082E95D38E.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/5E4406FFA5B02C432C0E5E082E95D38E.jpg" new file mode 100644 index 00000000..025bad96 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/5E4406FFA5B02C432C0E5E082E95D38E.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/6F236AF1B83A6005CAE432E6D69B1BD6.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/6F236AF1B83A6005CAE432E6D69B1BD6.jpg" new file mode 100644 index 00000000..35ea6ccc Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/6F236AF1B83A6005CAE432E6D69B1BD6.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/8069B82B47EBF00E9B79721612AD2778.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/8069B82B47EBF00E9B79721612AD2778.jpg" new file mode 100644 index 00000000..a00a0be8 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/8069B82B47EBF00E9B79721612AD2778.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/B583C76A08BA9FAFD22981B7E6BD20ED.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/B583C76A08BA9FAFD22981B7E6BD20ED.jpg" new file mode 100644 index 00000000..f216318b Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/B583C76A08BA9FAFD22981B7E6BD20ED.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/CBAB336F76F23526F3FEA5A0024DF83B.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/CBAB336F76F23526F3FEA5A0024DF83B.jpg" new file mode 100644 index 00000000..ebedca59 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/CBAB336F76F23526F3FEA5A0024DF83B.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/ED281191CADF0788B79649A7B9D091FE.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/ED281191CADF0788B79649A7B9D091FE.jpg" new file mode 100644 index 00000000..110e5511 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/ED281191CADF0788B79649A7B9D091FE.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908234.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908234.jpg" new file mode 100644 index 00000000..4b0fced2 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908234.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908247.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908247.jpg" new file mode 100644 index 00000000..c767009d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908247.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908278.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908278.jpg" new file mode 100644 index 00000000..d7d4f174 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908278.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908364.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908364.jpg" new file mode 100644 index 00000000..cf1cdabe Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908364.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908668.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908668.jpg" new file mode 100644 index 00000000..cfb5840f Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908668.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908778.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908778.jpg" new file mode 100644 index 00000000..271b8253 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908778.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908830.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908830.jpg" new file mode 100644 index 00000000..54e758ed Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869908830.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869911331.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869911331.jpg" new file mode 100644 index 00000000..73a6e474 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Image_1710869911331.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Screenshot_20231214_111330.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Screenshot_20231214_111330.jpg" new file mode 100644 index 00000000..163a153d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/Screenshot_20231214_111330.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702368527406.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702368527406.jpg" new file mode 100644 index 00000000..67be47c5 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702368527406.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702368530089.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702368530089.jpg" new file mode 100644 index 00000000..53fe8b9b Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702368530089.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702368533301.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702368533301.jpg" new file mode 100644 index 00000000..2758aa77 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702368533301.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702368551622.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702368551622.jpg" new file mode 100644 index 00000000..c6a4e0e6 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702368551622.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702368554164.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702368554164.jpg" new file mode 100644 index 00000000..f5a8eb6b Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702368554164.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702369533609.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702369533609.jpg" new file mode 100644 index 00000000..02a15aec Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/mmexport1702369533609.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/\345\261\217\345\271\225\346\210\252\345\233\276 2025-02-17 214038.png" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/\345\261\217\345\271\225\346\210\252\345\233\276 2025-02-17 214038.png" new file mode 100644 index 00000000..0b9221f6 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/\345\261\217\345\271\225\346\210\252\345\233\276 2025-02-17 214038.png" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/\345\261\217\345\271\225\346\210\252\345\233\276 2025-02-17 214129.png" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/\345\261\217\345\271\225\346\210\252\345\233\276 2025-02-17 214129.png" new file mode 100644 index 00000000..8db19494 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/\345\261\217\345\271\225\346\210\252\345\233\276 2025-02-17 214129.png" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/\345\261\217\345\271\225\346\210\252\345\233\276 2025-02-17 214223.png" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/\345\261\217\345\271\225\346\210\252\345\233\276 2025-02-17 214223.png" new file mode 100644 index 00000000..3a908c85 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\205\211\344\270\216\346\263\242\345\212\250/\345\261\217\345\271\225\346\210\252\345\233\276 2025-02-17 214223.png" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350229242.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350229242.jpg" new file mode 100644 index 00000000..f9a6f291 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350229242.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350230670.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350230670.jpg" new file mode 100644 index 00000000..90c96d85 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350230670.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350233054.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350233054.jpg" new file mode 100644 index 00000000..17f58367 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350233054.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350234159.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350234159.jpg" new file mode 100644 index 00000000..7dceb23a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350234159.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350235318.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350235318.jpg" new file mode 100644 index 00000000..b1a4eb4c Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350235318.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350236356.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350236356.jpg" new file mode 100644 index 00000000..54c05873 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350236356.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350237492.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350237492.jpg" new file mode 100644 index 00000000..a6d38add Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350237492.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350238604.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350238604.jpg" new file mode 100644 index 00000000..6ae405c4 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350238604.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350239786.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350239786.jpg" new file mode 100644 index 00000000..7cdaa177 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350239786.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350241217.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350241217.jpg" new file mode 100644 index 00000000..9155e5df Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350241217.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350242758.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350242758.jpg" new file mode 100644 index 00000000..1e60e08a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350242758.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350244234.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350244234.jpg" new file mode 100644 index 00000000..fc48b511 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350244234.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350245670.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350245670.jpg" new file mode 100644 index 00000000..988daddb Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350245670.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350247309.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350247309.jpg" new file mode 100644 index 00000000..d9ea0649 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350247309.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350248872.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350248872.jpg" new file mode 100644 index 00000000..b42c83b4 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350248872.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350250565.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350250565.jpg" new file mode 100644 index 00000000..ec748d29 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350250565.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350253035.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350253035.jpg" new file mode 100644 index 00000000..8b5d751e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350253035.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350255047.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350255047.jpg" new file mode 100644 index 00000000..81a9fb8c Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350255047.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350257334.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350257334.jpg" new file mode 100644 index 00000000..9de95ab4 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350257334.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350259379.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350259379.jpg" new file mode 100644 index 00000000..f5f10bb5 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\345\212\233\345\255\246/mmexport1711350259379.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696424994328.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696424994328.jpg" new file mode 100644 index 00000000..f2ed3d71 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696424994328.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696858480540.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696858480540.jpg" new file mode 100644 index 00000000..1932916a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696858480540.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696858721198.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696858721198.jpg" new file mode 100644 index 00000000..a29361bc Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696858721198.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696858742602.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696858742602.jpg" new file mode 100644 index 00000000..a29361bc Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696858742602.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696858746151.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696858746151.jpg" new file mode 100644 index 00000000..333f7da1 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696858746151.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696858748829.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696858748829.jpg" new file mode 100644 index 00000000..506e5581 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1696858748829.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073679086.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073679086.jpg" new file mode 100644 index 00000000..70b7f5f9 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073679086.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073685368.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073685368.jpg" new file mode 100644 index 00000000..a6390a99 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073685368.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073688269.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073688269.jpg" new file mode 100644 index 00000000..68493ad8 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073688269.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073690905.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073690905.jpg" new file mode 100644 index 00000000..46e5a8bc Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073690905.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073693425.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073693425.jpg" new file mode 100644 index 00000000..21d1b71b Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073693425.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073696075.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073696075.jpg" new file mode 100644 index 00000000..c9c03f26 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073696075.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073698844.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073698844.jpg" new file mode 100644 index 00000000..ee9c9289 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073698844.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073701525.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073701525.jpg" new file mode 100644 index 00000000..d6f7cdaf Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698073701525.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075891473.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075891473.jpg" new file mode 100644 index 00000000..3ce5a2fb Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075891473.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075896713.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075896713.jpg" new file mode 100644 index 00000000..5abfc568 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075896713.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075902739.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075902739.jpg" new file mode 100644 index 00000000..4f3d9f65 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075902739.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075905557.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075905557.jpg" new file mode 100644 index 00000000..313a009f Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075905557.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075908355.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075908355.jpg" new file mode 100644 index 00000000..d4516722 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075908355.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075911246.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075911246.jpg" new file mode 100644 index 00000000..1720ebdc Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075911246.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075917157.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075917157.jpg" new file mode 100644 index 00000000..5e4d29a0 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075917157.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075920324.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075920324.jpg" new file mode 100644 index 00000000..7083ec31 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698075920324.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698112843413.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698112843413.jpg" new file mode 100644 index 00000000..70b7f5f9 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1698112843413.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869882937.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869882937.jpg" new file mode 100644 index 00000000..23838269 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869882937.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908384.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908384.jpg" new file mode 100644 index 00000000..779ddf2d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908384.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908417.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908417.jpg" new file mode 100644 index 00000000..9a19a7e0 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908417.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908488.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908488.jpg" new file mode 100644 index 00000000..a6da3976 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908488.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908500.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908500.jpg" new file mode 100644 index 00000000..4bed840f Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908500.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908534.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908534.jpg" new file mode 100644 index 00000000..42ae0daf Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908534.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908572.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908572.jpg" new file mode 100644 index 00000000..d2b1a94d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908572.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908647.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908647.jpg" new file mode 100644 index 00000000..c3056032 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908647.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908712.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908712.jpg" new file mode 100644 index 00000000..6a156171 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908712.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908748.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908748.jpg" new file mode 100644 index 00000000..f29dc8c3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908748.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908790.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908790.jpg" new file mode 100644 index 00000000..4d6d5e23 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Image_1710869908790.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210432.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210432.jpg" new file mode 100644 index 00000000..1932916a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210432.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210434.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210434.jpg" new file mode 100644 index 00000000..a29361bc Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210434.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210437.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210437.jpg" new file mode 100644 index 00000000..333f7da1 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210437.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210442.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210442.jpg" new file mode 100644 index 00000000..7c947b47 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210442.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210446.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210446.jpg" new file mode 100644 index 00000000..506e5581 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210446.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210638.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210638.jpg" new file mode 100644 index 00000000..591aba6a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210638.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210640.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210640.jpg" new file mode 100644 index 00000000..e00a03fc Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210640.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210642.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210642.jpg" new file mode 100644 index 00000000..c88a7e59 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210642.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210645.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210645.jpg" new file mode 100644 index 00000000..b024a46c Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210645.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210647.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210647.jpg" new file mode 100644 index 00000000..ea54246d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231004_210647.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113103.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113103.jpg" new file mode 100644 index 00000000..10db1709 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113103.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113110.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113110.jpg" new file mode 100644 index 00000000..dea5b088 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113110.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113117.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113117.jpg" new file mode 100644 index 00000000..0e007921 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113117.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113123.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113123.jpg" new file mode 100644 index 00000000..9e0420dd Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113123.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113129.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113129.jpg" new file mode 100644 index 00000000..548a3345 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113129.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113133.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113133.jpg" new file mode 100644 index 00000000..bbafc4bd Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113133.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113137.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113137.jpg" new file mode 100644 index 00000000..0a1ccc0d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113137.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113140.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113140.jpg" new file mode 100644 index 00000000..1333fcd5 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113140.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113144.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113144.jpg" new file mode 100644 index 00000000..0d84861a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113144.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113148.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113148.jpg" new file mode 100644 index 00000000..6afe3e17 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/Screenshot_20231024_113148.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/mmexport1698114155264.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/mmexport1698114155264.jpg" new file mode 100644 index 00000000..f0349be4 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/mmexport1698114155264.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/mmexport1698114210837.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/mmexport1698114210837.jpg" new file mode 100644 index 00000000..f0349be4 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\224\265\347\243\201/mmexport1698114210837.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1710869908549.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1710869908549.jpg" new file mode 100644 index 00000000..c29eaf40 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1710869908549.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190717921.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190717921.jpg" new file mode 100644 index 00000000..27ea5db6 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190717921.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190717996.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190717996.jpg" new file mode 100644 index 00000000..3ba75167 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190717996.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718035.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718035.jpg" new file mode 100644 index 00000000..ecf35a4a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718035.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718070.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718070.jpg" new file mode 100644 index 00000000..7c0e75fd Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718070.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718104.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718104.jpg" new file mode 100644 index 00000000..8d541de5 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718104.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718106.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718106.jpg" new file mode 100644 index 00000000..9cc8ea68 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718106.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718139.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718139.jpg" new file mode 100644 index 00000000..58c233f5 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718139.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718251.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718251.jpg" new file mode 100644 index 00000000..c8b34bd5 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1711190718251.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1716778987267.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1716778987267.jpg" new file mode 100644 index 00000000..07f8ab81 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1716778987267.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1716779012152.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1716779012152.jpg" new file mode 100644 index 00000000..aee52460 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1716779012152.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1716779019650.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1716779019650.jpg" new file mode 100644 index 00000000..d80d4865 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Image_1716779019650.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145032.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145032.jpg" new file mode 100644 index 00000000..8fcc80e3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145032.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145040.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145040.jpg" new file mode 100644 index 00000000..2c377e00 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145040.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145047.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145047.jpg" new file mode 100644 index 00000000..0cd63284 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145047.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145051.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145051.jpg" new file mode 100644 index 00000000..6edfa0c3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145051.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145055.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145055.jpg" new file mode 100644 index 00000000..78ccecdc Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145055.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145059.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145059.jpg" new file mode 100644 index 00000000..f38534c1 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145059.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145104.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145104.jpg" new file mode 100644 index 00000000..a4acf24d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145104.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145107.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145107.jpg" new file mode 100644 index 00000000..67818606 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145107.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145110.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145110.jpg" new file mode 100644 index 00000000..b6f2920a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145110.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145114.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145114.jpg" new file mode 100644 index 00000000..f19755fd Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_145114.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_150137.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_150137.jpg" new file mode 100644 index 00000000..4ccc4ab0 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\345\260\217\346\265\213 \350\277\207\346\227\266 \347\216\260\344\275\277\347\224\250\345\255\246\346\240\241\351\242\230\345\272\223/\347\233\270\345\257\271\350\256\272\343\200\201\347\203\255\345\255\246\343\200\201\346\260\224\344\275\223/Screenshot_20240527_150137.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2018 A.docx" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2018 A.docx" new file mode 100644 index 00000000..7a56e0d7 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2018 A.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6d86c425ee81548114d0599ed537eed47aa837333dd76ad84d46a505f873e739 +size 93035 diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2019 A.docx" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2019 A.docx" new file mode 100644 index 00000000..ea893b74 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2019 A.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f2c432567f8afb7f82e8d1736a8bd6c0893610f297dd4638276d11603780e67d +size 209448 diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2020.docx" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2020.docx" new file mode 100644 index 00000000..e30a73a7 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2020.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:71266f4e13e2d39fcc3671656ca66d8ff82821d7572148b247b866d5f4e3d755 +size 669815 diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2021-1.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2021-1.jpg" new file mode 100644 index 00000000..814aeed9 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2021-1.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2021-2.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2021-2.jpg" new file mode 100644 index 00000000..59bac394 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2021-2.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2021-3.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2021-3.jpg" new file mode 100644 index 00000000..36f636fd Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2021-3.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2021-4.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2021-4.jpg" new file mode 100644 index 00000000..2c29e653 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2021-4.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2022-1.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2022-1.jpg" new file mode 100644 index 00000000..3469cf87 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2022-1.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2022-2.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2022-2.jpg" new file mode 100644 index 00000000..a3d49961 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2022-2.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2022-3.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2022-3.jpg" new file mode 100644 index 00000000..24932d66 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2022-3.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2022-4.jpg" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2022-4.jpg" new file mode 100644 index 00000000..8ef601f0 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\344\270\200\344\272\233\345\216\237\345\247\213\350\257\225\345\215\267/2022-4.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/14151\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\351\242\230\350\247\243.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/14151\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\351\242\230\350\247\243.doc" new file mode 100644 index 00000000..d9eaf114 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/14151\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\351\242\230\350\247\243.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/14151\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\267.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/14151\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\267.doc" new file mode 100644 index 00000000..72e376d2 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/14151\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\267.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/15161\343\200\212\345\244\247\347\211\251\343\200\213A\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\350\247\243\347\255\224.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/15161\343\200\212\345\244\247\347\211\251\343\200\213A\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\350\247\243\347\255\224.doc" new file mode 100644 index 00000000..27ae89a0 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/15161\343\200\212\345\244\247\347\211\251\343\200\213A\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\350\247\243\347\255\224.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/15161\343\200\212\345\244\247\347\211\251\343\200\213A\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\267.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/15161\343\200\212\345\244\247\347\211\251\343\200\213A\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\267.doc" new file mode 100644 index 00000000..725dc0da Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/15161\343\200\212\345\244\247\347\211\251\343\200\213A\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\267.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/15161\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\350\247\243\347\255\224.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/15161\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\350\247\243\347\255\224.doc" new file mode 100644 index 00000000..6a356ab8 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/15161\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\350\247\243\347\255\224.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/15161\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\267.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/15161\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\267.doc" new file mode 100644 index 00000000..28beda1a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/15161\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\267.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/16171\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\345\217\202\350\200\203\347\255\224\346\241\210.docx" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/16171\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\345\217\202\350\200\203\347\255\224\346\241\210.docx" new file mode 100644 index 00000000..5786d011 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/16171\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\345\217\202\350\200\203\347\255\224\346\241\210.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3dac286b4328c786351324b7b9db01bb2d8a991b8a432a236815e164405bf956 +size 162738 diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/17181\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206A\344\270\213\343\200\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\26720180111.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/17181\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206A\344\270\213\343\200\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\26720180111.doc" new file mode 100644 index 00000000..dda08f79 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/17181\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206A\344\270\213\343\200\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\26720180111.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/17181\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\345\217\202\350\200\203\347\255\224\346\241\21020180102.docx" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/17181\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\345\217\202\350\200\203\347\255\224\346\241\21020180102.docx" new file mode 100644 index 00000000..609d60bf --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/17181\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\345\217\202\350\200\203\347\255\224\346\241\21020180102.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:decde78821c5bb1182415fbcb41ba651c863172b8c505c79fd00c8b30907bef6 +size 262879 diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/17181\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\26720180111.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/17181\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\26720180111.doc" new file mode 100644 index 00000000..172d795d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/17181\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\26720180111.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\20513141\345\244\247\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\2672.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\20513141\345\244\247\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\2672.doc" new file mode 100644 index 00000000..c99db439 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\20513141\345\244\247\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\2672.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20510111\346\231\256\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267\347\255\224\346\241\210(A)\345\215\267.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20510111\346\231\256\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267\347\255\224\346\241\210(A)\345\215\267.doc" new file mode 100644 index 00000000..ab0ff8f1 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20510111\346\231\256\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267\347\255\224\346\241\210(A)\345\215\267.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20512131\346\231\256\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267\350\247\243\347\255\224.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20512131\346\231\256\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267\350\247\243\347\255\224.doc" new file mode 100644 index 00000000..eaf3f349 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20512131\346\231\256\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267\350\247\243\347\255\224.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20513141\345\244\247\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\2672\357\274\210B\345\215\267\357\274\211.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20513141\345\244\247\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\2672\357\274\210B\345\215\267\357\274\211.doc" new file mode 100644 index 00000000..c99db439 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20513141\345\244\247\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\2672\357\274\210B\345\215\267\357\274\211.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20513141\345\244\247\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\350\247\243\347\255\224.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20513141\345\244\247\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\350\247\243\347\255\224.doc" new file mode 100644 index 00000000..ca7a3c4b Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20513141\345\244\247\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\350\247\243\347\255\224.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20513141\345\244\247\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\350\247\243\347\255\224\346\226\260(1).doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20513141\345\244\247\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\350\247\243\347\255\224\346\226\260(1).doc" new file mode 100644 index 00000000..c8908909 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20513141\345\244\247\347\211\251B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\350\247\243\347\255\224\346\226\260(1).doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20514151\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\351\242\230\350\247\243.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20514151\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\351\242\230\350\247\243.doc" new file mode 100644 index 00000000..49f39fea Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20514151\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267A\345\215\267\351\242\230\350\247\243.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20514151\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\267.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20514151\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\267.doc" new file mode 100644 index 00000000..72e376d2 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\20514151\343\200\212\345\244\247\347\211\251\343\200\213B\344\270\213\346\234\237\346\234\253\350\257\225\345\215\267B\345\215\267.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\205\347\254\254\344\272\214\345\255\246\346\234\237\346\234\237\346\234\253\346\234\211\345\205\263\350\257\225\351\242\2302010\344\271\213\345\211\215.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\205\347\254\254\344\272\214\345\255\246\346\234\237\346\234\237\346\234\253\346\234\211\345\205\263\350\257\225\351\242\2302010\344\271\213\345\211\215.doc" new file mode 100644 index 00000000..3a28e107 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\205\347\254\254\344\272\214\345\255\246\346\234\237\346\234\237\346\234\253\346\234\211\345\205\263\350\257\225\351\242\2302010\344\271\213\345\211\215.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\205\347\254\254\344\272\214\345\255\246\346\234\237\346\234\237\346\234\253\350\257\225\351\242\2302010\344\271\213\345\211\215.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\205\347\254\254\344\272\214\345\255\246\346\234\237\346\234\237\346\234\253\350\257\225\351\242\2302010\344\271\213\345\211\215.doc" new file mode 100644 index 00000000..856d0c2e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\205\347\254\254\344\272\214\345\255\246\346\234\237\346\234\237\346\234\253\350\257\225\351\242\2302010\344\271\213\345\211\215.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\205\347\254\254\344\272\214\345\255\246\346\234\237\346\234\237\346\234\253\350\257\225\351\242\2302010\344\271\213\345\211\215111.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\205\347\254\254\344\272\214\345\255\246\346\234\237\346\234\237\346\234\253\350\257\225\351\242\2302010\344\271\213\345\211\215111.doc" new file mode 100644 index 00000000..439bf10c Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\342\230\205\342\230\205\342\230\205\342\230\205\347\254\254\344\272\214\345\255\246\346\234\237\346\234\237\346\234\253\350\257\225\351\242\2302010\344\271\213\345\211\215111.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/13141\345\244\247\347\211\251B\344\270\213\346\225\231\345\255\246\350\277\233\345\272\246\350\241\250.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/13141\345\244\247\347\211\251B\344\270\213\346\225\231\345\255\246\350\277\233\345\272\246\350\241\250.doc" new file mode 100644 index 00000000..4abef31f Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/13141\345\244\247\347\211\251B\344\270\213\346\225\231\345\255\246\350\277\233\345\272\246\350\241\250.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/14151\345\244\247\347\211\251B\344\270\213\346\225\231\345\255\246\350\277\233\345\272\246\350\241\250.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/14151\345\244\247\347\211\251B\344\270\213\346\225\231\345\255\246\350\277\233\345\272\246\350\241\250.doc" new file mode 100644 index 00000000..52b591e7 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/14151\345\244\247\347\211\251B\344\270\213\346\225\231\345\255\246\350\277\233\345\272\246\350\241\250.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/\342\230\205\342\230\205\342\230\205\347\254\25411\347\253\240 \346\214\257\345\212\250\345\222\214\346\263\242\345\212\250\344\276\213\351\242\230\357\274\233\347\254\25412\347\253\240 \346\263\242\345\212\250\345\205\211\345\255\246\344\276\213\351\242\230.ppt" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/\342\230\205\342\230\205\342\230\205\347\254\25411\347\253\240 \346\214\257\345\212\250\345\222\214\346\263\242\345\212\250\344\276\213\351\242\230\357\274\233\347\254\25412\347\253\240 \346\263\242\345\212\250\345\205\211\345\255\246\344\276\213\351\242\230.ppt" new file mode 100644 index 00000000..a5fe7a27 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/\342\230\205\342\230\205\342\230\205\347\254\25411\347\253\240 \346\214\257\345\212\250\345\222\214\346\263\242\345\212\250\344\276\213\351\242\230\357\274\233\347\254\25412\347\253\240 \346\263\242\345\212\250\345\205\211\345\255\246\344\276\213\351\242\230.ppt" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/\342\230\205\342\230\205\342\230\205\347\254\25411\347\253\240 \346\214\257\345\212\250\345\222\214\346\263\242\345\212\250\345\260\217\347\273\223\357\274\233\347\254\25412\347\253\240 \346\263\242\345\212\250\345\205\211\345\255\246\345\260\217\347\273\223.ppt" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/\342\230\205\342\230\205\342\230\205\347\254\25411\347\253\240 \346\214\257\345\212\250\345\222\214\346\263\242\345\212\250\345\260\217\347\273\223\357\274\233\347\254\25412\347\253\240 \346\263\242\345\212\250\345\205\211\345\255\246\345\260\217\347\273\223.ppt" new file mode 100644 index 00000000..c60b3f27 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/\342\230\205\342\230\205\342\230\205\347\254\25411\347\253\240 \346\214\257\345\212\250\345\222\214\346\263\242\345\212\250\345\260\217\347\273\223\357\274\233\347\254\25412\347\253\240 \346\263\242\345\212\250\345\205\211\345\255\246\345\260\217\347\273\223.ppt" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/\342\230\205\342\230\205\357\274\210\345\205\263\344\272\216\345\205\211\346\240\205\351\227\256\351\242\230\357\274\211\347\232\204\345\256\232\351\207\217\345\210\206\346\236\220.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/\342\230\205\342\230\205\357\274\210\345\205\263\344\272\216\345\205\211\346\240\205\351\227\256\351\242\230\357\274\211\347\232\204\345\256\232\351\207\217\345\210\206\346\236\220.doc" new file mode 100644 index 00000000..f58a743e Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/\342\230\205\342\230\205\357\274\210\345\205\263\344\272\216\345\205\211\346\240\205\351\227\256\351\242\230\357\274\211\347\232\204\345\256\232\351\207\217\345\210\206\346\236\220.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/\342\230\205\342\230\205\357\274\210\345\205\263\344\272\216\345\215\225\347\274\235\350\241\215\345\260\204\357\274\211\347\232\204\346\214\257\345\212\250\347\237\242\351\207\217\345\220\210\346\210\220\346\263\225\345\222\214\342\200\234\345\256\232\351\207\217\345\210\206\346\236\220\346\263\225\342\200\235.doc" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/\342\230\205\342\230\205\357\274\210\345\205\263\344\272\216\345\215\225\347\274\235\350\241\215\345\260\204\357\274\211\347\232\204\346\214\257\345\212\250\347\237\242\351\207\217\345\220\210\346\210\220\346\263\225\345\222\214\342\200\234\345\256\232\351\207\217\345\210\206\346\236\220\346\263\225\342\200\235.doc" new file mode 100644 index 00000000..1b44c28a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\345\244\247\347\211\251\344\270\213\346\234\237\346\234\25311\350\207\26318 2/\345\256\236\351\252\214/\342\230\205\342\230\205\357\274\210\345\205\263\344\272\216\345\215\225\347\274\235\350\241\215\345\260\204\357\274\211\347\232\204\346\214\257\345\212\250\347\237\242\351\207\217\345\220\210\346\210\220\346\263\225\345\222\214\342\200\234\345\256\232\351\207\217\345\210\206\346\236\220\346\263\225\342\200\235.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/2019\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267.docx" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/2019\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267.docx" new file mode 100644 index 00000000..21612200 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/2019\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c0b74144b93d15cf72e3d316ff4e5326ae6b30fcd616a2723fb7e79c5ea81c77 +size 577219 diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/2021\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267\345\217\202\350\200\203\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/2021\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267\345\217\202\350\200\203\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..a671aff4 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/2021\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267\345\217\202\350\200\203\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/2022\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/2022\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267.pdf" new file mode 100644 index 00000000..42217778 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/2022\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/2023\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213_\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/2023\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213_\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..299d8eb4 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/2023\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213_\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/22\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267 2.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/22\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267 2.pdf" new file mode 100644 index 00000000..a819bcd3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/22\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267 2.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/22\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/22\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267.pdf" new file mode 100644 index 00000000..a819bcd3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/22\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/_\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213_\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/_\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213_\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..299d8eb4 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/_\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213_\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267.pdf" new file mode 100644 index 00000000..a819bcd3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/\343\200\212\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213\343\200\213\346\234\237\344\270\255\350\257\225\345\215\267A\345\215\267.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213 \346\234\237\344\270\255 2020.11 (1).pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213 \346\234\237\344\270\255 2020.11 (1).pdf" new file mode 100644 index 00000000..0f6e2171 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\344\270\255/\345\244\247\345\255\246\347\211\251\347\220\206B\344\270\213 \346\234\237\344\270\255 2020.11 (1).pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/1819B\357\274\210A\345\215\267\357\274\211.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/1819B\357\274\210A\345\215\267\357\274\211.pdf" new file mode 100644 index 00000000..64dfc1dc Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/1819B\357\274\210A\345\215\267\357\274\211.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/19-20\345\244\247\347\211\251b\344\270\213.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/19-20\345\244\247\347\211\251b\344\270\213.pdf" new file mode 100644 index 00000000..1467a471 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/19-20\345\244\247\347\211\251b\344\270\213.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/2021\357\274\210A\345\215\267\357\274\211(1).pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/2021\357\274\210A\345\215\267\357\274\211(1).pdf" new file mode 100644 index 00000000..5faca773 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/2021\357\274\210A\345\215\267\357\274\211(1).pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/2021\357\274\210A\345\215\267\357\274\211\347\255\224\346\241\210.docx" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/2021\357\274\210A\345\215\267\357\274\211\347\255\224\346\241\210.docx" new file mode 100644 index 00000000..b1367922 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/2021\357\274\210A\345\215\267\357\274\211\347\255\224\346\241\210.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:2f25333d269942960a35c6dc03ed40bef73042e2f97bdfa79dfa4883d0fb6ea0 +size 211046 diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/2022.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/2022.pdf" new file mode 100644 index 00000000..9b298d08 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/2022.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/24B\344\270\213\346\234\237\346\234\253.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/24B\344\270\213\346\234\237\346\234\253.pdf" new file mode 100644 index 00000000..fbf76bfd Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/24B\344\270\213\346\234\237\346\234\253.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/3B\344\270\213\346\234\237\346\234\253 22B\345\215\267.pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/3B\344\270\213\346\234\237\346\234\253 22B\345\215\267.pdf" new file mode 100644 index 00000000..b2160cc1 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/3B\344\270\213\346\234\237\346\234\253 22B\345\215\267.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/\344\277\241\351\231\2422023\345\244\247\347\211\251b\344\270\213 (1).pdf" "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/\344\277\241\351\231\2422023\345\244\247\347\211\251b\344\270\213 (1).pdf" new file mode 100644 index 00000000..1467a471 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\345\244\247\347\211\251B\344\270\213/\350\257\225\345\215\267/\346\234\237\346\234\253/\344\277\241\351\231\2422023\345\244\247\347\211\251b\344\270\213 (1).pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/2023\346\257\233\346\246\202\346\200\235\350\200\203\351\242\230.docx" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/2023\346\257\233\346\246\202\346\200\235\350\200\203\351\242\230.docx" similarity index 100% rename from "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/2023\346\257\233\346\246\202\346\200\235\350\200\203\351\242\230.docx" rename to "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/2023\346\257\233\346\246\202\346\200\235\350\200\203\351\242\230.docx" diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/4-8\346\257\233\346\246\202\346\200\235\350\200\203\351\242\230.docx" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/4-8\346\257\233\346\246\202\346\200\235\350\200\203\351\242\230.docx" similarity index 100% rename from "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/4-8\346\257\233\346\246\202\346\200\235\350\200\203\351\242\230.docx" rename to "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/4-8\346\257\233\346\246\202\346\200\235\350\200\203\351\242\230.docx" diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\343\200\220\346\257\233\346\246\202\343\200\221\351\200\211\346\213\251\351\242\230\351\242\230\345\272\223 \346\234\200\345\256\214\346\225\264\347\211\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\343\200\220\346\257\233\346\246\202\343\200\221\351\200\211\346\213\251\351\242\230\351\242\230\345\272\223 \346\234\200\345\256\214\346\225\264\347\211\210.pdf" similarity index 100% rename from "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\343\200\220\346\257\233\346\246\202\343\200\221\351\200\211\346\213\251\351\242\230\351\242\230\345\272\223 \346\234\200\345\256\214\346\225\264\347\211\210.pdf" rename to "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\343\200\220\346\257\233\346\246\202\343\200\221\351\200\211\346\213\251\351\242\230\351\242\230\345\272\223 \346\234\200\345\256\214\346\225\264\347\211\210.pdf" diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\344\271\240\346\200\235\346\203\263\346\200\235\350\200\203\351\242\230\347\255\224\346\241\210\346\261\207\346\200\273.docx" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\344\271\240\346\200\235\346\203\263\346\200\235\350\200\203\351\242\230\347\255\224\346\241\210\346\261\207\346\200\273.docx" similarity index 100% rename from "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\344\271\240\346\200\235\346\203\263\346\200\235\350\200\203\351\242\230\347\255\224\346\241\210\346\261\207\346\200\273.docx" rename to "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\344\271\240\346\200\235\346\203\263\346\200\235\350\200\203\351\242\230\347\255\224\346\241\210\346\261\207\346\200\273.docx" diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\345\244\215\344\271\240\344\270\216\346\200\273\347\273\223.pptx" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\345\244\215\344\271\240\344\270\216\346\200\273\347\273\223.pptx" new file mode 100644 index 00000000..7d19ad0c --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\345\244\215\344\271\240\344\270\216\346\200\273\347\273\223.pptx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:436eb39b818ad9911fdf6f26ee4f1ba95ef4487213b73a383af3b8775e37f85e +size 12201334 diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\256\242\350\247\202\351\242\230\343\200\212\346\257\233\346\263\275\344\270\234\346\200\235\346\203\263\345\222\214\344\270\255\345\233\275\347\211\271\350\211\262\347\244\276\344\274\232\344\270\273\344\271\211\347\220\206\350\256\272\344\275\223\347\263\273\346\246\202\350\256\272\343\200\213\345\244\215\344\271\240\350\265\204\346\226\231.doc" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\345\256\242\350\247\202\351\242\230\343\200\212\346\257\233\346\263\275\344\270\234\346\200\235\346\203\263\345\222\214\344\270\255\345\233\275\347\211\271\350\211\262\347\244\276\344\274\232\344\270\273\344\271\211\347\220\206\350\256\272\344\275\223\347\263\273\346\246\202\350\256\272\343\200\213\345\244\215\344\271\240\350\265\204\346\226\231.doc" similarity index 100% rename from "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\256\242\350\247\202\351\242\230\343\200\212\346\257\233\346\263\275\344\270\234\346\200\235\346\203\263\345\222\214\344\270\255\345\233\275\347\211\271\350\211\262\347\244\276\344\274\232\344\270\273\344\271\211\347\220\206\350\256\272\344\275\223\347\263\273\346\246\202\350\256\272\343\200\213\345\244\215\344\271\240\350\265\204\346\226\231.doc" rename to "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\345\256\242\350\247\202\351\242\230\343\200\212\346\257\233\346\263\275\344\270\234\346\200\235\346\203\263\345\222\214\344\270\255\345\233\275\347\211\271\350\211\262\347\244\276\344\274\232\344\270\273\344\271\211\347\220\206\350\256\272\344\275\223\347\263\273\346\246\202\350\256\272\343\200\213\345\244\215\344\271\240\350\265\204\346\226\231.doc" diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\346\230\223\351\224\231\345\256\242\350\247\202\351\242\230.docx" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\346\230\223\351\224\231\345\256\242\350\247\202\351\242\230.docx" similarity index 100% rename from "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\346\230\223\351\224\231\345\256\242\350\247\202\351\242\230.docx" rename to "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\346\230\223\351\224\231\345\256\242\350\247\202\351\242\230.docx" diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\346\257\233\346\246\202PPT\346\200\235\350\200\203\351\242\230\346\261\207\346\200\2732023.docx" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\346\257\233\346\246\202PPT\346\200\235\350\200\203\351\242\230\346\261\207\346\200\2732023.docx" similarity index 100% rename from "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\346\257\233\346\246\202PPT\346\200\235\350\200\203\351\242\230\346\261\207\346\200\2732023.docx" rename to "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\346\257\233\346\246\202PPT\346\200\235\350\200\203\351\242\230\346\261\207\346\200\2732023.docx" diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\346\257\233\346\246\202\343\200\201\344\271\240\347\211\271\345\222\214\345\206\233\347\220\206\345\244\215\344\271\240\346\234\200\347\273\210\347\211\210.docx" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\346\257\233\346\246\202\343\200\201\344\271\240\347\211\271\345\222\214\345\206\233\347\220\206\345\244\215\344\271\240\346\234\200\347\273\210\347\211\210.docx" similarity index 100% rename from "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\346\257\233\346\246\202\343\200\201\344\271\240\347\211\271\345\222\214\345\206\233\347\220\206\345\244\215\344\271\240\346\234\200\347\273\210\347\211\210.docx" rename to "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\346\257\233\346\246\202\343\200\201\344\271\240\347\211\271\345\222\214\345\206\233\347\220\206\345\244\215\344\271\240\346\234\200\347\273\210\347\211\210.docx" diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\346\257\233\346\246\202\346\200\235\350\200\203\351\242\230 \350\241\245\345\205\205\347\211\210.doc" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\346\257\233\346\246\202\346\200\235\350\200\203\351\242\230 \350\241\245\345\205\205\347\211\210.doc" similarity index 100% rename from "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\346\257\233\346\246\202\346\200\235\350\200\203\351\242\230 \350\241\245\345\205\205\347\211\210.doc" rename to "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\346\257\233\346\246\202\346\200\235\350\200\203\351\242\230 \350\241\245\345\205\205\347\211\210.doc" diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\346\257\233\346\246\202\346\200\235\350\200\203\351\242\230\346\261\207\346\200\2732024.docx" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\346\257\233\346\246\202\346\200\235\350\200\203\351\242\230\346\261\207\346\200\2732024.docx" similarity index 100% rename from "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\346\257\233\346\246\202\346\200\235\350\200\203\351\242\230\346\261\207\346\200\2732024.docx" rename to "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\346\257\233\346\246\202\346\200\235\350\200\203\351\242\230\346\261\207\346\200\2732024.docx" diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\346\257\233\346\246\202\351\200\211\346\213\251\351\242\230.pdf" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\346\257\233\346\246\202\351\200\211\346\213\251\351\242\230.pdf" similarity index 100% rename from "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\346\257\233\346\246\202\351\200\211\346\213\251\351\242\230.pdf" rename to "\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\244\215\344\271\240\350\265\204\346\226\231/\346\257\233\346\246\202\351\200\211\346\213\251\351\242\230.pdf" diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\276\200\345\271\264\345\215\267 \344\270\223\344\270\232\344\270\215\346\230\216/\345\216\246\351\227\250\345\244\247\345\255\246\343\200\212\346\257\233\346\263\275\344\270\234\346\200\235\346\203\263\345\222\214\344\270\255\345\233\275\347\211\271\350\211\262\347\244\276\344\274\232\344\270\273\344\271\211\347\220\206\350\256\272\344\275\223\347\263\273\346\246\202\350\256\272\343\200\2132017-2018\345\255\246\345\271\264\346\234\237\346\234\253\350\257\225\345\215\267.pdf" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\276\200\345\271\264\345\215\267 \344\270\223\344\270\232\344\270\215\346\230\216/\345\216\246\351\227\250\345\244\247\345\255\246\343\200\212\346\257\233\346\263\275\344\270\234\346\200\235\346\203\263\345\222\214\344\270\255\345\233\275\347\211\271\350\211\262\347\244\276\344\274\232\344\270\273\344\271\211\347\220\206\350\256\272\344\275\223\347\263\273\346\246\202\350\256\272\343\200\2132017-2018\345\255\246\345\271\264\346\234\237\346\234\253\350\257\225\345\215\267.pdf" new file mode 100644 index 00000000..83eaa60c Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\276\200\345\271\264\345\215\267 \344\270\223\344\270\232\344\270\215\346\230\216/\345\216\246\351\227\250\345\244\247\345\255\246\343\200\212\346\257\233\346\263\275\344\270\234\346\200\235\346\203\263\345\222\214\344\270\255\345\233\275\347\211\271\350\211\262\347\244\276\344\274\232\344\270\273\344\271\211\347\220\206\350\256\272\344\275\223\347\263\273\346\246\202\350\256\272\343\200\2132017-2018\345\255\246\345\271\264\346\234\237\346\234\253\350\257\225\345\215\267.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\276\200\345\271\264\345\215\267 \344\270\223\344\270\232\344\270\215\346\230\216/\345\216\246\351\227\250\345\244\247\345\255\246\343\200\212\346\257\233\346\263\275\344\270\234\346\200\235\346\203\263\345\222\214\344\270\255\345\233\275\347\211\271\350\211\262\347\244\276\344\274\232\344\270\273\344\271\211\347\220\206\350\256\272\344\275\223\347\263\273\346\246\202\350\256\272\343\200\2132022-2023\345\255\246\345\271\264\346\234\237\346\234\253\350\257\225\345\215\267.pdf" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\276\200\345\271\264\345\215\267 \344\270\223\344\270\232\344\270\215\346\230\216/\345\216\246\351\227\250\345\244\247\345\255\246\343\200\212\346\257\233\346\263\275\344\270\234\346\200\235\346\203\263\345\222\214\344\270\255\345\233\275\347\211\271\350\211\262\347\244\276\344\274\232\344\270\273\344\271\211\347\220\206\350\256\272\344\275\223\347\263\273\346\246\202\350\256\272\343\200\2132022-2023\345\255\246\345\271\264\346\234\237\346\234\253\350\257\225\345\215\267.pdf" new file mode 100644 index 00000000..1eaf320a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\276\200\345\271\264\345\215\267 \344\270\223\344\270\232\344\270\215\346\230\216/\345\216\246\351\227\250\345\244\247\345\255\246\343\200\212\346\257\233\346\263\275\344\270\234\346\200\235\346\203\263\345\222\214\344\270\255\345\233\275\347\211\271\350\211\262\347\244\276\344\274\232\344\270\273\344\271\211\347\220\206\350\256\272\344\275\223\347\263\273\346\246\202\350\256\272\343\200\2132022-2023\345\255\246\345\271\264\346\234\237\346\234\253\350\257\225\345\215\267.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\276\200\345\271\264\345\215\267 \344\270\223\344\270\232\344\270\215\346\230\216/\345\216\246\351\227\250\345\244\247\345\255\246\343\200\212\346\257\233\346\263\275\344\270\234\346\200\235\346\203\263\345\222\214\344\270\255\345\233\275\347\211\271\350\211\262\347\244\276\344\274\232\344\270\273\344\271\211\347\220\206\350\256\272\344\275\223\347\263\273\346\246\202\350\256\272\347\220\206\343\200\2132021-2022\345\255\246\345\271\264\346\234\237\346\234\253\350\257\225\345\215\267.pdf" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\276\200\345\271\264\345\215\267 \344\270\223\344\270\232\344\270\215\346\230\216/\345\216\246\351\227\250\345\244\247\345\255\246\343\200\212\346\257\233\346\263\275\344\270\234\346\200\235\346\203\263\345\222\214\344\270\255\345\233\275\347\211\271\350\211\262\347\244\276\344\274\232\344\270\273\344\271\211\347\220\206\350\256\272\344\275\223\347\263\273\346\246\202\350\256\272\347\220\206\343\200\2132021-2022\345\255\246\345\271\264\346\234\237\346\234\253\350\257\225\345\215\267.pdf" new file mode 100644 index 00000000..ad56a0d8 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\276\200\345\271\264\345\215\267 \344\270\223\344\270\232\344\270\215\346\230\216/\345\216\246\351\227\250\345\244\247\345\255\246\343\200\212\346\257\233\346\263\275\344\270\234\346\200\235\346\203\263\345\222\214\344\270\255\345\233\275\347\211\271\350\211\262\347\244\276\344\274\232\344\270\273\344\271\211\347\220\206\350\256\272\344\275\223\347\263\273\346\246\202\350\256\272\347\220\206\343\200\2132021-2022\345\255\246\345\271\264\346\234\237\346\234\253\350\257\225\345\215\267.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\276\200\345\271\264\345\215\267 \344\270\223\344\270\232\344\270\215\346\230\216/\345\216\246\351\227\250\345\244\247\345\255\246\346\257\233\346\246\2022019\345\271\264\350\257\225\345\215\267\345\217\212\347\255\224\346\241\210\345\205\26112\351\241\265(1).pdf" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\276\200\345\271\264\345\215\267 \344\270\223\344\270\232\344\270\215\346\230\216/\345\216\246\351\227\250\345\244\247\345\255\246\346\257\233\346\246\2022019\345\271\264\350\257\225\345\215\267\345\217\212\347\255\224\346\241\210\345\205\26112\351\241\265(1).pdf" new file mode 100644 index 00000000..92537de8 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\276\200\345\271\264\345\215\267 \344\270\223\344\270\232\344\270\215\346\230\216/\345\216\246\351\227\250\345\244\247\345\255\246\346\257\233\346\246\2022019\345\271\264\350\257\225\345\215\267\345\217\212\347\255\224\346\241\210\345\205\26112\351\241\265(1).pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\276\200\345\271\264\345\215\267 \344\270\223\344\270\232\344\270\215\346\230\216/\345\216\246\351\227\250\345\244\247\345\255\246\346\257\233\346\263\275\344\270\234\346\200\235\346\203\263\345\222\214\344\270\255\345\233\275\347\211\271\350\211\262\347\244\276\344\274\232\344\270\273\344\271\211\344\275\223\347\263\273(1).pdf" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\276\200\345\271\264\345\215\267 \344\270\223\344\270\232\344\270\215\346\230\216/\345\216\246\351\227\250\345\244\247\345\255\246\346\257\233\346\263\275\344\270\234\346\200\235\346\203\263\345\222\214\344\270\255\345\233\275\347\211\271\350\211\262\347\244\276\344\274\232\344\270\273\344\271\211\344\275\223\347\263\273(1).pdf" new file mode 100644 index 00000000..432bb30d Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\345\276\200\345\271\264\345\215\267 \344\270\223\344\270\232\344\270\215\346\230\216/\345\216\246\351\227\250\345\244\247\345\255\246\346\257\233\346\263\275\344\270\234\346\200\235\346\203\263\345\222\214\344\270\255\345\233\275\347\211\271\350\211\262\347\244\276\344\274\232\344\270\273\344\271\211\344\275\223\347\263\273(1).pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\350\257\276\347\250\213\347\256\200\344\273\213.md" "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\350\257\276\347\250\213\347\256\200\344\273\213.md" new file mode 100644 index 00000000..5d429165 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/\346\257\233\346\246\202/\350\257\276\347\250\213\347\256\200\344\273\213.md" @@ -0,0 +1,5 @@ +### 同学1: + +* 期末考范围是简答题和选择题 +* 选择题期末考前(比如一周)会开放题库,刷一遍、认真记还是能几乎全对的 +* 简答题见``复习与总结.pptx``是yx老师整理的,非常好用!对着大纲划书即可。不过简答题肯定不会按照书上的课后题原模原样考,所以必须记内容而非框架 \ No newline at end of file diff --git "a/\345\244\247\344\272\214\344\270\212/\346\261\207\347\274\226\350\257\255\350\250\200/\344\275\234\344\270\232/1_\346\261\207\347\274\226\350\257\255\350\250\200\344\271\240\351\242\230\347\255\224\346\241\210.pdf" "b/\345\244\247\344\272\214\344\270\212/\346\261\207\347\274\226\350\257\255\350\250\200/\344\275\234\344\270\232/1_\346\261\207\347\274\226\350\257\255\350\250\200\344\271\240\351\242\230\347\255\224\346\241\210.pdf" new file mode 100644 index 00000000..ce90cf56 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\346\261\207\347\274\226\350\257\255\350\250\200/\344\275\234\344\270\232/1_\346\261\207\347\274\226\350\257\255\350\250\200\344\271\240\351\242\230\347\255\224\346\241\210.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\346\261\207\347\274\226\350\257\255\350\250\200/\346\234\237\346\234\253/\346\261\207\347\274\22624\347\272\247\346\234\237\346\234\253\350\214\203\345\233\264.pdf" "b/\345\244\247\344\272\214\344\270\212/\346\261\207\347\274\226\350\257\255\350\250\200/\346\234\237\346\234\253/\346\261\207\347\274\22624\347\272\247\346\234\237\346\234\253\350\214\203\345\233\264.pdf" new file mode 100644 index 00000000..7810a992 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\346\261\207\347\274\226\350\257\255\350\250\200/\346\234\237\346\234\253/\346\261\207\347\274\22624\347\272\247\346\234\237\346\234\253\350\214\203\345\233\264.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\346\261\207\347\274\226\350\257\255\350\250\200/\346\234\237\346\234\253/\346\261\207\347\274\226\350\257\255\350\250\200-\351\242\230\347\233\256-2022.pptx" "b/\345\244\247\344\272\214\344\270\212/\346\261\207\347\274\226\350\257\255\350\250\200/\346\234\237\346\234\253/\346\261\207\347\274\226\350\257\255\350\250\200-\351\242\230\347\233\256-2022.pptx" new file mode 100644 index 00000000..cdb4cf5d --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/\346\261\207\347\274\226\350\257\255\350\250\200/\346\234\237\346\234\253/\346\261\207\347\274\226\350\257\255\350\250\200-\351\242\230\347\233\256-2022.pptx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:cffd427ab92e7460f16537098c3601880abc19286cc2c67cb42896b79f4f0a6f +size 2759763 diff --git "a/\345\244\247\344\272\214\344\270\212/\346\261\207\347\274\226\350\257\255\350\250\200/\346\234\237\346\234\253/\346\261\207\347\274\226\350\257\255\350\250\200\347\273\203\344\271\240\351\242\230.ppt" "b/\345\244\247\344\272\214\344\270\212/\346\261\207\347\274\226\350\257\255\350\250\200/\346\234\237\346\234\253/\346\261\207\347\274\226\350\257\255\350\250\200\347\273\203\344\271\240\351\242\230.ppt" new file mode 100644 index 00000000..d0cc719a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\346\261\207\347\274\226\350\257\255\350\250\200/\346\234\237\346\234\253/\346\261\207\347\274\226\350\257\255\350\250\200\347\273\203\344\271\240\351\242\230.ppt" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\344\275\234\344\270\232\345\222\214\347\254\224\350\256\260/\347\246\273\346\225\243\346\225\260\345\255\246\351\242\230\350\247\243\357\274\210\347\254\254\345\205\255\347\211\210\357\274\211\350\200\277\347\264\240\344\272\221 \345\261\210\345\251\211\347\216\262 \345\274\240\347\253\213\346\230\202\346\270\205\345\215\216\345\244\247\345\255\246\345\207\272\347\211\210\347\244\276.pdf" "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\344\275\234\344\270\232\345\222\214\347\254\224\350\256\260/\347\246\273\346\225\243\346\225\260\345\255\246\351\242\230\350\247\243\357\274\210\347\254\254\345\205\255\347\211\210\357\274\211\350\200\277\347\264\240\344\272\221 \345\261\210\345\251\211\347\216\262 \345\274\240\347\253\213\346\230\202\346\270\205\345\215\216\345\244\247\345\255\246\345\207\272\347\211\210\347\244\276.pdf" new file mode 100644 index 00000000..fc47d3f5 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\344\275\234\344\270\232\345\222\214\347\254\224\350\256\260/\347\246\273\346\225\243\346\225\260\345\255\246\351\242\230\350\247\243\357\274\210\347\254\254\345\205\255\347\211\210\357\274\211\350\200\277\347\264\240\344\272\221 \345\261\210\345\251\211\347\216\262 \345\274\240\347\253\213\346\230\202\346\270\205\345\215\216\345\244\247\345\255\246\345\207\272\347\211\210\347\244\276.pdf" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/161701\347\246\273\346\225\243\346\225\260\345\255\246\357\274\241\347\255\224\346\241\210.doc" "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/161701\347\246\273\346\225\243\346\225\260\345\255\246\357\274\241\347\255\224\346\241\210.doc" new file mode 100644 index 00000000..a2b0608a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/161701\347\246\273\346\225\243\346\225\260\345\255\246\357\274\241\347\255\224\346\241\210.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/19.doc" "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/19.doc" new file mode 100644 index 00000000..44ea23b8 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/19.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/2019A\345\215\267.doc" "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/2019A\345\215\267.doc" new file mode 100644 index 00000000..2fd2c312 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/2019A\345\215\267.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/2022-2023\345\255\246\345\271\264A\345\215\267\347\255\224\346\241\210.docx" "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/2022-2023\345\255\246\345\271\264A\345\215\267\347\255\224\346\241\210.docx" new file mode 100644 index 00000000..5c12c138 --- /dev/null +++ "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/2022-2023\345\255\246\345\271\264A\345\215\267\347\255\224\346\241\210.docx" @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:253f3867d04a781ba8272112b71881e3e07cfa866b806d3a58b51220f44d5700 +size 623766 diff --git "a/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/2022\345\271\264\346\234\237\344\270\255\350\200\203A.doc" "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/2022\345\271\264\346\234\237\344\270\255\350\200\203A.doc" new file mode 100644 index 00000000..d37e73c4 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/2022\345\271\264\346\234\237\344\270\255\350\200\203A.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/2023\345\271\264\346\234\237\344\270\255\350\200\203A.doc" "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/2023\345\271\264\346\234\237\344\270\255\350\200\203A.doc" new file mode 100644 index 00000000..fde4e84a Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/2023\345\271\264\346\234\237\344\270\255\350\200\203A.doc" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/24\347\272\247\346\234\237\346\234\253\350\214\203\345\233\264/1.jpg" "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/24\347\272\247\346\234\237\346\234\253\350\214\203\345\233\264/1.jpg" new file mode 100644 index 00000000..75d5e9f3 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/24\347\272\247\346\234\237\346\234\253\350\214\203\345\233\264/1.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/24\347\272\247\346\234\237\346\234\253\350\214\203\345\233\264/2.jpg" "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/24\347\272\247\346\234\237\346\234\253\350\214\203\345\233\264/2.jpg" new file mode 100644 index 00000000..4ae58111 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/24\347\272\247\346\234\237\346\234\253\350\214\203\345\233\264/2.jpg" differ diff --git "a/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/\346\235\250\347\273\264\347\216\262\350\200\201\345\270\210\347\246\273\346\225\243\350\257\225\345\215\267\345\217\202\350\200\203.doc" "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/\346\235\250\347\273\264\347\216\262\350\200\201\345\270\210\347\246\273\346\225\243\350\257\225\345\215\267\345\217\202\350\200\203.doc" new file mode 100644 index 00000000..62f8cc68 Binary files /dev/null and "b/\345\244\247\344\272\214\344\270\212/\347\246\273\346\225\243\346\225\260\345\255\246/\346\234\237\346\234\253/\346\235\250\347\273\264\347\216\262\350\200\201\345\270\210\347\246\273\346\225\243\350\257\225\345\215\267\345\217\202\350\200\203.doc" differ