fix: reset timer_stop flag before spawning timer thread

During evolve(), the guest init sequence halts via OutBAction::Halt,
which sets timer_stop=true. When the guest later configures a timer
via PvTimerConfig, the timer thread inherits the already-true stop
flag and exits immediately without ever firing.

Reset the flag to false right before spawning the timer thread in
both KVM and MSHV backends. WHP was not affected because it creates
a fresh AtomicBool each time.

Signed-off-by: danbugs <danilochiarlone@gmail.com>

Author: danbugs

src/hyperlight_host/src/hypervisor/virtual_machine/kvm.rs

@@ -260,6 +260,9 @@ impl VirtualMachine for KvmVm {
                         if let Ok(bytes) = data[..4].try_into() {
                             let period_us = u32::from_le_bytes(bytes) as u64;
                             if period_us > 0 && self.timer_thread.is_none() {
+                                // Reset the stop flag — a previous halt (e.g. the
+                                // init halt during evolve()) may have set it.
+                                self.timer_stop.store(false, Ordering::Relaxed);
                                 let eventfd = self.timer_irq_eventfd.try_clone().map_err(|e| {
                                     RunVcpuError::Unknown(HypervisorError::KvmError(e.into()))
                                 })?;

src/hyperlight_host/src/hypervisor/virtual_machine/mshv.rs

@@ -639,6 +639,9 @@ impl MshvVm {
             if data.len() >= 4 {
                 let period_us = u32::from_le_bytes([data[0], data[1], data[2], data[3]]);
                 if period_us > 0 && self.timer_thread.is_none() {
+                    // Reset the stop flag — a previous halt (e.g. the
+                    // init halt during evolve()) may have set it.
+                    self.timer_stop.store(false, Ordering::Relaxed);
                     // Re-enable LAPIC if the guest disabled it (via WRMSR
                     // to MSR 0x1B clearing bit 11).  Some guests clear
                     // the global APIC enable when no I/O APIC is detected.