diff --git a/test/WaveOps/WaveActiveAllEqual.32.test b/test/WaveOps/WaveActiveAllEqual.32.test
new file mode 100644
index 000000000..bc1b327c7
--- /dev/null
+++ b/test/WaveOps/WaveActiveAllEqual.32.test
@@ -0,0 +1,372 @@
+#--- source.hlsl
+StructuredBuffer<int> In  : register(t0);
+StructuredBuffer<int2> In2  : register(t1);
+StructuredBuffer<int3> In3  : register(t2);
+StructuredBuffer<int4> In4  : register(t3);
+
+StructuredBuffer<uint> UIn  : register(t4);
+StructuredBuffer<uint2> UIn2  : register(t5);
+StructuredBuffer<uint3> UIn3  : register(t6);
+StructuredBuffer<uint4> UIn4  : register(t7);
+
+StructuredBuffer<float> FIn  : register(t8);
+StructuredBuffer<float2> FIn2  : register(t9);
+StructuredBuffer<float3> FIn3  : register(t10);
+StructuredBuffer<float4> FIn4  : register(t11);
+
+RWStructuredBuffer<int> Out : register(u12);
+RWStructuredBuffer<int> UOut : register(u13);
+RWStructuredBuffer<int> FOut : register(u14);
+
+// Expect all 4s, all elements will be the same.
+
+[numthreads(4,1,1)]
+void main(uint3 TID : SV_GroupThreadID)
+{
+    unsigned int index = 0;
+    bool Result = WaveActiveAllEqual(In[TID.x]);
+    Out[index + TID.x] = Result;
+    index += 4;
+
+    bool2 Result2 = WaveActiveAllEqual(In2[TID.x]);
+    Out[index + TID.x] = Result2.x;
+    index += 4;
+    Out[index + TID.x] = Result2.y;
+    index += 4;
+
+    bool3 Result3 = WaveActiveAllEqual(In3[TID.x]);
+    Out[index + TID.x] = Result3.x;
+    index += 4;
+    Out[index + TID.x] = Result3.y;
+    index += 4;
+    Out[index + TID.x] = Result3.z;
+    index += 4;
+
+    bool4 Result4 = WaveActiveAllEqual(In4[TID.x]);
+    Out[index + TID.x] = Result4.x;
+    index += 4;
+    Out[index + TID.x] = Result4.y;
+    index += 4;
+    Out[index + TID.x] = Result4.z;
+    index += 4;
+    Out[index + TID.x] = Result4.w;
+    index += 4;
+
+
+    // constant folding case
+    bool4 ResultCF = WaveActiveAllEqual(int4(1,1,1,1));
+    Out[index + TID.x] = ResultCF.x;
+    index += 4;
+    Out[index + TID.x] = ResultCF.y;
+    index += 4;
+    Out[index + TID.x] = ResultCF.z;
+    index += 4;
+    Out[index + TID.x] = ResultCF.w;
+    index += 4;
+
+    unsigned int uindex = 0;
+    bool UResult = WaveActiveAllEqual(UIn[TID.x]);    
+    UOut[uindex + TID.x] = UResult;
+    uindex += 4;
+    
+    bool2 UResult2 = WaveActiveAllEqual(UIn2[TID.x]);
+    UOut[uindex + TID.x] = UResult2.x;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult2.y;
+    uindex += 4;    
+
+    bool3 UResult3 = WaveActiveAllEqual(UIn3[TID.x]);
+    UOut[uindex + TID.x] = UResult3.x;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult3.y;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult3.z;
+    uindex += 4; 
+
+    bool4 UResult4 = WaveActiveAllEqual(UIn4[TID.x]);
+    UOut[uindex + TID.x] = UResult4.x;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult4.y;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult4.z;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult4.w;
+    uindex += 4;
+
+    // constant folding case
+    bool4 UResultCF = WaveActiveAllEqual(uint4(1,1,1,1));
+    UOut[uindex + TID.x] = UResultCF.x;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResultCF.y;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResultCF.z;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResultCF.w;
+    uindex += 4;
+
+    unsigned int findex = 0;
+    bool FResult = WaveActiveAllEqual(FIn[TID.x]);    
+    FOut[findex + TID.x] = FResult;
+    findex += 4;
+
+    bool2 FResult2 = WaveActiveAllEqual(FIn2[TID.x]);
+    FOut[findex + TID.x] = FResult2.x;
+    findex += 4;
+    FOut[findex + TID.x] = FResult2.y;
+    findex += 4;
+
+    bool3 FResult3 = WaveActiveAllEqual(FIn3[TID.x]);
+    FOut[findex + TID.x] = FResult3.x;
+    findex += 4;
+    FOut[findex + TID.x] = FResult3.x;
+    findex += 4;
+    FOut[findex + TID.x] = FResult3.y;
+    findex += 4;
+
+    bool4 FResult4 = WaveActiveAllEqual(FIn4[TID.x]);
+    FOut[findex + TID.x] = FResult4.x;
+    findex += 4;
+    FOut[findex + TID.x] = FResult4.y;
+    findex += 4;
+    FOut[findex + TID.x] = FResult4.x;
+    findex += 4;
+    FOut[findex + TID.x] = FResult4.y;
+    findex += 4;
+
+    // constant folding case
+    bool4 FResultCF = WaveActiveAllEqual(float4(1,1,1,1));
+    FOut[findex + TID.x] = FResultCF.x;
+    findex += 4;
+    FOut[findex + TID.x] = FResultCF.y;
+    findex += 4;
+    FOut[findex + TID.x] = FResultCF.x;
+    findex += 4;
+    FOut[findex + TID.x] = FResultCF.y;
+    findex += 4;
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Int32
+    Stride: 4
+    Data: [ -1, -1, -1, -1]
+  - Name: In2
+    Format: Int32
+    Stride: 8
+    Data: [ -1, -1, -1, -1, -1, -1, -1, -1]
+  - Name: In3
+    Format: Int32
+    Stride: 12
+    Data: [ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1]
+  - Name: In4
+    Format: Int32
+    Stride: 16
+    Data: [ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1]
+  - Name: UIn
+    Format: UInt32
+    Stride: 4
+    Data: [ 1, 1, 1, 1]
+  - Name: UIn2
+    Format: UInt32
+    Stride: 8
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1]
+  - Name: UIn3
+    Format: UInt32
+    Stride: 12
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
+  - Name: UIn4
+    Format: UInt32
+    Stride: 16
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+  - Name: FIn
+    Format: Float32
+    Stride: 4
+    Data: [ 1.0, 1.0, 1.0, 1.0 ]
+  - Name: FIn2
+    Format: Float32
+    Stride: 8
+    Data: [ 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0 ]
+  - Name: FIn3
+    Format: Float32
+    Stride: 12
+    Data: [ 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0 ]
+  - Name: FIn4
+    Format: Float32
+    Stride: 16
+    Data: [ 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0 ]
+
+  - Name: Out
+    Format: Int32
+    Stride: 4
+    FillSize: 224
+  - Name: UOut
+    Format: Int32
+    Stride: 4
+    FillSize: 224 
+  - Name: FOut
+    Format: Int32
+    Stride: 4
+    FillSize: 224
+  
+  - Name: ExpectedOut
+    Format: Int32
+    Stride: 4
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+  - Name: UExpectedOut
+    Format: Int32
+    Stride: 4
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+  - Name: FExpectedOut
+    Format: Int32
+    Stride: 4
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+  
+Results:
+  - Result: ExpectedOut
+    Rule: BufferExact
+    Actual: Out
+    Expected: ExpectedOut
+  - Result: UExpectedOut
+    Rule: BufferExact
+    Actual: UOut
+    Expected: UExpectedOut
+  - Result: FExpectedOut
+    Rule: BufferExact
+    Actual: FOut
+    Expected: FExpectedOut
+  
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: In2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: In3
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: In4
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: UIn
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: UIn2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+    - Name: UIn3
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 6
+        Space: 0
+      VulkanBinding:
+        Binding: 6
+    - Name: UIn4
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 7
+        Space: 0
+      VulkanBinding:
+        Binding: 7
+    - Name: FIn
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 8
+        Space: 0
+      VulkanBinding:
+        Binding: 8
+    - Name: FIn2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 9
+        Space: 0
+      VulkanBinding:
+        Binding: 9
+    - Name: FIn3
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 10
+        Space: 0
+      VulkanBinding:
+        Binding: 10
+    - Name: FIn4
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 11
+        Space: 0
+      VulkanBinding:
+        Binding: 11
+    - Name: Out
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 12
+        Space: 0
+      VulkanBinding:
+        Binding: 12
+    - Name: UOut
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 13
+        Space: 0
+      VulkanBinding:
+        Binding: 13
+    - Name: FOut
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 14
+        Space: 0
+      VulkanBinding:
+        Binding: 14
+...
+#--- end
+
+# Bug: https://github.com/llvm/offload-test-suite/issues/943
+# XFAIL: Intel && Vulkan
+
+# Bug: https://github.com/llvm/offload-test-suite/issues/981
+# XFAIL: Clang
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o 
diff --git a/test/WaveOps/WaveActiveAllEqual.Wave128.test b/test/WaveOps/WaveActiveAllEqual.Wave128.test
new file mode 100644
index 000000000..654b9692b
--- /dev/null
+++ b/test/WaveOps/WaveActiveAllEqual.Wave128.test
@@ -0,0 +1,351 @@
+#--- source.hlsl
+StructuredBuffer<int> In1  : register(t0);
+StructuredBuffer<int> In2  : register(t1);
+StructuredBuffer<int2> InVec1  : register(t2);
+StructuredBuffer<int2> InVec2  : register(t3);
+RWStructuredBuffer<bool> Out1 : register(u4);
+RWStructuredBuffer<bool> Out2 : register(u5);
+RWStructuredBuffer<bool> Out3 : register(u6);
+RWStructuredBuffer<bool2> Out4 : register(u7);
+RWStructuredBuffer<bool2> Out5 : register(u8);
+RWStructuredBuffer<bool2> Out6 : register(u9);
+
+[WaveSize(128)]
+[numthreads(128, 1, 1)]
+void main(uint3 TID : SV_DispatchThreadID) {
+  // First test, we expect all true for even threads, since at the call site,
+  // all values are identical: 1
+  bool Result1 = false;
+  if (TID.x % 2 == 0)
+    Result1 = WaveActiveAllEqual(In1[TID.x]);
+
+  Out1[TID.x] = Result1;
+
+  // Second test, just like the first test, except there's
+  // a different value, the 2 at the front of In2. Expect all falses.
+  bool Result2 = false;
+  if (TID.x % 2 == 0)
+    Result2 = WaveActiveAllEqual(In2[TID.x]);
+
+  Out2[TID.x] = Result2;
+
+  // Third test, just like test 2, except the first value
+  // is excluded. Expect trues for even threads except the first thread.
+  bool Result3 = false;
+  if (TID.x % 2 == 0 && TID.x != 0)
+    Result3 = WaveActiveAllEqual(In2[TID.x]);
+
+  Out3[TID.x] = Result3;
+
+  // Fourth test, just test that identical vectors pass.
+  // Expect all trues for all threads.
+  bool2 Result4 = WaveActiveAllEqual(InVec1[TID.x]);
+  Out4[TID.x] = Result4;
+
+  // Fifth, test that non-identical vectors fail.
+  // Expect [false, true] for all threads.
+  // This is because the 2nd component of each vector is identical,
+  // so it sets the 2nd component of the boolean vector result of 
+  // WaveActiveAllEqual to true.
+  bool2 Result5 = WaveActiveAllEqual(InVec2[TID.x]);
+  Out5[TID.x] = Result5;
+
+  // Sixth and finally, test that identical vectors pass 
+  // in the right conditions. Expect [true, true] for relevant threads.
+  bool2 Result6 = false;
+  if (TID.x != 0)
+      Result6 = WaveActiveAllEqual(InVec2[TID.x]);
+
+  Out6[TID.x] = Result6;
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In1
+    Format: Int32
+    Stride: 4
+    Data: [1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: In2
+    Format: Int32
+    Stride: 4
+    Data: [2, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: InVec1
+    Format: Int32
+    Stride: 8
+    Data: [1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: InVec2
+    Format: Int32
+    Stride: 8
+    Data: [2, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: Out1
+    Format: Bool
+    Stride: 4
+    FillSize: 512
+  - Name: Out2
+    Format: Bool
+    Stride: 4
+    FillSize: 512
+  - Name: Out3
+    Format: Bool
+    Stride: 4
+    FillSize: 512
+  - Name: Out4
+    Format: Bool
+    Stride: 8
+    FillSize: 1024
+  - Name: Out5
+    Format: Bool
+    Stride: 8
+    FillSize: 1024
+  - Name: Out6
+    Format: Bool
+    Stride: 8
+    FillSize: 1024
+  - Name: ExpectedOut1
+    Format: Bool
+    Stride: 4
+    Data: [1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: ExpectedOut2
+    Format: Bool
+    Stride: 4
+    Data: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+  - Name: ExpectedOut3
+    Format: Bool
+    Stride: 4
+    Data: [0, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: ExpectedOut4
+    Format: Bool
+    Stride: 8
+    Data: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
+  - Name: ExpectedOut5
+    Format: Bool
+    Stride: 8
+    Data: [0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1]
+  - Name: ExpectedOut6
+    Format: Bool
+    Stride: 8
+    Data: [0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
+
+  
+Results:
+  - Result: Test1
+    Rule: BufferExact
+    Actual: Out1
+    Expected: ExpectedOut1
+  - Result: Test2
+    Rule: BufferExact
+    Actual: Out2
+    Expected: ExpectedOut2
+  - Result: Test3
+    Rule: BufferExact
+    Actual: Out3
+    Expected: ExpectedOut3
+  - Result: Test4
+    Rule: BufferExact
+    Actual: Out4
+    Expected: ExpectedOut4
+  - Result: Test5
+    Rule: BufferExact
+    Actual: Out5
+    Expected: ExpectedOut5
+  - Result: Test6
+    Rule: BufferExact
+    Actual: Out6
+    Expected: ExpectedOut6
+  
+DescriptorSets:
+  - Resources:    
+    - Name: In1
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: In2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: InVec1
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: InVec2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: Out1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: Out2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+    - Name: Out3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 6
+        Space: 0
+      VulkanBinding:
+        Binding: 6
+    - Name: Out4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 7
+        Space: 0
+      VulkanBinding:
+        Binding: 7
+    - Name: Out5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 8
+        Space: 0
+      VulkanBinding:
+        Binding: 8
+    - Name: Out6
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 9
+        Space: 0
+      VulkanBinding:
+        Binding: 9
+...
+#--- end
+
+# REQUIRES: WaveSize_128
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o
diff --git a/test/WaveOps/WaveActiveAllEqual.Wave32.test b/test/WaveOps/WaveActiveAllEqual.Wave32.test
new file mode 100644
index 000000000..1944f915b
--- /dev/null
+++ b/test/WaveOps/WaveActiveAllEqual.Wave32.test
@@ -0,0 +1,261 @@
+#--- source.hlsl
+StructuredBuffer<int> In1  : register(t0);
+StructuredBuffer<int> In2  : register(t1);
+StructuredBuffer<int2> InVec1  : register(t2);
+StructuredBuffer<int2> InVec2  : register(t3);
+RWStructuredBuffer<bool> Out1 : register(u4);
+RWStructuredBuffer<bool> Out2 : register(u5);
+RWStructuredBuffer<bool> Out3 : register(u6);
+RWStructuredBuffer<bool2> Out4 : register(u7);
+RWStructuredBuffer<bool2> Out5 : register(u8);
+RWStructuredBuffer<bool2> Out6 : register(u9);
+
+[WaveSize(32)]
+[numthreads(32, 1, 1)]
+void main(uint3 TID : SV_DispatchThreadID) {
+  // First test, we expect all true for even threads, since at the call site,
+  // all values are identical: 1
+  bool Result1 = false;
+  if (TID.x % 2 == 0)
+    Result1 = WaveActiveAllEqual(In1[TID.x]);
+
+  Out1[TID.x] = Result1;
+
+  // Second test, just like the first test, except there's
+  // a different value, the 2 at the front of In2. Expect all falses.
+  bool Result2 = false;
+  if (TID.x % 2 == 0)
+    Result2 = WaveActiveAllEqual(In2[TID.x]);
+
+  Out2[TID.x] = Result2;
+
+  // Third test, just like test 2, except the first value
+  // is excluded. Expect trues for even threads except the first thread.
+  bool Result3 = false;
+  if (TID.x % 2 == 0 && TID.x != 0)
+    Result3 = WaveActiveAllEqual(In2[TID.x]);
+
+  Out3[TID.x] = Result3;
+
+  // Fourth test, just test that identical vectors pass.
+  // Expect all trues for all threads.
+  bool2 Result4 = WaveActiveAllEqual(InVec1[TID.x]);
+  Out4[TID.x] = Result4;
+
+  // Fifth, test that non-identical vectors fail.
+  // Expect [false, true] for all threads.
+  // This is because the 2nd component of each vector is identical,
+  // so it sets the 2nd component of the boolean vector result of 
+  // WaveActiveAllEqual to true.
+  bool2 Result5 = WaveActiveAllEqual(InVec2[TID.x]);
+  Out5[TID.x] = Result5;
+
+  // Sixth and finally, test that identical vectors pass 
+  // in the right conditions. Expect [true, true] for relevant threads.
+  bool2 Result6 = false;
+  if (TID.x != 0)
+      Result6 = WaveActiveAllEqual(InVec2[TID.x]);
+
+  Out6[TID.x] = Result6;
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In1
+    Format: Int32
+    Stride: 4
+    Data: [1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: In2
+    Format: Int32
+    Stride: 4
+    Data: [2, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: InVec1
+    Format: Int32
+    Stride: 8
+    Data: [1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: InVec2
+    Format: Int32
+    Stride: 8
+    Data: [2, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: Out1
+    Format: Bool
+    Stride: 4
+    FillSize: 128
+  - Name: Out2
+    Format: Bool
+    Stride: 4
+    FillSize: 128
+  - Name: Out3
+    Format: Bool
+    Stride: 4
+    FillSize: 128
+  - Name: Out4
+    Format: Bool
+    Stride: 8
+    FillSize: 256
+  - Name: Out5
+    Format: Bool
+    Stride: 8
+    FillSize: 256
+  - Name: Out6
+    Format: Bool
+    Stride: 8
+    FillSize: 256
+  - Name: ExpectedOut1
+    Format: Bool
+    Stride: 4
+    Data: [1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: ExpectedOut2
+    Format: Bool
+    Stride: 4
+    Data: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+  - Name: ExpectedOut3
+    Format: Bool
+    Stride: 4
+    Data: [0, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: ExpectedOut4
+    Format: Bool
+    Stride: 8
+    Data: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
+  - Name: ExpectedOut5
+    Format: Bool
+    Stride: 8
+    Data: [0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1]
+  - Name: ExpectedOut6
+    Format: Bool
+    Stride: 8
+    Data: [0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
+
+  
+Results:
+  - Result: Test1
+    Rule: BufferExact
+    Actual: Out1
+    Expected: ExpectedOut1
+  - Result: Test2
+    Rule: BufferExact
+    Actual: Out2
+    Expected: ExpectedOut2
+  - Result: Test3
+    Rule: BufferExact
+    Actual: Out3
+    Expected: ExpectedOut3
+  - Result: Test4
+    Rule: BufferExact
+    Actual: Out4
+    Expected: ExpectedOut4
+  - Result: Test5
+    Rule: BufferExact
+    Actual: Out5
+    Expected: ExpectedOut5
+  - Result: Test6
+    Rule: BufferExact
+    Actual: Out6
+    Expected: ExpectedOut6
+  
+DescriptorSets:
+  - Resources:    
+    - Name: In1
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: In2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: InVec1
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: InVec2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: Out1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: Out2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+    - Name: Out3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 6
+        Space: 0
+      VulkanBinding:
+        Binding: 6
+    - Name: Out4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 7
+        Space: 0
+      VulkanBinding:
+        Binding: 7
+    - Name: Out5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 8
+        Space: 0
+      VulkanBinding:
+        Binding: 8
+    - Name: Out6
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 9
+        Space: 0
+      VulkanBinding:
+        Binding: 9
+...
+#--- end
+
+# REQUIRES: WaveSize_32
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o
diff --git a/test/WaveOps/WaveActiveAllEqual.Wave64.test b/test/WaveOps/WaveActiveAllEqual.Wave64.test
new file mode 100644
index 000000000..9fcfe3334
--- /dev/null
+++ b/test/WaveOps/WaveActiveAllEqual.Wave64.test
@@ -0,0 +1,291 @@
+#--- source.hlsl
+StructuredBuffer<int> In1  : register(t0);
+StructuredBuffer<int> In2  : register(t1);
+StructuredBuffer<int2> InVec1  : register(t2);
+StructuredBuffer<int2> InVec2  : register(t3);
+RWStructuredBuffer<bool> Out1 : register(u4);
+RWStructuredBuffer<bool> Out2 : register(u5);
+RWStructuredBuffer<bool> Out3 : register(u6);
+RWStructuredBuffer<bool2> Out4 : register(u7);
+RWStructuredBuffer<bool2> Out5 : register(u8);
+RWStructuredBuffer<bool2> Out6 : register(u9);
+
+[WaveSize(64)]
+[numthreads(64, 1, 1)]
+void main(uint3 TID : SV_DispatchThreadID) {
+  // First test, we expect all true for even threads, since at the call site,
+  // all values are identical: 1
+  bool Result1 = false;
+  if (TID.x % 2 == 0)
+    Result1 = WaveActiveAllEqual(In1[TID.x]);
+
+  Out1[TID.x] = Result1;
+
+  // Second test, just like the first test, except there's
+  // a different value, the 2 at the front of In2. Expect all falses.
+  bool Result2 = false;
+  if (TID.x % 2 == 0)
+    Result2 = WaveActiveAllEqual(In2[TID.x]);
+
+  Out2[TID.x] = Result2;
+
+  // Third test, just like test 2, except the first value
+  // is excluded. Expect trues for even threads except the first thread.
+  bool Result3 = false;
+  if (TID.x % 2 == 0 && TID.x != 0)
+    Result3 = WaveActiveAllEqual(In2[TID.x]);
+
+  Out3[TID.x] = Result3;
+
+  // Fourth test, just test that identical vectors pass.
+  // Expect all trues for all threads.
+  bool2 Result4 = WaveActiveAllEqual(InVec1[TID.x]);
+  Out4[TID.x] = Result4;
+
+  // Fifth, test that non-identical vectors fail.
+  // Expect [false, true] for all threads.
+  // This is because the 2nd component of each vector is identical,
+  // so it sets the 2nd component of the boolean vector result of 
+  // WaveActiveAllEqual to true.
+  bool2 Result5 = WaveActiveAllEqual(InVec2[TID.x]);
+  Out5[TID.x] = Result5;
+
+  // Sixth and finally, test that identical vectors pass 
+  // in the right conditions. Expect [true, true] for relevant threads.
+  bool2 Result6 = false;
+  if (TID.x != 0)
+      Result6 = WaveActiveAllEqual(InVec2[TID.x]);
+
+  Out6[TID.x] = Result6;
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In1
+    Format: Int32
+    Stride: 4
+    Data: [1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: In2
+    Format: Int32
+    Stride: 4
+    Data: [2, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: InVec1
+    Format: Int32
+    Stride: 8
+    Data: [1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: InVec2
+    Format: Int32
+    Stride: 8
+    Data: [2, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: Out1
+    Format: Bool
+    Stride: 4
+    FillSize: 256
+  - Name: Out2
+    Format: Bool
+    Stride: 4
+    FillSize: 256
+  - Name: Out3
+    Format: Bool
+    Stride: 4
+    FillSize: 256
+  - Name: Out4
+    Format: Bool
+    Stride: 8
+    FillSize: 512
+  - Name: Out5
+    Format: Bool
+    Stride: 8
+    FillSize: 512
+  - Name: Out6
+    Format: Bool
+    Stride: 8
+    FillSize: 512
+  - Name: ExpectedOut1
+    Format: Bool
+    Stride: 4
+    Data: [1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: ExpectedOut2
+    Format: Bool
+    Stride: 4
+    Data: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+  - Name: ExpectedOut3
+    Format: Bool
+    Stride: 4
+    Data: [0, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0,
+ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]
+  - Name: ExpectedOut4
+    Format: Bool
+    Stride: 8
+    Data: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
+  - Name: ExpectedOut5
+    Format: Bool
+    Stride: 8
+    Data: [0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1,
+ 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1]
+  - Name: ExpectedOut6
+    Format: Bool
+    Stride: 8
+    Data: [0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
+
+  
+Results:
+  - Result: Test1
+    Rule: BufferExact
+    Actual: Out1
+    Expected: ExpectedOut1
+  - Result: Test2
+    Rule: BufferExact
+    Actual: Out2
+    Expected: ExpectedOut2
+  - Result: Test3
+    Rule: BufferExact
+    Actual: Out3
+    Expected: ExpectedOut3
+  - Result: Test4
+    Rule: BufferExact
+    Actual: Out4
+    Expected: ExpectedOut4
+  - Result: Test5
+    Rule: BufferExact
+    Actual: Out5
+    Expected: ExpectedOut5
+  - Result: Test6
+    Rule: BufferExact
+    Actual: Out6
+    Expected: ExpectedOut6
+  
+DescriptorSets:
+  - Resources:    
+    - Name: In1
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: In2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: InVec1
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: InVec2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: Out1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: Out2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+    - Name: Out3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 6
+        Space: 0
+      VulkanBinding:
+        Binding: 6
+    - Name: Out4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 7
+        Space: 0
+      VulkanBinding:
+        Binding: 7
+    - Name: Out5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 8
+        Space: 0
+      VulkanBinding:
+        Binding: 8
+    - Name: Out6
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 9
+        Space: 0
+      VulkanBinding:
+        Binding: 9
+...
+#--- end
+
+# REQUIRES: WaveSize_64
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o
diff --git a/test/WaveOps/WaveActiveAllEqual.fp16.test b/test/WaveOps/WaveActiveAllEqual.fp16.test
new file mode 100644
index 000000000..63f3c3617
--- /dev/null
+++ b/test/WaveOps/WaveActiveAllEqual.fp16.test
@@ -0,0 +1,160 @@
+#--- source.hlsl
+StructuredBuffer<half> In  : register(t0);
+StructuredBuffer<half2> In2  : register(t1);
+StructuredBuffer<half3> In3  : register(t2);
+StructuredBuffer<half4> In4  : register(t3);
+
+RWStructuredBuffer<int> Out : register(u4);
+
+[numthreads(4,1,1)]
+void main(uint3 TID : SV_GroupThreadID)
+{
+    unsigned int index = 0;
+    bool Result = WaveActiveAllEqual(In[TID.x]);
+    Out[index + TID.x] = Result;
+    index += 4;
+
+    bool2 Result2 = WaveActiveAllEqual(In2[TID.x]);
+    Out[index + TID.x] = Result2.x;
+    index += 4;
+    Out[index + TID.x] = Result2.y;
+    index += 4;
+
+    bool3 Result3 = WaveActiveAllEqual(In3[TID.x]);
+    Out[index + TID.x] = Result3.x;
+    index += 4;
+    Out[index + TID.x] = Result3.y;
+    index += 4;
+    Out[index + TID.x] = Result3.z;
+    index += 4;
+
+    bool4 Result4 = WaveActiveAllEqual(In4[TID.x]);
+    Out[index + TID.x] = Result4.x;
+    index += 4;
+    Out[index + TID.x] = Result4.y;
+    index += 4;
+    Out[index + TID.x] = Result4.z;
+    index += 4;
+    Out[index + TID.x] = Result4.w;
+    index += 4;
+
+
+    // constant folding case
+    bool4 ResultCF = WaveActiveAllEqual(half4(1,1,1,1));
+    Out[index + TID.x] = ResultCF.x;
+    index += 4;
+    Out[index + TID.x] = ResultCF.y;
+    index += 4;
+    Out[index + TID.x] = ResultCF.z;
+    index += 4;
+    Out[index + TID.x] = ResultCF.w;
+    index += 4;
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  # Everything is 0xbc00, which is -1.0
+  - Name: In
+    Format: Float16
+    Stride: 2
+    Data: [ 0xbc00, 0xbc00, 0xbc00, 0xbc00]
+  - Name: In2
+    Format: Float16
+    Stride: 4
+    Data: [ 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00]
+  - Name: In3
+    Format: Float16
+    Stride: 6
+    Data: [ 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00]
+  - Name: In4
+    Format: Float16
+    Stride: 8
+    Data: [ 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00, 0xbc00]
+
+  - Name: Out
+    Format: Int32
+    Stride: 4
+    FillSize: 224
+  - Name: UOut
+    Format: Int32
+    Stride: 4
+    FillSize: 224
+  
+  - Name: ExpectedOut
+    Format: Int32
+    Stride: 2
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+  - Name: UExpectedOut
+    Format: Int32
+    Stride: 2
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+  
+Results:
+  - Result: ExpectedOut
+    Rule: BufferExact
+    Actual: Out
+    Expected: ExpectedOut
+  
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: In2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: In3
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: In4
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: Out
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+
+...
+#--- end
+
+# Bug: https://github.com/llvm/offload-test-suite/issues/943
+# XFAIL: Intel && Vulkan
+
+# Bug: https://github.com/llvm/offload-test-suite/issues/981
+# XFAIL: Clang
+
+# REQUIRES Half
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -enable-16bit-types -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o 
diff --git a/test/WaveOps/WaveActiveAllEqual.fp64.test b/test/WaveOps/WaveActiveAllEqual.fp64.test
new file mode 100644
index 000000000..5786810b7
--- /dev/null
+++ b/test/WaveOps/WaveActiveAllEqual.fp64.test
@@ -0,0 +1,168 @@
+#--- source.hlsl
+StructuredBuffer<double> In  : register(t0);
+StructuredBuffer<double2> In2  : register(t1);
+StructuredBuffer<double3> In3  : register(t2);
+StructuredBuffer<double4> In4  : register(t3);
+
+RWStructuredBuffer<int> Out : register(u4);
+
+// Expect all 4s, all elements will be the same.
+
+[numthreads(4,1,1)]
+void main(uint3 TID : SV_GroupThreadID)
+{
+    unsigned int index = 0;
+    bool Result = WaveActiveAllEqual(In[TID.x]);
+    Out[index + TID.x] = Result;
+    index += 4;
+
+    bool2 Result2 = WaveActiveAllEqual(In2[TID.x]);
+    Out[index + TID.x] = Result2.x;
+    index += 4;
+    Out[index + TID.x] = Result2.y;
+    index += 4;
+
+    bool3 Result3 = WaveActiveAllEqual(In3[TID.x]);
+    Out[index + TID.x] = Result3.x;
+    index += 4;
+    Out[index + TID.x] = Result3.y;
+    index += 4;
+    Out[index + TID.x] = Result3.z;
+    index += 4;
+
+    bool4 Result4 = WaveActiveAllEqual(In4[TID.x]);
+    Out[index + TID.x] = Result4.x;
+    index += 4;
+    Out[index + TID.x] = Result4.y;
+    index += 4;
+    Out[index + TID.x] = Result4.z;
+    index += 4;
+    Out[index + TID.x] = Result4.w;
+    index += 4;
+
+
+    // constant folding case
+    bool4 ResultCF = WaveActiveAllEqual(double4(1,1,1,1));
+    Out[index + TID.x] = ResultCF.x;
+    index += 4;
+    Out[index + TID.x] = ResultCF.y;
+    index += 4;
+    Out[index + TID.x] = ResultCF.z;
+    index += 4;
+    Out[index + TID.x] = ResultCF.w;
+    index += 4;
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:  
+  - Name: In
+    Format: Float64
+    Stride: 8
+    Data: [ -1.0, -1.0, -1.0, -1.0]
+  - Name: In2
+    Format: Float64
+    Stride: 16
+    Data: [ -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0]
+  - Name: In3
+    Format: Float64
+    Stride: 24
+    Data: [ -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0]
+  - Name: In4
+    Format: Float64
+    Stride: 32
+    Data: [ -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0, -1.0]
+
+  - Name: Out
+    Format: Int32
+    Stride: 8
+    FillSize: 224
+  - Name: UOut
+    Format: Int32
+    Stride: 8
+    FillSize: 224
+  
+  - Name: ExpectedOut
+    Format: Int32
+    Stride: 8
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+  - Name: UExpectedOut
+    Format: Int32
+    Stride: 8
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+  
+Results:
+  - Result: ExpectedOut
+    Rule: BufferExact
+    Actual: Out
+    Expected: ExpectedOut
+  
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: In2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: In3
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: In4
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: Out
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+
+...
+#--- end
+
+# Bug: https://github.com/llvm/offload-test-suite/issues/944
+# XFAIL: Intel && DirectX
+
+# Bug: https://github.com/llvm/offload-test-suite/issues/943
+# XFAIL: Intel && Vulkan
+
+# Bug: https://github.com/llvm/offload-test-suite/issues/981
+# XFAIL: Clang
+
+# Metal doesn't support 64-bit wave operations
+# Bug: https://github.com/llvm/offload-test-suite/issues/355
+# XFAIL: Metal
+
+# REQUIRES double
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -enable-16bit-types -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o 
diff --git a/test/WaveOps/WaveActiveAllEqual.int16.test b/test/WaveOps/WaveActiveAllEqual.int16.test
new file mode 100644
index 000000000..57846cc0d
--- /dev/null
+++ b/test/WaveOps/WaveActiveAllEqual.int16.test
@@ -0,0 +1,262 @@
+#--- source.hlsl
+StructuredBuffer<int16_t> In  : register(t0);
+StructuredBuffer<int16_t2> In2  : register(t1);
+StructuredBuffer<int16_t3> In3  : register(t2);
+StructuredBuffer<int16_t4> In4  : register(t3);
+
+StructuredBuffer<uint16_t> UIn  : register(t4);
+StructuredBuffer<uint16_t2> UIn2  : register(t5);
+StructuredBuffer<uint16_t3> UIn3  : register(t6);
+StructuredBuffer<uint16_t4> UIn4  : register(t7);
+
+RWStructuredBuffer<int> Out : register(u8);
+RWStructuredBuffer<int> UOut : register(u9);
+
+[numthreads(4,1,1)]
+void main(uint3 TID : SV_GroupThreadID)
+{
+    unsigned int index = 0;
+    bool Result = WaveActiveAllEqual(In[TID.x]);
+    Out[index + TID.x] = Result;
+    index += 4;
+
+    bool2 Result2 = WaveActiveAllEqual(In2[TID.x]);
+    Out[index + TID.x] = Result2.x;
+    index += 4;
+    Out[index + TID.x] = Result2.y;
+    index += 4;
+
+    bool3 Result3 = WaveActiveAllEqual(In3[TID.x]);
+    Out[index + TID.x] = Result3.x;
+    index += 4;
+    Out[index + TID.x] = Result3.y;
+    index += 4;
+    Out[index + TID.x] = Result3.z;
+    index += 4;
+
+    bool4 Result4 = WaveActiveAllEqual(In4[TID.x]);
+    Out[index + TID.x] = Result4.x;
+    index += 4;
+    Out[index + TID.x] = Result4.y;
+    index += 4;
+    Out[index + TID.x] = Result4.z;
+    index += 4;
+    Out[index + TID.x] = Result4.w;
+    index += 4;
+
+
+    // constant folding case
+    bool4 ResultCF = WaveActiveAllEqual(int16_t4(1,1,1,1));
+    Out[index + TID.x] = ResultCF.x;
+    index += 4;
+    Out[index + TID.x] = ResultCF.y;
+    index += 4;
+    Out[index + TID.x] = ResultCF.z;
+    index += 4;
+    Out[index + TID.x] = ResultCF.w;
+    index += 4;
+
+
+
+    unsigned int uindex = 0;
+    bool UResult = WaveActiveAllEqual(UIn[TID.x]);
+    UOut[uindex + TID.x] = UResult;
+    uindex += 4;
+
+    bool2 UResult2 = WaveActiveAllEqual(UIn2[TID.x]);
+    UOut[uindex + TID.x] = UResult2.x;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult2.y;
+    uindex += 4;
+
+    bool3 UResult3 = WaveActiveAllEqual(UIn3[TID.x]);
+    UOut[uindex + TID.x] = UResult3.x;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult3.y;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult3.z;
+    uindex += 4;
+
+    bool4 UResult4 = WaveActiveAllEqual(UIn4[TID.x]);
+    UOut[uindex + TID.x] = UResult4.x;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult4.y;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult4.z;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult4.w;
+    uindex += 4;
+
+
+    // constant folding case
+    bool4 UResultCF = WaveActiveAllEqual(uint16_t4(1,1,1,1));
+    UOut[uindex + TID.x] = UResultCF.x;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResultCF.y;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResultCF.z;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResultCF.w;
+    uindex += 4;
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Int16
+    Stride: 2
+    Data: [ -1, -1, -1, -1]
+  - Name: In2
+    Format: Int16
+    Stride: 4
+    Data: [ -1, -1, -1, -1, -1, -1, -1, -1]
+  - Name: In3
+    Format: Int16
+    Stride: 6
+    Data: [ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1]
+  - Name: In4
+    Format: Int16
+    Stride: 8
+    Data: [ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1]
+  - Name: UIn
+    Format: UInt16
+    Stride: 2
+    Data: [ 1, 1, 1, 1]
+  - Name: UIn2
+    Format: UInt16
+    Stride: 4
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1]
+  - Name: UIn3
+    Format: UInt16
+    Stride: 6
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
+  - Name: UIn4
+    Format: UInt16
+    Stride: 8
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+
+  - Name: Out
+    Format: Int32
+    Stride: 2
+    FillSize: 224
+  - Name: UOut
+    Format: Int32
+    Stride: 2
+    FillSize: 224
+  
+  - Name: ExpectedOut
+    Format: Int32
+    Stride: 2
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+  - Name: UExpectedOut
+    Format: Int32
+    Stride: 2
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+  
+Results:
+  - Result: ExpectedOut
+    Rule: BufferExact
+    Actual: Out
+    Expected: ExpectedOut
+  - Result: UExpectedOut
+    Rule: BufferExact
+    Actual: UOut
+    Expected: UExpectedOut
+  
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: In2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: In3
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: In4
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: UIn
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: UIn2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+    - Name: UIn3
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 6
+        Space: 0
+      VulkanBinding:
+        Binding: 6
+    - Name: UIn4
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 7
+        Space: 0
+      VulkanBinding:
+        Binding: 7
+    - Name: Out
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 8
+        Space: 0
+      VulkanBinding:
+        Binding: 8
+    - Name: UOut
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 9
+        Space: 0
+      VulkanBinding:
+        Binding: 9
+...
+#--- end
+
+# Bug: https://github.com/llvm/offload-test-suite/issues/943
+# XFAIL: Intel && Vulkan
+
+# Bug: https://github.com/llvm/offload-test-suite/issues/981
+# XFAIL: Clang
+
+# REQUIRES Int16
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -enable-16bit-types -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o 
diff --git a/test/WaveOps/WaveActiveAllEqual.int64.test b/test/WaveOps/WaveActiveAllEqual.int64.test
new file mode 100644
index 000000000..f786d8d70
--- /dev/null
+++ b/test/WaveOps/WaveActiveAllEqual.int64.test
@@ -0,0 +1,271 @@
+#--- source.hlsl
+StructuredBuffer<int64_t> In  : register(t0);
+StructuredBuffer<int64_t2> In2  : register(t1);
+StructuredBuffer<int64_t3> In3  : register(t2);
+StructuredBuffer<int64_t4> In4  : register(t3);
+
+StructuredBuffer<uint64_t> UIn  : register(t4);
+StructuredBuffer<uint64_t2> UIn2  : register(t5);
+StructuredBuffer<uint64_t3> UIn3  : register(t6);
+StructuredBuffer<uint64_t4> UIn4  : register(t7);
+
+RWStructuredBuffer<int> Out : register(u8);
+RWStructuredBuffer<int> UOut : register(u9);
+
+// Expect all 4s, all elements will be the same.
+
+[numthreads(4,1,1)]
+void main(uint3 TID : SV_GroupThreadID)
+{
+    unsigned int index = 0;
+    bool Result = WaveActiveAllEqual(In[TID.x]);
+    Out[index + TID.x] = Result;
+    index += 4;
+
+    bool2 Result2 = WaveActiveAllEqual(In2[TID.x]);
+    Out[index + TID.x] = Result2.x;
+    index += 4;
+    Out[index + TID.x] = Result2.y;
+    index += 4;
+
+    bool3 Result3 = WaveActiveAllEqual(In3[TID.x]);
+    Out[index + TID.x] = Result3.x;
+    index += 4;
+    Out[index + TID.x] = Result3.y;
+    index += 4;
+    Out[index + TID.x] = Result3.z;
+    index += 4;
+
+    bool4 Result4 = WaveActiveAllEqual(In4[TID.x]);
+    Out[index + TID.x] = Result4.x;
+    index += 4;
+    Out[index + TID.x] = Result4.y;
+    index += 4;
+    Out[index + TID.x] = Result4.z;
+    index += 4;
+    Out[index + TID.x] = Result4.w;
+    index += 4;
+
+
+    // constant folding case
+    bool4 ResultCF = WaveActiveAllEqual(int64_t4(1,1,1,1));
+    Out[index + TID.x] = ResultCF.x;
+    index += 4;
+    Out[index + TID.x] = ResultCF.y;
+    index += 4;
+    Out[index + TID.x] = ResultCF.z;
+    index += 4;
+    Out[index + TID.x] = ResultCF.w;
+    index += 4;
+
+
+
+    unsigned int uindex = 0;
+    bool UResult = WaveActiveAllEqual(UIn[TID.x]);
+    UOut[uindex + TID.x] = UResult;
+    uindex += 4;
+
+    bool2 UResult2 = WaveActiveAllEqual(UIn2[TID.x]);
+    UOut[uindex + TID.x] = UResult2.x;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult2.y;
+    uindex += 4;
+
+    bool3 UResult3 = WaveActiveAllEqual(UIn3[TID.x]);
+    UOut[uindex + TID.x] = UResult3.x;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult3.y;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult3.z;
+    uindex += 4;
+
+    bool4 UResult4 = WaveActiveAllEqual(UIn4[TID.x]);
+    UOut[uindex + TID.x] = UResult4.x;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult4.y;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult4.z;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult4.w;
+    uindex += 4;
+
+
+    // constant folding case
+    bool4 UResultCF = WaveActiveAllEqual(uint64_t4(1,1,1,1));
+    UOut[uindex + TID.x] = UResultCF.x;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResultCF.y;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResultCF.z;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResultCF.w;
+    uindex += 4;
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Int64
+    Stride: 8
+    Data: [ -1, -1, -1, -1]
+  - Name: In2
+    Format: Int64
+    Stride: 16
+    Data: [ -1, -1, -1, -1, -1, -1, -1, -1]
+  - Name: In3
+    Format: Int64
+    Stride: 24
+    Data: [ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1]
+  - Name: In4
+    Format: Int64
+    Stride: 32
+    Data: [ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1]
+  - Name: UIn
+    Format: UInt64
+    Stride: 8
+    Data: [ 1, 1, 1, 1]
+  - Name: UIn2
+    Format: UInt64
+    Stride: 16
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1]
+  - Name: UIn3
+    Format: UInt64
+    Stride: 24
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
+  - Name: UIn4
+    Format: UInt64
+    Stride: 32
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+
+  - Name: Out
+    Format: Int32
+    Stride: 8
+    FillSize: 224
+  - Name: UOut
+    Format: Int32
+    Stride: 8
+    FillSize: 224
+  
+  - Name: ExpectedOut
+    Format: Int32
+    Stride: 4
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+  - Name: UExpectedOut
+    Format: Int32
+    Stride: 4
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+  
+Results:
+  - Result: ExpectedOut
+    Rule: BufferExact
+    Actual: Out
+    Expected: ExpectedOut
+  - Result: UExpectedOut
+    Rule: BufferExact
+    Actual: UOut
+    Expected: UExpectedOut
+  
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: In2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: In3
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: In4
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: UIn
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: UIn2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+    - Name: UIn3
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 6
+        Space: 0
+      VulkanBinding:
+        Binding: 6
+    - Name: UIn4
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 7
+        Space: 0
+      VulkanBinding:
+        Binding: 7
+    - Name: Out
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 8
+        Space: 0
+      VulkanBinding:
+        Binding: 8
+    - Name: UOut
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 9
+        Space: 0
+      VulkanBinding:
+        Binding: 9
+...
+#--- end
+
+# Bug: https://github.com/llvm/offload-test-suite/issues/944
+# XFAIL: Intel && DirectX
+
+# Bug: https://github.com/llvm/offload-test-suite/issues/943
+# XFAIL: Intel && Vulkan
+
+# Bug: https://github.com/llvm/offload-test-suite/issues/981
+# XFAIL: Clang
+
+# Metal doesn't support 64-bit wave operations
+# Bug: https://github.com/llvm/offload-test-suite/issues/355
+# XFAIL: Metal
+
+# REQUIRES Int64
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -enable-16bit-types -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o