Add configurable CS to clock-start delay

Acording to spec:
t_DSV (data strobe valid) which is the time from
CS# going low to the first hyperbus clock can be
at most 2 clock periods long (12ns@166MHz).
This shrinks the RWDS valid window down to
one period centered on CA4 (5th data transaction).
Meaning it is valid around the 3rd rising edge of CK.

Problem:
With additional routing delay this may cause the
RWDS sample register (clocked by clk_i) to miss
the stable period of RWDS.

Solution:
Delaying the clock is allowed and gives RWDS more
time to arrive and creates a larger stable window.

It is possible to set this to zero to increase throughput.

Author: phsauter

src/hyperbus_cfg_regs.sv

@@ -30,10 +30,10 @@ module hyperbus_cfg_regs #(
     `include "common_cells/registers.svh"
 
     // Internal Parameters
-    localparam int unsigned NumBaseRegs     = 11;
+    localparam int unsigned NumBaseRegs     = 12;
     localparam int unsigned NumRegs         = 2*NumChips + NumBaseRegs;
     localparam int unsigned RegsBits        = cf_math_pkg::idx_width(NumRegs);
-    localparam int unsigned RegStrbWidth    = RegDataWidth/8;                   // TODO ASSERT: Must be power of two >= 16!!
+    localparam int unsigned RegStrbWidth    = RegDataWidth/8;
 
     // Data and index types
     typedef logic [RegsBits-1:0]        reg_idx_t;
@@ -59,6 +59,7 @@ module hyperbus_cfg_regs #(
         if (sel_reg_mapped) begin
             rfield = {
                 crange_q,
+                reg_data_t'(cfg_q.csn_to_ck_cycles),
                 reg_data_t'(cfg_q.t_csh_cycles),
                 reg_data_t'(cfg_q.which_phy),
                 reg_data_t'(cfg_q.phys_in_use),
@@ -99,6 +100,7 @@ module hyperbus_cfg_regs #(
                 'h8: cfg_d.phys_in_use              = (NumPhys==1) ? 0 : ( (~wmask & cfg_q.phys_in_use ) | (wmask & reg_req_i.wdata) );
                 'h9: cfg_d.which_phy                = (NumPhys==1) ? 0 : ( (~wmask & cfg_q.which_phy   ) | (wmask & reg_req_i.wdata) );
                 'ha: cfg_d.t_csh_cycles             = (~wmask & cfg_q.t_csh_cycles            ) | (wmask & reg_req_i.wdata);
+                'hb: cfg_d.csn_to_ck_cycles         = (~wmask & cfg_q.csn_to_ck_cycles        ) | (wmask & reg_req_i.wdata);
                 default: begin
                     {sel_chip, chip_reg} = sel_reg - NumBaseRegs;
                     crange_d[sel_chip][chip_reg] = (~wmask & crange_q[sel_chip][chip_reg]) |  (wmask & reg_req_i.wdata);

src/hyperbus_phy.sv

@@ -269,15 +269,32 @@ module hyperbus_phy import hyperbus_pkg::*; #(
                 if (trans_valid_i & ~b_pending_q & r_outstand_q == '0) begin
                     tf_d    = trans_i;
                     cs_d    = trans_cs_i;
-                    // Send 3 CA words (t_CSS respected through clock delay)
-                    timer_d = 2;
-                    state_d = SendCA;
-                    // Enable output driver (needs to be enabled one cycle
-                    // earlier since tri-state enables of IO pads are quite
-                    // slow compared to the data pins)
+
+                    if(cfg_i.csn_to_ck_cycles != 0) begin
+                        // asser CS but delay hyper_ck to allow more time
+                        // for memory to drive RWDS (to satisfy t_DSV)
+                        state_d = DelayCK;
+                        timer_d = cfg_i.csn_to_ck_cycles -1;
+                    end else begin
+                        // max throughput when memory RWDS signal arrives early
+                        state_d = SendCA;
+                        // Send 3 CA words (t_CSS respected through clock delay)
+                        timer_d = 2;
+                    end
+                    
+                    // Enable output driver (needs to be enabled at least 
+                    // one cycle earlier since tri-state enables of IO pads
+                    // are quite slow compared to the data pins)
                     trx_tx_data_oe = 1'b1;
                 end
             end
+            DelayCK: begin
+                trx_clk_ena = 1'b0;
+                if (ctl_timer_zero) begin
+                    timer_d = 2; // Send 3 CA words
+                    state_d = SendCA;
+                end
+            end
             SendCA: begin
                 // Dataflow handled outside FSM
                 trx_clk_ena         = 1'b1;

src/hyperbus_pkg.sv

@@ -20,7 +20,8 @@ package hyperbus_pkg;
         logic           address_space;
         logic           phys_in_use;
         logic           which_phy;
-        logic [3:0]     t_csh_cycles; //add an configurable Tcsh for high freq operation(200MHz Hyperram)
+        logic [3:0]     t_csh_cycles; // add an configurable Tcsh for high freq operation(200MHz Hyperram)
+        logic [3:0]     csn_to_ck_cycles; // delay hyper_ck after CS is asserted (more time for t_DSV)
     } hyper_cfg_t;
 
     typedef struct packed {
@@ -40,6 +41,7 @@ package hyperbus_pkg;
     typedef enum logic[3:0] {
         Startup,
         Idle,
+        DelayCK,
         SendCA,
         WaitLatAccess,
         Read,
@@ -74,7 +76,8 @@ package hyperbus_pkg;
             address_space:              'b0,
             phys_in_use:                NumPhys-1,
             which_phy:                  NumPhys-1,
-            t_csh_cycles:               'h1
+            t_csh_cycles:               'h1,
+            csn_to_ck_cycles:           'h2
         };
 
         return cfg;