diff --git a/.gitignore b/.gitignore
new file mode 100644
index 00000000..f20dda8c
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,10 @@
+fpga
+install
+ips
+ipstools
+pulp-builder
+pulp-rt-examples
+*mk
+*pyc
+*.f
+*.json
\ No newline at end of file
diff --git a/fpga/.gitignore b/fpga/.gitignore
index c764b3a0..f9fceac6 100644
--- a/fpga/.gitignore
+++ b/fpga/.gitignore
@@ -1,5 +1,30 @@
-pulpissimo/*
-pulpissimo_genesys2.bin
-pulpissimo_genesys2.bit
-pulpissimo_zcu104.bin
-pulpissimo_zcu104.bit
+pulp_cluster/*.edf
+pulp_cluster/*.v
+pulpemu/pulpemu.*
+ips/*/ip/
+*.jou
+*.log
+*.cache/
+*.hw/
+*.runs/
+*.srcs/
+*.xpr
+*.xci
+*.Xil
+*.mif
+*.swp
+vivado_*
+reports*
+*bin
+*bit
+
+sim/.cxl*
+sim/ips_inputs
+sim/vcompile/rtl/*
+sim/vcompile/ips/*
+sim/models
+sim/modelsim.ini.bak
+*sim.v
+*sdf
+*.mcs
+*.prm
\ No newline at end of file
diff --git a/fpga/Makefile b/fpga/Makefile
index 3528176b..924cb4bb 100644
--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -1,48 +1,48 @@
-.DEFAULT_GOAL:=help
-
-all: genesys2 zcu104 nexys_video ## Generates the bitstream for all supported boards board.
-
-clean_all: clean_genesys2 clean_zcu104 clean_nexys_video ## Removes synthesis output and bitstreams for all boards.
-
-genesys2: ## Generates the bistream for the genesys2 board
-	cd pulpissimo-genesys2; make all
-	cp pulpissimo-genesys2/pulpissimo_genesys2.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_genesys2.bit
-	cp pulpissimo-genesys2/pulpissimo_genesys2.runs/impl_1/xilinx_pulpissimo.bin pulpissimo_genesys2.bin
-	@echo "Bitstream generation for genesys2 board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_genesys2.bit and ./pulpissimo_genesys2.bin"
-
-clean_genesys2: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the genesys2 board.
-	cd pulpissimo-genesys2; make clean
-	rm -f pulpissimo_genesys2.bit
-	rm -f pulpissimo_genesys2.bin
-
-zcu104: ## Generates the bistream for the zcu104 board
-	cd pulpissimo-zcu104; make all
-	cp pulpissimo-zcu104/pulpissimo_zcu104.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_zcu104.bit
-	cp pulpissimo-zcu104/pulpissimo_zcu104.runs/impl_1/xilinx_pulpissimo.bin pulpissimo_zcu104.bin
-	@echo "Bitstream generation for zcu104 board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_zcu104.bit and ./pulpissimo_zcu104.bin"
-
-clean_zcu104: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the zcu104 board.
-	cd pulpissimo-zcu104; make clean
-	rm -f pulpissimo_zcu104.bit
-	rm -f pulpissimo_zcu104.bin
-
-nexys_video: ## Generates the bistream for the nexys_video board
-	cd pulpissimo-nexys_video; make all
-	cp pulpissimo-nexys_video/pulpissimo-nexys_video.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_nexys_video.bit
-	cp pulpissimo-nexys_video/pulpissimo-nexys_video.runs/impl_1/xilinx_pulpissimo.bin pulpissimo_nexys_video.bin
-	@echo "Bitstream generation for nexys_video board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_nexys_video.bit and ./pulpissimo_nexys_video.bin"
-
-clean_nexys_video: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the nexys_video board.
-	cd pulpissimo-nexys_video; make clean
-	rm -f pulpissimo_nexys_video.bit
-	rm -f pulpissimo_nexys_video.bin
-
-help: ## Show this help message
-	@echo "PULPissimo on FPGA"
-	@echo ""
-	@echo "Call make with one of the supported FPGA boards as arguments to generate the bitstream in the corresponding folder. "
-	@echo "E.g. 'make genesys2' to generate the bitstream for the genesys2 board in pulpissimo-genesy2 subdirectory."
-	@echo "By default make invokes 'vivado'  to start Xilinx Vivado. This behaviour can be overriden by setting the make variable 'VIVADO'"
-	@echo "e.g. make genesys2 VIVADO='vivado-2018.3 vivado' for ETH centos machines."
-	@echo ""
-	@grep -E '^[a-zA-Z0-9_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'
+include fpga-settings.mk
+
+all: synth impl
+
+gui:
+	cd pulpemu; make clean-impl gui
+
+impl:
+	cd pulpemu; make clean-impl impl
+
+ips: mem clk
+
+generate_bitstream: ips synth-pulpcluster synth-pulpemu
+
+mem:
+	cd ips/xilinx_interleaved_ram; make clean all
+	cd ips/xilinx_private_ram; make clean all
+	cd ips/xilinx_rom_bank_2048x32; make clean all
+	cd ips/xilinx_tcdm_bank_1024x32; make clean all
+	cd ips/xilinx_tcdm_bank_2048x32; make clean all
+
+clk: ## Synthesizes the Xilinx Clocking Manager IPs
+	cd ips/xilinx_clk_mngr; make clean all
+	cd ips/xilinx_slow_clk_mngr; make clean all
+
+synth: synth-pulpcluster synth-pulpemu
+
+synth-pulpcluster:
+	cd pulp_cluster; make clean all
+
+synth-pulpemu:
+	cd pulpemu; make clean all
+
+cleanall: clean-ips clean-ulpcluster clean-pulpemu
+
+clean-ulpcluster:
+	cd pulp_cluster; make clean
+
+clean-pulpemu:
+	cd pulpemu; make clean
+
+clean-ips:
+	cd ips/xilinx_interleaved_ram; make clean
+	cd ips/xilinx_private_ram; make clean
+	cd ips/xilinx_rom_bank_2048x32; make clean
+	cd ips/xilinx_tcdm_bank_1024x32; make clean
+	cd ips/xilinx_tcdm_bank_2048x32; make clean
+	cd ips/xilinx_clk_mngr; make clean
diff --git a/fpga/README.md b/fpga/README.md
new file mode 100644
index 00000000..8e0e0d8b
--- /dev/null
+++ b/fpga/README.md
@@ -0,0 +1,257 @@
+# FPGA
+
+PULP has been implemented on FPGA for various Xilinx FPGA boards
+
+
+### CurrentlySupported Boards
+
+* Xilinx ZCU102
+* Xilinx VCU118
+
+### Bitstream Generation
+In order to generate the PULP bitstream for a supported target FPGA board
+first generate the necessary synthesis include scripts by starting the
+`update-ips` script in the PULP-open root directory:
+
+```Shell
+./update-ips
+./generate-scripts-fpga 
+```
+This will parse the ips_list.yml using the PULP IPApproX IP management tool to
+generate tcl scripts for all the IPs used in the PULP project. These files
+are later on sourced by Vivado to generate the bitstream for PULP.
+
+Now switch to the fpga subdirectory and source the right board:
+
+```Shell
+cd fpga
+source sourceme.sh
+```
+Choose the platfom.
+
+
+### VIVADO IPs
+
+Before synthesizing the Design you should implement the Vivado-related ips. 
+To do this run the following Makefile command:
+
+```Shell
+make ips
+```
+
+This will implement all the mem bram macros and the IPs needed by the design
+
+
+### PULP CLUSTER SYNTHESIS
+
+First we need to synthesize the cluster
+To do this run the following Makefile command:
+
+```Shell
+make synth-pulpcluster
+```
+
+
+### TOP LEVEL (PULP) SYNTHESIS AND IMPLEMENTATION
+
+If you already synthesized the cluster you can run the following command:
+
+```Shell
+make synth-pulpemu
+```
+
+Otherwise you can run the following, which synthesizes the cluster, the top and then generates the bitstream
+
+```Shell
+make synth
+```
+
+
+### Bitstream Flashing
+Start Vivado then:
+
+```
+Open Hardware Manager
+Open Target
+Program device
+```
+Be sure you are loading ".bit" file to the fpga board.
+
+### Compiling Applications for the FPGA Target
+To run or debug applications for the FPGA you need to use a recent version of
+the PULP-SDK (tag 2019.11.05 is fully stable for FPGA). Configure the SDK for the FPGA
+platform by running the following commands within the SDK's root directory:
+
+```Shell
+source configs/pulp.sh
+source configs/fpgas/pulp/genesys2.sh
+```
+
+In order for the SDK to be able to configure clock dividers (e.g. the ones for
+the UART module) to the right values it needs to know which frequencies
+PULP is running at. You can find the default frequencies in the above
+mentioned board specific README files.
+
+In our application we need to override two weakly defined variables in our
+source code to configure the SDK to use these frequencies:
+```C
+#include <stdio.h>
+#include <rt/rt_api.h>
+
+int __rt_fpga_fc_frequency = <Core Frequency> // e.g. 20000000 for 20MHz;
+int __rt_fpga_periph_frequency = <SoC Frequency> // e.g. 10000000 for 10MHz;
+
+int main()
+{
+...
+}
+```
+
+By default, the baudrate of the UART is set to `115200`.
+
+Add the following global variable declaration to your application in case
+you want to change it:
+
+```C
+unsigned int __rt_iodev_uart_baudrate = your baudrate;
+```
+
+Compile your application with
+
+```Shell
+make clean all io=uart
+```
+This command builds the ELF binary with UART as the default io peripheral.
+The binary will be stored at `build/pulp/[app_name]/[app_name]`.
+
+### GDB and OpenOCD
+In order to execute our application on the FPGA we need to load the binary into
+PULPissimo's L2 memory. To do so we can use OpenOCD in conjunction with GDB to
+communicate with the internal RISC-V debug module.
+
+PULP uses JTAG as a communication channel between OpenOCD and the Core.
+Have a look at the board specific README file on how to connect your PC with
+PULP's JTAG port.
+
+Due to a long outstanding issue in the RISC-V OpenOCD project (issue #359) the
+riscv/riscv-openocd does not work with PULPissimo. However there is a small
+workaround that we incorporated in a patched version of openocd. If you have
+access to the artifactory server, the patched openocd binary is installed by
+default with the `make deps` command in the SDK. If you don't have access to the
+precompiled binaries you can automatically download and compile the patched
+OPENOCD from source. You will need to install the following dependencies on your
+machine before you can compile OpenOCD:
+
+- `autoconf` >= 2.64
+- `automake` >= 1.14
+- `texinfo`
+- `make`
+- `libtool`
+- `pkg-config` >= 0.23 (or compatible)
+- `libusb-1.0`
+- `libftdi`
+- `libusb-0.1` or `libusb-compat-0.1` for some older drivers
+
+After installing those dependecies with you OS' package manager you can
+download, apply the patch and compile OpenOCD with:
+
+```Shell
+source sourceme.sh && ./pulp-tools/bin/plpbuild checkout build --p openocd --stdout
+```
+
+The SDK will automatically set the environment variable `OPENOCD` to the
+installation path of this patched version.
+
+Launch openocd with one of the provided or your own configuration file for the
+target board as an argument.
+
+E.g.:
+
+```Shell
+$OPENOCD/bin/openocd -f pulp/fpga/openocd-zcu102-olimex-arm-usb-ocd-h.cfg
+```
+In a seperate terminal launch gdb from your `pulp_riscv_gcc` installation passing
+the ELF file as an argument with:
+
+`$PULP_RISCV_GCC_TOOLCHAIN_CI/bin/riscv32-unknown-elf-gdb  PATH_TO_YOUR_ELF_FILE`
+
+In gdb, run:
+
+```
+(gdb) target remote localhost:3333
+```
+
+to connect to the OpenOCD server.
+
+In a third terminal launch a serial port client (e.g. `screen` or `minicom`) on
+Linux to riderect the UART output from PULPissimo with e.g.:
+
+```Shell
+screen /dev/ttyUSB0 115200
+```
+
+the ttyUSB0 target may change.
+
+Now you are ready to debug!
+
+In gdb, load the program into L2:
+
+```
+(gdb) load
+```
+and run the programm:
+
+```
+(gdb) continue
+```
+Of course you can also benefit from the debug capabilities that GDB provides.
+
+E.g. see the disasembled binary:
+```
+(gdb) disas
+```
+List the current C function, set a break point at line 25, continue and have fun!
+
+```
+(gdb) list
+21
+22  int main()
+23  {
+24    while (1) {
+25      printf("Hello World!\n\r");
+26     for (volatile int i=0; i<1000000; i++);
+27    }
+28    return 0;
+29  }
+
+(gdb) b 25
+Breakpoint 1 at 0x1c0083d2: file test.c, line 25.
+(gdb) c
+Continuing.
+
+Breakpoint 1, main () at test.c:25
+25      printf("Hello World!\n\r");
+
+
+(gdb) disas
+Dump of assembler code for function main:
+   0x1c0083d4 <+22>:    li  a1,1
+   0x1c0083d6 <+24>:    blt s0,a5,0x1c0083e8 <main+42>
+=> 0x1c0083da <+28>:    lw  a5,12(sp)
+   0x1c0083dc <+30>:    slli    a1,a1,0x1
+   0x1c0083de <+32>:    addi    a5,a5,1
+   0x1c0083e0 <+34>:    sw  a5,12(sp)
+
+(gdb) monitor reg a5
+a5 (/32): 0x000075B7
+
+```
+Not all gdb commands work as expected on the riscv-dbg target.
+To get a list of available gdb commands execute:
+```
+monitor help
+```
+
+Most notably the command `info registers` does not work. Use `monitor reg`
+instead which has the same effect.
+
diff --git a/fpga/pulpissimo-genesys2/tcl/messages.tcl b/fpga/common/messages.tcl
similarity index 100%
rename from fpga/pulpissimo-genesys2/tcl/messages.tcl
rename to fpga/common/messages.tcl
diff --git a/fpga/docs/README.md b/fpga/docs/README.md
new file mode 100644
index 00000000..10a14ade
--- /dev/null
+++ b/fpga/docs/README.md
@@ -0,0 +1,12 @@
+# Simple Guide
+
+## VEGA/GAP9
+
+1. All the scripts are in master branch.
+2. Document <ZC706_PULPEMU_GAP9.pdf> <ZCU102_PULPEMU_GAP9.pdf> are for VEGA/GAP9 fpga implementation.
+
+## GAP8
+
+1. All the scripts are in GAP8 branch.
+2. Can also use <ZC706_PULPEMU_GAP9.pdf> <ZCU102_PULPEMU_GAP9.pdf> for GAP8 fpga implementation. The only difference is that in GAP8, there is no <pad_bootmode> pin.
+
diff --git a/fpga/pulpissimo-zcu104/fpga-settings.mk b/fpga/fpga-settings.mk
similarity index 77%
rename from fpga/pulpissimo-zcu104/fpga-settings.mk
rename to fpga/fpga-settings.mk
index 28d84697..2e13a04b 100644
--- a/fpga/pulpissimo-zcu104/fpga-settings.mk
+++ b/fpga/fpga-settings.mk
@@ -1,7 +1,5 @@
-export BOARD=zcu104
-export XILINX_PART=xczu7ev-ffvc1156-2-e
-export XILINX_BOARD=xilinx.com:zcu104:part0:1.1
 export FC_CLK_PERIOD_NS=50
+export CL_CLK_PERIOD_NS=50
 export PER_CLK_PERIOD_NS=100
 export SLOW_CLK_PERIOD_NS=30517
 #Must also change the localparam 'L2_BANK_SIZE' in pulp_soc.sv accordingly
diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/.gitignore b/fpga/ips/xilinx_clk_mngr/.gitignore
similarity index 100%
rename from fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/.gitignore
rename to fpga/ips/xilinx_clk_mngr/.gitignore
diff --git a/fpga/ips/xilinx_clk_mngr/Makefile b/fpga/ips/xilinx_clk_mngr/Makefile
new file mode 100644
index 00000000..21698d87
--- /dev/null
+++ b/fpga/ips/xilinx_clk_mngr/Makefile
@@ -0,0 +1,21 @@
+PROJECT:=xilinx_clk_mngr
+
+all:
+	vivado -mode batch -source tcl/run.tcl
+	mkdir -p ip
+	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
+	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
+
+gui:
+	vivado -mode gui -source tcl/run.tcl &
+
+clean:
+	rm -rf ip/*
+	mkdir -p ip
+	rm -rf ${PROJECT}.*
+	rm -rf component.xml
+	rm -rf vivado*.jou
+	rm -rf vivado*.log
+	rm -rf vivado*.str
+	rm -rf xgui
+	rm -rf .Xil
diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/tcl/run.tcl b/fpga/ips/xilinx_clk_mngr/tcl/run.tcl
similarity index 77%
rename from fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/tcl/run.tcl
rename to fpga/ips/xilinx_clk_mngr/tcl/run.tcl
index 2310e43b..0b92652d 100644
--- a/fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/tcl/run.tcl
+++ b/fpga/ips/xilinx_clk_mngr/tcl/run.tcl
@@ -1,4 +1,5 @@
 set partNumber $::env(XILINX_PART)
+set boardName  $::env(XILINX_BOARD)
 
 if [info exists ::env(BOARD)] {
     set BOARD $::env(BOARD)
@@ -14,17 +15,23 @@ if [info exists ::env(XILINX_BOARD)] {
 if [info exists ::env(FC_CLK_PERIOD_NS)] {
     set FC_CLK_PERIOD_NS $::env(FC_CLK_PERIOD_NS)
 } else {
-    set FC_CLK_PERIOD_NS 10.000
+    set FC_CLK_PERIOD_NS 50.000
+}
+if [info exists ::env(CL_CLK_PERIOD_NS)] {
+    set CL_CLK_PERIOD_NS $::env(CL_CLK_PERIOD_NS)
+} else {
+    set CL_CLK_PERIOD_NS 50.000
 }
 if [info exists ::env(PER_CLK_PERIOD_NS)] {
     set PER_CLK_PERIOD_NS $::env(PER_CLK_PERIOD_NS)
 } else {
-    set PER_CLK_PERIOD_NS 20.000
+    set PER_CLK_PERIOD_NS 100.000
 }
 
 
 set FC_CLK_FREQ_MHZ [expr 1000 / $FC_CLK_PERIOD_NS]
 set PER_CLK_FREQ_MHZ [expr 1000 / $PER_CLK_PERIOD_NS]
+set CL_CLK_FREQ_MHZ  [expr 1000 / $CL_CLK_PERIOD_NS]
 
 set ipName xilinx_clk_mngr
 
@@ -33,6 +40,9 @@ set_property board_part $boardName [current_project]
 
 create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
 
+#CONFIG.CLKOUT3_USED {true}      
+#CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {$CL_CLK_FREQ_MHZ} \                                           
+
 set_property -dict [eval list CONFIG.PRIM_IN_FREQ {125.000} \
                         CONFIG.NUM_OUT_CLKS {2} \
                         CONFIG.CLKOUT2_USED {true} \
@@ -45,5 +55,5 @@ set_property -dict [eval list CONFIG.PRIM_IN_FREQ {125.000} \
 
 generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
 create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
+launch_run -jobs 12 ${ipName}_synth_1
 wait_on_run ${ipName}_synth_1
diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_interleaved_ram/.gitignore b/fpga/ips/xilinx_interleaved_ram/.gitignore
similarity index 100%
rename from fpga/pulpissimo-genesys2/ips/xilinx_interleaved_ram/.gitignore
rename to fpga/ips/xilinx_interleaved_ram/.gitignore
diff --git a/fpga/ips/xilinx_interleaved_ram/Makefile b/fpga/ips/xilinx_interleaved_ram/Makefile
new file mode 100644
index 00000000..85876b93
--- /dev/null
+++ b/fpga/ips/xilinx_interleaved_ram/Makefile
@@ -0,0 +1,21 @@
+PROJECT:=xilinx_interleaved_ram
+
+all:
+	vivado -mode batch -source tcl/run.tcl
+	mkdir -p ip
+	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
+	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
+
+gui:
+	vivado -mode gui -source tcl/run.tcl &
+
+clean:
+	rm -rf ip/*
+	mkdir -p ip
+	rm -rf ${PROJECT}.*
+	rm -rf component.xml
+	rm -rf vivado*.jou
+	rm -rf vivado*.log
+	rm -rf vivado*.str
+	rm -rf xgui
+	rm -rf .Xil
diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_interleaved_ram/tcl/run.tcl b/fpga/ips/xilinx_interleaved_ram/tcl/run.tcl
similarity index 79%
rename from fpga/pulpissimo-zcu104/ips/xilinx_interleaved_ram/tcl/run.tcl
rename to fpga/ips/xilinx_interleaved_ram/tcl/run.tcl
index a2e84f23..c46f21fb 100644
--- a/fpga/pulpissimo-zcu104/ips/xilinx_interleaved_ram/tcl/run.tcl
+++ b/fpga/ips/xilinx_interleaved_ram/tcl/run.tcl
@@ -1,20 +1,11 @@
 set partNumber $::env(XILINX_PART)
-
-if [info exists ::env(BOARD)] {
-    set BOARD $::env(BOARD)
-} else {
-    error "BOARD is not defined. Please source the sourceme.sh file."
-    exit
-}
-if [info exists ::env(XILINX_BOARD)] {
-	set boardName  $::env(XILINX_BOARD)
-}
+set boardName  $::env(XILINX_BOARD)
 
 # detect target ram size
 if [info exists ::env(INTERLEAVED_BANK_SIZE)] {
     set INTERLEAVED_BANK_SIZE $::env(INTERLEAVED_BANK_SIZE)
 } else {
-    set INTERLEAVED_BANK_SIZE 4096
+    set INTERLEAVED_BANK_SIZE 28672
 }
 
 set ipName xilinx_interleaved_ram
diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_private_ram/.gitignore b/fpga/ips/xilinx_private_ram/.gitignore
similarity index 100%
rename from fpga/pulpissimo-genesys2/ips/xilinx_private_ram/.gitignore
rename to fpga/ips/xilinx_private_ram/.gitignore
diff --git a/fpga/ips/xilinx_private_ram/Makefile b/fpga/ips/xilinx_private_ram/Makefile
new file mode 100644
index 00000000..7e81754f
--- /dev/null
+++ b/fpga/ips/xilinx_private_ram/Makefile
@@ -0,0 +1,21 @@
+PROJECT:=xilinx_private_ram
+
+all:
+	vivado -mode batch -source tcl/run.tcl
+	mkdir -p ip
+	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
+	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
+
+gui:
+	vivado -mode gui -source tcl/run.tcl &
+
+clean:
+	rm -rf ip/*
+	mkdir -p ip
+	rm -rf ${PROJECT}.*
+	rm -rf component.xml
+	rm -rf vivado*.jou
+	rm -rf vivado*.log
+	rm -rf vivado*.str
+	rm -rf xgui
+	rm -rf .Xil
diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_private_ram/tcl/run.tcl b/fpga/ips/xilinx_private_ram/tcl/run.tcl
similarity index 79%
rename from fpga/pulpissimo-genesys2/ips/xilinx_private_ram/tcl/run.tcl
rename to fpga/ips/xilinx_private_ram/tcl/run.tcl
index 78493b37..e2f21dee 100644
--- a/fpga/pulpissimo-genesys2/ips/xilinx_private_ram/tcl/run.tcl
+++ b/fpga/ips/xilinx_private_ram/tcl/run.tcl
@@ -1,20 +1,11 @@
 set partNumber $::env(XILINX_PART)
-
-if [info exists ::env(BOARD)] {
-    set BOARD $::env(BOARD)
-} else {
-    error "BOARD is not defined. Please source the sourceme.sh file."
-    exit
-}
-if [info exists ::env(XILINX_BOARD)] {
-	set boardName  $::env(XILINX_BOARD)
-}
+set boardName  $::env(XILINX_BOARD)
 
 # detect target ram size
 if [info exists ::env(PRIVATE_BANK_SIZE)] {
     set PRIVATE_BANK_SIZE $::env(PRIVATE_BANK_SIZE)
 } else {
-    set PRIVATE_BANK_SIZE 4096
+    set PRIVATE_BANK_SIZE 8192
 }
 
 set ipName xilinx_private_ram
diff --git a/fpga/ips/xilinx_rom_bank_2048x32/Makefile b/fpga/ips/xilinx_rom_bank_2048x32/Makefile
new file mode 100644
index 00000000..dd59873c
--- /dev/null
+++ b/fpga/ips/xilinx_rom_bank_2048x32/Makefile
@@ -0,0 +1,21 @@
+PROJECT:=xilinx_rom_bank_2048x32
+
+all:
+	vivado -mode batch -source tcl/run.tcl
+	mkdir -p ip
+	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
+	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
+
+gui:
+	vivado -mode gui -source tcl/run.tcl &
+
+clean:
+	rm -rf ip/*
+	mkdir -p ip
+	rm -rf ${PROJECT}.*
+	rm -rf component.xml
+	rm -rf vivado*.jou
+	rm -rf vivado*.log
+	rm -rf vivado*.str
+	rm -rf xgui
+	rm -rf .Xil
diff --git a/fpga/ips/xilinx_rom_bank_2048x32/boot_code.coe b/fpga/ips/xilinx_rom_bank_2048x32/boot_code.coe
new file mode 100644
index 00000000..5cbe3e78
--- /dev/null
+++ b/fpga/ips/xilinx_rom_bank_2048x32/boot_code.coe
@@ -0,0 +1,2050 @@
+memory_initialization_radix=2;
+memory_initialization_vector=
+00001000100000000000000001101111,
+00001000010000000000000001101111,
+00001000000000000000000001101111,
+00000111110000000000000001101111,
+00000111100000000000000001101111,
+00000111010000000000000001101111,
+00000111000000000000000001101111,
+00000110110000000000000001101111,
+00000110100000000000000001101111,
+00000110010000000000000001101111,
+00000110000000000000000001101111,
+00000101110000000000000001101111,
+00000101100000000000000001101111,
+00000101010000000000000001101111,
+00000101000000000000000001101111,
+00000100110000000000000001101111,
+00000100100000000000000001101111,
+00000100010000000000000001101111,
+00000100000000000000000001101111,
+00000011110000000000000001101111,
+00000011100000000000000001101111,
+00000011010000000000000001101111,
+00000011000000000000000001101111,
+00000010110000000000000001101111,
+00000010100000000000000001101111,
+00000010010000000000000001101111,
+00000010000000000000000001101111,
+00000001110000000000000001101111,
+00000001100000000000000001101111,
+00000001010000000000000001101111,
+00000001000000000000000001101111,
+00000000110000000000000001101111,
+00000000110000000000000001101111,
+00000000000000000000000001101111,
+00110000001000000000000001110011,
+00000010000110001010000100010111,
+01001101010000010000000100010011,
+01011000010000000000000001101111,
+10000101100000101000000100110010,
+00011010000100001001011110110111,
+00000000000001111010000000100011,
+00010000010100000000000001110011,
+10000111101101111011111111110101,
+10000111100100110001110000011000,
+10100000001000110000000000000111,
+10000010001000110000000000000111,
+10100100001000110000000000000111,
+10010001001000110000001000000111,
+10000010001000110000001000000111,
+10000000100000100000001000000111,
+00011100000110001000011110110111,
+00000000000001111000011110010011,
+10010101001111100000010100010010,
+11001011000010010100010101111000,
+00000010101101111100011110000011,
+11111100000101111011011110110011,
+00100011000000111100011110000001,
+10000011000000100000010101000101,
+10000000100000100100010100000001,
+11001010001001100001000100000001,
+00011100000110001000010010110111,
+00000000000001001000011110010011,
+00000000000101111100011110000011,
+11001100001000101100111000000110,
+11000110010011101100100001001010,
+10001011101000011100010001010010,
+10101001001101111100101111001001,
+00100111100000110001110000011000,
+10000100001010101001011111001001,
+00011100000110001010010100110111,
+00000000000001001000010010010011,
+00001001000100111000100110101110,
+00001010000100111001011111001001,
+11000111100110011001100000000101,
+10011000000001010000010100010011,
+00000000000010010010000000100011,
+00110111100000000001000011101111,
+00111101010010010010100000000011,
+10000111000100111000011111001110,
+10000110100100110000000101010100,
+10000110001000100000000001010100,
+10000101010100101000010110100010,
+00010100111000000001000011101111,
+00000010101101001100011110000011,
+00111100000010010010101000100011,
+11000011101100011000101111000001,
+11101101101110001000011010110111,
+11111111110010011000010110010011,
+01000111100000010101011101111101,
+00110010000001101000011010010011,
+00000000101101111110101001100011,
+00100111100000111001010001001110,
+01000111000100111111111111000100,
+10000010011000111111111111110111,
+00110111000011010000001011100111,
+00000000111101000000011000110011,
+00000000000001100100011000000011,
+11010000111110111000111100110001,
+01010101000100110000000010000011,
+00000111001100110000000000010111,
+10001111011101011100000000000111,
+00000111100001011000111100101001,
+01000000111100101011111111000001,
+01000100110100100100010001100010,
+01001001101100100100100101000010,
+01100001000001010100101000100010,
+01010111000100111000000010000010,
+01100111101101110100000001010101,
+00000111100100010001101000010000,
+10010111001111100000011100001010,
+01000111100001010100001100010100,
+00000000101001111001010100110011,
+11111111111101010100010100010011,
+11000011000010001000110101110101,
+10010111101101111000000010000010,
+00000111001101110001101000010000,
+11000011110110000000010000000000,
+00000000110001111000011000010011,
+10010101100100110100001000010100,
+11011011011000110000000001010110,
+10000110100100110000000000000101,
+01000010100101000000001001000111,
+00000001010001111000011010010011,
+00000111101000011100001010011000,
+10000000100000101100001110011000,
+00010000010100000000000001110011,
+01110001001110011011011111000101,
+10000100001101111101110000100010,
+11010100010100100001110000011000,
+00000000000001000000010000010011,
+00011010000100000010101000110111,
+11010110010011101101101000100110,
+11010000010110101101001001010110,
+11001100011000101100111001011110,
+10001001101010101100101001100110,
+00001000000010100000110010010011,
+11011000010010101101111000000110,
+10000100101100101000010100101110,
+00001011100100111000101010101110,
+01011100000000010000100000000000,
+00100100100001000000101100010011,
+00001001000010100000101000010011,
+01010100011000101110110010011001,
+01010100110100100101000011110010,
+01011001101100100101100101000010,
+01011010100100100101101000100010,
+01001011111100100101101100000010,
+01001100110100100100110001100010,
+01100001001000011000010110110010,
+01010111100000111011110101100001,
+00000100001000110000001101010100,
+11010110100100110010010110000100,
+11010111000100110000000010001001,
+00000100101000110000000010000111,
+11110111100100110010010011100100,
+00000101001000110000111111110111,
+01000111100000110010010011110100,
+00000101101000110000001101110100,
+00000111000100110010010000000100,
+00000110001000111111100000000000,
+00000110101000110010010011100100,
+00000111001000110010010011110100,
+11110110100100110010010011100100,
+00000111101000110000111111110110,
+00001000001000110010010011010100,
+11110110100100110010010011100100,
+00001000101000110000111111111001,
+00001001001000110010010011010100,
+00001001101000110010010000000100,
+11000111101100110010010011100100,
+00001010001000111100000000000111,
+01000111100001010010010011110100,
+00000101011101001100100100110011,
+11010001011000110100011100110101,
+00000111100100110000001010010111,
+00001010101000111111110000000000,
+00000111100100110010010011110100,
+11110111100100111111111111111001,
+00001011001000110000111111110111,
+00000111100100110010010011110100,
+00001011101000110000010000000000,
+01000111010000010010010011110100,
+00000110000000000000011110010011,
+00000000111110110100011100100011,
+00000010101101000100011110000011,
+10011001110010100000011100000101,
+11000000000101111001011110110011,
+00000111100111100000011110011101,
+00000001100101111000011010110011,
+10100010001010111000010110110110,
+10100000001000110000000101010101,
+10010111110100100000000100100101,
+00000110101000010100010111000001,
+10000110101111101100001010001100,
+00000001011001101010001000101011,
+00000111101000011100001010011000,
+11000110001010101100001110001100,
+00111101010101011100010000110010,
+10000100101100111001101011001010,
+01000110001000100100000100100100,
+10111111000110010100010100110010,
+00011100000110001000011100110111,
+00000000000001110000011100010011,
+00000000010001110100011110000011,
+11000010001101111001011110110011,
+00100100111101110010010000100011,
+00000010101001110100011110000011,
+11111100000101111011011010110011,
+11000001110001101100011010110011,
+00100100110101110010011000100011,
+00100000000001110000011010110111,
+00000110101101111000110101010101,
+00101000001000111001000000000000,
+00000110100001010010010010100111,
+00100100110101110010101000100011,
+11000010000101111001011110110011,
+00011010000100000010011100110111,
+00001010000001110000011100010011,
+10010111101110100000011110011110,
+00011100000110001000011010110111,
+10000110100100111000011100111110,
+00100010001010110010010010000110,
+01000110110000010000000011010111,
+00000111101000011100001100010100,
+11000011100110000100011101010001,
+00010001000000011011010110011001,
+10000100001010101100110000100010,
+11000110001011100100010101100001,
+11001110000001101100010000110010,
+01000101101100100011101100010101,
+00011110011000110100011000100010,
+10000111101101110001000000000101,
+10000111000100110001110000011000,
+01000110100000110000000000000111,
+10000111100100110000001010000111,
+10110110101100110000000000000111,
+11101110110110011111101000100110,
+00000000010001110100011110000011,
+00100000000001110000010100110111,
+00100000000011110000100000110111,
+11000010001101111001011110110011,
+00100100111101110010010000100011,
+00000010101001110100011110000011,
+11111100000101111011011010110011,
+11000001110001101100011010110011,
+00100100110101110010011000100011,
+00000000001101010000011010010011,
+00100100110101110010100000100011,
+11011110100001000001011010110011,
+00000001000001101110011010110011,
+11101110100001000011010000110011,
+00100100110101110010101000100011,
+00000110100100111000110001001001,
+00000101001101111111111111110110,
+00101100001000110111000001000111,
+10001110110010010010010010000111,
+00100100110101110010111000100011,
+10010000000000000000011010110111,
+00100000001000110000011010000101,
+10010111101100110010011011010111,
+00100110101101111100001000010111,
+00000111100111100001101000010000,
+00001000000001101000011100010011,
+10000101001110101001011100111110,
+00000000101101010010001000101011,
+00001010000001101000011010010011,
+10010111101101101100000100010000,
+01000110010100010000011100100001,
+00011100000110001000011010110111,
+10000110100100111100001100010000,
+10000111001111100010010010000110,
+00000000110101110010001000101011,
+11000011000101000100011011110001,
+11000011100100000000011110100001,
+01000000111100100100010001100010,
+10111011101101010110000100000101,
+00000100000101101011110101100011,
+00000010101001111100011100000011,
+11111100000101110011011010110011,
+01110110100100111110001010110001,
+00100111001101110000001000000111,
+00000111000100110001101000010000,
+11001010100001010100101000000111,
+00000011000101111010011010000011,
+11000011000000001000110001010101,
+00000010101001111100011110000011,
+00011010000100000010011100110111,
+00001000000001110000011100010011,
+11000010000101111001011110110011,
+00000111100111100000011110100001,
+10000111001111101001011110111010,
+00000000101101110010001000101011,
+00000111101000011100001100010000,
+11000011100110000100011101010001,
+01000100001100111011111101000101,
+10111111110100011100000110000100,
+00011010000100000010011100110111,
+01001010100001110010000000100011,
+10000101001000101011011111110001,
+01000000111100100100010001100010,
+00000000011011110110000100000101,
+01000000111100100001010000010000,
+01100001000001010100010001100010,
+10000111001101111000000010000010,
+00100111101101110001110000011000,
+00000111000100110001101000010000,
+00000101100001100000000000000111,
+00100100101001110001010000100011,
+01001010000001111000011010010011,
+11000001100001011100010110110011,
+00000111000100111100001010001100,
+10000110100100110010010010000111,
+11000010100110000100100100000111,
+01001001010001111000011100010011,
+11000011000101000100011010001001,
+01001001100001111000011110010011,
+11000011100110000100011101010001,
+10010111101101111011100111011001,
+10000111000100110001101000010000,
+01100110100100010000000001000111,
+00000111110100011100001100010100,
+01000111011000110100011100000001,
+10010111101101110000000010100111,
+01100111000100010001101000010000,
+10000000100000101100011110011000,
+00010000010100000000000001110011,
+00000111000001011100001110010100,
+00010001000000011011011111101101,
+01000100101101111100101000100110,
+11000010010101100001101000010000,
+11001110000001101100000001011010,
+11001000010010101100110000100010,
+11000100010100101100011001001110,
+00000111010001001000010010010011,
+01001011000010010100101010000101,
+00110110011010010100010101101101,
+10100000001000111110010101000001,
+01000000100000000000000101010100,
+00010000000001000111011110010011,
+01000101000010011100101111001101,
+11101001001111010011111010100101,
+00111010001100111000000000100101,
+00110100001100111111000001110100,
+00100011011000111111100000110100,
+01000110011000110000010000100100,
+11011000011110010000000010001011,
+00000010000101000010011101100011,
+00100111011000110011111000000101,
+00111101111000110000011001000100,
+01000101000110011111111001010100,
+11100001010000010011111010000001,
+00000000000001001010000000100011,
+00000000000001001010100100000011,
+00000000100110010101100100010011,
+11110000011110010011100100110011,
+00000110010110010011011101100011,
+00110111100101010100010100000101,
+01000101011100011011011111110101,
+11110101011000010011111000000101,
+00011010000100000100011110110111,
+10100000000000011101101111100000,
+00011100000110001000011110110111,
+00000000000001111000011110010011,
+00000000000001111101011100000011,
+01000000001110100101101000010011,
+11001110001101000010011100110011,
+00000000111001111001000000100011,
+00000010100001111100011100000011,
+11000010000010100010011100110011,
+00000010111001111000010000100011,
+01000100011000100100000011110010,
+01001001010000100100010011010010,
+01001010001000100100100110110010,
+01001011000000100100101010010010,
+10000000100000100110000100000101,
+00110100111011010100010100010101,
+10100000001000111110100100011001,
+01000101000001010000000101010100,
+10101001100000110011011100111001,
+11011001100100110000000000000100,
+10111001101100110000000010011001,
+10000100010011101111000001111001,
+10000100010010101011011110011101,
+01000101000001011011011110001101,
+10110111100100010011110111011101,
+10010110001011101000011110101010,
+00000000110001011001001101100011,
+11000111000010111000000010000010,
+10000000101010110000000000010101,
+10111111110011010000000011100111,
+01000111101101110111000100111001,
+11011110000001100001101000010000,
+11011010001001101101110000100010,
+11010110010011101101100001001010,
+11010010010101101101010001010010,
+11001110010111101101000001011010,
+11001010011001101100110001100010,
+11000110011011101100100001101010,
+00000111110001111010011110000011,
+00011100000110001010010010110111,
+11111000001101111011011110110011,
+10010111110001001000011100010011,
+00111100111101110010110000100011,
+00000000001001111011011101100011,
+00011100000000000000011110110111,
+10010111100000100100001110011100,
+01000111100001011010000000000001,
+10010111110001001000010010010011,
+00011100000110001000100110110111,
+00111100111101001010101000100011,
+10000111100100111100000010011100,
+10000111100100110000000000001001,
+10000100000100110000010111000111,
+01010000111110110000000000001001,
+10101000001010110000000111110010,
+00000000000000010000000000000111,
+00011010000100000110011110110111,
+10000111000100110101100101111101,
+00100000001000110000000001000111,
+10000111000100110000000100100111,
+00100000001000110000000010000111,
+10000111000100110000000100100111,
+00100000001000110000000011000111,
+10000111000100110000000100100111,
+00100000001000110000000100000111,
+10000111000100110000000100100111,
+00100000001000110000000101000111,
+10000111000100110000000100100111,
+00100000001000110000000110000111,
+10000111000100110000000100100111,
+00100000001000110000000111000111,
+10000111100100110000000100100111,
+10100000001000110000001000000111,
+01000111101101110000000100100111,
+10100111100000110001101000010000,
+10011110011000110000110001000111,
+00111010111000010001000000000111,
+00000000000101000100011110000011,
+00000010000001111111011110010011,
+10010111101101111100011110001001,
+10100000001000110001101000010000,
+01000111100000111000000100100111,
+01000111000001010000001010000100,
+00100111101100110100011010001001,
+01010111000000111100001000000111,
+00000100001000110000000000000100,
+10100111001100110000001011110100,
+00010000001000111100111000110110,
+00000111000000110000000011100100,
+01001101011000110000001010110100,
+10110111101100110000000000000111,
+10010001011000111111101000100111,
+01000111100000110000111000000111,
+01000111000010010000000001000100,
+11000010001101110010011110110011,
+00000000111101000000001000100011,
+00000010100001000100011110000011,
+11111010001001111011011110110011,
+00000000001001111011011001100011,
+00000000000010011000010100010011,
+01101111101000000000000011101111,
+00000010101101000100011110000011,
+00000010000001111111011110010011,
+01000111100001011110011110000001,
+00000010111101000001111000100011,
+00000010101001000100011110000011,
+00000100000001111111011100010011,
+01000111000001011110011100000001,
+00000010111001000000000010100011,
+00010000000001111110011110110011,
+00000000000001111100010101100011,
+00001100101000110100011111000001,
+01000111100000110000001011110100,
+10110111101100110000001010000100,
+11101111110010011111101000100111,
+00000010101001000100010100000011,
+00011010000100000010011100110111,
+00010101001100110100001100010100,
+01000111100001011100001000010101,
+00000000101001111001011110110011,
+11000011000111001000111111010101,
+00110100000101010000010100001101,
+00000010101101000100010100000011,
+11111100000101010011011110110011,
+00100111001101111100111110010001,
+01000011000101000001101000010000,
+11000000000101010001010100110011,
+01000111100001010000010100011101,
+00000000101001111001011110110011,
+11000011000111001000111111010101,
+00110100000000010000010100001010,
+00000010101101000100011110000011,
+11111100000101111011011110110011,
+00001001000100111100011110011101,
+00000110000100110000010010000100,
+10000101110010100010000001000000,
+00111100001001010100010100000001,
+00001010100100110100101000000101,
+00100101100000110000001000000000,
+11000101100100010000000101001001,
+00000001100010010010011000000011,
+00000001000010010010010100000011,
+00001010000001010011010000001101,
+00010110111000110000100101000001,
+01000101000001011111111101011010,
+11001101000011010011000011010101,
+00110000110000010011100001010101,
+10111101111001010011101100001101,
+00000000000101111011011101100011,
+00000000010001000100011110000011,
+11000010001100000010011110110011,
+10110001111000111011011100000101,
+10111111000000011111001000100111,
+11111000000101111011001011100011,
+00011010000100000010011100110111,
+00000101000100110100001100011100,
+11000111101100110000001000000000,
+11000011000111001100000010000111,
+00000101000100110011101001001001,
+10110111101001010000001000010000,
+00000000000001000101100100000011,
+00011001001100110100010100001001,
+00111000011110011100010000111001,
+00100100000001010001001001100011,
+00100010000010010000111101100011,
+11111010001010010011101011100011,
+00110000011110010100010100011101,
+00100010000001010001101001100011,
+00000010100001000100011110000011,
+11111010001001111011011110110011,
+00100010000101111011010101100011,
+01000000000000000000011110010011,
+10101110001000110100010101000101,
+00111000100011010011110011110100,
+00010100000001010001101101100011,
+00000010100001000100011110000011,
+11111010001001111011011110110011,
+00100000000001111001100101100011,
+11110000111011110100010101010101,
+11100101010110011000010111111111,
+00000010100001000100011110000011,
+11000011110110011000101110010001,
+00000010101001000100011110000011,
+00000000010001000100010110000011,
+00100000000001110000011010110111,
+11111100000101111011011000110011,
+11000010001101011001010110110011,
+00100100101101000010010000100011,
+11000001110001100100011000110011,
+00100100110001000010011000100011,
+00000110011001101000011100010011,
+00100100111001000010100000100011,
+10010000000000000000011100110111,
+00100100111001000010101000100011,
+00100100101101000010010000100011,
+00100100110001000010011000100011,
+00001001100101101000011010010011,
+00100100110101000010100000100011,
+00101010001000110000011100000101,
+10010111101100110010010011100100,
+00100111001101111100001000010111,
+00000111000100110001101000010000,
+00000111100111100000101000000111,
+10000110101101111001011110111010,
+10000111001111100001110000011000,
+00100100100001101000011010010011,
+00000000110101110010001000101011,
+00000010000000000000011010010011,
+00000111101000011100001100010100,
+11000011100110000100011101010001,
+01000111100000110011000011001101,
+01000101010100010000001010000100,
+00000100000001111111011110010011,
+01000101000000111100001110011001,
+00111110111101010000001110000100,
+11110000111011110100010101011001,
+11101101000000011111110010101111,
+00111101100001001010011110000011,
+00000000000101111011100101100011,
+00000010100001000100011110000011,
+11000111100000011000101111000001,
+00001010101100000000010100010011,
+01000101011101010011010000110001,
+11111010110011111111000011101111,
+01000111100000111110110100100101,
+10110111001100110000001010010100,
+11001011000100011111110000010111,
+11000111100010011000101110001001,
+00111101100001001010011110000011,
+00000000000101111011010101100011,
+00000010110001000100010100000011,
+01000111100000110011001011100101,
+11110111000100110000001010010100,
+11001011000100010000000001000111,
+11000111100010011000101110100001,
+00111101100001001010011110000011,
+00000000000101111011010101100011,
+00000010110101000100010100000011,
+01000111100000110011001011110001,
+11110111000100110000001010010100,
+11001011000110010000000100000111,
+00000010000001111111011110010011,
+10100111100000111100011110001001,
+10110101011000110011110110000100,
+01000101000000110000000000010111,
+00110010011111010000001011100100,
+00000010100101000100011110000011,
+00000001000001111111011100010011,
+11100111101100111100111100000001,
+11010110011000110001000000000111,
+10100111100000110000000000000111,
+10110101011000110011110110000100,
+01000101000000110000000000010111,
+00110010011110010000001011110100,
+11110000111011110100010101011101,
+11101001000000011111001011101111,
+00000010100001000100011110000011,
+11000111100000011000101110100001,
+00000011000001000100010100000011,
+01000101001100010011011010101001,
+11110001100011111111000011101111,
+00001001000100111110110100000001,
+10000101110010100110010011000100,
+00010001100000000000011000010011,
+00000101100100110011001011011001,
+10000101010010100001000110000000,
+11110010010011111111000011101111,
+01000101001011010100011110000101,
+00111100111101001010101000100011,
+11101111010011111111000011101111,
+11100000000001010001100011100011,
+01100101110001000000100110010011,
+00001100101101110100101100000001,
+10001011101101110000000100000000,
+00100111100000110001110000011000,
+01100001011000110110010100000100,
+01000101001111010010011011111011,
+11101101010011111111000011101111,
+00100110101101111110010100110001,
+00000111101101110001101000010000,
+10000111000100110000000001010000,
+00000111100110010010101001000110,
+01100111101101111100001100011100,
+01010111011111010001101000010000,
+00000000010001111000011000010011,
+10000110000100111100001000011000,
+11000010000110000000000010000111,
+00000000110001111000011000010011,
+10000110000100111100001000011000,
+11000010000110000000000100000111,
+00000001010001111000011000010011,
+10000110000100111100001000011000,
+11000010000110000000000110000111,
+00000001110001111000011000010011,
+10000111100100111100001000011000,
+11000011100110000000001000000111,
+00000000000001101010000000100011,
+11110000111011110100010100110101,
+00011111111000111110100000101111,
+01000111100000111101100000000101,
+11110111100100110000000000010100,
+11000111100010010000001000000111,
+00011010000100001001011110110111,
+10000000000001111010000000100011,
+01100101010001000010011110000011,
+00011100000000000000011100110111,
+10010111100000101100001100011100,
+00111100010001011010000000000001,
+01100111100001011010000000000001,
+10111001011000111011101111110001,
+01000101010010010001110000010111,
+11100100110011111111000011101111,
+11110000111011110100010101010001,
+11100001001011011110010001101111,
+00000000010001000100011100000011,
+00011010000100000010011110110111,
+01001000000001111000011110010011,
+11000010001101110001011100110011,
+00000100111001111010100000100011,
+00000010101001000100011100000011,
+11111100000101110011011100110011,
+01000111000011011100001101011101,
+00000010111001111010100000100011,
+00000010000001111010010000100011,
+00000010101001000100011100000011,
+00000010000001110111011100010011,
+00100111000000111100101101011001,
+10100110001000110000001100010100,
+01000110100000110000001011100111,
+01000111100000110000001110010100,
+00100111001101110000001000010100,
+00000111000100110000101001100110,
+10001111010101011000000000000111,
+10001111110110010000011110111010,
+00100111001101110000011010010110,
+10001111110101010001101000010000,
+01001000000001110000011100010011,
+00000010111101110010001000100011,
+11110000111011110100010101011001,
+11100001001111011101110111101111,
+00111101100001001010011110000011,
+00000110000101111011000001100011,
+00000010100001000100011110000011,
+11001011101110011000101111000001,
+01100100100001000000100100010011,
+01010101010100000000010110010011,
+00001010101000000000010100010011,
+01100100000001000010010000100011,
+00000101100100110011001001111101,
+00000101000100110010101010100000,
+00110010010101010000010101010000,
+01010101010100000000010110010011,
+00001001000000000000010100010011,
+01000110000010010011101001101001,
+01000101000000011000010111001010,
+10000101101111111111000011101111,
+00000101000100110100010110000001,
+00110010011000010000111100000000,
+01100100101001000101011100000011,
+00000011110001000101011110000011,
+00000000111101110000101001100011,
+00111010010001010100010101010101,
+01000111000101011011111101110101,
+00000111001101111011111110110001,
+10110111101101010000000100000000,
+11110000111011110100010101010101,
+11100001000101011101011100101111,
+00000010100001000100011110000011,
+11001111100100011000101110010001,
+01010101010100000000010110010011,
+00001111000000000000010100010011,
+01000111100000110011101010001001,
+11110111100100110000001010000100,
+11000111100000010000010000000111,
+00000011100001000100010100000011,
+01000111100000110011101010101101,
+11110111100100110000001010000100,
+11000111100011010000001000000111,
+01010101010100000000010110010011,
+00001010101000000000010100010011,
+00000101100100110011001000111101,
+00000101000100110010101010100000,
+00110010000101010000010101010000,
+01010101010100000000010110010011,
+00000011100000000000010100010011,
+01100101001001010011101000101001,
+00000101000100110100010110000001,
+00111010000000011110000010110101,
+11110000111011110100010101110101,
+00010001111000111101000101101111,
+01000111100000111101111000000101,
+10110111001100110000001010010100,
+11001111000000011111110000010111,
+11000111100010011000101110001001,
+00111101100001001010011110000011,
+00000000000101111011011101100011,
+00000010110001000100010100000011,
+01010101010100000000010110010011,
+01000111100000110011000011011101,
+11110111000100110000001010010100,
+11001111000000010000000001000111,
+11000111100010011000101110100001,
+00111101100001001010011110000011,
+00000000000101111011011101100011,
+00000010110101000100010100000011,
+00101010101000000000010110010011,
+01000111100000110011000011011001,
+11110111000100110000001010010100,
+11001111000010010000000100000111,
+00000010000001111111011110010011,
+10100111100000111100011110001001,
+10110111011000110011110110000100,
+01000101000000110000000000010111,
+00000101100100110000001011100100,
+00110000010101010101010101010000,
+00000010100101000100011110000011,
+00000100000001111111011100010011,
+11010110000001110000101011100011,
+00010000000001111110011110110011,
+00000000000001111101100001100011,
+00011100000110001010011110110111,
+11010101010001111010011110000011,
+11010110000101111011000011100011,
+00000010111101000100010100000011,
+01010101010100000000010110010011,
+10111011100010010011100010101101,
+00000000000010011000010100010011,
+10110011100001010010100010110101,
+11110000111011110100010100111001,
+11100101000101011100011101101111,
+00000000010010011010101000000011,
+00000000000010011010110110000011,
+00000000100010011010101010000011,
+11100100000000000000011110110111,
+00000000111110100000110100110011,
+10100111000000110100110000000001,
+01101011011000110000000011001001,
+10100101100000110000000011101100,
+10100101000000110000000010001001,
+11110000111011110000000001001001,
+00001011000001011100011011101111,
+10110011100101010000100111000001,
+00111101110001001010100100000011,
+00000001001010101111011001100011,
+00000000001110101000100100010011,
+11000010000010010011100100110011,
+01111100011000111000011001001010,
+10000101110100100000000110011101,
+11110000111011111000010101101110,
+10011010010010101110111001001111,
+10001010101100111001110111001010,
+00001100000001010100000100101010,
+10000101100100111011111101111101,
+10000101011011100111011010001011,
+11101100111011111111000011101111,
+10000101100100111000011001001010,
+10000101010100100111011010001011,
+10110111110001010011001010000001,
+00011010000100000110011110110111,
+01000011100110000000011110100001,
+11000110000001100001000101000001,
+11000010001001101100010000100010,
+11000001100001110011011100110011,
+01000011100110001100001110011000,
+11000001101001110011011100110011,
+01000011100110001100001110011000,
+11000001101101110011011100110011,
+00100111001101111100001110011000,
+01000011000111000001101000010000,
+11000000111001111100011110110011,
+01110111001101111100001100011100,
+01000111110000010001101000010000,
+00000000111101110010100000100011,
+00100110001000110100011110011101,
+10010111101101110000000011110111,
+00000110101101110001101000010000,
+11001011110101000000001000000000,
+00000000000000100000011110110111,
+00000100011101111000011110010011,
+00000000111101110010000000100011,
+00011010000100001001011110110111,
+00000000110001111000100000010011,
+00000010000000000000011100110111,
+00000000010001111000010110010011,
+00000000100001111000011000010011,
+00110000000001000111011011110011,
+00000000000010000010100010000011,
+00000000011010001001001100010011,
+00000000000000110100100101100011,
+00000000011100111100000110011000,
+11000010000110000001000001010000,
+00110000000001101001000001110011,
+00000111110100011011011111010101,
+10010000011100111100001110011000,
+00000111100000110011000000000110,
+11011110011000110000001010110101,
+01000111100000110000000000000111,
+00100111001101110000000001000101,
+00000111000100110001101000010000,
+10010111101100110111100000000111,
+11000111101100111100001000110111,
+00101100001000111100000010000111,
+00100100101101110000001011110111,
+10000100000100110001101000010000,
+01000111101111010111100000000100,
+00000100111101000010001000100011,
+00000010000001000010011000100011,
+00001100000000000000011110010011,
+00000010111101000010011000100011,
+11110000111011110100010100001001,
+00000111100100111111011000001111,
+00100110001000110000111000000000,
+10010111101101110000001011110100,
+10000111100100110001110000011000,
+00000111001101110111011010000111,
+10100110001000110000000000000010,
+00100111000000110001111011100111,
+01000110100001010000001011000100,
+11001110100001101010011100110011,
+00000010111001000010011000100011,
+00000011101000000000011100110111,
+00000010111001000010000000100011,
+01111001000001001000011100010011,
+10000111100100111100001100011100,
+00000111000100110111100101000100,
+11000011100110000010000101000000,
+01111001100001001000010010010011,
+11000000100111000100011111000001,
+10111110101011111111000011101111,
+01000000101100100100010000100010,
+01000101000010010100010010010010,
+11110000011011110000000101000001,
+00100111101101111111000010001111,
+10000111000100110001101000010000,
+00100110100000110111100000000111,
+00001000000100110000001011000111,
+00100110101100110000010000000000,
+00100110001000111100111010001000,
+00000110101101110000001011010111,
+00100101010110110001110100000000,
+00100010001000111000011011010101,
+11000011000011000000001010100111,
+01111000010001111000011100010011,
+10000111100100111100001100010000,
+01000111010000010111100010000111,
+11110000011011111100001110011000,
+01000111100000111011101001001111,
+11110111100100110000001010110101,
+11101011100100010000010000000111,
+00011100000110001001011110110111,
+01110110100001111000011110010011,
+00001000010100100101000011111011,
+00000000000001111000000010101011,
+10000000100000100000000000000001,
+00000010101101010100011110000011,
+00000100000001111111011110010011,
+11110111101101111100101110011101,
+10100111100000110001101000010000,
+10010110101101110010111000000111,
+01000110001101110001110000011000,
+10000111001111100000011010000100,
+00000010111001010001111100100011,
+00010000000001111101011110110011,
+00100001010000000000011100010011,
+00000100111001111101011110110011,
+10000111100010010000011110001101,
+01110110100001101000011010010011,
+00000110000100110100011100000001,
+10010011011000111100101110010110,
+10000000100000100000000011100111,
+00000000110001110000010110110011,
+01000001100011000000010110001010,
+10100010001010110000011100000101,
+10110111111101010000000010110110,
+01000101000000011000011110101010,
+11111100000101011011011100110011,
+10001101001111011100001100010001,
+00010000000001111110011010110011,
+00000000000101111001011100010011,
+00001111111101110111011110010011,
+00000000000001101101011001100011,
+00000001101101110100011110010011,
+00001111111101111111011110010011,
+11111101111110011000000110000101,
+00100111100000111000000010000010,
+01000001100110000011000111100101,
+11001110001000100001000100000001,
+11000001100111001000111110111001,
+00110010001001010010011100000011,
+11001100001001100100000111011100,
+10001111101110011100101001001010,
+00100111000000111100000111011100,
+01000101100111000011001001100101,
+11000110010100101100100001001110,
+11000101100111001000111110111001,
+00110010101001010010011100000011,
+11000100010101100100010111011100,
+10001111101110011100001001011010,
+11000101110111001100000001011110,
+00110010111001010000001100010011,
+01000000111110110100111000100101,
+01000001100110000001010000011110,
+01110111110101110000001101000001,
+01110110110101111001000000000111,
+10010111101010101001001000000111,
+11000110000000111001011010101010,
+11000111100000110010000000000111,
+01110110110101110010000000000110,
+01110111010101111001000000010111,
+10010110101010101001001000010111,
+11000110100000111001011100101010,
+01000111000000110010000000000110,
+10010110010101110010000000000111,
+00010110010101111110000011000111,
+01000001110110001101100011010111,
+01110011110101111100000110010000,
+01110111110101111001000000000110,
+01110110110101111001000000000111,
+10010111101010101001001000000111,
+11001000000000111001011010101010,
+11000111100000110010000000000111,
+01110110110101110010000000000110,
+01110111010101111001000000010111,
+10010110101010101001001000010111,
+11000110100000111001011100101010,
+01000111000000110010000000000110,
+10010111110101110010000000000111,
+01110010110101111110000100000111,
+00010111110101111001001000000110,
+01000101100110001101100011010111,
+01111111010101111100000111011100,
+01110110110101111001000000010110,
+10010110101010101001000000000111,
+00100000000001101100100010000011,
+10010010000001110111011011010111,
+11001000000000111001011010101010,
+01110110110101110010000000000110,
+01110111010101111001000000010111,
+10010110101010101001001000010111,
+11000110100000111001011100101010,
+01000111000000110010000000000110,
+00011000010101110010000000000111,
+01111110110101111110000100011000,
+00011000010101111001001000010110,
+01000101110110001101100011010111,
+00000001000001011010010000100011,
+11101000011110000111111111010111,
+10010000000001110111011011010111,
+11001001000000111001011010101010,
+01110110110101110010000000000110,
+10010110101010101001001000000111,
+00100000000001101100100010000011,
+10010000000101110111011011010111,
+10010010000101110111011101010111,
+10010111001010101001011010101010,
+00100000000001101100011010000011,
+00100000000001110100011100000011,
+11100001001010001001100101010111,
+00000001111101011010010000100011,
+11011000110101110001100101010111,
+11110010100110010111100111010111,
+11000011110001111111011101010111,
+10100110001000111100000111011000,
+01110100100000110000000100110101,
+01111000100000110000000001110101,
+01110100000000110000000001010101,
+01110110100000110000000111100101,
+11111010010101110000000111010101,
+10011000110101111001000000010111,
+10011000110101111110000010011000,
+11110100110101111101100010000110,
+11110110110101111001001000010111,
+00001010101100111001001000000111,
+11001011100000110000000101000101,
+00000100001100110001000000001010,
+00001010101100110000000011010101,
+11110111110101110000000010010101,
+01000100000000111001000000000111,
+11001011000000110001000000000100,
+01111010000000110001000000001010,
+01110110100000110000000101000101,
+01110100100000110000000011010101,
+00001010101100110000000010010101,
+01110111100000110000000011110101,
+11001010100000110000000011110101,
+00010110110101110001000000001010,
+10010110110101111110000011011010,
+10010100010101111101100010010111,
+01110111110101111110000010001011,
+10010100010101111001001000011000,
+01111010010101111101100101101010,
+01110100110101111001000000001000,
+00001010101100111001000000011000,
+11001011100000110000000011110101,
+11001000101100110001000000001010,
+00001010101100110000000010001000,
+01111000010101110000000101000101,
+00000100001100111001001000001000,
+11001011000000110000000010010101,
+01000100000000110001000000001010,
+00001010101100110001000000000100,
+11001010100000110000000100000101,
+10010100010101110001000000001010,
+01110111100000111110000010001011,
+01110100100000110000000011110101,
+10010100010101110000000010010101,
+01111000000000111101100101101010,
+10001110101000010000000100000101,
+00000001010001010111010000000011,
+10010100110101111000111010110001,
+11001000101100111110000010010111,
+11000110101100110000000111111000,
+00010100110101110000000100110110,
+11001000101100111101100010001000,
+01111010010101110000000100111000,
+01111001110101111001000000001001,
+01110100010101111001001000011001,
+00001010101100111001001000001001,
+01111001010101110000000010000101,
+00000111101100111001000000011001,
+00001000001100110000000100110101,
+11000111100000110000000101000101,
+11001011000000110001000000000111,
+01001000000000110001000000001010,
+00001010101100110001000000001000,
+11001010100000110000000100100101,
+00011000010101110001000000001010,
+01000111101100111110000011111000,
+10011000010101110000000011000111,
+01110110000000111101100101101010,
+10001111101001010000000100110101,
+00000001010001010111010010000011,
+00000000100001010111010000000011,
+00000001000001111100011110110011,
+00000001001001010111100000000011,
+11100000110001001001011001010111,
+10010010101010101001001110101010,
+00010000000000101100001010000011,
+11011000100010000001011001010111,
+11001000000000111001111100101010,
+10011110101010100001000000000011,
+00010000000011110100111100000011,
+00010000000011101100111010000011,
+11100001000000101001100001010111,
+00000001111101110100011100110011,
+11011001111011101001100001010111,
+01000111001100111000111100110001,
+10100000001000110000000100000111,
+11000001110101000000000100010101,
+11000101110110001100010110011100,
+11111111000000110010011000000011,
+00000000110010001100100010110011,
+00000001000101011010000000100011,
+11111111010000110010111010000011,
+11001110101100111000011001000110,
+10100010001000110000000111010110,
+00100110100000110000000111010101,
+11001000101100111111111110000011,
+10100100001000110000000011010111,
+00100111100000110000000100010101,
+10001111101110011111111111000011,
+01110111010101111100010111011100,
+10010111001010101001000000000110,
+00100000000001110100100000000011,
+10010010000001100111011101010111,
+01000011000000111001011100101010,
+01110111010101110010000000000111,
+01110110010101111001000000010110,
+10010111001010101001001000010110,
+01000110100000111001011000101010,
+01000111000000110010000000000111,
+00010110010101110010000000000110,
+01000100011100101110000100000011,
+11011000110101110001011001010111,
+10010000000011101111011101010111,
+10010111001010101100000110010000,
+00100000000001110100011000000011,
+10010010000011101111011101010111,
+01000110100000111001011100101010,
+11110111010101110010000000000111,
+10010111001010101001000000011110,
+00100000000001110100100000000011,
+10010010000111101111011101010111,
+01000111000000111001011100101010,
+10010110010101110010000000000111,
+11110110110101111110000011000110,
+00010110010101111001001000001000,
+11000001110100001101100100000111,
+11000011000000111001011010101010,
+11110110110101110010000000000110,
+11110111010101111001000000011000,
+10010110101010101001000000001000,
+00100000000001101100100000000011,
+11110110110101111001011100101010,
+01000111000000111001001000011000,
+10010110101010100010000000000111,
+00100000000001101100011010000011,
+11100000111000110001011101010111,
+11011001000001101001011101010111,
+10010010000001111111100001010111,
+11110110110101111100010110011000,
+10011000001010101001000000000111,
+00100000000010000100001100000011,
+11111000010101111001011010101010,
+11110111110101111001000000010111,
+11000110100000111001001000010111,
+10011000001010100010000000000110,
+01001000100000111001011110101010,
+11001000000000110010000000001000,
+00010111110101110010000000000111,
+01110111010101111110000011010011,
+00010111110101111110100001110111,
+01110110110101111101100100011000,
+11110111110101111100001111000110,
+11000001110101001111001010010111,
+11000101110111001100010110011000,
+00111011111001010010100000000011,
+01000110001100110100000110010000,
+11000001100100000000000100000110,
+00111100001001010010011000000011,
+11000001110101001000111010110001,
+00111100011001010010011010000011,
+11000101100110001000111100110101,
+00111100101001010010011100000011,
+11000101110111001000111110111001,
+01001001010100100100010011100010,
+01001010001100100100100111000010,
+01001011000100100100101010100010,
+01100001000001010100101110000010,
+01110001010111011000000010000010,
+11000010101001101100010010100010,
+11011110010011101100000011001010,
+11011100010100101100011010000110,
+11011000010110101101101001010110,
+10000100001010101101011001011110,
+10001001001100101000010010101110,
+00000110011000111000100110111110,
+01000010100111000001001000001000,
+00110000000101010000111000010011,
+00101111001000110100001100101001,
+01000010110111000011000011110101,
+00110010111101010010000100100011,
+00100011001000110100011010011100,
+01000110110111000011001011110101,
+00110010111101010010010100100011,
+00110010111001010000011110010011,
+00001000000100110100000011111011,
+00000000011101101100111010000011,
+00000000000001101100010110000011,
+00000000101101101100111100000011,
+00000001110101000000011000110011,
+00100000000001100100011000000011,
+00000000010001101100100010000011,
+00000000100001101100100000000011,
+10000000001000111000110110110001,
+00000110001100110000000010110110,
+01000110000000110000000111100100,
+11001111100000110010000000000110,
+00000111110000010000000000110110,
+00000000110010001100100010110011,
+00000000111101101100011000000011,
+00000001000101101000001000100011,
+00000001111101000000001010110011,
+00000000110001000000010100110011,
+00100000000001010100010100000011,
+00000000101010000100100000110011,
+00000001000001101000010000100011,
+00100000000000101100001010000011,
+00000000110001101100010100000011,
+00000000010101010100010100110011,
+00000000101001101000011000100011,
+00000000000111100100001010001011,
+00000000010101011100010110110011,
+00000000000101101100001010000011,
+00000000101101101000000000100011,
+00000000010101011100010110110011,
+00000000010101101100001010000011,
+00000000101101101000000010100011,
+00000000010110001100100010110011,
+00000000100101101100001010000011,
+00000001000101101000001010100011,
+00000000010110000100100000110011,
+00000000110101101100001010000011,
+00000001000001101000010010100011,
+00000000010101010100010100110011,
+00000000001001101100001010000011,
+00000000101001101000011010100011,
+00000000010101011100010110110011,
+00000000011001101100001010000011,
+00000000101101101000000100100011,
+00000000101111111100010110110011,
+00000000010110001100100010110011,
+00000000101001101100001010000011,
+00000001000101101000001100100011,
+00000001000111101100100010110011,
+00000000010110000100100000110011,
+00000001000001101000010100100011,
+00000000111001101100001010000011,
+00000000101101101000000110100011,
+00000001000011110100100000110011,
+00000000010101010100010100110011,
+00000000101001101000011100100011,
+01000010100100001000110100110001,
+00000001000101101000001110100011,
+00000001000001101000010110100011,
+00000000101001101000011110100011,
+11111110110001111010100000100011,
+10101010001000110100001011010000,
+01000110100100001111111011000111,
+11111110110001111010110000100011,
+10101110001000110100011011010000,
+01001010010000011111111011000111,
+00000011010010011100101000110011,
+11001100000000100100001100011100,
+11001000001111101000101011001010,
+01001011000000010100001101011100,
+00011011100100111100101000111110,
+10000111110110100000000001001011,
+01001001011000111001101110100110,
+00001000000011000000011101001011,
+00000100000010100110101000110011,
+11001110010100101000010100100010,
+01000110010000010011110001101101,
+00000000000000000111011111010111,
+11000010001111101100000000111110,
+11000110001111101100010000111110,
+10000101100010101000011010001010,
+11000110000010011011011100110011,
+00000010110010011110011000110011,
+01000000110101011000011110110011,
+00000110110001111100010101100011,
+01000110010000100100011110000010,
+10001111101100011001011101001010,
+01000110000100101100000000111110,
+10001111101100010100011111010010,
+01000110011000101100001000111110,
+10001111101100010100011110100010,
+01000110011100101100010000111110,
+10001111101100010100011110110010,
+00000111101100111100011000111110,
+11000110011000110100000100100111,
+01000000101101100000010100110111,
+01000100100101100100010000100110,
+01011001111100100100100100000110,
+01011010110100100101101001100010,
+01011011101100100101101101000010,
+10000000100000100110000101100001,
+10000101001000100000100000001100,
+00111100100000011100111000111110,
+00001000000101000000101100000101,
+00000001000010101000011000010011,
+00000000010000111101000011111011,
+00000000010010111010011100001011,
+00000000010001101010010110001011,
+10100010001010111000111100101101,
+10001010101100100000000011101010,
+10010111101001101011011110001101,
+00000000111001111111011110000011,
+00000000111101011000000010101011,
+11000111100010111011011101100001,
+00000000101010110000000000010110,
+10110111011001010000000011110111,
+11010010001001100111000101111001,
+11001110010011101101000001001010,
+11001010010101101100110001010010,
+11000010011001101100010001100010,
+11010100001000101101011000000110,
+11000110010111101100100001011010,
+00001001100100111000010010101010,
+00001100000100110010000000000101,
+00001001000100110001000000000101,
+01001010000000010011000000000101,
+00001100100100110100101011000001,
+01110100000100110001000000000000,
+10001011101100110000111111111010,
+00001011001100110000000101000100,
+01000101100010010000000101001100,
+11110000111011111000010100100010,
+10000000101010111001101100111111,
+01000101100011010000000010101011,
+11110000111011111000010100100010,
+00000100000001011001101001111111,
+00000000101010110000000010101011,
+00001111111101000111010000010011,
+11111110100010101001000111100011,
+00001010010000010000101011000001,
+00001111111110101111101010010011,
+11111101100110100001010111100011,
+01000111000001010100011010000101,
+00010000000001110110011000110011,
+10001111001100010000011100000110,
+00010000000001110110011110110011,
+01000111011011011000011001111101,
+10001111001111011000111101110001,
+00000000000101101001011110010011,
+11100111101100111000111110110101,
+11110110100100110001000000000111,
+00000110100010100000111111110111,
+11100111101100111000111110110101,
+11110110100100110001000000000111,
+00000110100100100000111111110111,
+11100111101100111000111110110101,
+11010110000100110001000000000111,
+01000110101001010100000111110111,
+10001111101101011000111011110001,
+00001111111101111111011010010011,
+00000000011101101101011000010011,
+00000000000101101001011110010011,
+11000110000100111000111111010001,
+10001111101100010000011000110110,
+00000000011001101101010110010011,
+00000000001001101001011000010011,
+10001111101100011000111001001101,
+00000000010101101101010110010011,
+00000000001101101001011000010011,
+10001111101100011000111001001101,
+00000000010001101101010110010011,
+00000000010001101001011000010011,
+01110111000100111000111001001101,
+10001111101100010000111111110111,
+00000000111110011100011100100011,
+11111000000101110011000011100011,
+00000110001100000000011110010011,
+00100000111101001000000000100011,
+01000100100000010100010100000001,
+00000000101010110100100111111001,
+00000100100001010000000010101001,
+00000001001101001001111101100011,
+01010100001000100101000010110010,
+01011001000000100101010010010010,
+01001010011000100100100111110010,
+01001011010000100100101011010010,
+01001100001000100100101110110010,
+01100001010001010100110010010010,
+11110100000100111000000010000010,
+01000101000001010000111111110100,
+11111100000101000010101111100011,
+00010100011111010100010110001001,
+10001100000111111111000011101111,
+00001111111101000111010000010011,
+00000000000000001011111111000101,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000,
+00000000000000000000000000000000;
diff --git a/fpga/ips/xilinx_rom_bank_2048x32/tcl/run.tcl b/fpga/ips/xilinx_rom_bank_2048x32/tcl/run.tcl
new file mode 100644
index 00000000..97ac741a
--- /dev/null
+++ b/fpga/ips/xilinx_rom_bank_2048x32/tcl/run.tcl
@@ -0,0 +1,13 @@
+set partNumber $::env(XILINX_PART)
+set boardName  $::env(XILINX_BOARD)
+
+create_project xilinx_rom_bank_2048x32 . -part $partNumber
+set_property board_part $boardName [current_project]
+create_ip -name blk_mem_gen -vendor xilinx.com -library ip -module_name xilinx_rom_bank_2048x32
+set_property -dict [list CONFIG.Memory_Type {Single_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {2048} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Use_RSTA_Pin {true} ] [get_ips xilinx_rom_bank_2048x32]
+exec cp boot_code.coe xilinx_rom_bank_2048x32.srcs/sources_1/ip/boot_code.coe
+set_property -dict [list CONFIG.Load_Init_File {true} CONFIG.Coe_File {../boot_code.coe} CONFIG.Fill_Remaining_Memory_Locations {true}] [get_ips xilinx_rom_bank_2048x32]
+generate_target all [get_files ./xilinx_rom_bank_2048x32.srcs/sources_1/ip/xilinx_rom_bank_2048x32/xilinx_rom_bank_2048x32.xci]
+create_ip_run [get_files -of_objects [get_fileset sources_1] ./xilinx_rom_bank_2048x32.srcs/sources_1/ip/xilinx_rom_bank_2048x32/xilinx_rom_bank_2048x32.xci]
+launch_run -jobs 8 xilinx_rom_bank_2048x32_synth_1
+wait_on_run xilinx_rom_bank_2048x32_synth_1
diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/.gitignore b/fpga/ips/xilinx_slow_clk_mngr/.gitignore
similarity index 100%
rename from fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/.gitignore
rename to fpga/ips/xilinx_slow_clk_mngr/.gitignore
diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/Makefile b/fpga/ips/xilinx_slow_clk_mngr/Makefile
similarity index 66%
rename from fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/Makefile
rename to fpga/ips/xilinx_slow_clk_mngr/Makefile
index e3ba47bf..d1c8d65c 100644
--- a/fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/Makefile
+++ b/fpga/ips/xilinx_slow_clk_mngr/Makefile
@@ -1,27 +1,20 @@
 PROJECT:=xilinx_slow_clk_mngr
 VIVADO ?= vivado
 VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
-MODE=batch
-
-include ../../fpga-settings.mk
 
 .DEFAULT_GOAL:=help
 
-.PHONY: help all gui clean
-
-all: MODE=batch ## Create and synthesize the IP in batch mode.
-
-gui: MODE=gui  ## Create and synthesize the IP in GUI mode.
+.PHONY: help
 
-all gui: $(PROJECT).xpr
-
-$(PROJECT).xpr: ../../fpga-settings.mk tcl/run.tcl
-	make clean
-	$(VIVADO) -mode $(MODE) -source tcl/run.tcl
+all: ## Create and synthesize the IP in batch mode.
+	vivado -mode batch -source tcl/run.tcl
 	mkdir -p ip
 	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
 	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
 
+gui: ## Create and synthesize the IP in GUI mode.
+	vivado-2018.2 vivado -mode gui -source tcl/run.tcl &
+
 clean: ## Remove all build products
 	rm -rf ip/*
 	mkdir -p ip
diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/Makefile b/fpga/ips/xilinx_slow_clk_mngr/Makefile~
similarity index 66%
rename from fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/Makefile
rename to fpga/ips/xilinx_slow_clk_mngr/Makefile~
index e3ba47bf..3709d058 100644
--- a/fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/Makefile
+++ b/fpga/ips/xilinx_slow_clk_mngr/Makefile~
@@ -1,27 +1,20 @@
 PROJECT:=xilinx_slow_clk_mngr
 VIVADO ?= vivado
 VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
-MODE=batch
-
-include ../../fpga-settings.mk
 
 .DEFAULT_GOAL:=help
 
-.PHONY: help all gui clean
-
-all: MODE=batch ## Create and synthesize the IP in batch mode.
-
-gui: MODE=gui  ## Create and synthesize the IP in GUI mode.
+.PHONY: help
 
-all gui: $(PROJECT).xpr
-
-$(PROJECT).xpr: ../../fpga-settings.mk tcl/run.tcl
-	make clean
-	$(VIVADO) -mode $(MODE) -source tcl/run.tcl
+all: ## Create and synthesize the IP in batch mode.
+	$(VIVADO) -mode batch -source tcl/run.tcl
 	mkdir -p ip
 	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
 	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
 
+gui: ## Create and synthesize the IP in GUI mode.
+	$(VIVADO) -mode gui -source tcl/run.tcl &
+
 clean: ## Remove all build products
 	rm -rf ip/*
 	mkdir -p ip
diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/tcl/run.tcl b/fpga/ips/xilinx_slow_clk_mngr/tcl/run.tcl
similarity index 96%
rename from fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/tcl/run.tcl
rename to fpga/ips/xilinx_slow_clk_mngr/tcl/run.tcl
index a14c2958..891315bd 100644
--- a/fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/tcl/run.tcl
+++ b/fpga/ips/xilinx_slow_clk_mngr/tcl/run.tcl
@@ -17,7 +17,7 @@ if [info exists ::env(SLOW_CLK_PERIOD_NS)] {
     set SLOW_CLK_PERIOD_NS 30517
 }
 
-# Multiply frequency by 250 as there is a clock divider (by 250) after the
+# Multiply frequency by 256 as there is a clock divider (by 256) after the
 # slow_clk_mngr since the MMCMs do not support clocks slower then 4.69 MHz.
 set SLOW_CLK_FREQ_MHZ [expr 1000 * 256 / $SLOW_CLK_PERIOD_NS]
 
diff --git a/fpga/ips/xilinx_tcdm_bank_1024x32/Makefile b/fpga/ips/xilinx_tcdm_bank_1024x32/Makefile
new file mode 100644
index 00000000..af2eaed6
--- /dev/null
+++ b/fpga/ips/xilinx_tcdm_bank_1024x32/Makefile
@@ -0,0 +1,21 @@
+PROJECT:=xilinx_tcdm_bank_1024x32
+
+all:
+	vivado -mode batch -source tcl/run.tcl
+	mkdir -p ip
+	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
+	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
+
+gui:
+	vivado-2018.2 vivado -mode gui -source tcl/run.tcl &
+
+clean:
+	rm -rf ip/*
+	mkdir -p ip
+	rm -rf ${PROJECT}.*
+	rm -rf component.xml
+	rm -rf vivado*.jou
+	rm -rf vivado*.log
+	rm -rf vivado*.str
+	rm -rf xgui
+	rm -rf .Xil
diff --git a/fpga/ips/xilinx_tcdm_bank_1024x32/tcl/run.tcl b/fpga/ips/xilinx_tcdm_bank_1024x32/tcl/run.tcl
new file mode 100644
index 00000000..f1195f60
--- /dev/null
+++ b/fpga/ips/xilinx_tcdm_bank_1024x32/tcl/run.tcl
@@ -0,0 +1,11 @@
+set partNumber $::env(XILINX_PART)
+set boardName  $::env(XILINX_BOARD)
+
+create_project xilinx_tcdm_bank_1024x32 . -part $partNumber
+set_property board_part $boardName [current_project]
+create_ip -name blk_mem_gen -vendor xilinx.com -library ip -module_name xilinx_tcdm_bank_1024x32
+set_property -dict [list CONFIG.Memory_Type {Single_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {1024} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Use_RSTA_Pin {true}] [get_ips xilinx_tcdm_bank_1024x32]
+generate_target all [get_files ./xilinx_tcdm_bank_1024x32.srcs/sources_1/ip/xilinx_tcdm_bank_1024x32/xilinx_tcdm_bank_1024x32.xci]
+create_ip_run [get_files -of_objects [get_fileset sources_1] ./xilinx_tcdm_bank_1024x32.srcs/sources_1/ip/xilinx_tcdm_bank_1024x32/xilinx_tcdm_bank_1024x32.xci]
+launch_run -jobs 8 xilinx_tcdm_bank_1024x32_synth_1
+wait_on_run xilinx_tcdm_bank_1024x32_synth_1
diff --git a/fpga/ips/xilinx_tcdm_bank_2048x32/Makefile b/fpga/ips/xilinx_tcdm_bank_2048x32/Makefile
new file mode 100644
index 00000000..f2eca5f6
--- /dev/null
+++ b/fpga/ips/xilinx_tcdm_bank_2048x32/Makefile
@@ -0,0 +1,21 @@
+PROJECT:=xilinx_tcdm_bank_2048x32
+
+all:
+	vivado -mode batch -source tcl/run.tcl
+	mkdir -p ip
+	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
+	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
+
+gui:
+	vivado-2018.2 vivado -mode gui -source tcl/run.tcl &
+
+clean:
+	rm -rf ip/*
+	mkdir -p ip
+	rm -rf ${PROJECT}.*
+	rm -rf component.xml
+	rm -rf vivado*.jou
+	rm -rf vivado*.log
+	rm -rf vivado*.str
+	rm -rf xgui
+	rm -rf .Xil
diff --git a/fpga/ips/xilinx_tcdm_bank_2048x32/tcl/run.tcl b/fpga/ips/xilinx_tcdm_bank_2048x32/tcl/run.tcl
new file mode 100644
index 00000000..7f70ec0d
--- /dev/null
+++ b/fpga/ips/xilinx_tcdm_bank_2048x32/tcl/run.tcl
@@ -0,0 +1,11 @@
+set partNumber $::env(XILINX_PART)
+set boardName  $::env(XILINX_BOARD)
+
+create_project xilinx_tcdm_bank_2048x32 . -part $partNumber
+set_property board_part $boardName [current_project]
+create_ip -name blk_mem_gen -vendor xilinx.com -library ip -module_name xilinx_tcdm_bank_2048x32
+set_property -dict [list CONFIG.Memory_Type {Single_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {2048} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Use_RSTA_Pin {true}] [get_ips xilinx_tcdm_bank_2048x32]
+generate_target all [get_files ./xilinx_tcdm_bank_2048x32.srcs/sources_1/ip/xilinx_tcdm_bank_2048x32/xilinx_tcdm_bank_2048x32.xci]
+create_ip_run [get_files -of_objects [get_fileset sources_1] ./xilinx_tcdm_bank_2048x32.srcs/sources_1/ip/xilinx_tcdm_bank_2048x32/xilinx_tcdm_bank_2048x32.xci]
+launch_run -jobs 8 xilinx_tcdm_bank_2048x32_synth_1
+wait_on_run xilinx_tcdm_bank_2048x32_synth_1
diff --git a/fpga/pulpissimo-zcu104/openocd-zcu104-olimex-arm-usb-ocd-h.cfg b/fpga/openocd-zcu102-olimex-arm-usb-ocd-h.cfg
similarity index 100%
rename from fpga/pulpissimo-zcu104/openocd-zcu104-olimex-arm-usb-ocd-h.cfg
rename to fpga/openocd-zcu102-olimex-arm-usb-ocd-h.cfg
diff --git a/fpga/pulp_cluster/Makefile b/fpga/pulp_cluster/Makefile
new file mode 100644
index 00000000..bedd85dc
--- /dev/null
+++ b/fpga/pulp_cluster/Makefile
@@ -0,0 +1,20 @@
+PROJECT:=pulp_cluster
+
+all:
+	vivado-2018.2 vivado -mode batch -source tcl/run.tcl
+
+gui:
+	vivado -mode gui -source tcl/run.tcl &
+
+clean:
+	rm -rf ${PROJECT}.xpr
+	rm -rf ${PROJECT}.data
+	rm -rf ${PROJECT}.runs
+	rm -rf ${PROJECT}.srcs
+	rm -rf ${PROJECT}.cache
+	rm -rf ${PROJECT}.hw
+	rm -rf component.xml
+	rm -rf vivado*
+	rm -rf .Xil
+	rm -rf xgui
+
diff --git a/fpga/pulp_cluster/postsynth_names.py b/fpga/pulp_cluster/postsynth_names.py
new file mode 100755
index 00000000..17f8719d
--- /dev/null
+++ b/fpga/pulp_cluster/postsynth_names.py
@@ -0,0 +1,28 @@
+#!/usr/bin/env python
+import sys
+
+with open("pulp_cluster_funcsim.v", "rb") as f:
+    f_s = f.readlines()
+
+with open("pulp_cluster_funcsim.v", "rb") as f:
+    f_str = f.read()
+
+module_list = []
+
+for line in f_s:
+    lsplit = line.split()
+    try:
+        if lsplit[0] == "module" and lsplit[1] != "pulp_cluster":
+            module_list.append(lsplit[1])
+    except IndexError:
+        continue
+
+print "Replacing postsynthesis names"
+for mod in module_list:
+    # print "   %s" % mod
+    f_str = f_str.replace("%s "  % mod, "pulp_cluster_postsynth_%s "  % mod)
+    f_str = f_str.replace("%s\n" % mod, "pulp_cluster_postsynth_%s\n" % mod)
+
+with open("pulp_cluster_postsynt.v", "wb") as f:
+    f.write(f_str)
+
diff --git a/fpga/pulp_cluster/tcl/.gitignore b/fpga/pulp_cluster/tcl/.gitignore
new file mode 100644
index 00000000..fda3137b
--- /dev/null
+++ b/fpga/pulp_cluster/tcl/.gitignore
@@ -0,0 +1,3 @@
+*_add_files.tcl
+*_inc_dirs.tcl
+*_src_files.tcl
\ No newline at end of file
diff --git a/fpga/pulp_cluster/tcl/constraints.xdc b/fpga/pulp_cluster/tcl/constraints.xdc
new file mode 100644
index 00000000..7736ac9c
--- /dev/null
+++ b/fpga/pulp_cluster/tcl/constraints.xdc
@@ -0,0 +1,11 @@
+## Boundary
+set_input_delay 0.5    [all_inputs]
+# set_load        0.1    [all_outputs] # only post-synthesis
+
+create_clock -period 10 -name clk_i [get_ports clk_i]
+
+set_false_path -from [all_inputs]
+set_false_path -to   [all_outputs]
+
+set_false_path -through [get_pins rstgen_i/s_rst_n_reg/Q]
+set_false_path -from [get_clocks tck_i] -to [get_clocks clk_i]
diff --git a/fpga/pulp_cluster/tcl/create_path_groups.xdc b/fpga/pulp_cluster/tcl/create_path_groups.xdc
new file mode 100644
index 00000000..6daaa496
--- /dev/null
+++ b/fpga/pulp_cluster/tcl/create_path_groups.xdc
@@ -0,0 +1,5 @@
+group_path -name CORE_DATA_REQ -weight 2.000 -through [list [get_nets CORE*core_region_i/*_CORE/data_addr_o*] [get_nets CORE*core_region_i/*_CORE/data_wdata_o*] [get_nets CORE*core_region_i/*_CORE/data_we_o*] [get_nets CORE*core_region_i/*_CORE/data_req_o*] [get_nets CORE*core_region_i/*_CORE/data_be_o*] [get_nets CORE*core_region_i/*_CORE/data_gnt_i*]]
+group_path -name CORE_DATA_RESP -weight 2.000 -through [list [get_nets CORE*core_region_i/*_CORE/data_rdata_i*] [get_nets CORE*core_region_i/*_CORE/data_rvalid_i*]]
+group_path -name CORE_INSTR_REQ -weight 2.000 -through [list [get_nets CORE*core_region_i/*_CORE/instr_addr_o*] [get_nets CORE*core_region_i/*_CORE/instr_req_o*] [get_nets CORE*core_region_i/*_CORE/instr_gnt_i*]]
+group_path -name CORE_INSTR_RESP -weight 2.000 -through [list [get_nets CORE*core_region_i/*_CORE/instr_rdata_i*] [get_nets CORE*core_region_i/*_CORE/instr_rvalid_i*]]
+group_path -name CORE_R2R -weight 2.000 -from [filter [all_registers ] {name =~ CORE*core_region_i*}] -to [filter [all_registers ] {name =~ CORE*core_region_i*}]
diff --git a/fpga/pulp_cluster/tcl/run.tcl b/fpga/pulp_cluster/tcl/run.tcl
new file mode 100644
index 00000000..25f11113
--- /dev/null
+++ b/fpga/pulp_cluster/tcl/run.tcl
@@ -0,0 +1,64 @@
+# create project
+create_project pulp_cluster . -force -part $::env(XILINX_PART)
+set_property board_part $::env(XILINX_BOARD) [current_project]
+
+# set up includes
+source tcl/ips_inc_dirs.tcl
+source tcl/rtl_inc_dirs.tcl
+set_property include_dirs $INCLUDE_DIRS [current_fileset]
+
+# set up meaningful errors
+source ../common/messages.tcl
+
+# setup source files
+source tcl/ips_src_files.tcl
+source tcl/rtl_src_files.tcl
+
+# add IPs
+source tcl/ips_add_files.tcl
+source tcl/rtl_add_files.tcl
+
+add_files -norecurse -scan_for_includes  $IPS/pulp_soc/rtl/components/pulp_interfaces.sv
+
+# add memory cuts + FPU IPs
+read_ip $FPGA_IPS/xilinx_tcdm_bank_1024x32/ip/xilinx_tcdm_bank_1024x32.xci
+read_ip $FPGA_IPS/xilinx_tcdm_bank_2048x32/ip/xilinx_tcdm_bank_2048x32.xci
+
+# set pulp_cluster as top
+set_property top pulp_cluster [current_fileset]
+
+# needed only if used in batch mode
+update_compile_order -fileset sources_1
+update_compile_order -fileset sim_1
+
+# add constraints
+add_files -fileset constrs_1 -norecurse tcl/constraints.xdc
+set_property target_constrs_file tcl/constraints.xdc [current_fileset -constrset]
+# create path groups
+add_files -fileset constrs_1 -norecurse tcl/create_path_groups.xdc
+set_property target_constrs_file tcl/create_path_groups.xdc [current_fileset -constrset]
+
+# run synthesis
+# first try will fail
+catch {synth_design -rtl -name rtl_1 -verilog_define PULP_FPGA_EMUL=1 -verilog_define PERF_COUNTERS=1 -verilog_define RISCV=1 -gated_clock_conversion on -constrset constrs_1}
+update_compile_order -fileset sources_1
+synth_design -rtl -name rtl_1 -verilog_define PULP_FPGA_EMUL=1 -verilog_define PERF_COUNTERS=1 -verilog_define RISCV=1 -gated_clock_conversion on -constrset constrs_1
+
+set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY none [get_runs synth_1]
+
+launch_runs synth_1 -jobs 28
+wait_on_run synth_1
+open_run synth_1
+
+# save EDIF netlist
+write_edif -force pulp_cluster.edf
+write_verilog -force -mode synth_stub pulp_cluster_stub.v
+write_verilog -force -mode funcsim pulp_cluster_funcsim.v
+
+# reports
+exec mkdir -p reports/
+exec rm -rf reports/*
+check_timing                                                            -file reports/pulp_cluster.check_timing.rpt
+report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/pulp_cluster.timing_WORST_100.rpt
+report_timing -nworst 1 -delay_type max -sort_by group                  -file reports/pulp_cluster.timing.rpt
+report_utilization -hierarchical                                        -file reports/pulp_cluster.utilization.rpt
diff --git a/fpga/pulpemu/.gitignore b/fpga/pulpemu/.gitignore
new file mode 100644
index 00000000..ab76b8ed
--- /dev/null
+++ b/fpga/pulpemu/.gitignore
@@ -0,0 +1,2 @@
+!/gap-emu-*.bin
+save
\ No newline at end of file
diff --git a/fpga/pulpemu/Makefile b/fpga/pulpemu/Makefile
new file mode 100644
index 00000000..03908747
--- /dev/null
+++ b/fpga/pulpemu/Makefile
@@ -0,0 +1,86 @@
+PROJECT:=pulpemu
+PROBES?=0
+
+all: ${BOARD}
+
+vcu118: synth bootgen_vcu
+
+zcu102: synth bootgen_zynq_mp
+
+zc706: synth bootgen_zynq
+
+synth:
+	vivado-2018.2 vivado -mode batch -source tcl/run.tcl
+
+impl:
+	rm -rf .Xil
+	vivado-2018.2 vivado -mode batch -source tcl/impl.tcl
+	cp ${PROJECT}.runs/impl_1/${PROJECT}.bit .
+	cp ${PROJECT}.runs/impl_1/*.dcp .
+
+gui:
+	vivado-2018.2 vivado -mode gui -source tcl/setup_impl.tcl &
+
+gui-synth:
+	vivado-2018.2 vivado -mode gui -source tcl/run.tcl &
+
+gui-impl:
+	vivado-2018.2 vivado -mode gui -source tcl/impl.tcl &
+
+bootgen_zynq_mp:
+	cp ${PROJECT}.runs/impl_1/${PROJECT}.bit board/${BOARD}/${PROJECT}.bit
+	bootgen -image board/${BOARD}/output.bif -arch zynqmp -o board/${BOARD}/BOOT.bin -w on
+	cp board/${BOARD}/BOOT.bin "board/${BOARD}/`./board/get-bitstream-name.sh`"
+
+bootgen_zynq:
+	cp ${PROJECT}.runs/impl_1/${PROJECT}.bit board/${BOARD}/${PROJECT}.bit
+	bootgen -image board/${BOARD}/output.bif -arch zynq -o board/${BOARD}/BOOT.bin -w on
+	cp board/${BOARD}/BOOT.bin "board/${BOARD}/`./board/get-bitstream-name.sh`"
+
+bootgen_vcu:
+	cp ${PROJECT}.runs/impl_1/${PROJECT}.bit board/${BOARD}/${PROJECT}.bit
+	vivado-2018.2 vivado -mode tcl -source board/${BOARD}/bit_to_mcs.tcl
+	cp board/${BOARD}/${PROJECT}.mcs "board/${BOARD}/`./board/get-bitstream-name.sh`"
+
+program_fpga_vcu:
+	vivado-2018.2 vivado -mode tcl -source board/${BOARD}/program_fpga.tcl
+
+program_spi_vcu:
+	bash board/${BOARD}/guide.sh
+	vivado-2018.2 vivado -mode tcl -source board/${BOARD}/program_spi.tcl
+
+qspiflash:
+	program_flash -f board/BOOT.bin -offset 0 -flash_type \
+	qspi_dual_parallel -fsbl board/${BOARD}/fsbl.elf \
+	-cable type xilinx_tcf url TCP:127.0.0.1:3121
+
+continue:
+	vivado-2018.2 vivado -mode gui ${PROJECT}.xpr
+
+clean-impl:
+	rm -rf ${PROJECT}.runs/impl_1
+
+clean:
+	rm -rf ${PROJECT}.hw
+	rm -rf ${PROJECT}.xpr
+	rm -rf ${PROJECT}.data
+	rm -rf ${PROJECT}.runs
+	rm -rf ${PROJECT}.srcs
+	rm -rf ps7_*
+	rm -rf ${PROJECT}.sim
+	rm -rf ${PROJECT}.sdk
+	rm -rf ${PROJECT}.cache
+	rm -rf ${PROJECT}.ioplanning
+	rm -rf ${PROJECT}.hwdef
+	rm -rf *.log
+	rm -rf ulpsoc.txt
+	rm -rf pulp_cluster.txt
+	rm -rf component.xml
+	rm -rf vivado*
+	rm -rf xgui
+	rm -rf .Xil
+	rm -rf ps_clock*
+	rm -rf ${PROJECT}*
+	rm -rf ${PROJECT}.edf
+	rm -rf board/BOOT.bin
+	rm -rf board/${PROJECT}.bit
diff --git a/fpga/pulpemu/bitstream.bif b/fpga/pulpemu/bitstream.bif
new file mode 100644
index 00000000..56387e45
--- /dev/null
+++ b/fpga/pulpemu/bitstream.bif
@@ -0,0 +1,5 @@
+bitstream : {
+[bootloader]../board/fsbl.elf
+pulpemu.bit
+../board/u-boot.elf
+}
diff --git a/fpga/pulpemu/board/get-bitstream-name.sh b/fpga/pulpemu/board/get-bitstream-name.sh
new file mode 100755
index 00000000..596bf2b4
--- /dev/null
+++ b/fpga/pulpemu/board/get-bitstream-name.sh
@@ -0,0 +1,11 @@
+#!/bin/bash
+tag=$(git describe --abbrev=0 --tags --exact-match 2> /dev/null)
+if [ $? != 0 ]; then
+  commit_hash=`git rev-parse --short HEAD`
+  branch_name=`git rev-parse --abbrev-ref HEAD`
+  name=emu-${branch_name}-${commit_hash}.bit.bin
+else
+  name=emu-${tag}.bit.bin
+fi
+echo $name
+
diff --git a/fpga/pulpemu/board/vcu118/bit_to_mcs.tcl b/fpga/pulpemu/board/vcu118/bit_to_mcs.tcl
new file mode 100644
index 00000000..9a4d44e1
--- /dev/null
+++ b/fpga/pulpemu/board/vcu118/bit_to_mcs.tcl
@@ -0,0 +1,2 @@
+write_cfgmem -force -format mcs -size 256 -interface SPIx8 -loadbit {up 0x00000000 "./board/vcu118/pulpemu.bit" } -file "./board/vcu118/pulpemu.mcs"
+exit
diff --git a/fpga/pulpemu/board/vcu118/guide.sh b/fpga/pulpemu/board/vcu118/guide.sh
new file mode 100644
index 00000000..f914ab68
--- /dev/null
+++ b/fpga/pulpemu/board/vcu118/guide.sh
@@ -0,0 +1,5 @@
+#!/bin/bash
+
+read -p "Before flashing QSPI : Set SW16 to <0101> (1 = on, Position 1 to Position 4). y / n ? " known
+read -p "After   flashed QSPI : Set SW16 to <0001> (1 = on, Position 1 to Position 4). y / n ? " known
+read -p "If you have any questions, please see <../docs/xtp445-vcu118-restoring-flash-c-2018-2.pdf> for help. y / n ? " known
diff --git a/fpga/pulpemu/board/vcu118/program_fpga.tcl b/fpga/pulpemu/board/vcu118/program_fpga.tcl
new file mode 100644
index 00000000..2821140d
--- /dev/null
+++ b/fpga/pulpemu/board/vcu118/program_fpga.tcl
@@ -0,0 +1,13 @@
+open_hw
+
+connect_hw_server  -url localhost:3121
+
+open_hw_target
+current_hw_device [get_hw_devices xcvu9p_0]
+set_property PROGRAM.FILE {./board/vcu118/pulpemu.bit} [get_hw_devices xcvu9p_0]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xcvu9p_0] 0]
+create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4_x8}] 0]
+set_property FULL_PROBES.FILE {} [get_hw_devices xcvu9p_0]
+program_hw_devices [get_hw_devices xcvu9p_0]
+refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0]
+exit
diff --git a/fpga/pulpemu/board/vcu118/program_spi.tcl b/fpga/pulpemu/board/vcu118/program_spi.tcl
new file mode 100644
index 00000000..7400acf0
--- /dev/null
+++ b/fpga/pulpemu/board/vcu118/program_spi.tcl
@@ -0,0 +1,30 @@
+set_param xicom.use_bitstream_version_check false
+open_hw
+catch {disconnect_hw_server localhost:3121}
+connect_hw_server -url localhost:3121
+current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
+set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/*]
+open_hw_target
+current_hw_device [lindex [get_hw_devices xcvu9p_0] 0]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xcvu9p_0] 0]
+create_hw_cfgmem -hw_device [lindex [get_hw_devices] 0] -mem_dev  [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4_x8}] 0]
+set_property PROGRAM.BLANK_CHECK  0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
+set_property PROGRAM.ERASE  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
+set_property PROGRAM.CFG_PROGRAM  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
+set_property PROGRAM.VERIFY  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
+set_property PROGRAM.CHECKSUM  0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
+refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0]
+set_property PROGRAM.ADDRESS_RANGE  {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
+set_property PROGRAM.FILES [list "./board/vcu118/pulpemu_primary.mcs" "./board/vcu118/pulpemu_secondary.mcs" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0]]
+set_property PROGRAM.PRM_FILES [list "./board/vcu118/pulpemu_primary.prm" "./board/vcu118/pulpemu_secondary.prm" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0]]
+set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
+set_property PROGRAM.BLANK_CHECK  0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
+set_property PROGRAM.ERASE  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
+set_property PROGRAM.CFG_PROGRAM  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
+set_property PROGRAM.VERIFY  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
+set_property PROGRAM.CHECKSUM  0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
+if {![string equal [get_property PROGRAM.HW_CFGMEM_TYPE  [lindex [get_hw_devices] 0]] [get_property MEM_TYPE [get_property CFGMEM_PART [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]]]] }  { create_hw_bitstream -hw_device [lindex [get_hw_devices] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices] 0]]; program_hw_devices [lindex [get_hw_devices] 0]; }; 
+program_hw_cfgmem -hw_cfgmem [get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices] 0 ]]
+close_hw_target [current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]]
+disconnect_hw_server localhost:3121
+close_hw
diff --git a/fpga/pulpemu/board/zc706/fsbl.elf b/fpga/pulpemu/board/zc706/fsbl.elf
new file mode 100755
index 00000000..1a551adc
Binary files /dev/null and b/fpga/pulpemu/board/zc706/fsbl.elf differ
diff --git a/fpga/pulpemu/board/zc706/output.bif b/fpga/pulpemu/board/zc706/output.bif
new file mode 100644
index 00000000..7e495ab0
--- /dev/null
+++ b/fpga/pulpemu/board/zc706/output.bif
@@ -0,0 +1,6 @@
+//arch = zynq; split = false; format = BIN
+the_ROM_image:
+{
+	[bootloader]board/zc706/fsbl.elf
+	board/zc706/pulpemu.bit
+}
\ No newline at end of file
diff --git a/fpga/pulpemu/board/zcu102/fsbl.elf b/fpga/pulpemu/board/zcu102/fsbl.elf
new file mode 100755
index 00000000..5a327b70
Binary files /dev/null and b/fpga/pulpemu/board/zcu102/fsbl.elf differ
diff --git a/fpga/pulpemu/board/zcu102/output.bif b/fpga/pulpemu/board/zcu102/output.bif
new file mode 100644
index 00000000..51d45d80
--- /dev/null
+++ b/fpga/pulpemu/board/zcu102/output.bif
@@ -0,0 +1,7 @@
+//arch = zynqmp; split = false; format = BIN
+the_ROM_image:
+{
+	[fsbl_config]a53_x64
+	[bootloader]board/zcu102/fsbl.elf
+	[destination_device = pl]board/zcu102/pulpemu.bit
+}
\ No newline at end of file
diff --git a/fpga/pulpemu/get-bitstream-name.sh b/fpga/pulpemu/get-bitstream-name.sh
new file mode 100755
index 00000000..e48b60ce
--- /dev/null
+++ b/fpga/pulpemu/get-bitstream-name.sh
@@ -0,0 +1,11 @@
+#!/bin/bash
+tag=$(git describe --abbrev=0 --tags --exact-match 2> /dev/null)
+if [ $? != 0 ]; then
+  commit_hash=`git rev-parse --short HEAD`
+  branch_name=`git rev-parse --abbrev-ref HEAD`
+  name=vega-emu-${branch_name}-${commit_hash}.bit.bin
+else
+  name=vega-emu-${tag}.bit.bin
+fi
+echo $name
+
diff --git a/fpga/pulpemu/scripts/gen_probes_ltx.py b/fpga/pulpemu/scripts/gen_probes_ltx.py
new file mode 100644
index 00000000..8327e2e6
--- /dev/null
+++ b/fpga/pulpemu/scripts/gen_probes_ltx.py
@@ -0,0 +1,37 @@
+import yaml
+
+yaml_file = "probes.yaml"
+with open(yaml_file, "r") as f:
+    yaml_stream = f.read()
+yaml_dic = {'dic' : yaml.load(yaml_stream), 'key' : 'yaml_dic'}
+ilas = yaml_dic['dic']['ilas']
+
+print """<?xml version="1.0" encoding="UTF-8"?>
+<probeData version="1" minor="1">
+  <probeset name="EDA_PROBESET" active="true">
+"""
+for k,ila in enumerate(ilas):
+  for i,probe in enumerate(ila['probes']):
+    print """    <!-- %s %s -->
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="COMPARE_VALUE.0" value="eq%d&apos;hX"/>
+        <Option Id="CORE_LOCATION" value="1:%d"/>
+        <Option Id="HW_ILA" value="%s"/>
+        <Option Id="PROBE_PORT" value="%d"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="%d"/>
+      </probeOptions>
+      <nets>""" % (ila['int_name'], probe['name'], probe['bits'], k, ila['name'], i, probe['bits'])
+    if probe['bits']==1:
+      print """        <net name="%s/%s"/>""" % (ila['int_name'], probe['name'])
+    else:
+      for j in xrange(probe['bits']-1,-1,-1):
+        print """        <net name="%s/%s[%d]"/>""" % (ila['int_name'], probe['name'], j)
+    print """      </nets>
+    </probe>
+"""
+
+print """  </probeset>
+</probeData>
+"""
diff --git a/fpga/pulpemu/scripts/probes.yaml b/fpga/pulpemu/scripts/probes.yaml
new file mode 100644
index 00000000..89940433
--- /dev/null
+++ b/fpga/pulpemu/scripts/probes.yaml
@@ -0,0 +1,656 @@
+#
+# Probes to generate probe LTX file
+# 
+ilas:
+  - core: "1:0"
+    name: "ulpsoc_i/l2_ila_i"
+    int_name: "l2"
+    probes:
+       - name: int_csn
+         bits: 1
+       - name: int_wen
+         bits: 1
+       - name: int_ben
+         bits: 8
+       - name: int_add
+         bits: 32
+       - name: int_wdata
+         bits: 64
+       - name: int_rdata
+         bits: 64
+       - name: ext_en
+         bits: 1
+       - name: ext_we
+         bits: 8
+       - name: ext_addr
+         bits: 15
+       - name: ext_din
+         bits: 64
+       - name: ext_dout
+         bits: 64
+       - name: spy_timer
+         bits: 16
+  - core: "1:1"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/CORE[0].core_region_i/or1200_top_i/or1200_cpu/core_ila_i"
+    int_name: "core0"
+    probes:
+       - name: fetch_en_i
+         bits: 1
+       - name: if_pc
+         bits: 32
+       - name: if_insn
+         bits: 32
+       - name: id_insn
+         bits: 32
+       - name: ex_insn
+         bits: 32
+       - name: wb_insn
+         bits: 32
+       - name: except_flushpipe 
+         bits: 1
+       - name: except_start     
+         bits: 1
+       - name: except_started   
+         bits: 1
+       - name: except_align     
+         bits: 1
+       - name: except_dtlbmiss  
+         bits: 1
+       - name: except_dmmufault 
+         bits: 1
+       - name: except_illegal   
+         bits: 1
+       - name: except_itlbmiss  
+         bits: 1
+       - name: except_immufault 
+         bits: 1
+       - name: except_ibuserr   
+         bits: 1
+       - name: except_dbuserr   
+         bits: 1
+       - name: dcpu_adr_o       
+         bits: 32
+       - name: dcpu_dat_o       
+         bits: 32
+       - name: dcpu_dat_i       
+         bits: 32
+       - name: dcpu_ack_i       
+         bits: 1
+       - name: rf_dataw
+         bits: 32
+       - name: rf_datawa
+         bits: 32
+       - name: rf_datawb
+         bits: 32
+       - name: rf_datawc
+         bits: 32
+       - name: rf_dataa
+         bits: 32
+       - name: rf_datab
+         bits: 32
+       - name: spy_timer        
+         bits: 16
+  - core: "1:2"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/CORE[0].core_region_i/or1200_top_i/icache_ila_i"
+    int_name: "icache0"
+    probes:
+       - name: ic_en
+         bits: 1
+       - name: icqmem_adr_qmem
+         bits: 32
+       - name: icqmem_sel_qmem
+         bits: 4
+       - name: icqmem_tag_qmem
+         bits: 4
+       - name: icqmem_dat_ic
+         bits: 32
+       - name: icqmem_ack_ic
+         bits: 1
+       - name: icbiu_adr_ic
+         bits: 32
+       - name: icbiu_dat_biu
+         bits: 64
+       - name: icbiu_ack_biu
+         bits: 1
+       - name: spy_timer
+         bits: 16
+  - core: "1:3"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/CORE[1].core_region_i/or1200_top_i/or1200_cpu/core_ila_i"
+    int_name: "core1"
+    probes:
+       - name: fetch_en_i
+         bits: 1
+       - name: if_pc
+         bits: 32
+       - name: if_insn
+         bits: 32
+       - name: id_insn
+         bits: 32
+       - name: ex_insn
+         bits: 32
+       - name: wb_insn
+         bits: 32
+       - name: except_flushpipe 
+         bits: 1
+       - name: except_start     
+         bits: 1
+       - name: except_started   
+         bits: 1
+       - name: except_align     
+         bits: 1
+       - name: except_dtlbmiss  
+         bits: 1
+       - name: except_dmmufault 
+         bits: 1
+       - name: except_illegal   
+         bits: 1
+       - name: except_itlbmiss  
+         bits: 1
+       - name: except_immufault 
+         bits: 1
+       - name: except_ibuserr   
+         bits: 1
+       - name: except_dbuserr   
+         bits: 1
+       - name: dcpu_adr_o       
+         bits: 32
+       - name: dcpu_dat_o       
+         bits: 32
+       - name: dcpu_dat_i       
+         bits: 32
+       - name: dcpu_ack_i       
+         bits: 1
+       - name: rf_dataw
+         bits: 32
+       - name: rf_datawa
+         bits: 32
+       - name: rf_datawb
+         bits: 32
+       - name: rf_datawc
+         bits: 32
+       - name: rf_dataa
+         bits: 32
+       - name: rf_datab
+         bits: 32
+       - name: spy_timer        
+         bits: 16
+  - core: "1:4"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/CORE[1].core_region_i/or1200_top_i/icache_ila_i"
+    int_name: "icache1"
+    probes:
+       - name: ic_en
+         bits: 1
+       - name: icqmem_adr_qmem
+         bits: 32
+       - name: icqmem_sel_qmem
+         bits: 4
+       - name: icqmem_tag_qmem
+         bits: 4
+       - name: icqmem_dat_ic
+         bits: 32
+       - name: icqmem_ack_ic
+         bits: 1
+       - name: icbiu_adr_ic
+         bits: 32
+       - name: icbiu_dat_biu
+         bits: 64
+       - name: icbiu_ack_biu
+         bits: 1
+       - name: spy_timer
+         bits: 16
+  - core: "1:5"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/CORE[2].core_region_i/or1200_top_i/or1200_cpu/core_ila_i"
+    int_name: "core2"
+    probes:
+       - name: fetch_en_i
+         bits: 1
+       - name: if_pc
+         bits: 32
+       - name: if_insn
+         bits: 32
+       - name: id_insn
+         bits: 32
+       - name: ex_insn
+         bits: 32
+       - name: wb_insn
+         bits: 32
+       - name: except_flushpipe 
+         bits: 1
+       - name: except_start     
+         bits: 1
+       - name: except_started   
+         bits: 1
+       - name: except_align     
+         bits: 1
+       - name: except_dtlbmiss  
+         bits: 1
+       - name: except_dmmufault 
+         bits: 1
+       - name: except_illegal   
+         bits: 1
+       - name: except_itlbmiss  
+         bits: 1
+       - name: except_immufault 
+         bits: 1
+       - name: except_ibuserr   
+         bits: 1
+       - name: except_dbuserr   
+         bits: 1
+       - name: dcpu_adr_o       
+         bits: 32
+       - name: dcpu_dat_o       
+         bits: 32
+       - name: dcpu_dat_i       
+         bits: 32
+       - name: dcpu_ack_i       
+         bits: 1
+       - name: rf_dataw
+         bits: 32
+       - name: rf_datawa
+         bits: 32
+       - name: rf_datawb
+         bits: 32
+       - name: rf_datawc
+         bits: 32
+       - name: rf_dataa
+         bits: 32
+       - name: rf_datab
+         bits: 32
+       - name: spy_timer        
+         bits: 16
+  - core: "1:6"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/CORE[2].core_region_i/or1200_top_i/icache_ila_i"
+    int_name: "icache2"
+    probes:
+       - name: ic_en
+         bits: 1
+       - name: icqmem_adr_qmem
+         bits: 32
+       - name: icqmem_sel_qmem
+         bits: 4
+       - name: icqmem_tag_qmem
+         bits: 4
+       - name: icqmem_dat_ic
+         bits: 32
+       - name: icqmem_ack_ic
+         bits: 1
+       - name: icbiu_adr_ic
+         bits: 32
+       - name: icbiu_dat_biu
+         bits: 64
+       - name: icbiu_ack_biu
+         bits: 1
+       - name: spy_timer
+         bits: 16
+  - core: "1:7"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/CORE[3].core_region_i/or1200_top_i/or1200_cpu/core_ila_i"
+    int_name: "core3"
+    probes:
+       - name: fetch_en_i
+         bits: 1
+       - name: if_pc
+         bits: 32
+       - name: if_insn
+         bits: 32
+       - name: id_insn
+         bits: 32
+       - name: ex_insn
+         bits: 32
+       - name: wb_insn
+         bits: 32
+       - name: except_flushpipe 
+         bits: 1
+       - name: except_start     
+         bits: 1
+       - name: except_started   
+         bits: 1
+       - name: except_align     
+         bits: 1
+       - name: except_dtlbmiss  
+         bits: 1
+       - name: except_dmmufault 
+         bits: 1
+       - name: except_illegal   
+         bits: 1
+       - name: except_itlbmiss  
+         bits: 1
+       - name: except_immufault 
+         bits: 1
+       - name: except_ibuserr   
+         bits: 1
+       - name: except_dbuserr   
+         bits: 1
+       - name: dcpu_adr_o       
+         bits: 32
+       - name: dcpu_dat_o       
+         bits: 32
+       - name: dcpu_dat_i       
+         bits: 32
+       - name: dcpu_ack_i       
+         bits: 1
+       - name: rf_dataw
+         bits: 32
+       - name: rf_datawa
+         bits: 32
+       - name: rf_datawb
+         bits: 32
+       - name: rf_datawc
+         bits: 32
+       - name: rf_dataa
+         bits: 32
+       - name: rf_datab
+         bits: 32
+       - name: spy_timer        
+         bits: 16
+  - core: "1:8"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/CORE[3].core_region_i/or1200_top_i/icache_ila_i"
+    int_name: "icache3"
+    probes:
+       - name: ic_en
+         bits: 1
+       - name: icqmem_adr_qmem
+         bits: 32
+       - name: icqmem_sel_qmem
+         bits: 4
+       - name: icqmem_tag_qmem
+         bits: 4
+       - name: icqmem_dat_ic
+         bits: 32
+       - name: icqmem_ack_ic
+         bits: 1
+       - name: icbiu_adr_ic
+         bits: 32
+       - name: icbiu_dat_biu
+         bits: 64
+       - name: icbiu_ack_biu
+         bits: 1
+       - name: spy_timer
+         bits: 16
+  - core: "1:9"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/tcdm_sram_7_ila_i"
+    int_name: "sram7"
+    probes:
+       - name: csn
+         bits: 1
+       - name: wen
+         bits: 1
+       - name: wmn
+         bits: 32
+       - name: add
+         bits: 8
+       - name: wdata
+         bits: 32
+       - name: rdata
+         bits: 32
+       - name: spy_timer        
+         bits: 16
+  - core: "1:10"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/tcdm_sram_6_ila_i"
+    int_name: "sram6"
+    probes:
+       - name: csn
+         bits: 1
+       - name: wen
+         bits: 1
+       - name: wmn
+         bits: 32
+       - name: add
+         bits: 8
+       - name: wdata
+         bits: 32
+       - name: rdata
+         bits: 32
+       - name: spy_timer        
+         bits: 16
+  - core: "1:11"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/tcdm_sram_5_ila_i"
+    int_name: "sram5"
+    probes:
+       - name: csn
+         bits: 1
+       - name: wen
+         bits: 1
+       - name: wmn
+         bits: 32
+       - name: add
+         bits: 8
+       - name: wdata
+         bits: 32
+       - name: rdata
+         bits: 32
+       - name: spy_timer        
+         bits: 16
+  - core: "1:12"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/tcdm_sram_4_ila_i"
+    int_name: "sram4"
+    probes:
+       - name: csn
+         bits: 1
+       - name: wen
+         bits: 1
+       - name: wmn
+         bits: 32
+       - name: add
+         bits: 8
+       - name: wdata
+         bits: 32
+       - name: rdata
+         bits: 32
+       - name: spy_timer        
+         bits: 16
+  - core: "1:13"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/tcdm_sram_3_ila_i"
+    int_name: "sram3"
+    probes:
+       - name: csn
+         bits: 1
+       - name: wen
+         bits: 1
+       - name: wmn
+         bits: 32
+       - name: add
+         bits: 8
+       - name: wdata
+         bits: 32
+       - name: rdata
+         bits: 32
+       - name: spy_timer        
+         bits: 16
+  - core: "1:14"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/tcdm_sram_2_ila_i"
+    int_name: "sram2"
+    probes:
+       - name: csn
+         bits: 1
+       - name: wen
+         bits: 1
+       - name: wmn
+         bits: 32
+       - name: add
+         bits: 8
+       - name: wdata
+         bits: 32
+       - name: rdata
+         bits: 32
+       - name: spy_timer        
+         bits: 16
+  - core: "1:15"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/tcdm_sram_1_ila_i"
+    int_name: "sram1"
+    probes:
+       - name: csn
+         bits: 1
+       - name: wen
+         bits: 1
+       - name: wmn
+         bits: 32
+       - name: add
+         bits: 8
+       - name: wdata
+         bits: 32
+       - name: rdata
+         bits: 32
+       - name: spy_timer        
+         bits: 16
+  - core: "1:16"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/tcdm_sram_0_ila_i"
+    int_name: "sram0"
+    probes:
+       - name: csn
+         bits: 1
+       - name: wen
+         bits: 1
+       - name: wmn
+         bits: 32
+       - name: add
+         bits: 8
+       - name: wdata
+         bits: 32
+       - name: rdata
+         bits: 32
+       - name: spy_timer        
+         bits: 16
+  - core: "1:17"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/tcdm_scm_7_ila_i"
+    int_name: "scm7"
+    probes:
+       - name: ren
+         bits: 1
+       - name: wen
+         bits: 1
+       - name: ben
+         bits: 4
+       - name: add
+         bits: 7
+       - name: wdata
+         bits: 32
+       - name: rdata
+         bits: 32
+       - name: spy_timer
+         bits: 16
+  - core: "1:18"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/tcdm_scm_6_ila_i"
+    int_name: "scm6"
+    probes:
+       - name: ren
+         bits: 1
+       - name: wen
+         bits: 1
+       - name: ben
+         bits: 4
+       - name: add
+         bits: 7
+       - name: wdata
+         bits: 32
+       - name: rdata
+         bits: 32
+       - name: spy_timer
+         bits: 16
+  - core: "1:19"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/tcdm_scm_5_ila_i"
+    int_name: "scm5"
+    probes:
+       - name: ren
+         bits: 1
+       - name: wen
+         bits: 1
+       - name: ben
+         bits: 4
+       - name: add
+         bits: 7
+       - name: wdata
+         bits: 32
+       - name: rdata
+         bits: 32
+       - name: spy_timer
+         bits: 16
+  - core: "1:20"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/tcdm_scm_4_ila_i"
+    int_name: "scm4"
+    probes:
+       - name: ren
+         bits: 1
+       - name: wen
+         bits: 1
+       - name: ben
+         bits: 4
+       - name: add
+         bits: 7
+       - name: wdata
+         bits: 32
+       - name: rdata
+         bits: 32
+       - name: spy_timer
+         bits: 16
+  - core: "1:21"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/tcdm_scm_3_ila_i"
+    int_name: "scm3"
+    probes:
+       - name: ren
+         bits: 1
+       - name: wen
+         bits: 1
+       - name: ben
+         bits: 4
+       - name: add
+         bits: 7
+       - name: wdata
+         bits: 32
+       - name: rdata
+         bits: 32
+       - name: spy_timer
+         bits: 16
+  - core: "1:22"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/tcdm_scm_2_ila_i"
+    int_name: "scm2"
+    probes:
+       - name: ren
+         bits: 1
+       - name: wen
+         bits: 1
+       - name: ben
+         bits: 4
+       - name: add
+         bits: 7
+       - name: wdata
+         bits: 32
+       - name: rdata
+         bits: 32
+       - name: spy_timer
+         bits: 16
+  - core: "1:23"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/tcdm_scm_1_ila_i"
+    int_name: "scm1"
+    probes:
+       - name: ren
+         bits: 1
+       - name: wen
+         bits: 1
+       - name: ben
+         bits: 4
+       - name: add
+         bits: 7
+       - name: wdata
+         bits: 32
+       - name: rdata
+         bits: 32
+       - name: spy_timer
+         bits: 16
+  - core: "1:24"
+    name: "ulpsoc_i/cluster_i/ulpcluster_i/tcdm_scm_0_ila_i"
+    int_name: "scm0"
+    probes:
+       - name: ren
+         bits: 1
+       - name: wen
+         bits: 1
+       - name: ben
+         bits: 4
+       - name: add
+         bits: 7
+       - name: wdata
+         bits: 32
+       - name: rdata
+         bits: 32
+       - name: spy_timer
+         bits: 16
diff --git a/fpga/pulpemu/tcl/.gitignore b/fpga/pulpemu/tcl/.gitignore
new file mode 100644
index 00000000..fda3137b
--- /dev/null
+++ b/fpga/pulpemu/tcl/.gitignore
@@ -0,0 +1,3 @@
+*_add_files.tcl
+*_inc_dirs.tcl
+*_src_files.tcl
\ No newline at end of file
diff --git a/fpga/pulpemu/tcl/constraints.xdc b/fpga/pulpemu/tcl/constraints.xdc
new file mode 100644
index 00000000..8a96160d
--- /dev/null
+++ b/fpga/pulpemu/tcl/constraints.xdc
@@ -0,0 +1,58 @@
+#######################################
+#  _______ _           _              #
+# |__   __(_)         (_)             #
+#    | |   _ _ __ ___  _ _ __   __ _  #
+#    | |  | | '_ ` _ \| | '_ \ / _` | #
+#    | |  | | | | | | | | | | | (_| | #
+#    |_|  |_|_| |_| |_|_|_| |_|\__, | #
+#                               __/ | #
+#                              |___/  #
+#######################################
+
+
+#Create constraint for the clock input of the zcu102 board
+create_clock -period 8.000 -name ref_clk [get_ports ref_clk_p]
+set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets ref_clk]
+
+#I2S and CAM interface are not used in this FPGA port. Set constraints to
+#disable the clock
+set_case_analysis 0 i_pulpissimo/safe_domain_i/cam_pclk_o
+set_case_analysis 0 i_pulpissimo/safe_domain_i/i2s_slave_sck_o
+#set_input_jitter tck 1.000
+
+## JTAG
+create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_jtag_tck]
+set_input_jitter tck 1.000
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_jtag_tck_IBUF_inst/O]
+
+
+# minimize routing delay
+set_input_delay -clock tck -clock_fall 5.000 [get_ports pad_jtag_tdi]
+set_input_delay -clock tck -clock_fall 5.000 [get_ports pad_jtag_tms]
+set_output_delay -clock tck 5.000 [get_ports pad_jtag_tdo]
+
+set_max_delay -to   [get_ports pad_jtag_tdo] 20.000
+set_max_delay -from [get_ports pad_jtag_tms] 20.000
+set_max_delay -from [get_ports pad_jtag_tdi] 20.000
+
+set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000
+set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000
+set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000
+
+
+# reset signal
+set_false_path -from [get_ports pad_reset]
+
+# Set ASYNC_REG attribute for ff synchronizers to place them closer together and
+# increase MTBF
+set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/apb_adv_timer_i/u_tim0/u_in_stage/r_ls_clk_sync_reg*]
+set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/apb_adv_timer_i/u_tim1/u_in_stage/r_ls_clk_sync_reg*]
+set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/apb_adv_timer_i/u_tim2/u_in_stage/r_ls_clk_sync_reg*]
+set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/apb_adv_timer_i/u_tim3/u_in_stage/r_ls_clk_sync_reg*]
+set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*]
+set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*]
+set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*]
+
+# Create asynchronous clock group between slow-clk and SoC clock. Those clocks
+# are considered asynchronously and proper synchronization regs are in place
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/safe_domain_i/i_slow_clk_gen/slow_clk_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fpga_clk_gen/soc_clk_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fpga_clk_gen/cluster_clk_o]]
diff --git a/fpga/pulpemu/tcl/debug.tcl b/fpga/pulpemu/tcl/debug.tcl
new file mode 100644
index 00000000..a033ae46
--- /dev/null
+++ b/fpga/pulpemu/tcl/debug.tcl
@@ -0,0 +1,96 @@
+set_property mark_debug true [get_nets [list {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[28]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[1]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[47]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[33]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[62]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[1]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[13]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[42]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[27]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[56]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[9]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[16]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[6]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[6]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[35]} ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_ready {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[21]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[50]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[15]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[9]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[5]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[30]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[15]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[44]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[4]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[23]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[23]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[52]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[0]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[39]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[18]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[48]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[32]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[61]} ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_valid {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[11]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[21]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[40]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[27]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[56]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[11]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[7]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[7]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[36]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[4]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[20]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[0]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[29]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[29]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[58]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[15]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[44]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[15]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[24]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[53]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[38]} ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_valid {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[27]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[17]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[46]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[32]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[61]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[17]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[12]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[41]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[26]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[55]} ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_ready {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[8]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[15]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[5]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[34]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[63]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[4]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[20]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[14]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[7]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[2]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[59]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[14]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[43]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[3]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[22]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[22]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[51]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[9]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[38]} ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_b_valid {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[1]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[47]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[31]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[60]} ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_ready {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[6]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[25]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[25]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[54]} ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_ready ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_b_ready {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[11]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[40]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[11]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[4]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[20]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[34]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[63]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[23]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[13]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[42]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[29]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[58]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[13]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[9]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[38]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[22]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[51]} ulpsoc_i/soc_bus_wrap_i/soc_l2_master_b_valid {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[11]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[30]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[5]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[30]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[17]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[46]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[10]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[4]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[26]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[55]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[3]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[10]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[29]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[18]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[48]} ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_valid {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[34]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[63]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[18]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[14]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[43]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[28]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[57]} ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_ready {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[17]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[7]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[7]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[36]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[22]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[51]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[3]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[31]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[60]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[16]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[45]} ulpsoc_i/soc_bus_wrap_i/soc_l2_master_b_ready {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[5]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[24]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[24]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[53]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[3]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[10]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[10]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[19]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[49]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[33]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[62]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[22]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[12]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[41]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[28]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[57]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[12]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[9]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[8]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[37]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[21]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[50]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[10]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[2]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[2]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[59]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[16]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[45]} ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_ready {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[3]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[25]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[54]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[0]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[39]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[13]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[3]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[32]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[61]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[18]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[48]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[12]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[8]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[28]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[57]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[12]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[41]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[30]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[20]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[4]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[20]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[7]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[36]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[16]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[45]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[2]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[59]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[18]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[9]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[9]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[38]} ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_valid {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[24]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[53]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[5]} ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_valid {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[33]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[62]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[1]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[47]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[7]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[26]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[26]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[55]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[12]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[41]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[12]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[21]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[50]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[35]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[24]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[14]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[43]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[2]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[59]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[14]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[0]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[39]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[23]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[52]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[12]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[31]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[31]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[60]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[1]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[47]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[11]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[5]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[27]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[56]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[11]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[40]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[2]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[19]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[19]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[49]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[6]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[35]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[15]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[44]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[29]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[58]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[1]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[8]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[8]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[37]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[23]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[52]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[4]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[32]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[61]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[17]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[46]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[20]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[10]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[3]} ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_ready {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[26]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[55]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[10]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[6]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[6]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[35]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[19]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[49]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[9]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[28]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[28]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[57]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[14]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[43]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[14]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[23]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[52]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[37]} ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_valid {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[26]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[16]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[45]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[31]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[60]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[16]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[11]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[40]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[25]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[54]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[7]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[14]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[4]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[33]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[62]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[19]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[49]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[13]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[6]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[29]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[58]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[13]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[42]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[31]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[21]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[21]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[50]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[8]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[37]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[17]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[46]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[5]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[30]} ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_ready {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[19]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[0]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[39]} ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_last {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[25]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[54]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[0]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[8]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[34]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[63]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[18]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[48]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[8]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[27]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[27]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[56]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[13]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[42]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[13]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[22]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[51]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[36]} ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_valid {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[15]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[25]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[44]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[5]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[30]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[15]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[3]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[10]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[24]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[53]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[6]}]]
+create_debug_core u_ila_0 ila
+set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 6 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list ps7_wrapper_i/ps7_i/ps7_clk ]]
+set_property port_width 13 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[3]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[4]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[5]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[6]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[7]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[8]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[9]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[10]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[11]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[12]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[13]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[14]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_addr[15]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[0]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[1]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[2]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[3]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[4]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[5]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[6]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[7]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[8]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[9]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[10]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[11]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[12]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[13]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[14]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[15]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[16]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[17]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[18]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[19]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[20]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[21]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[22]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[23]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[24]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[25]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[26]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[27]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[28]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[29]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[30]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[31]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[32]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[33]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[34]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[35]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[36]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[37]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[38]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[39]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[40]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[41]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[42]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[43]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[44]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[45]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[46]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[47]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[48]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[49]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[50]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[51]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[52]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[53]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[54]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[55]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[56]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[57]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[58]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[59]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[60]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[61]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[62]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_data[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[0]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[1]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[2]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[3]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[4]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[5]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[6]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[7]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[8]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[9]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[10]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[11]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[12]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[13]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[14]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[15]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[16]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[17]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[18]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[19]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[20]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[21]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[22]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[23]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[24]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[25]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[26]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[27]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[28]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[29]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[30]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[31]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[32]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[33]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[34]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[35]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[36]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[37]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[38]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[39]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[40]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[41]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[42]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[43]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[44]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[45]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[46]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[47]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[48]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[49]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[50]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[51]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[52]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[53]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[54]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[55]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[56]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[57]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[58]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[59]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[60]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[61]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[62]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_data[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[0]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[1]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[2]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[3]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[4]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[5]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[6]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[7]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[8]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[9]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[10]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[11]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[12]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[13]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[14]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[15]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[16]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[17]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[18]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[19]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[20]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[21]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[22]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[23]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[24]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[25]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[26]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[27]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[28]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[29]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[30]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_addr[31]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[0]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[1]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[2]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[3]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[4]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[5]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[6]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[7]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[8]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[9]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[10]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[11]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[12]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[13]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[14]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[15]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[16]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[17]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[18]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[19]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[20]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[21]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[22]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[23]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[24]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[25]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[26]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[27]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[28]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[29]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[30]} {ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_addr[31]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[0]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[1]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[2]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[3]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[4]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[5]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[6]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[7]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[8]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[9]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[10]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[11]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[12]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[13]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[14]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[15]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[16]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[17]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[18]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[19]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[20]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[21]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[22]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[23]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[24]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[25]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[26]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[27]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[28]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[29]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[30]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[31]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[32]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[33]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[34]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[35]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[36]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[37]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[38]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[39]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[40]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[41]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[42]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[43]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[44]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[45]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[46]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[47]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[48]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[49]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[50]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[51]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[52]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[53]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[54]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[55]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[56]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[57]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[58]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[59]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[60]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[61]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[62]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_data[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[0]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[1]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[2]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[3]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[4]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[5]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[6]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[7]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[8]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[9]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[10]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[11]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[12]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[13]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[14]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[15]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[16]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[17]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[18]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[19]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[20]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[21]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[22]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[23]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[24]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[25]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[26]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[27]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[28]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[29]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[30]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[31]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[32]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[33]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[34]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[35]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[36]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[37]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[38]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[39]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[40]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[41]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[42]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[43]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[44]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[45]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[46]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[47]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[48]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[49]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[50]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[51]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[52]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[53]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[54]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[55]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[56]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[57]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[58]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[59]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[60]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[61]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[62]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_data[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 13 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[3]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[4]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[5]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[6]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[7]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[8]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[9]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[10]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[11]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[12]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[13]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[14]} {ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_addr[15]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_ready ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_ar_valid ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_ready ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_aw_valid ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_b_ready ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_b_valid ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_ready ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_r_valid ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_last ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list ulpsoc_i/soc_bus_wrap_i/cluster_instr_slave_w_ready ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_ready ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list ulpsoc_i/soc_bus_wrap_i/soc_l2_master_ar_valid ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_ready ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list ulpsoc_i/soc_bus_wrap_i/soc_l2_master_aw_valid ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list ulpsoc_i/soc_bus_wrap_i/soc_l2_master_b_ready ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list ulpsoc_i/soc_bus_wrap_i/soc_l2_master_b_valid ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_ready ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe25]
+connect_debug_port u_ila_0/probe25 [get_nets [list ulpsoc_i/soc_bus_wrap_i/soc_l2_master_r_valid ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe26]
+connect_debug_port u_ila_0/probe26 [get_nets [list ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_ready ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe27]
+connect_debug_port u_ila_0/probe27 [get_nets [list ulpsoc_i/soc_bus_wrap_i/soc_l2_master_w_valid ]]
+
diff --git a/fpga/pulpemu/tcl/false_paths.tcl b/fpga/pulpemu/tcl/false_paths.tcl
new file mode 100644
index 00000000..e483856d
--- /dev/null
+++ b/fpga/pulpemu/tcl/false_paths.tcl
@@ -0,0 +1,11 @@
+set_false_path -from [get_pins {ulpsoc_i/cluster_i/ulpcluster_i/cluster_int_region_i/cluster_peripherals_i/cluster_control_unit_i/r_fetch_en_reg[*]/C}]
+set_false_path -from [get_pins ulpsoc_i/cluster_i/ulpcluster_i/rstgen_i/s_rst_n_reg/C]
+set_false_path -from [get_pins ulpsoc_i/i_clk_rst_gen/i_rst_gen_soc/s_rst_n_reg/C]
+set_false_path -through [get_nets {ulpsoc_i/i_clk_rst_gen/rstn_cluster_sync_o}]
+set_false_path -through [get_nets {ulpsoc_i/i_clk_rst_gen/rstn_sync_o}]
+#set_false_path -from [get_clocks {ref_clk_i}] -to [get_clocks {ulpsoc_clk}]
+#set_false_path -from [get_clocks {ulpsoc_clk}] -to [get_clocks {ref_clk_i}]
+#set_false_path -from [get_clocks {spi_clk}] -to [get_clocks {ulpsoc_clk}]
+#set_false_path -from [get_clocks {ulpsoc_clk}] -to [get_clocks {spi_clk}]
+#set_false_path -from [get_clocks {ref_clk_i}] -to [get_clocks {spi_clk}]
+#set_false_path -from [get_clocks {spi_clk}] -to [get_clocks {ref_clk_i}]
diff --git a/fpga/pulpemu/tcl/floorplan.xdc b/fpga/pulpemu/tcl/floorplan.xdc
new file mode 100644
index 00000000..124ba594
--- /dev/null
+++ b/fpga/pulpemu/tcl/floorplan.xdc
@@ -0,0 +1,6 @@
+create_pblock pblock_cluster_i
+add_cells_to_pblock [get_pblocks pblock_cluster_i] [get_cells -quiet [list ulpsoc_i/cluster_i]]
+resize_pblock [get_pblocks pblock_cluster_i] -add {SLICE_X32Y62:SLICE_X143Y274}
+resize_pblock [get_pblocks pblock_cluster_i] -add {DSP48_X2Y26:DSP48_X5Y109}
+resize_pblock [get_pblocks pblock_cluster_i] -add {RAMB18_X3Y26:RAMB18_X6Y109}
+resize_pblock [get_pblocks pblock_cluster_i] -add {RAMB36_X3Y13:RAMB36_X6Y54}
diff --git a/fpga/pulpemu/tcl/fmc_board.ucf b/fpga/pulpemu/tcl/fmc_board.ucf
new file mode 100644
index 00000000..2a480718
--- /dev/null
+++ b/fpga/pulpemu/tcl/fmc_board.ucf
@@ -0,0 +1,73 @@
+
+NET  FMC_MSPI_SCK              LOC = AD16 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L18P_T2_10
+NET  FMC_MSPI_SDIO03           LOC = AJ16 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L4P_T0_10
+NET  FMC_MSPI_SDIO02           LOC = AA15 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L20P_T3_10
+NET  FMC_MSPI_SDIO01           LOC = AK16 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L4N_T0_10
+NET  FMC_MSPI_SDIO00           LOC = AA14 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L20N_T3_10
+NET  FMC_MSPI_NCS0             LOC = AH28 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L19P_T3_12
+NET  FMC_MSPI_NCS1             LOC = AF30 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L16P_T2_12
+NET  FMC_MSPI_NCS2             LOC = AG30 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L16N_T2_12
+
+NET  FMC_SSPI_SCK              LOC = AE13 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L11P_T1_SRCC_10
+NET  FMC_SSPI_NCS              LOC = AF13 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L11N_T1_SRCC_10
+NET  FMC_SSPI_SDIO03           LOC = AE12 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L7P_T1_10
+NET  FMC_SSPI_SDIO02           LOC = AF12 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L7N_T1_10
+NET  FMC_SSPI_SDIO01           LOC = AJ15 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L5P_T0_10
+NET  FMC_SSPI_SDIO00           LOC = AK15 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L5N_T0_10
+
+NET  FMC_SENS_INT0             LOC = AB15 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L22P_T3_10
+NET  FMC_SENS_INT1             LOC = AB14 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L22N_T3_10
+NET  FMC_SENS_INT2             LOC = AH26 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L23P_T3_12
+
+NET  FMC_I2S_SCK0              LOC = AG29 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L15N_T2_DQS_12
+NET  FMC_I2S_SDI0              LOC = AE25 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L18P_T2_12
+NET  FMC_I2S_SDI1              LOC = AD25 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L10P_T1_12
+NET  FMC_I2S_SDI2              LOC = AF25 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L18N_T2_12
+NET  FMC_I2S_SDI3              LOC = AE26 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L10N_T1_12
+
+NET  FMC_I2C_SCL               LOC = Y30  | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L1P_T0_12
+NET  FMC_I2C_SDA               LOC = AA30 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L1N_T0_12
+
+NET  FMC_ADC_SDI0              LOC = AD29 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L9N_T1_DQS_12
+NET  FMC_ADC_SDI1              LOC = AB29 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L2P_T0_12
+NET  FMC_ADC_SDI2              LOC = AB30 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L2N_T0_12
+NET  FMC_ADC_SDI3              LOC = Y26  | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L3P_T0_DQS_12
+NET  FMC_ADC_SCK               LOC = Y27  | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L3N_T0_DQS_12
+NET  FMC_ADC_NCS               LOC = AH27 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L23N_T3_12
+
+NET  FMC_GPIO0                 LOC = AF15 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L14P_T2_SRCC_10
+NET  FMC_GPIO1                 LOC = AG15 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L14N_T2_SRCC_10
+NET  FMC_GPIO2                 LOC = AB12 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L21P_T3_DQS_10
+NET  FMC_GPIO3                 LOC = AC12 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L21N_T3_DQS_10
+NET  FMC_GPIO4                 LOC = AD13 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L9N_T1_DQS_10
+NET  FMC_GPIO5                 LOC = AD14 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L9P_T1_DQS_10
+NET  FMC_GPIO6                 LOC = AH12 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L10N_T1_10
+NET  FMC_GPIO7                 LOC = AG12 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L10P_T1_10
+
+NET  FMC_LOOP0_O               LOC = AE18 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L17P_T2_10
+NET  FMC_LOOP0_I               LOC = AE17 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L17N_T2_10
+NET  FMC_LOOP1_O               LOC = AG26 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L17P_T2_12
+NET  FMC_LOOP1_I               LOC = AG27 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L17N_T2_12
+NET  FMC_LOOP2_O               LOC = AK27 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L22P_T3_12
+NET  FMC_LOOP2_I               LOC = AK28 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L22N_T3_12
+NET  FMC_LOOP3_O               LOC = AE16 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L16P_T2_10
+NET  FMC_LOOP3_I               LOC = AE15 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L16N_T2_10
+NET  FMC_LOOP4_O               LOC = AH14 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L8P_T1_10
+NET  FMC_LOOP4_I               LOC = AH13 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L8N_T1_10
+
+NET  FMC_CAM_PCLK              LOC = AB27 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L11P_T1_SRCC_12
+NET  FMC_CAM_HREF              LOC = AC27 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L11N_T1_SRCC_12
+NET  FMC_CAM_VSYNC             LOC = AF17 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L15N_T2_DQS_10
+NET  FMC_CAM_D0                LOC = AK26 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L24N_T3_12
+NET  FMC_CAM_D1                LOC = AJ26 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L24P_T3_12
+NET  FMC_CAM_D2                LOC = AE27 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L14P_T2_SRCC_12
+NET  FMC_CAM_D3                LOC = AJ30 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L20P_T3_12
+NET  FMC_CAM_D4                LOC = AF27 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L14N_T2_SRCC_12
+NET  FMC_CAM_D5                LOC = AK30 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L20N_T3_12
+NET  FMC_CAM_D6                LOC = AH16 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L6N_T0_VREF_10
+NET  FMC_CAM_D7                LOC = AJ29 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L21N_T3_DQS_12
+NET  FMC_CAM_SCK               LOC = AC14 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L19P_T3_10
+NET  FMC_CAM_MOSI              LOC = AC13 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L19N_T3_VREF_10
+NET  FMC_CAM_MISO              LOC = AF18 | IOSTANDARD=LVCMOS25; # Bank  10 VCCO - VADJ_FPGA - IO_L15P_T2_DQS_10
+NET  FMC_CAM_NCS               LOC = AJ28 | IOSTANDARD=LVCMOS25; # Bank  12 VCCO - VADJ_FPGA - IO_L21P_T3_DQS_12
+
diff --git a/fpga/pulpemu/tcl/fmc_board_vcu118.xdc b/fpga/pulpemu/tcl/fmc_board_vcu118.xdc
new file mode 100644
index 00000000..895d79d7
--- /dev/null
+++ b/fpga/pulpemu/tcl/fmc_board_vcu118.xdc
@@ -0,0 +1,174 @@
+#############################################################
+#  _____ ____         _____      _   _   _                  #
+# |_   _/ __ \       / ____|    | | | | (_)                 #
+#   | || |  | |_____| (___   ___| |_| |_ _ _ __   __ _ ___  #
+#   | || |  | |______\___ \ / _ \ __| __| | '_ \ / _` / __| #
+#  _| || |__| |      ____) |  __/ |_| |_| | | | | (_| \__ \ #
+# |_____\____/      |_____/ \___|\__|\__|_|_| |_|\__, |___/ #
+#                                                 __/ |     #
+#                                                |___/      #
+#############################################################
+
+## Sys clock (ok)
+set_property -dict {PACKAGE_PIN AY23 IOSTANDARD LVDS} [get_ports ref_clk_n]
+set_property -dict {PACKAGE_PIN AY24 IOSTANDARD LVDS} [get_ports ref_clk_p]
+
+## Reset (ok)
+set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS12} [get_ports pad_reset]
+
+## Buttons (ok)
+#set_property -dict {PACKAGE_PIN BF22 IOSTANDARD LVCMOS18} [get_ports btn0_i]
+#set_property -dict {PACKAGE_PIN BD23 IOSTANDARD LVCMOS18} [get_ports btn1_i]
+#set_property -dict {PACKAGE_PIN BE23 IOSTANDARD LVCMOS18} [get_ports btn2_i]
+#set_property -dict {PACKAGE_PIN BB24 IOSTANDARD LVCMOS18} [get_ports btn3_i]
+
+## PMOD 0 (J52 on Virtex) (ok)
+## PMOD 0   --- JTAG
+######################################################################
+# JTAG mapping (OK)
+######################################################################
+set_property -dict {PACKAGE_PIN AY14 IOSTANDARD LVCMOS18} [get_ports pad_jtag_tms]
+set_property -dict {PACKAGE_PIN AY15 IOSTANDARD LVCMOS18} [get_ports pad_jtag_tdi]
+set_property -dict {PACKAGE_PIN AW15 IOSTANDARD LVCMOS18} [get_ports pad_jtag_tdo]
+set_property -dict {PACKAGE_PIN AV15 IOSTANDARD LVCMOS18} [get_ports pad_jtag_tck]
+set_property -dict {PACKAGE_PIN AV16 IOSTANDARD LVCMOS18} [get_ports pad_jtag_trst]
+
+
+#set_property -dict {PACKAGE_PIN AV16 IOSTANDARD LVCMOS18} [get_ports pad_pmod0_4]
+#set_property -dict {PACKAGE_PIN AU16 IOSTANDARD LVCMOS18} [get_ports pad_pmod0_5]
+#set_property -dict {PACKAGE_PIN AT15 IOSTANDARD LVCMOS18} [get_ports pad_pmod0_6]
+#set_property -dict {PACKAGE_PIN AT16 IOSTANDARD LVCMOS18} [get_ports pad_pmod0_7]
+
+## PMOD 1 (ok)
+#set_property -dict {PACKAGE_PIN N28  IOSTANDARD LVCMOS12} [get_ports pad_pmod1_0]
+#set_property -dict {PACKAGE_PIN M30  IOSTANDARD LVCMOS12} [get_ports pad_pmod1_1]
+#set_property -dict {PACKAGE_PIN N30  IOSTANDARD LVCMOS12} [get_ports pad_pmod1_2]
+#set_property -dict {PACKAGE_PIN P30  IOSTANDARD LVCMOS12} [get_ports pad_pmod1_3]
+#set_property -dict {PACKAGE_PIN P29  IOSTANDARD LVCMOS12} [get_ports pad_pmod1_4]
+#set_property -dict {PACKAGE_PIN L31  IOSTANDARD LVCMOS12} [get_ports pad_pmod1_5]
+#set_property -dict {PACKAGE_PIN M31  IOSTANDARD LVCMOS12} [get_ports pad_pmod1_6]
+#set_property -dict {PACKAGE_PIN R29  IOSTANDARD LVCMOS12} [get_ports pad_pmod1_7]
+
+## UART (ok)
+######################################################################
+# UART mapping
+######################################################################
+set_property -dict {PACKAGE_PIN AW25  IOSTANDARD LVCMOS18} [get_ports pad_uart_rx]
+set_property -dict {PACKAGE_PIN BB21  IOSTANDARD LVCMOS18} [get_ports pad_uart_tx]
+
+#set_property -dict {PACKAGE_PIN BB22  IOSTANDARD LVCMOS18} [get_ports pad_uart_rts]
+#set_property -dict {PACKAGE_PIN AY25  IOSTANDARD LVCMOS18} [get_ports pad_uart_cts]
+
+## LEDs (ok)
+#set_property -dict {PACKAGE_PIN AT32 IOSTANDARD LVCMOS12} [get_ports led0_o]
+#set_property -dict {PACKAGE_PIN AV34 IOSTANDARD LVCMOS12} [get_ports led1_o]
+#set_property -dict {PACKAGE_PIN AY30 IOSTANDARD LVCMOS12} [get_ports led2_o]
+#set_property -dict {PACKAGE_PIN BB32 IOSTANDARD LVCMOS12} [get_ports led3_o]
+
+## Switches (ok)
+#set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS12} [get_ports switch0_i]
+#set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS12} [get_ports switch1_i]
+#set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS12} [get_ports switch2_i]
+#set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS12} [get_ports switch3_i]
+
+## I2C Bus
+#set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports pad_i2c0_scl]
+#set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS33} [get_ports pad_i2c0_sda]
+
+## HDMI CTL
+#set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports pad_hdmi_scl]
+#set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports pad_hdmi_sda]
+
+
+######################################################################
+# QSPI mapping (OK)
+######################################################################
+# PULP pad_qspi_sdio0 - FPGA BD11 - FMC  H8  
+set_property -dict "PACKAGE_PIN BD11 IOSTANDARD LVCMOS18"   [get_ports FMC_qspi_sdio0]
+# PULP pad_qspi_sdio1 - FPGA BC13 - FMC G16
+set_property -dict "PACKAGE_PIN BC13 IOSTANDARD LVCMOS18"   [get_ports FMC_qspi_sdio1]
+# PULP pad_qspi_sdio2 - FPGA BF12 - FMC H10
+set_property -dict "PACKAGE_PIN BF12 IOSTANDARD LVCMOS18"  [get_ports FMC_qspi_sdio2]
+# PULP pad_qspi_sdio3 - FPGA AY9 - FMC G6
+set_property -dict "PACKAGE_PIN AY9 IOSTANDARD LVCMOS18"   [get_ports FMC_qspi_sdio3]
+# PULP pad_qspi_csn0 - FPGA BB16 - FMC H19
+set_property -dict "PACKAGE_PIN BB16 IOSTANDARD LVCMOS18"  [get_ports FMC_qspi_csn0]
+# PULP pad_qspi_sck - FPGA BC14 - FMC G15
+set_property -dict "PACKAGE_PIN BC14 IOSTANDARD LVCMOS18"   [get_ports FMC_qspi_sck]
+# GAP pad_spim0_sck - FPGA BC11 - FMC H7
+set_property -dict "PACKAGE_PIN BC11 IOSTANDARD LVCMOS18"   [get_ports FMC_qspi_csn1]
+
+######################################################################
+# SDIO mapping (TO CHECK)
+######################################################################
+# PULP pad_sdio_sdio0 - FPGA N28 - ZCU102 GPIO PMOD HEADER J53.1
+set_property -dict "PACKAGE_PIN N28 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_data0]
+# PULP pad_sdio_sdio1 - FPGA M30 - ZCU102 GPIO PMOD HEADER J53.3
+set_property -dict "PACKAGE_PIN M30 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_data1]
+# PULP pad_sdio_sdio2 - FPGA N30 - ZCU102 GPIO PMOD HEADER J53.5
+set_property -dict "PACKAGE_PIN N30 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_data2]
+# PULP pad_sdio_sdio3 - FPGA P30 - ZCU102 GPIO PMOD HEADER J53.7
+set_property -dict "PACKAGE_PIN P30 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_data3]
+# PULP pad_sdio_cmd - FPGA P29 - ZCU102 GPIO PMOD HEADER J53.2
+set_property -dict "PACKAGE_PIN P29 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_cmd]
+# PULP pad_sdio_sck - FPGA L31 - ZCU102 GPIO PMOD HEADER J53.4
+set_property -dict "PACKAGE_PIN L31 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_sck]
+
+######################################################################
+# I2S master mapping (OK)
+######################################################################
+# PULP pad_i2s_mst_sck - FPGA AR13 - FMC H29
+set_property -dict "PACKAGE_PIN AR13 IOSTANDARD LVCMOS18" [get_ports FMC_i2s0_sck]
+# PULP pad_i2s_mst_ws - FPGA AW8 - FMC C18
+set_property -dict "PACKAGE_PIN AW8 IOSTANDARD LVCMOS18" [get_ports FMC_i2s0_ws]
+# PULP pad_i2s_slv_sdi0 - FPGA BB7 - FMC D1 -- not mappable --mapped into H2 (dummy)
+set_property -dict "PACKAGE_PIN BB7 IOSTANDARD LVCMOS18" [get_ports FMC_i2s0_sdi]
+# PULP pad_i2s_slv_sdi1 - FPGA BD13 - FMC C10
+set_property -dict "PACKAGE_PIN BD13 IOSTANDARD LVCMOS18" [get_ports FMC_i2s1_sdi]
+
+######################################################################
+# I2C0 mapping (OK)
+######################################################################
+# PULP pad_i3c2_scl - FPGA AJ12 - FMC H38
+set_property -dict "PACKAGE_PIN AJ12 IOSTANDARD LVCMOS18"  [get_ports FMC_i2c0_scl]
+# PULP pad_i3c2_sda - FPGA AJ13 - FMC H37
+set_property -dict "PACKAGE_PIN AJ13 IOSTANDARD LVCMOS18"  [get_ports FMC_i2c0_sda]
+
+######################################################################
+# Camera mapping (OK)
+######################################################################
+# PULP pad_cam_pclk - FPGA AR14 - FMC D20
+set_property -dict "PACKAGE_PIN AR14 IOSTANDARD LVCMOS18" [get_ports FMC_cam_pclk]
+# PULP pad_cam_hsync - FPGA AT14 - FMC D21
+set_property -dict "PACKAGE_PIN AT14 IOSTANDARD LVCMOS18" [get_ports FMC_cam_hsync]
+# PULP pad_cam_data0 - FPGA AP16 - FMC D24
+set_property -dict "PACKAGE_PIN AP16 IOSTANDARD LVCMOS18" [get_ports FMC_cam_data0]
+# PULP pad_cam_data1 - FPGA AN16 - FMC D23
+set_property -dict "PACKAGE_PIN AN16 IOSTANDARD LVCMOS18" [get_ports FMC_cam_data1]
+# PULP pad_cam_data2 - FPGA AP12 - FMC C22
+set_property -dict "PACKAGE_PIN AP12 IOSTANDARD LVCMOS18"  [get_ports FMC_cam_data2]
+# PULP pad_cam_data3 - FPGA AK15 - FMC D26
+set_property -dict "PACKAGE_PIN AK15 IOSTANDARD LVCMOS18" [get_ports FMC_cam_data3]
+# PULP pad_cam_data4 - FPGA AR12 - FMC C23
+set_property -dict "PACKAGE_PIN AR12 IOSTANDARD LVCMOS18"  [get_ports FMC_cam_data4]
+# PULP pad_cam_data5 - FPGA AL15 - FMC D27
+set_property -dict "PACKAGE_PIN AL15 IOSTANDARD LVCMOS18" [get_ports FMC_cam_data5]
+# PULP pad_cam_data6 - FPGA AY7 - FMC D18
+set_property -dict "PACKAGE_PIN AY7 IOSTANDARD LVCMOS18" [get_ports FMC_cam_data6]
+# PULP pad_cam_data7 - FPGA AM14 - FMC C27
+set_property -dict "PACKAGE_PIN AM14 IOSTANDARD LVCMOS18" [get_ports FMC_cam_data7]
+# PULP pad_cam_vsync - FPGA AW7 - FMC C19
+set_property -dict "PACKAGE_PIN AW7 IOSTANDARD LVCMOS18" [get_ports FMC_cam_vsync]
+
+
+#LED
+#set_property PACKAGE_PIN AG14 [get_ports LED]
+#set_property IOSTANDARD LVCMOS33 [get_ports LED]
+
+set_property MARK_DEBUG true [get_nets pulp_chip_i/pad_jtag_tdi]
+set_property MARK_DEBUG true [get_nets pulp_chip_i/pad_jtag_tdo]
+set_property MARK_DEBUG true [get_nets pulp_chip_i/pad_jtag_tck]
+set_property MARK_DEBUG true [get_nets pulp_chip_i/pad_jtag_tms]
+set_property MARK_DEBUG true [get_nets pulp_chip_i/pad_reset_n]
+set_property MARK_DEBUG true [get_nets pulp_chip_i/s_ref_clk]
+set_property MARK_DEBUG true [get_nets pulp_chip_i/s_bootsel]
diff --git a/fpga/pulpemu/tcl/fmc_board_zc706.xdc b/fpga/pulpemu/tcl/fmc_board_zc706.xdc
new file mode 100644
index 00000000..8dfb4082
--- /dev/null
+++ b/fpga/pulpemu/tcl/fmc_board_zc706.xdc
@@ -0,0 +1,229 @@
+######################################################################
+# Sensorboard J5 HPC0 FMC mapping
+######################################################################
+
+######################################################################
+# PWM mapping
+######################################################################
+# GAP pad_pwm0 - FPGA AK17 - FMC  H7
+set_property -dict "PACKAGE_PIN AK17 IOSTANDARD LVCMOS25"   [get_ports FMC_pwm0]
+# GAP pad_pwm1 - FPGA AB14 - FMC  H20
+set_property -dict "PACKAGE_PIN AB14 IOSTANDARD LVCMOS25"   [get_ports FMC_pwm1]
+# GAP pad_pwm2 - FPGA AH26 - FMC  H22
+set_property -dict "PACKAGE_PIN AH26 IOSTANDARD LVCMOS25"   [get_ports FMC_pwm2]
+# GAP pad_pwm3 - FPGA AH27 - FMC  H23
+set_property -dict "PACKAGE_PIN AH27 IOSTANDARD LVCMOS25"   [get_ports FMC_pwm3]
+
+######################################################################
+# QSPI mapping
+######################################################################
+# GAP pad_qspi_sdio0 - FPGA AK18 - FMC  H8
+set_property -dict "PACKAGE_PIN AK18 IOSTANDARD LVCMOS25"   [get_ports FMC_qspi_sdio0]
+# GAP pad_qspi_sdio1 - FPGA AF24 - FMC G16
+set_property -dict "PACKAGE_PIN AF24 IOSTANDARD LVCMOS25"   [get_ports FMC_qspi_sdio1]
+# GAP pad_qspi_sdio2 - FPGA AJ20 - FMC H10
+set_property -dict "PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25"  [get_ports FMC_qspi_sdio2]
+# GAP pad_qspi_sdio3 - FPGA AF20 - FMC G6
+set_property -dict "PACKAGE_PIN AF20 IOSTANDARD LVCMOS25"   [get_ports FMC_qspi_sdio3]
+# GAP pad_qspi_csn0 - FPGA Y22 - FMC H19
+set_property -dict "PACKAGE_PIN Y22 IOSTANDARD LVCMOS25"  [get_ports FMC_qspi_cs0]
+# GAP pad_qspi_sck - FPGA AF23 - FMC G15
+set_property -dict "PACKAGE_PIN AF23 IOSTANDARD LVCMOS25"   [get_ports FMC_qspi_sck]
+
+######################################################################
+# SDIO mapping (If use SDIO)
+######################################################################
+# GAP pad_sdio_sdio0 - FPGA D20 - ZC706 GPIO PMOD HEADER J57.1
+#set_property -dict "PACKAGE_PIN D20 IOSTANDARD LVCMOS25"  [get_ports FMC_qspi_sdio0]
+# GAP pad_sdio_sdio1 - FPGA E20 - ZC706 GPIO PMOD HEADER J57.3
+#set_property -dict "PACKAGE_PIN E20 IOSTANDARD LVCMOS25"  [get_ports FMC_qspi_sdio1]
+# GAP pad_sdio_sdio2 - FPGA D22 - ZC706 GPIO PMOD HEADER J57.5
+#set_property -dict "PACKAGE_PIN D22 IOSTANDARD LVCMOS25"  [get_ports FMC_qspi_sdio2]
+# GAP pad_sdio_sdio3 - FPGA E22 - ZC706 GPIO PMOD HEADER J57.7
+#set_property -dict "PACKAGE_PIN E22 IOSTANDARD LVCMOS25"  [get_ports FMC_qspi_sdio3]
+# GAP pad_sdio_cmd - FPGA F20 - ZC706 GPIO PMOD HEADER J57.2
+#set_property -dict "PACKAGE_PIN F20 IOSTANDARD LVCMOS25"  [get_ports FMC_qspi_cs0]
+# GAP pad_sdio_sck - FPGA G20 - ZC706 GPIO PMOD HEADER J57.4
+#set_property -dict "PACKAGE_PIN G20 IOSTANDARD LVCMOS25"  [get_ports FMC_qspi_sck]
+
+######################################################################
+# SPIM0 mapping
+######################################################################
+# GAP pad_spim0_sck - FPGA AF19 - FMC G12
+set_property -dict "PACKAGE_PIN AF19 IOSTANDARD LVCMOS25"   [get_ports FMC_spim0_sck]
+# GAP pad_spim0_csn - FPGA AG19 - FMC G13
+set_property -dict "PACKAGE_PIN AG19 IOSTANDARD LVCMOS25"   [get_ports FMC_spim0_cs0]
+# GAP pad_spim0_miso - FPGA N27 - FMC G37
+set_property -dict "PACKAGE_PIN N27 IOSTANDARD LVCMOS25"  [get_ports FMC_spim0_miso]
+# GAP pad_spim0_mosi - FPGA AJ24 - FMC H14
+set_property -dict "PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25"   [get_ports FMC_spim0_mosi]
+
+######################################################################
+# I3C0 mapping
+######################################################################
+# GAP pad_i3c0_scl - FPGA AB29 - FMC H34
+set_property -dict "PACKAGE_PIN AB29 IOSTANDARD LVCMOS25"  [get_ports FMC_i3c0_scl]
+# GAP pad_i3c0_sda - FPGA AE26 - FMC H32
+set_property -dict "PACKAGE_PIN AE26 IOSTANDARD LVCMOS25"  [get_ports FMC_i3c0_sda]
+
+######################################################################
+# UART0 mapping
+######################################################################
+# GAP pad_uart0_rx - FPGA G2 - ZC706 GPIO LED DS9
+set_property -dict "PACKAGE_PIN G2 IOSTANDARD LVCMOS15" [get_ports FMC_uart0_rx]
+# GAP pad_uart0_tx - FPGA W21 - ZC706 GPIO LED DS10
+set_property -dict "PACKAGE_PIN W21 IOSTANDARD LVCMOS25" [get_ports FMC_uart0_tx]
+
+######################################################################
+# UART1 mapping
+######################################################################
+# GAP pad_uart1_rx - FPGA AE22 - FMC H4
+set_property -dict "PACKAGE_PIN AE22 IOSTANDARD LVCMOS25" [get_ports FMC_uart1_rx]
+# GAP pad_uart1_tx - FPGA AF22 - FMC H5
+set_property -dict "PACKAGE_PIN AF22 IOSTANDARD LVCMOS25" [get_ports FMC_uart1_tx]
+
+######################################################################
+# SPIM1 mapping
+######################################################################
+# GAP pad_spim1_sck - FPGA AD29 - FMC G34
+set_property -dict "PACKAGE_PIN AD29 IOSTANDARD LVCMOS25"  [get_ports FMC_spim1_sck]
+# GAP pad_spim1_cs0 - FPGA AF25 - FMC G31
+set_property -dict "PACKAGE_PIN AF25 IOSTANDARD LVCMOS25"   [get_ports FMC_spim1_cs0]
+# GAP pad_spim1_miso - FPGA N26 - FMC G36
+set_property -dict "PACKAGE_PIN N26 IOSTANDARD LVCMOS25"   [get_ports FMC_spim1_miso]
+# GAP pad_spim1_mosi - FPGA AC29 - FMC G33
+set_property -dict "PACKAGE_PIN AC29 IOSTANDARD LVCMOS25"  [get_ports FMC_spim1_mosi]
+
+######################################################################
+# I3C1 mapping
+######################################################################
+# GAP pad_i3c1_scl - FPGA AG25 - FMC C15
+set_property -dict "PACKAGE_PIN AG25 IOSTANDARD LVCMOS25"  [get_ports FMC_i3c1_scl]
+# GAP pad_i3c1_sda - FPGA AG24 - FMC C14
+set_property -dict "PACKAGE_PIN AG24 IOSTANDARD LVCMOS25"  [get_ports FMC_i3c1_sda]
+
+######################################################################
+# I2S master mapping
+######################################################################
+# GAP pad_i2s_mst_sck - FPGA U30 - FMC H29
+set_property -dict "PACKAGE_PIN U30 IOSTANDARD LVCMOS25" [get_ports FMC_i2s_mst_sck]
+# GAP pad_i2s_mst_sdi0 - FPGA AB30 - FMC H35
+set_property -dict "PACKAGE_PIN AB30 IOSTANDARD LVCMOS25" [get_ports FMC_i2s_mst_sdo0]
+# GAP pad_i2s_mst_sdi1 - FPGA AD25 - FMC H31
+set_property -dict "PACKAGE_PIN AD25 IOSTANDARD LVCMOS25" [get_ports FMC_i2s_mst_sdo1]
+# GAP pad_i2s_mst_ws - FPGA AF30 - FMC H28
+set_property -dict "PACKAGE_PIN AF30 IOSTANDARD LVCMOS25" [get_ports FMC_i2s_mst_ws]
+
+######################################################################
+# I2S slave mapping
+######################################################################
+# GAP pad_i2s_slv_sck - FPGA V28 - FMC C26
+set_property -dict "PACKAGE_PIN V28 IOSTANDARD LVCMOS25" [get_ports FMC_i2s_slv_sck]
+# GAP pad_i2s_slv_sdi0 - FPGA AG22 - FMC C10
+set_property -dict "PACKAGE_PIN AG22 IOSTANDARD LVCMOS25" [get_ports FMC_i2s_slv_sdi0]
+# GAP pad_i2s_slv_sdi1 - FPGA AC24 - FMC C18
+set_property -dict "PACKAGE_PIN AC24 IOSTANDARD LVCMOS25" [get_ports FMC_i2s_slv_sdi1]
+# GAP pad_i2s_slv_ws - FPGA AH22 - FMC C11
+set_property -dict "PACKAGE_PIN AH22 IOSTANDARD LVCMOS25" [get_ports FMC_i2s_slv_ws]
+
+######################################################################
+# SPIM2 mapping
+######################################################################
+# GAP pad_spim2_sck - FPGA AE25 - FMC G30
+set_property -dict "PACKAGE_PIN AE25 IOSTANDARD LVCMOS25"   [get_ports FMC_spim2_sck]
+# GAP pad_spim2_csn - FPGA AG29 - FMC G28
+set_property -dict "PACKAGE_PIN AG29 IOSTANDARD LVCMOS25"   [get_ports FMC_spim2_cs0]
+# GAP pad_spim2_miso - FPGA AF29 - FMC G27
+set_property -dict "PACKAGE_PIN AF29 IOSTANDARD LVCMOS25"  [get_ports FMC_spim2_miso]
+# GAP pad_spim2_mosi - FPGA AJ19 - FMC G10
+set_property -dict "PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25"   [get_ports FMC_spim2_mosi]
+
+######################################################################
+# I3C2/I2C0 mapping
+######################################################################
+# GAP pad_i3c2_scl - FPGA R21 - FMC H38
+set_property -dict "PACKAGE_PIN R21 IOSTANDARD LVCMOS25"  [get_ports FMC_i3c2_scl]
+# GAP pad_i3c2_sda - FPGA P21 - FMC H37
+set_property -dict "PACKAGE_PIN P21 IOSTANDARD LVCMOS25"  [get_ports FMC_i3c2_sda]
+
+######################################################################
+# Camera mapping
+######################################################################
+# GAP pad_cam_pclk - FPGA V23 - FMC D20
+set_property -dict "PACKAGE_PIN V23 IOSTANDARD LVCMOS25" [get_ports FMC_cam_pclk]
+# GAP pad_cam_hsync - FPGA W24 - FMC D21
+set_property -dict "PACKAGE_PIN W24 IOSTANDARD LVCMOS25" [get_ports FMC_cam_hsync]
+# GAP pad_cam_data0 - FPGA P26 - FMC D24
+set_property -dict "PACKAGE_PIN P26 IOSTANDARD LVCMOS25" [get_ports FMC_cam_data0]
+# GAP pad_cam_data1 - FPGA P25 - FMC D23
+set_property -dict "PACKAGE_PIN P25 IOSTANDARD LVCMOS25" [get_ports FMC_cam_data1]
+# GAP pad_cam_data2 - FPGA W25 - FMC C22
+set_property -dict "PACKAGE_PIN W25 IOSTANDARD LVCMOS25"  [get_ports FMC_cam_data2]
+# GAP pad_cam_data3 - FPGA R28 - FMC D26
+set_property -dict "PACKAGE_PIN R28 IOSTANDARD LVCMOS25" [get_ports FMC_cam_data3]
+# GAP pad_cam_data4 - FPGA W26 - FMC C23
+set_property -dict "PACKAGE_PIN W26 IOSTANDARD LVCMOS25"  [get_ports FMC_cam_data4]
+# GAP pad_cam_data5 - FPGA T28 - FMC D27
+set_property -dict "PACKAGE_PIN T28 IOSTANDARD LVCMOS25" [get_ports FMC_cam_data5]
+# GAP pad_cam_data6 - FPGA AA23 - FMC D18
+set_property -dict "PACKAGE_PIN AA23 IOSTANDARD LVCMOS25" [get_ports FMC_cam_data6]
+# GAP pad_cam_data7 - FPGA V29 - FMC C27
+set_property -dict "PACKAGE_PIN V29 IOSTANDARD LVCMOS25" [get_ports FMC_cam_data7]
+# GAP pad_cam_vsync - FPGA AD24 - FMC C19
+set_property -dict "PACKAGE_PIN AD24 IOSTANDARD LVCMOS25" [get_ports FMC_cam_vsync]
+
+######################################################################
+# HYPERBUS mapping
+######################################################################
+# GAP alt2 pad_hyper_ck - FPGA AG21 - FMC D8
+set_property -dict "PACKAGE_PIN AG21 IOSTANDARD LVCMOS25"  [get_ports FMC_hyper_ck]
+# GAP alt2 pad_hyper_ckn - FPGA AH21 - FMC D9
+set_property -dict "PACKAGE_PIN AH21 IOSTANDARD LVCMOS25"  [get_ports FMC_hyper_ckn]
+# GAP alt2 pad_hyper_rwds - FPGA AA22 - FMC D17
+set_property -dict "PACKAGE_PIN AA22 IOSTANDARD LVCMOS25"  [get_ports FMC_hyper_rwds]
+# GAP alt2 pad_hyper_csn0 - FPGA W28 - FMC G25
+set_property -dict "PACKAGE_PIN W28 IOSTANDARD LVCMOS25"  [get_ports FMC_hyper_csn0]
+# GAP alt2 pad_hyper_csn1 - FPGA V27 - FMC G24
+set_property -dict "PACKAGE_PIN V27 IOSTANDARD LVCMOS25"  [get_ports FMC_hyper_csn1]
+# GAP alt2 pad_hyper_dq0 - FPGA AH23 - FMC D11
+set_property -dict "PACKAGE_PIN AH23 IOSTANDARD LVCMOS25"  [get_ports FMC_hyper_dq0]
+# GAP alt2 pad_hyper_dq1 - FPGA AH24 - FMC D12
+set_property -dict "PACKAGE_PIN AH24 IOSTANDARD LVCMOS25"  [get_ports FMC_hyper_dq1]
+# GAP alt2 pad_hyper_dq2 - FPGA AD21 - FMC D14
+set_property -dict "PACKAGE_PIN AD21 IOSTANDARD LVCMOS25"   [get_ports FMC_hyper_dq2]
+# GAP alt2 pad_hyper_dq3 - FPGA AE21 - FMC D15
+set_property -dict "PACKAGE_PIN AE21 IOSTANDARD LVCMOS25"   [get_ports FMC_hyper_dq3]
+# GAP alt2 pad_hyper_dq4 - FPGA AA24 - FMC G18
+set_property -dict "PACKAGE_PIN AA24 IOSTANDARD LVCMOS25"  [get_ports FMC_hyper_dq4]
+# GAP alt2 pad_hyper_dq5 - FPGA AB24 - FMC G19
+set_property -dict "PACKAGE_PIN AB24 IOSTANDARD LVCMOS25" [get_ports FMC_hyper_dq5]
+# GAP alt2 pad_hyper_dq6 - FPGA U25 - FMC G21
+set_property -dict "PACKAGE_PIN U25 IOSTANDARD LVCMOS25"  [get_ports FMC_hyper_dq6]
+# GAP alt2 pad_hyper_dq7 - FPGA V26 - FMC G22
+set_property -dict "PACKAGE_PIN V26 IOSTANDARD LVCMOS25"  [get_ports FMC_hyper_dq7]
+
+######################################################################
+# Reset mapping
+######################################################################
+# GAP pad_reset_n - FPGA AJ21 - ZC706 GPIO PMOD HEADER J58.1
+set_property -dict "PACKAGE_PIN AJ21 IOSTANDARD LVCMOS25"  [get_ports FMC_reset_n]
+
+######################################################################
+# JTAG mapping
+######################################################################
+# GAP pad_jtag_tdo - FPGA AB16 - ZC706 GPIO PMOD HEADER J58.7
+set_property -dict "PACKAGE_PIN AB16 IOSTANDARD LVCMOS25"  [get_ports FMC_jtag_tdo]
+# GAP pad_jtag_tck - FPGA Y20 - ZC706 GPIO PMOD HEADER J58.2
+set_property -dict "PACKAGE_PIN Y20 IOSTANDARD LVCMOS25"  [get_ports FMC_jtag_tck]
+# GAP pad_jtag_tms - FPGA AA20 - ZC706 GPIO PMOD HEADER J58.4
+set_property -dict "PACKAGE_PIN AA20 IOSTANDARD LVCMOS25"  [get_ports FMC_jtag_tms]
+# GAP pad_jtag_tdi - FPGA AC18 - ZC706 GPIO PMOD HEADER J58.6
+set_property -dict "PACKAGE_PIN AC18 IOSTANDARD LVCMOS25"  [get_ports FMC_jtag_tdi]
+# GAP pad_jtag_trst - FPGA AC19 - ZC706 GPIO PMOD HEADER J58.8
+set_property -dict "PACKAGE_PIN AC19 IOSTANDARD LVCMOS25"  [get_ports FMC_jtag_trst]
+# GAP pad_bootmode - FPGA AB21 - ZC706 GPIO PMOD HEADER J58.5
+set_property -dict "PACKAGE_PIN AB21 IOSTANDARD LVCMOS25"  [get_ports FMC_bootmode]
+
+#LED
+set_property PACKAGE_PIN Y21 [get_ports LED]
+set_property IOSTANDARD LVCMOS25 [get_ports LED]
diff --git a/fpga/pulpemu/tcl/fmc_board_zcu102.xdc b/fpga/pulpemu/tcl/fmc_board_zcu102.xdc
new file mode 100644
index 00000000..4b162893
--- /dev/null
+++ b/fpga/pulpemu/tcl/fmc_board_zcu102.xdc
@@ -0,0 +1,181 @@
+#############################################################
+#  _____ ____         _____      _   _   _                  #
+# |_   _/ __ \       / ____|    | | | | (_)                 #
+#   | || |  | |_____| (___   ___| |_| |_ _ _ __   __ _ ___  #
+#   | || |  | |______\___ \ / _ \ __| __| | '_ \ / _` / __| #
+#  _| || |__| |      ____) |  __/ |_| |_| | | | | (_| \__ \ #
+# |_____\____/      |_____/ \___|\__|\__|_|_| |_|\__, |___/ #
+#                                                 __/ |     #
+#                                                |___/      #
+#############################################################
+
+## Sys clock
+set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVDS_25} [get_ports ref_clk_n]
+set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVDS_25} [get_ports ref_clk_p]
+
+## Reset
+######################################################################
+# Reset mapping
+######################################################################
+set_property -dict {PACKAGE_PIN AM13 IOSTANDARD LVCMOS33} [get_ports pad_reset]
+
+## Buttons
+#set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS33} [get_ports btn0_i]
+#set_property -dict {PACKAGE_PIN AG13 IOSTANDARD LVCMOS33} [get_ports btn1_i]
+#set_property -dict {PACKAGE_PIN AE14 IOSTANDARD LVCMOS33} [get_ports btn2_i]
+#set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS33} [get_ports btn3_i]
+
+## PMOD 0   --- JTAG
+######################################################################
+# JTAG mapping
+######################################################################
+set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tms]
+set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tdi]
+set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tdo]
+set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tck]
+
+#set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS33} [get_ports pad_pmod0_4]
+#set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS33} [get_ports pad_pmod0_5]
+#set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports pad_pmod0_6]
+#set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS33} [get_ports pad_pmod0_7]
+
+## PMOD 1
+#set_property -dict {PACKAGE_PIN D20  IOSTANDARD LVCMOS33} [get_ports pad_pmod1_0]
+#set_property -dict {PACKAGE_PIN E20  IOSTANDARD LVCMOS33} [get_ports pad_pmod1_1]
+#set_property -dict {PACKAGE_PIN D22  IOSTANDARD LVCMOS33} [get_ports pad_pmod1_2]
+#set_property -dict {PACKAGE_PIN E22  IOSTANDARD LVCMOS33} [get_ports pad_pmod1_3]
+#set_property -dict {PACKAGE_PIN F20  IOSTANDARD LVCMOS33} [get_ports pad_pmod1_4]
+#set_property -dict {PACKAGE_PIN G20  IOSTANDARD LVCMOS33} [get_ports pad_pmod1_5]
+#set_property -dict {PACKAGE_PIN J20  IOSTANDARD LVCMOS33} [get_ports pad_pmod1_6]
+#set_property -dict {PACKAGE_PIN J19  IOSTANDARD LVCMOS33} [get_ports pad_pmod1_7]
+
+## UART
+######################################################################
+# UART mapping
+######################################################################
+set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS33} [get_ports pad_uart_rx]
+set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports pad_uart_tx]
+
+
+#set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS33} [get_ports pad_uart_rts]
+#set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS33} [get_ports pad_uart_cts]
+
+## LEDs
+#set_property -dict {PACKAGE_PIN AG14 IOSTANDARD LVCMOS33} [get_ports led0_o]
+#set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS33} [get_ports led1_o]
+#set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS33} [get_ports led2_o]
+#set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS33} [get_ports led3_o]
+
+## Switches
+#set_property -dict {PACKAGE_PIN AN14 IOSTANDARD LVCMOS33} [get_ports switch0_i]
+#set_property -dict {PACKAGE_PIN AP14 IOSTANDARD LVCMOS33} [get_ports switch1_i]
+#set_property -dict {PACKAGE_PIN AM14 IOSTANDARD LVCMOS33} [get_ports switch2_i]
+#set_property -dict {PACKAGE_PIN AN13 IOSTANDARD LVCMOS33} [get_ports switch3_i]
+
+## I2C Bus
+#set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports pad_i2c0_scl]
+#set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS33} [get_ports pad_i2c0_sda]
+
+## HDMI CTL
+#set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS33} [get_ports pad_hdmi_scl]
+#set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports pad_hdmi_sda]
+
+
+#LED
+######################################################################
+# JTAG mapping
+######################################################################
+#set_property PACKAGE_PIN AG14 [get_ports LED]
+#set_property IOSTANDARD LVCMOS33 [get_ports LED]
+
+######################################################################
+# I2C0 mapping
+######################################################################
+# PULP pad_i3c2_scl - FPGA T11 - FMC H38
+set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS18} [get_ports FMC_i2c0_scl]
+# PULP pad_i3c2_sda - FPGA U11 - FMC H37
+set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS18} [get_ports FMC_i2c0_sda]
+
+
+######################################################################
+# I2S master mapping
+######################################################################
+# PULP pad_i2s_mst_sck - FPGA K12 - FMC H29
+set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports FMC_i2s0_sck]
+# PULP pad_i2s_mst_ws - FPGA AC7 - FMC C18
+set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVCMOS18} [get_ports FMC_i2s0_ws]
+# PULP pad_i2s_slv_sdi0 - FPGA AB4 - FMC D8
+set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18} [get_ports FMC_i2s0_sdi]
+# PULP pad_i2s_slv_sdi1 - FPGA AC2 - FMC C10
+set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18} [get_ports FMC_i2s1_sdi]
+
+
+######################################################################
+# SDIO mapping
+######################################################################
+# PULP pad_sdio_sdio0 - FPGA D20 - ZCU102 GPIO PMOD HEADER J87.1
+set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33} [get_ports FMC_sdio_data0]
+# PULP pad_sdio_sdio1 - FPGA E20 - ZCU102 GPIO PMOD HEADER J87.3
+set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS33} [get_ports FMC_sdio_data1]
+# PULP pad_sdio_sdio2 - FPGA D22 - ZCU102 GPIO PMOD HEADER J87.5
+set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS33} [get_ports FMC_sdio_data2]
+# PULP pad_sdio_sdio3 - FPGA E22 - ZCU102 GPIO PMOD HEADER J87.7
+set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS33} [get_ports FMC_sdio_data3]
+# PULP pad_sdio_cmd - FPGA F20 - ZCU102 GPIO PMOD HEADER J87.2
+set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVCMOS33} [get_ports FMC_sdio_cmd]
+# PULP pad_sdio_sck - FPGA G20 - ZCU102 GPIO PMOD HEADER J87.4
+set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS33} [get_ports FMC_sdio_sck]
+
+
+######################################################################
+# QSPI mapping
+######################################################################
+# PULP pad_qspi_sdio0 - FPGA V1 - FMC  H8
+set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS18} [get_ports FMC_qspi_sdio0]
+# PULP pad_qspi_sdio1 - FPGA W6 - FMC G16
+set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18} [get_ports FMC_qspi_sdio1]
+# PULP pad_qspi_sdio2 - FPGA AA2 - FMC H10
+set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVCMOS18} [get_ports FMC_qspi_sdio2]
+# PULP pad_qspi_sdio3 - FPGA Y4 - FMC G6
+set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS18} [get_ports FMC_qspi_sdio3]
+# PULP pad_qspi_csn0 - FPGA Y10 - FMC H19
+set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18} [get_ports FMC_qspi_csn0]
+# PULP pad_qspi_sck - FPGA W7 - FMC G15
+set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18} [get_ports FMC_qspi_sck]
+# GAP pad_spim0_sck - FPGA V2 - FMC H7
+set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS18} [get_ports FMC_qspi_csn1]
+
+
+######################################################################
+# Camera mapping
+######################################################################
+# PULP pad_cam_pclk - FPGA P11 - FMC D20
+set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18} [get_ports FMC_cam_pclk]
+# PULP pad_cam_hsync - FPGA N11 - FMC D21
+set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18} [get_ports FMC_cam_hsync]
+# PULP pad_cam_data0 - FPGA K16 - FMC D24
+set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports FMC_cam_data0]
+# PULP pad_cam_data1 - FPGA L16 - FMC D23
+set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports FMC_cam_data1]
+# PULP pad_cam_data2 - FPGA N9 - FMC C22
+set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18} [get_ports FMC_cam_data2]
+# PULP pad_cam_data3 - FPGA L15 - FMC D26
+set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports FMC_cam_data3]
+# PULP pad_cam_data4 - FPGA N8 - FMC C23
+set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports FMC_cam_data4]
+# PULP pad_cam_data5 - FPGA K15 - FMC D27
+set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports FMC_cam_data5]
+# PULP pad_cam_data6 - FPGA AC8 - FMC D18
+set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVCMOS18} [get_ports FMC_cam_data6]
+# PULP pad_cam_data7 - FPGA L10 - FMC C27
+set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS18} [get_ports FMC_cam_data7]
+# PULP pad_cam_vsync - FPGA AC6 - FMC C19
+set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18} [get_ports FMC_cam_vsync]
+
+set_property MARK_DEBUG true [get_nets pulp_chip_i/pad_jtag_tdi]
+set_property MARK_DEBUG true [get_nets pulp_chip_i/pad_jtag_tdo]
+set_property MARK_DEBUG true [get_nets pulp_chip_i/pad_jtag_tck]
+set_property MARK_DEBUG true [get_nets pulp_chip_i/pad_jtag_tms]
+set_property MARK_DEBUG true [get_nets pulp_chip_i/pad_reset_n]
+set_property MARK_DEBUG true [get_nets pulp_chip_i/s_ref_clk]
+set_property MARK_DEBUG true [get_nets pulp_chip_i/s_bootsel]
diff --git a/fpga/pulpemu/tcl/impl.tcl b/fpga/pulpemu/tcl/impl.tcl
new file mode 100644
index 00000000..74b6ef18
--- /dev/null
+++ b/fpga/pulpemu/tcl/impl.tcl
@@ -0,0 +1,51 @@
+# set for RuntimeOptimized implementation
+set_property "steps.opt_design.args.directive"   "RuntimeOptimized" [get_runs impl_1]
+set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
+set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
+set_property "steps.phys_opt_design.args.is_enabled" true [get_runs impl_1]
+set_property "steps.phys_opt_design.args.directive" "ExploreWithHoldFix" [get_runs impl_1]
+set_property "steps.post_route_phys_opt_design.args.is_enabled" true [get_runs impl_1]
+set_property "steps.post_route_phys_opt_design.args.directive" "ExploreWithAggressiveHoldFix" [get_runs impl_1]
+
+launch_runs impl_1 -jobs 12
+wait_on_run impl_1
+
+catch {
+# Set only for VCU device to flash SPI flash fast
+open_run impl_1
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8         [get_designs impl_1]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES      [get_designs impl_1]
+reset_run impl_1
+}
+
+# reports
+exec mkdir -p reports/
+exec rm -rf reports/*
+check_timing                                                                                         -file reports/pulpemu.check_timing.rpt
+
+catch {
+report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack                              -file reports/pulpemu.timing_WORST_100.rpt
+report_timing -group CLUSTER_CLK -max_paths 100 -nworst 100 -delay_type max -sort_by slack           -file reports/pulpemu.timing_CLUSTER_WORST_100.rpt
+report_timing -group SOC_CLK -max_paths 100 -nworst 100 -delay_type max -sort_by slack               -file reports/pulpemu.timing_SOC_WORST_100.rpt
+report_timing -nworst 1 -delay_type max -sort_by group                                               -file reports/pulpemu.timing.rpt
+report_utilization -hierarchical                                                                     -file reports/pulpemu.utilization.rpt
+report_utilization -hierarchical -hierarchical_depth 1                                               -file reports/pulpemu.area_top.rpt
+report_utilization -hierarchical -hierarchical_depth 2 -cells pulp_chip_i                            -file reports/pulpemu.area_pulp_chip.rpt
+report_utilization -hierarchical -hierarchical_depth 2 -cells pulp_chip_i/soc_domain_i/pulp_soc_i      -file reports/pulpemu.area_soc.rpt
+report_utilization -hierarchical -hierarchical_depth 2 -cells pulp_chip_i/cluster_domain_i/cluster_i -file reports/pulpemu.area_cluster.rpt
+}
+
+launch_runs impl_1 -to_step write_bitstream -jobs 12
+wait_on_run impl_1
+
+
+# output Verilog netlist + SDC for timing simulation
+write_verilog -force -mode funcsim pulpemu_funcsim.v
+write_verilog -force -mode timesim pulpemu_timesim.v
+write_sdf     -force pulpemu_timesim.sdf
+
+# copy bitstream
+exec cp pulpemu.runs/impl_1/pulpemu.bit .
+if [info exists ::env(SDK_WORKSPACE)] {
+    exec cp pulpemu.bit $SDK_WORKSPACE/.
+}
diff --git a/fpga/pulpemu/tcl/run.tcl b/fpga/pulpemu/tcl/run.tcl
new file mode 100644
index 00000000..2902b35b
--- /dev/null
+++ b/fpga/pulpemu/tcl/run.tcl
@@ -0,0 +1,122 @@
+# setup
+if [info exists ::env(SDK_WORKSPACE)] {
+    set SDK_WORKSPACE $::env(SDK_WORKSPACE)
+}
+
+
+# detect board
+if [info exists ::env(BOARD)] {
+    set BOARD $::env(BOARD)
+} else {
+    puts "Please execute 'source ../sourceme.sh first before you start vivado in order to setup necessary environment variables."
+    exit
+}
+if [info exists ::env(XILINX_BOARD)] {
+    set XILINX_BOARD $::env(XILINX_BOARD)
+}
+
+# create project
+create_project pulpemu . -force -part $::env(XILINX_PART)
+set_property board_part $::env(XILINX_BOARD) [current_project]
+
+# set up meaningful errors
+source ../common/messages.tcl
+
+#include ip inc dirs
+source tcl/ips_inc_dirs.tcl
+source tcl/rtl_inc_dirs.tcl
+set_property include_dirs $INCLUDE_DIRS [current_fileset]
+
+# setup source files
+source tcl/ips_src_files.tcl
+source tcl/rtl_src_files.tcl
+
+# add IPs
+source tcl/ips_add_files.tcl
+source tcl/rtl_add_files.tcl
+
+# detect target clock
+if [info exists ::env(FC_CLK_PERIOD_NS)] {
+    set FC_CLK_PERIOD_NS $::env(FC_CLK_PERIOD_NS)
+} else {
+    set FC_CLK_PERIOD_NS 10.000
+}
+set CLK_HALFPERIOD_NS [expr ${FC_CLK_PERIOD_NS} / 2.0]
+
+# add memory cuts + other FPGA IPs
+read_ip $FPGA_IPS/xilinx_interleaved_ram/ip/xilinx_interleaved_ram.xci
+read_ip $FPGA_IPS/xilinx_private_ram/ip/xilinx_private_ram.xci
+read_ip $FPGA_IPS/xilinx_rom_bank_2048x32/ip/xilinx_rom_bank_2048x32.xci
+read_ip $FPGA_IPS/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci
+read_ip $FPGA_IPS/xilinx_slow_clk_mngr/ip/xilinx_slow_clk_mngr.xci
+
+
+
+# add pulp_cluster
+catch {
+add_files -norecurse ../pulp_cluster/pulp_cluster.edf \
+                     ../pulp_cluster/pulp_cluster_stub.v
+}
+
+# needed only if used in batch mode
+update_compile_order -fileset sources_1
+update_compile_order -fileset sim_1
+
+# add constraints
+add_files -fileset constrs_1 -norecurse tcl/constraints.xdc
+set_property target_constrs_file tcl/constraints.xdc [current_fileset -constrset]
+add_files -fileset constrs_1 -norecurse "tcl/fmc_board_$::env(BOARD).xdc"
+set_property target_constrs_file "tcl/fmc_board_$::env(BOARD).xdc" [current_fileset -constrset]
+
+# workaround for Maestro packages
+set_property source_mgmt_mode DisplayOnly [current_project]
+
+# set pulpemu as top
+set_property top pulpemu [current_fileset]
+
+# elaborate
+set_msg_config -id {Synth 8-350} -new_severity {CRITICAL WARNING}
+
+catch {
+synth_design -rtl -name rtl_1 -verilog_define PULP_FPGA_EMUL=1 -verilog_define USE_CLUSTER_NETLIST=1 -flatten_hierarchy none
+}
+
+update_compile_order -fileset sources_1
+
+synth_design -rtl -name rtl_1 -verilog_define PULP_FPGA_EMUL=1 -verilog_define USE_CLUSTER_NETLIST=1 -flatten_hierarchy none
+
+# set unconnected stuff as ERROR if not in block design
+set_msg_config -id {[Synth 8-350]} -new_severity "critical warning"
+set_msg_config -id {[Synth 8-3352]} -new_severity "critical warning"
+set_property "steps.synth_design.args.flatten_hierarchy" "none"     [get_runs synth_1]
+set_property "steps.synth_design.args.directive" "RuntimeOptimized" [get_runs synth_1]
+
+# launch synthesis
+launch_runs synth_1 -job 12
+wait_on_run synth_1
+
+open_run synth_1 -name netlist_1
+set_property needs_refresh false [get_runs synth_1]
+
+# Remove unused IOBUF cells in padframe (they are not optimized away since the
+# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i
+# )
+remove_cell i_pulp/pad_frame_i/padinst_bootsel
+
+# export synthesis netlist 
+catch {
+exec mkdir -p ./save/synth
+write_edif    -force ./save/synth/pulpemu.edn
+write_verilog -force -mode synth_stub ./save/synth/pulpemu_stub.v
+write_verilog -force -mode funcsim    ./save/synth/pulpemu_funcsim.v
+}
+
+# export hardware design for sdk
+if [info exists ::env(SDK_WORKSPACE)] {
+    write_hwdef -force -file $SDK_WORKSPACE/pulpemu.hdf
+} else {
+    write_hwdef -force -file ./pulpemu.hdf
+}
+
+# run implementation
+source tcl/impl.tcl
diff --git a/fpga/pulpemu/tcl/setup_impl.tcl b/fpga/pulpemu/tcl/setup_impl.tcl
new file mode 100644
index 00000000..8b3e9909
--- /dev/null
+++ b/fpga/pulpemu/tcl/setup_impl.tcl
@@ -0,0 +1,58 @@
+set CLK_PERIOD 10.000
+set CLK_WAVEFORM { 0.000 5.000 }
+
+create_project pulpemu_top . -part xc7z045ffg900-2
+set_property board xilinx.com:zynq:zc706:1.1 [current_project]
+set_property design_mode GateLvl [current_fileset]
+add_files -norecurse ./pulpemu.edf
+add_files -norecurse ../ulpcluster/ulpcluster.edf
+add_files -norecurse ../ips/xilinx_tcdm_bank_512x32/ip/xilinx_tcdm_bank_512x32.dcp
+add_files -norecurse ../ips/xilinx_l2_mem_8192x64/ip/xilinx_l2_mem_8192x64.dcp
+add_files -norecurse ../ips/xilinx_tcdm_bank_256x32/ip/xilinx_tcdm_bank_256x32.dcp
+add_files -norecurse ../ips/xilinx_ic_ram_128x32/ip/xilinx_ic_ram_128x32.dcp
+add_files -norecurse ../ips/xilinx_core_ila/ip/xilinx_core_ila.dcp
+add_files -norecurse ../ips/xilinx_icache_ila/ip/xilinx_icache_ila.dcp
+add_files -norecurse ../ips/xilinx_tcdm_scm_ila/ip/xilinx_tcdm_scm_ila.dcp
+add_files -norecurse ../ips/xilinx_tcdm_sram_ila/ip/xilinx_tcdm_sram_ila.dcp
+set_property top pulpemu [current_fileset]
+link_design -name netlist_1
+
+# false paths
+source tcl/false_paths.tcl
+
+# clocks
+create_clock -period ${CLK_PERIOD} -name ref_clk_i  -waveform ${CLK_WAVEFORM} [get_nets {ref_clk_i}]
+create_clock -period ${CLK_PERIOD} -name ps7_clk -waveform ${CLK_WAVEFORM} [get_pins {ps7_wrapper_i/ps7_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]}]
+create_clock -period ${CLK_PERIOD} -name ulpsoc_clk -waveform ${CLK_WAVEFORM} [get_nets {ulpsoc_i/i_clk_rst_gen/clk_manager_i/clk_o}]
+create_clock -period 100 -name spi_clk -waveform { 0.0 50.0 } [ get_nets {spi_slave_clk_r}]
+
+# pins
+set_property package_pin AJ21    [get_ports PULP_SPI_clk]
+set_property is_loc_fixed true   [get_ports [list  PULP_SPI_clk]]
+set_property IOSTANDARD LVCMOS25 [get_ports PULP_SPI_clk]
+set_property PULLTYPE NONE       [get_ports PULP_SPI_clk]
+set_property package_pin AK12    [get_ports PULP_SPI_cs]
+set_property is_loc_fixed true   [get_ports [list  PULP_SPI_cs]]
+set_property IOSTANDARD LVCMOS25 [get_ports PULP_SPI_cs]
+set_property PULLTYPE PULLUP     [get_ports PULP_SPI_cs]
+set_property package_pin AA13    [get_ports PULP_SPI_sdo]
+set_property is_loc_fixed true   [get_ports [list  PULP_SPI_sdo]]
+set_property IOSTANDARD LVCMOS25 [get_ports PULP_SPI_sdo]
+set_property PULLTYPE PULLUP     [get_ports PULP_SPI_sdo]
+set_property package_pin AH18    [get_ports PULP_SPI_sdi]
+set_property is_loc_fixed true   [get_ports [list  PULP_SPI_sdi]]
+set_property IOSTANDARD LVCMOS25 [get_ports PULP_SPI_sdi]
+set_property PULLTYPE PULLUP     [get_ports PULP_SPI_sdi]
+set_property package_pin Y20     [get_ports PULP_SPI_mode_1]
+set_property is_loc_fixed true   [get_ports [list  PULP_SPI_mode_1]]
+set_property IOSTANDARD LVCMOS25 [get_ports PULP_SPI_mode_1]
+set_property PULLTYPE PULLUP     [get_ports PULP_SPI_mode_1]
+set_property package_pin AA20    [get_ports PULP_SPI_mode_0]
+set_property is_loc_fixed true   [get_ports [list  PULP_SPI_mode_0]]
+set_property IOSTANDARD LVCMOS25 [get_ports PULP_SPI_mode_0]
+set_property PULLTYPE PULLUP     [get_ports PULP_SPI_mode_0]
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PULP_SPI_clk_IBUF]
+
+save_constraints
+
+#source tcl/probes.tcl
diff --git a/fpga/pulpissimo-genesys2/.gitignore b/fpga/pulpissimo-genesys2/.gitignore
deleted file mode 100644
index 3f35710f..00000000
--- a/fpga/pulpissimo-genesys2/.gitignore
+++ /dev/null
@@ -1,22 +0,0 @@
-#Ignore vivado project files generated by the tcl script
-**/.Xil/*
-**/reports/*
-**/*.cache/*
-**/*.hw/*
-**/*.ip_user_files/*
-**/*.runs/*
-**/*.sim/*
-**/*.srcs/*
-*.edf
-*.xpr
-*.jou
-*.log
-
-.cxl.*
-
-*_stub.v
-gmon.out
-
-/pulpissimo/**/pulpissimo.bit
-
-**/xdc/constraints.xdc
diff --git a/fpga/pulpissimo-genesys2/Makefile b/fpga/pulpissimo-genesys2/Makefile
deleted file mode 100644
index bd1a6083..00000000
--- a/fpga/pulpissimo-genesys2/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-PROJECT:=pulpissimo_genesys2
-VIVADO ?= vivado
-VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
-
-include fpga-settings.mk
-
-.DEFAULT_GOAL:=help
-
-.PHONY: help all gui ips clean-ips clk clean-clk ram clean-ram clean
-
-all: ips ## Generate the bitstream for pulpissimo with vivado in batch mode. The vivado invocation command may be overriden with the env variable VIVADO.
-	$(VIVADO) -mode batch -source tcl/run.tcl
-
-gui: ips ## Generates the bitstream for pulpissimo with vivado in GUI mode. The vivado invocation command may be overriden with the env variable VIVADO.
-	$(VIVADO) -mode gui -source tcl/run.tcl &
-
-ips: clk ram ## Synthesizes necessary xilinx IP
-
-clean-ips: clean-clk clean-ram ## Clean all IPs
-
-clk: ## Synthesizes the Xilinx Clocking Manager IPs
-	cd ips/xilinx_clk_mngr; make all
-	cd ips/xilinx_slow_clk_mngr; make all
-
-clean-clk: ## Removes all Clocking Wizard IP outputs
-	cd ips/xilinx_clk_mngr; make clean
-	cd ips/xilinx_slow_clk_mngr; make clean
-
-ram: ## Synthesizes the Xilinx Block Memory Generator IPs for PULPissimo's L2 Ram
-	cd ips/xilinx_interleaved_ram; make all
-	cd ips/xilinx_private_ram; make all
-
-clean-ram: ## Removes all Block Ram IP outputs related to l2 ram
-	cd ips/xilinx_interleaved_ram; make clean
-	cd ips/xilinx_private_ram; make clean
-
-clean: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*)
-	rm -rf ${PROJECT}.*[^'bit']
-	rm -rf ${PROJECT}.*[^'bin']
-	rm -rf *.log
-	rm -rf vivado*
-
-help:
-	@grep -E -h '^[a-zA-Z_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'
diff --git a/fpga/pulpissimo-genesys2/README.md b/fpga/pulpissimo-genesys2/README.md
deleted file mode 100644
index e8c7dc12..00000000
--- a/fpga/pulpissimo-genesys2/README.md
+++ /dev/null
@@ -1,56 +0,0 @@
-# PULPissimo on the Digilent Genesys2 Board
-[\[Documentation\]](https://reference.digilentinc.com/reference/programmable-logic/genesys-2/start)
-
-## Bitstream Generation
-In the fpga folder, run
-```Shell
-make genesys2
-```
-which will generate `pulpissimo_genesys2.bit`.
-Use Vivado to load it into the FPGA.
-
-## Default SoC and Core Frequencies
-
-By default the clock generating IPs are synthesized to provide the following frequencies to PULPissimo:
-
-| Clock Domain   | Default Frequency on Genesys2 board |
-|----------------|-------------------------------------|
-| Core Frequency | 20 MHz                              |
-| SoC Frequency  | 10 MHz                              |
-
-
-## Peripherals
-PULPissimo is connected to the following board peripherals:
-
-
-| PULPissimo Pin | Mapped Board Peripheral                             |
-|----------------|-----------------------------------------------------|
-| `SPIM0` pins   | QSPI Flash                                          |
-| `I2C0` pins    | I2C Bus (connects to Board Current Measurement ICs) |
-| `spim_csn1`    | LED0                                                |
-| `cam_pclk`     | LED1                                                |
-| `cam_hsync`    | LED2                                                |
-| `cam_data0`    | LED3                                                |
-| `cam_data1`    | Switch 1                                            |
-| `cam_data2`    | Switch 2                                            |
-| `cam_data3`    | Button C                                            |
-| `cam_data4`    | Button D                                            |
-| `cam_data5`    | Button L                                            |
-| `cam_data6`    | Button R                                            |
-| `cam_data7`    | Button U                                            |
-
-### Reset Button
-The USER RESET button (BTN1) resets the RISC-V CPU.
-
-### UART
-PULPissimo's UART port is mapped to the onboard FTDI FT232R USB-UART bridge and thus accessible through the UART micro-USB connector J15.
-
-### JTAG
-PULPIssimo's JTAG plug is connected to Channel 0 of the onboard FTDI USB JTAG
-programmer. Therefore we can attach OpenOCD withouth the need of an external
-JTAG programmer. Just attach a micro-USB cable to the JTAG SW17 micro-USB connector and use the
-provided OpenOCD configuration file:
-
-```Shell
-$OPENOCD/bin/openocd -f pulpissimo/fpga/pulpissimo-genesys2/openocd-genesys2.cfg
-```
diff --git a/fpga/pulpissimo-genesys2/constraints/genesys2.xdc b/fpga/pulpissimo-genesys2/constraints/genesys2.xdc
deleted file mode 100644
index a165b732..00000000
--- a/fpga/pulpissimo-genesys2/constraints/genesys2.xdc
+++ /dev/null
@@ -1,213 +0,0 @@
-#######################################
-#  _______ _           _              #
-# |__   __(_)         (_)             #
-#    | |   _ _ __ ___  _ _ __   __ _  #
-#    | |  | | '_ ` _ \| | '_ \ / _` | #
-#    | |  | | | | | | | | | | | (_| | #
-#    |_|  |_|_| |_| |_|_|_| |_|\__, | #
-#                               __/ | #
-#                              |___/  #
-#######################################
-
-
-#Create constraint for the clock input of the genesys2 board
-create_clock -period 5.000 -name ref_clk [get_ports ref_clk_p]
-
-#I2S and CAM interface are not used in this FPGA port. Set constraints to
-#disable the clock
-set_case_analysis 0 i_pulpissimo/safe_domain_i/cam_pclk_o
-set_case_analysis 0 i_pulpissimo/safe_domain_i/i2s_slave_sck_o
-#set_input_jitter tck 1.000
-
-## JTAG
-create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_jtag_tck]
-set_input_jitter tck 1.000
-
-
-# minimize routing delay
-set_input_delay -clock tck -clock_fall 5.000 [get_ports pad_jtag_tdi]
-set_input_delay -clock tck -clock_fall 5.000 [get_ports pad_jtag_tms]
-set_output_delay -clock tck 5.000 [get_ports pad_jtag_tdo]
-set_false_path -from [get_ports pad_jtag_trst]
-
-set_max_delay -to [get_ports pad_jtag_tdo] 20.000
-set_max_delay -from [get_ports pad_jtag_tms] 20.000
-set_max_delay -from [get_ports pad_jtag_tdi] 20.000
-set_max_delay -from [get_ports pad_jtag_trst] 20.000
-
-set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000
-set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000
-set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000
-
-
-# reset signal
-set_false_path -from [get_ports pad_reset_n]
-
-# Set ASYNC_REG attribute for ff synchronizers to place them closer together and
-# increase MTBF
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/apb_adv_timer_i/u_tim0/u_in_stage/r_ls_clk_sync_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/apb_adv_timer_i/u_tim1/u_in_stage/r_ls_clk_sync_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/apb_adv_timer_i/u_tim2/u_in_stage/r_ls_clk_sync_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/apb_adv_timer_i/u_tim3/u_in_stage/r_ls_clk_sync_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*]
-
-# Create asynchronous clock group between slow-clk and SoC clock. Those clocks
-# are considered asynchronously and proper synchronization regs are in place
-set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/safe_domain_i/i_slow_clk_gen/i_slow_clk_mngr/inst/mmcm_adv_inst/CLKOUT0]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fpga_clk_gen/i_clk_manager/inst/mmcm_adv_inst/CLKOUT0]]
-
-
-#############################################################
-#  _____ ____         _____      _   _   _                  #
-# |_   _/ __ \       / ____|    | | | | (_)                 #
-#   | || |  | |_____| (___   ___| |_| |_ _ _ __   __ _ ___  #
-#   | || |  | |______\___ \ / _ \ __| __| | '_ \ / _` / __| #
-#  _| || |__| |      ____) |  __/ |_| |_| | | | | (_| \__ \ #
-# |_____\____/      |_____/ \___|\__|\__|_|_| |_|\__, |___/ #
-#                                                 __/ |     #
-#                                                |___/      #
-#############################################################
-
-## Sys clock
-set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVDS} [get_ports ref_clk_n]
-set_property -dict {PACKAGE_PIN AD12 IOSTANDARD LVDS} [get_ports ref_clk_p]
-
-
-## Buttons
-set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports pad_reset_n]
-set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS12} [get_ports btnc_i]
-set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS12} [get_ports btnd_i]
-set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS12} [get_ports btnl_i]
-set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS12} [get_ports btnr_i]
-set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS12} [get_ports btnu_i]
-
-## To use FTDI FT2232 JTAG
-set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVCMOS33} [get_ports pad_jtag_trst]
-set_property -dict {PACKAGE_PIN AD27 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tck]
-set_property -dict {PACKAGE_PIN W27 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tdi]
-set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tdo]
-set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tms]
-
-## UART
-set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS33} [get_ports pad_uart_tx]
-set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports pad_uart_rx]
-
-## LEDs
-set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS33} [get_ports led0_o]
-set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports led1_o]
-set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS33} [get_ports led2_o]
-set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS33} [get_ports led3_o]
-#set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports ]
-#set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS33} [get_ports ]
-#set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports ]
-#set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports ]
-
-## Switches
-set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS12} [get_ports switch0_i]
-set_property -dict {PACKAGE_PIN G25 IOSTANDARD LVCMOS12} [get_ports switch1_i]
-#set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS12} [get_ports {}]
-# set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS12} [get_ports {}]
-# set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS12} [get_ports {}]
-# set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS12} [get_ports {}]
-# set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS33} [get_ports {}]
-# set_property -dict {PACKAGE_PIN P27 IOSTANDARD LVCMOS33} [get_ports {}]
-
-## I2C Bus
-set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVCMOS33} [get_ports pad_i2c0_scl]
-set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS33} [get_ports pad_i2c0_sda]
-
-## QSPI Flash
-set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports pad_spim_csn0]
-#set_property -dict { PACKAGE_PIN P24   IOSTANDARD LVCMOS33 } [get_ports { pad_spim_sdio0 }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_d[0]
-set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS33} [get_ports pad_spim_sdio1]
-set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS33} [get_ports pad_spim_sdio2]
-set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS33} [get_ports pad_spim_sdio3]
-
-
-## OLED Display
-set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS18} [get_ports oled_dc_o]
-set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS18} [get_ports oled_rst_o]
-set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVCMOS18} [get_ports oled_spim_sck_o]
-set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS18} [get_ports oled_spim_mosi_o]
-set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS33} [get_ports oled_vbat_o]
-set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS18} [get_ports oled_vdd_o]
-
-
-#############################################
-## SD Card
-#############################################
-#set_property -dict { PACKAGE_PIN P28   IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L8N_T1_D12_14 Sch=sd_cd
-set_property -dict {PACKAGE_PIN R29 IOSTANDARD LVCMOS33} [get_ports pad_sdio_cmd]
-set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports pad_sdio_data0]
-set_property -dict {PACKAGE_PIN R30 IOSTANDARD LVCMOS33} [get_ports pad_sdio_data1]
-set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS33} [get_ports pad_sdio_data2]
-set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS33} [get_ports pad_sdio_data3]
-set_property -dict {PACKAGE_PIN AE24 IOSTANDARD LVCMOS33} [get_ports sdio_reset_o]
-set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports pad_sdio_clk]
-
-
-
-# set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports spi_clk_o]
-# set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS33} [get_ports spi_ss]
-# set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports spi_miso]
-# set_property -dict {PACKAGE_PIN R29 IOSTANDARD LVCMOS33} [get_ports spi_mosi]
-# set_property -dict { PACKAGE_PIN P28   IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L8N_T1_D12_14 Sch=sd_cd
-# set_property -dict { PACKAGE_PIN R29   IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L7N_T1_D10_14 Sch=sd_cmd
-# set_property -dict { PACKAGE_PIN R26   IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0]
-# set_property -dict { PACKAGE_PIN R30   IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1]
-# set_property -dict { PACKAGE_PIN P29   IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2]
-# set_property -dict { PACKAGE_PIN T30   IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3]
-# set_property -dict { PACKAGE_PIN AE24  IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset
-# set_property -dict { PACKAGE_PIN R28   IOSTANDARD LVCMOS33 } [get_ports { sd_clk }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk
-
-# create_generated_clock -name sd_fast_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 2 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/fast_clk_reg/Q]
-# create_generated_clock -name sd_slow_clk -source [get_pins clk_mmcm/sd_sys_clk] -divide_by 200 [get_pins chipset_impl/piton_sd_top/sdc_controller/clock_divider0/slow_clk_reg/Q]
-# create_generated_clock -name sd_clk_out -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_fast_clk [get_ports sd_clk_out]
-# create_generated_clock -name sd_clk_out_1 -source [get_pins sd_clk_oddr/C] -divide_by 1 -add -master_clock sd_slow_clk [get_ports sd_clk_out]
-
-# create_clock -period 40.000 -name VIRTUAL_sd_fast_clk -waveform {0.000 20.000}
-# create_clock -period 4000.000 -name VIRTUAL_sd_slow_clk -waveform {0.000 2000.000}
-
-# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
-# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports {sd_dat[*]}]
-# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports {sd_dat[*]}]
-# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports {sd_dat[*]}]
-# set_output_delay -clock [get_clocks sd_clk_out] -min -add_delay 5.000 [get_ports sd_cmd]
-# set_output_delay -clock [get_clocks sd_clk_out] -max -add_delay 15.000 [get_ports sd_cmd]
-# set_output_delay -clock [get_clocks sd_clk_out_1] -min -add_delay 5.000 [get_ports sd_cmd]
-# set_output_delay -clock [get_clocks sd_clk_out_1] -max -add_delay 1500.000 [get_ports sd_cmd]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports {sd_dat[*]}]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports {sd_dat[*]}]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports {sd_dat[*]}]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports {sd_dat[*]}]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -min -add_delay 20.000 [get_ports sd_cmd]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_fast_clk] -max -add_delay 35.000 [get_ports sd_cmd]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -min -add_delay 2000.000 [get_ports sd_cmd]
-# set_input_delay -clock [get_clocks VIRTUAL_sd_slow_clk] -max -add_delay 3500.000 [get_ports sd_cmd]
-# set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks sd_clk_out] -group [get_clocks -include_generated_clocks sd_clk_out_1]
-# set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks {VIRTUAL_sd_fast_clk sd_fast_clk}] -group [get_clocks -include_generated_clocks {sd_slow_clk VIRTUAL_sd_slow_clk}]
-# set_clock_groups -asynchronous -group [get_clocks [list [get_clocks -of_objects [get_pins clk_mmcm/chipset_clk]]]] -group [get_clocks -filter { NAME =~  "*sd*" }]
-
-## PMOD Header JD
-#set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS33}     [get_ports { jd[0]}]
-#set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVCMOS33}     [get_ports { jd[1]}]
-#set_property -dict { PACKAGE_PIN V24   IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L23N_T3_A02_D18_14 Sch=jd[3]
-#set_property -dict { PACKAGE_PIN W22   IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L24N_T3_A00_D16_14 Sch=jd[4]
-#set_property -dict { PACKAGE_PIN U24   IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L23P_T3_A03_D19_14 Sch=jd[7]
-#set_property -dict { PACKAGE_PIN Y26   IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L1P_T0_13 Sch=jd[8]
-#set_property -dict { PACKAGE_PIN V22   IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L22N_T3_A04_D20_14 Sch=jd[9]
-#set_property -dict { PACKAGE_PIN W21   IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L24P_T3_A01_D17_14 Sch=jd[10]## PMOD Header JD
-#set_property -dict { PACKAGE_PIN V27   IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L16N_T2_A15_D31_14 Sch=jd[1]
-#set_property -dict { PACKAGE_PIN Y30   IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L8P_T1_13 Sch=jd[2]
-#set_property -dict { PACKAGE_PIN V24   IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L23N_T3_A02_D18_14 Sch=jd[3]
-#set_property -dict { PACKAGE_PIN W22   IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L24N_T3_A00_D16_14 Sch=jd[4]
-#set_property -dict { PACKAGE_PIN U24   IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L23P_T3_A03_D19_14 Sch=jd[7]
-#set_property -dict { PACKAGE_PIN Y26   IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L1P_T0_13 Sch=jd[8]
-#set_property -dict { PACKAGE_PIN V22   IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L22N_T3_A04_D20_14 Sch=jd[9]
-#set_property -dict { PACKAGE_PIN W21   IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L24P_T3_A01_D17_14 Sch=jd[10]
-
-
-# Genesys 2 has a quad SPI flash
-set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
-
diff --git a/fpga/pulpissimo-genesys2/elf_run.gdb b/fpga/pulpissimo-genesys2/elf_run.gdb
deleted file mode 100644
index cba53bd0..00000000
--- a/fpga/pulpissimo-genesys2/elf_run.gdb
+++ /dev/null
@@ -1,4 +0,0 @@
-target remote localhost:3333
-monitor reset halt
-load
-continue
\ No newline at end of file
diff --git a/fpga/pulpissimo-genesys2/elf_run.sh b/fpga/pulpissimo-genesys2/elf_run.sh
deleted file mode 100755
index 06f2f60d..00000000
--- a/fpga/pulpissimo-genesys2/elf_run.sh
+++ /dev/null
@@ -1,17 +0,0 @@
-#!/bin/bash
-
-trap "exit" INT TERM
-trap "kill 0" EXIT
-
-
-SCRIPTDIR=$(dirname $0)
-UART_TTY=${PULP_GENESYS2_UART_TTY:=/dev/ttyUSB0}
-UART_BAUDRATE=${PULP_GENESYS2_UART_BAUDRATE:=115200}
-
-#Execute gdb and connect to openocd via pipe
-$OPENOCD/bin/openocd -f $SCRIPTDIR/openocd-genesys2.cfg &
-$PULP_RISCV_GCC_TOOLCHAIN_CI/bin/riscv32-unknown-elf-gdb -x $SCRIPTDIR/elf_run.gdb $1 &
-sleep 3
-minicom -D $UART_TTY -b $UART_BAUDRATE
-
-
diff --git a/fpga/pulpissimo-genesys2/fpga-settings.mk b/fpga/pulpissimo-genesys2/fpga-settings.mk
deleted file mode 100644
index 6d6495bb..00000000
--- a/fpga/pulpissimo-genesys2/fpga-settings.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-export BOARD=genesys2
-export XILINX_PART=xc7k325tffg900-2
-export XILINX_BOARD=digilentinc.com:genesys2:part0:1.1
-export FC_CLK_PERIOD_NS=50
-export PER_CLK_PERIOD_NS=100
-export SLOW_CLK_PERIOD_NS=30517
-#Must also change the localparam 'L2_BANK_SIZE' in pulp_soc.sv accordingly
-export INTERLEAVED_BANK_SIZE=28672
-#Must also change the localparam 'L2_BANK_SIZE_PRI' in pulp_soc.sv accordingly
-export PRIVATE_BANK_SIZE=8192
-$(info Setting environment variables for $(BOARD) board)
-
diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/Makefile b/fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/Makefile
deleted file mode 100644
index 978b9cee..00000000
--- a/fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/Makefile
+++ /dev/null
@@ -1,37 +0,0 @@
-PROJECT:=xilinx_clk_mngr
-VIVADO ?= vivado
-VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
-MODE=batch
-
-include ../../fpga-settings.mk
-
-.DEFAULT_GOAL:=help
-
-.PHONY: help all gui clean
-
-all: MODE=batch ## Create and synthesize the IP in batch mode.
-
-gui: MODE=gui  ## Create and synthesize the IP in GUI mode.
-
-all gui: $(PROJECT).xpr
-
-$(PROJECT).xpr: ../../fpga-settings.mk tcl/run.tcl
-	make clean
-	$(VIVADO) -mode $(MODE) -source tcl/run.tcl
-	mkdir -p ip
-	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
-	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
-
-clean: ## Remove all build products
-	rm -rf ip/*
-	mkdir -p ip
-	rm -rf ${PROJECT}.*
-	rm -rf component.xml
-	rm -rf vivado*.jou
-	rm -rf vivado*.log
-	rm -rf vivado*.str
-	rm -rf xgui
-	rm -rf .Xil
-
-help: ## Shows this help message
-	@grep -E -h '^[a-zA-Z0-9_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'
diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/tcl/run.tcl b/fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/tcl/run.tcl
deleted file mode 100644
index 0ae49ff0..00000000
--- a/fpga/pulpissimo-genesys2/ips/xilinx_clk_mngr/tcl/run.tcl
+++ /dev/null
@@ -1,49 +0,0 @@
-set partNumber $::env(XILINX_PART)
-
-if [info exists ::env(BOARD)] {
-    set BOARD $::env(BOARD)
-} else {
-    error "BOARD is not defined. Please source the sourceme.sh file."
-    exit
-}
-if [info exists ::env(XILINX_BOARD)] {
-	set boardName  $::env(XILINX_BOARD)
-}
-
-# detect target clock
-if [info exists ::env(FC_CLK_PERIOD_NS)] {
-    set FC_CLK_PERIOD_NS $::env(FC_CLK_PERIOD_NS)
-} else {
-    set FC_CLK_PERIOD_NS 10.000
-}
-if [info exists ::env(PER_CLK_PERIOD_NS)] {
-    set PER_CLK_PERIOD_NS $::env(PER_CLK_PERIOD_NS)
-} else {
-    set PER_CLK_PERIOD_NS 20.000
-}
-
-
-set FC_CLK_FREQ_MHZ [expr 1000 / $FC_CLK_PERIOD_NS]
-set PER_CLK_FREQ_MHZ [expr 1000 / $PER_CLK_PERIOD_NS]
-
-set ipName xilinx_clk_mngr
-
-create_project $ipName . -part $partNumber
-set_property board_part $boardName [current_project]
-
-create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
-
-set_property -dict [eval list CONFIG.PRIM_IN_FREQ {200.000} \
-                        CONFIG.NUM_OUT_CLKS {2} \
-                        CONFIG.CLKOUT2_USED {true} \
-                        CONFIG.RESET_TYPE {ACTIVE_LOW} \
-                        CONFIG.RESET_PORT {resetn} \
-                        CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {$FC_CLK_FREQ_MHZ} \
-                        CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {$PER_CLK_FREQ_MHZ} \
-                        CONFIG.CLKIN1_JITTER_PS {50.0} \
-                       ] [get_ips $ipName]
-
-generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_interleaved_ram/Makefile b/fpga/pulpissimo-genesys2/ips/xilinx_interleaved_ram/Makefile
deleted file mode 100644
index 08752831..00000000
--- a/fpga/pulpissimo-genesys2/ips/xilinx_interleaved_ram/Makefile
+++ /dev/null
@@ -1,37 +0,0 @@
-PROJECT:=xilinx_interleaved_ram
-VIVADO ?= vivado
-VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
-MODE=batch
-
-include ../../fpga-settings.mk
-
-.DEFAULT_GOAL:=help
-
-.PHONY: help all gui clean
-
-all: MODE=batch ## Create and synthesize the IP in batch mode.
-
-gui: MODE=gui  ## Create and synthesize the IP in GUI mode.
-
-all gui: $(PROJECT).xpr
-
-$(PROJECT).xpr: ../../fpga-settings.mk tcl/run.tcl
-	make clean
-	$(VIVADO) -mode $(MODE) -source tcl/run.tcl
-	mkdir -p ip
-	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
-	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
-
-clean: ## Remove all build products
-	rm -rf ip/*
-	mkdir -p ip
-	rm -rf ${PROJECT}.*
-	rm -rf component.xml
-	rm -rf vivado*.jou
-	rm -rf vivado*.log
-	rm -rf vivado*.str
-	rm -rf xgui
-	rm -rf .Xil
-
-help: ## Shows this help message
-	@grep -E -h '^[a-zA-Z0-9_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'
diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_interleaved_ram/tcl/run.tcl b/fpga/pulpissimo-genesys2/ips/xilinx_interleaved_ram/tcl/run.tcl
deleted file mode 100644
index a2e84f23..00000000
--- a/fpga/pulpissimo-genesys2/ips/xilinx_interleaved_ram/tcl/run.tcl
+++ /dev/null
@@ -1,38 +0,0 @@
-set partNumber $::env(XILINX_PART)
-
-if [info exists ::env(BOARD)] {
-    set BOARD $::env(BOARD)
-} else {
-    error "BOARD is not defined. Please source the sourceme.sh file."
-    exit
-}
-if [info exists ::env(XILINX_BOARD)] {
-	set boardName  $::env(XILINX_BOARD)
-}
-
-# detect target ram size
-if [info exists ::env(INTERLEAVED_BANK_SIZE)] {
-    set INTERLEAVED_BANK_SIZE $::env(INTERLEAVED_BANK_SIZE)
-} else {
-    set INTERLEAVED_BANK_SIZE 4096
-}
-
-set ipName xilinx_interleaved_ram
-
-create_project $ipName . -part $partNumber
-set_property board_part $boardName [current_project]
-
-create_ip -name blk_mem_gen -vendor xilinx.com -library ip -module_name $ipName
-
-set_property -dict [eval list CONFIG.Use_Byte_Write_Enable {true} \
-                     CONFIG.Byte_Size {8} \
-                     CONFIG.Write_Width_A {32} \
-                     CONFIG.Write_Depth_A {$INTERLEAVED_BANK_SIZE} \
-                     CONFIG.Read_Width_A {32} \
-                     CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
-                    ] [get_ips $ipName]
-
-generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_private_ram/Makefile b/fpga/pulpissimo-genesys2/ips/xilinx_private_ram/Makefile
deleted file mode 100644
index 4734e7ad..00000000
--- a/fpga/pulpissimo-genesys2/ips/xilinx_private_ram/Makefile
+++ /dev/null
@@ -1,37 +0,0 @@
-PROJECT:=xilinx_private_ram
-VIVADO ?= vivado
-VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
-MODE=batch
-
-include ../../fpga-settings.mk
-
-.DEFAULT_GOAL:=help
-
-.PHONY: help all gui clean
-
-all: MODE=batch ## Create and synthesize the IP in batch mode.
-
-gui: MODE=gui  ## Create and synthesize the IP in GUI mode.
-
-all gui: $(PROJECT).xpr
-
-$(PROJECT).xpr: ../../fpga-settings.mk tcl/run.tcl
-	make clean
-	$(VIVADO) -mode $(MODE) -source tcl/run.tcl
-	mkdir -p ip
-	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
-	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
-
-clean: ## Remove all build products
-	rm -rf ip/*
-	mkdir -p ip
-	rm -rf ${PROJECT}.*
-	rm -rf component.xml
-	rm -rf vivado*.jou
-	rm -rf vivado*.log
-	rm -rf vivado*.str
-	rm -rf xgui
-	rm -rf .Xil
-
-help: ## Shows this help message
-	@grep -E -h '^[a-zA-Z0-9_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'
diff --git a/fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/tcl/run.tcl b/fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/tcl/run.tcl
deleted file mode 100644
index a7cfbf0c..00000000
--- a/fpga/pulpissimo-genesys2/ips/xilinx_slow_clk_mngr/tcl/run.tcl
+++ /dev/null
@@ -1,45 +0,0 @@
-set partNumber $::env(XILINX_PART)
-
-if [info exists ::env(BOARD)] {
-    set BOARD $::env(BOARD)
-} else {
-    error "BOARD is not defined. Please source the sourceme.sh file."
-    exit
-}
-if [info exists ::env(XILINX_BOARD)] {
-	set boardName  $::env(XILINX_BOARD)
-}
-
-# detect target clock
-if [info exists ::env(SLOW_CLK_PERIOD_NS)] {
-    set SLOW_CLK_PERIOD_NS $::env(SLOW_CLK_PERIOD_NS)
-} else {
-    set SLOW_CLK_PERIOD_NS 30517
-}
-
-# Multiply frequency by 250 as there is a clock divider (by 250) after the
-# slow_clk_mngr since the MMCMs do not support clocks slower then 4.69 MHz.
-set SLOW_CLK_FREQ_MHZ [expr 1000 * 256 / $SLOW_CLK_PERIOD_NS]
-
-set ipName xilinx_slow_clk_mngr
-
-create_project $ipName . -part $partNumber
-set_property board_part $boardName [current_project]
-
-create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
-
-set_property -dict [eval list CONFIG.PRIM_IN_FREQ {200.000} \
-                        CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {$SLOW_CLK_FREQ_MHZ} \
-                        CONFIG.USE_SAFE_CLOCK_STARTUP {true} \
-                        CONFIG.USE_LOCKED {false} \
-                        CONFIG.RESET_TYPE {ACTIVE_LOW} \
-                        CONFIG.CLKIN1_JITTER_PS {50.0} \
-                        CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \
-                        CONFIG.RESET_PORT {resetn} \
-                       ] [get_ips $ipName]
-
-
-generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
diff --git a/fpga/pulpissimo-genesys2/openocd-genesys2.cfg b/fpga/pulpissimo-genesys2/openocd-genesys2.cfg
deleted file mode 100644
index b0de8583..00000000
--- a/fpga/pulpissimo-genesys2/openocd-genesys2.cfg
+++ /dev/null
@@ -1,46 +0,0 @@
-adapter_khz     1000
-
-interface ftdi
-ftdi_vid_pid 0x0403 0x6010
-
-# Channel 1 is taken by Xilinx JTAG
-ftdi_channel 0
-
-# links:
-# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html
-# 
-# Bit  MPSSE     FT2232    JTAG    Type   Description
-# Bit0 TCK       ADBUS0    TCK     Out    Clock Signal Output
-# Bit1 TDI       ADBUS1    TDI     Out    Serial Data Out
-# Bit2 TDO       ADBUS2    TDO     In     Serial Data In
-# Bit3 TMS       ADBUS3    TMS     Out    Select Signal Out
-# Bit4 GPIOL0    ADBUS4    nTRST   In/Out General Purpose I/O 
-# this corresponds to the following in/out layout, with TMS initially set to 1
-ftdi_layout_init 0x0018 0x001b
-# we only have to specify nTRST, the others are assigned correctly by default
-ftdi_layout_signal nTRST -ndata 0x0010
-
-set _CHIPNAME riscv
-
-jtag newtap $_CHIPNAME unknown0 -irlen 5 -expected-id 0x10102001
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x249511C3
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0x3e0
-
-gdb_report_data_abort enable
-gdb_report_register_access_error enable
-
-riscv set_reset_timeout_sec 120
-riscv set_command_timeout_sec 120
-
-# prefer to use sba for system bus access
-riscv set_prefer_sba on
-
-# dump jtag chain
-scan_chain
-
-
-init
-halt
-echo "Ready for Remote Connections"
diff --git a/fpga/pulpissimo-genesys2/rtl/xilinx_pulpissimo.v b/fpga/pulpissimo-genesys2/rtl/xilinx_pulpissimo.v
deleted file mode 100644
index b301a900..00000000
--- a/fpga/pulpissimo-genesys2/rtl/xilinx_pulpissimo.v
+++ /dev/null
@@ -1,148 +0,0 @@
-//-----------------------------------------------------------------------------
-// Title         : PULPissimo Verilog Wrapper
-//-----------------------------------------------------------------------------
-// File          : xilinx_pulpissimo.v
-// Author        : Manuel Eggimann  <meggimann@iis.ee.ethz.ch>
-// Created       : 21.05.2019
-//-----------------------------------------------------------------------------
-// Description :
-// Verilog Wrapper of PULPissimo to use the module within Xilinx IP integrator.
-//-----------------------------------------------------------------------------
-// Copyright (C) 2013-2019 ETH Zurich, University of Bologna
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License. You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-//-----------------------------------------------------------------------------
-
-module xilinx_pulpissimo
-  (
-   input wire  ref_clk_p,
-   input wire  ref_clk_n,
-
-//   inout wire  pad_spim_sdio0,
-   inout wire  pad_spim_sdio1,
-   inout wire  pad_spim_sdio2,
-   inout wire  pad_spim_sdio3,
-   inout wire  pad_spim_csn0,
-   inout wire  pad_spim_sck,
-
-   inout wire  pad_uart_rx,
-   inout wire  pad_uart_tx,
-
-   inout wire  led0_o, //Mapped to spim_csn1
-   inout wire  led1_o, //Mapped to cam_pclk
-   inout wire  led2_o, //Mapped to cam_hsync
-   inout wire  led3_o, //Mapped to cam_data0
-
-   inout wire  switch0_i, //Mapped to cam_data1
-   inout wire  switch1_i, //Mapped to cam_data2
-
-   inout wire  btnc_i, //Mapped to cam_data3
-   inout wire  btnd_i, //Mapped to cam_data4
-   inout wire  btnl_i, //Mapped to cam_data5
-   inout wire  btnr_i, //Mapped to cam_data6
-   inout wire  btnu_i, //Mapped to cam_data7
-
-   inout wire  oled_spim_sck_o, //Mapped to spim_sck
-   inout wire  oled_spim_mosi_o, //Mapped to spim_sdio0
-   inout wire  oled_rst_o, //Mapped to i2s0_sck
-   inout wire  oled_dc_o, //Mapped to i2s0_ws
-   inout wire  oled_vbat_o, // Mapped to i2s0_sdi
-   inout wire  oled_vdd_o, // Mapped to i2s1_sdi
-
-   inout wire  sdio_reset_o, //Reset signal for SD card need to be driven low to
-                             //power the onboard sd-card. Mapped to cam_vsync.
-   inout wire  pad_sdio_clk,
-   inout wire  pad_sdio_cmd,
-   inout wire  pad_sdio_data0,
-   inout wire  pad_sdio_data1,
-   inout wire  pad_sdio_data2,
-   inout wire  pad_sdio_data3,
-
-   inout wire  pad_i2c0_sda,
-   inout wire  pad_i2c0_scl,
-
-   input wire  pad_reset_n,
-   inout wire  pad_bootsel,
-
-   input wire  pad_jtag_tck,
-   input wire  pad_jtag_tdi,
-   output wire pad_jtag_tdo,
-   input wire  pad_jtag_tms,
-   input wire  pad_jtag_trst
- );
-
-  localparam CORE_TYPE = 0; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY)
-  localparam USE_FPU   = 1;
-  localparam USE_HWPE = 0;
-
-  wire        ref_clk;
-
-
-  //Differential to single ended clock conversion
-  IBUFGDS
-    #(
-      .IOSTANDARD("LVDS"),
-      .DIFF_TERM("FALSE"),
-      .IBUF_LOW_PWR("FALSE"))
-  i_sysclk_iobuf
-    (
-     .I(ref_clk_p),
-     .IB(ref_clk_n),
-     .O(ref_clk)
-     );
-
-  pulpissimo
-    #(.CORE_TYPE(CORE_TYPE),
-      .USE_FPU(USE_FPU),
-      .USE_HWPE(USE_HWPE)
-      ) i_pulpissimo
-      (
-       .pad_spim_sdio0(oled_spim_mosi_o),
-       .pad_spim_sdio1(pad_spim_sdio1),
-       .pad_spim_sdio2(pad_spim_sdio2),
-       .pad_spim_sdio3(pad_spim_sdio3),
-       .pad_spim_csn0(pad_spim_csn0),
-       .pad_spim_csn1(led0_o),
-       .pad_spim_sck(oled_spim_sck_o),
-       .pad_uart_rx(pad_uart_rx),
-       .pad_uart_tx(pad_uart_tx),
-       .pad_cam_pclk(led1_o),
-       .pad_cam_hsync(led2_o),
-       .pad_cam_data0(led3_o),
-       .pad_cam_data1(switch0_i),
-       .pad_cam_data2(switch1_i),
-       .pad_cam_data3(btnc_i),
-       .pad_cam_data4(btnd_i),
-       .pad_cam_data5(btnl_i),
-       .pad_cam_data6(btnr_i),
-       .pad_cam_data7(btnu_i),
-       .pad_cam_vsync(sdio_reset_o),
-       .pad_sdio_clk(pad_sdio_clk),
-       .pad_sdio_cmd(pad_sdio_cmd),
-       .pad_sdio_data0(pad_sdio_data0),
-       .pad_sdio_data1(pad_sdio_data1),
-       .pad_sdio_data2(pad_sdio_data2),
-       .pad_sdio_data3(pad_sdio_data3),
-       .pad_i2c0_sda(pad_i2c0_sda),
-       .pad_i2c0_scl(pad_i2c0_scl),
-       .pad_i2s0_sck(oled_rst_o),
-       .pad_i2s0_ws(oled_dc_o),
-       .pad_i2s0_sdi(oled_vbat_o),
-       .pad_i2s1_sdi(oled_vdd_o),
-       .pad_reset_n(pad_reset_n),
-       .pad_jtag_tck(pad_jtag_tck),
-       .pad_jtag_tdi(pad_jtag_tdi),
-       .pad_jtag_tdo(pad_jtag_tdo),
-       .pad_jtag_tms(pad_jtag_tms),
-       .pad_jtag_trst(pad_jtag_trst),
-       .pad_xtal_in(ref_clk),
-       .pad_bootsel()
-       );
-
-endmodule
diff --git a/fpga/pulpissimo-genesys2/tcl/.gitignore b/fpga/pulpissimo-genesys2/tcl/.gitignore
deleted file mode 100644
index 587a0fa6..00000000
--- a/fpga/pulpissimo-genesys2/tcl/.gitignore
+++ /dev/null
@@ -1,6 +0,0 @@
-#Ignore tcl files generated by ipstools
-ips_add_files.tcl
-ips_inc_dirs.tcl
-ips_src_files.tcl
-rtl_add_files.tcl
-rtl_src_files.tcl
\ No newline at end of file
diff --git a/fpga/pulpissimo-genesys2/tcl/run.tcl b/fpga/pulpissimo-genesys2/tcl/run.tcl
deleted file mode 100644
index b62025a7..00000000
--- a/fpga/pulpissimo-genesys2/tcl/run.tcl
+++ /dev/null
@@ -1,132 +0,0 @@
-set project pulpissimo_genesys2
-set RTL ../../../rtl
-set IPS ../../../ips
-set CONSTRS constraints
-
-
-# detect board
-if [info exists ::env(BOARD)] {
-    set BOARD $::env(BOARD)
-} else {
-    puts "Please execute 'source ../sourceme.sh first before you start vivado in order to setup necessary environment variables."
-    exit
-}
-if [info exists ::env(XILINX_BOARD)] {
-    set XILINX_BOARD $::env(XILINX_BOARD)
-}
-
-# create project
-create_project $project . -force -part $::env(XILINX_PART)
-set_property board_part $XILINX_BOARD [current_project]
-
-# set up meaningfull errors
-source tcl/messages.tcl
-
-# set up includes
-source ../pulpissimo/tcl/ips_inc_dirs.tcl
-set_property include_dirs $INCLUDE_DIRS [current_fileset]
-set_property include_dirs $INCLUDE_DIRS [current_fileset -simset]
-
-# setup and add IP source files
-source ../pulpissimo/tcl/ips_src_files.tcl
-source ../pulpissimo/tcl/ips_add_files.tcl
-
-# setup and add RTL source files
-source ../pulpissimo/tcl/rtl_src_files.tcl
-source ../pulpissimo/tcl/rtl_add_files.tcl
-
-# Override IPSApprox default variables
-set FPGA_RTL rtl
-set FPGA_IPS ips
-
-# remove duplicate incompatible modules
-remove_files $IPS/pulp_soc/rtl/components/axi_slice_dc_slave_wrap.sv
-remove_file $IPS/pulp_soc/rtl/components/axi_slice_dc_master_wrap.sv
-remove_file $IPS/tech_cells_generic/pad_functional_xilinx.sv
-
-# Set Verilog Defines.
-set DEFINES "FPGA_TARGET_XILINX=1 PULP_FPGA_EMUL=1 AXI4_XCHECK_OFF=1"
-if { $BOARD == "genesys2" } {
-    set DEFINES "$DEFINES GENESYS2=1"
-}
-set_property verilog_define $DEFINES [current_fileset]
-
-# detect target clock
-if [info exists ::env(FC_CLK_PERIOD_NS)] {
-    set FC_CLK_PERIOD_NS $::env(FC_CLK_PERIOD_NS)
-} else {
-    set FC_CLK_PERIOD_NS 10.000
-}
-set CLK_HALFPERIOD_NS [expr ${FC_CLK_PERIOD_NS} / 2.0]
-
-# Add toplevel wrapper
-add_files -norecurse $FPGA_RTL/xilinx_pulpissimo.v
-
-# Add Xilinx IPs
-read_ip $FPGA_IPS/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci
-read_ip $FPGA_IPS/xilinx_slow_clk_mngr/ip/xilinx_slow_clk_mngr.xci
-read_ip $FPGA_IPS/xilinx_interleaved_ram/ip/xilinx_interleaved_ram.xci
-read_ip $FPGA_IPS/xilinx_private_ram/ip/xilinx_private_ram.xci
-
-# Add wrappers and xilinx specific techcells
-add_files -norecurse $FPGA_RTL/fpga_clk_gen.sv
-add_files -norecurse $FPGA_RTL/fpga_slow_clk_gen.sv
-add_files -norecurse $FPGA_RTL/fpga_interleaved_ram.sv
-add_files -norecurse $FPGA_RTL/fpga_private_ram.sv
-add_files -norecurse $FPGA_RTL/fpga_bootrom.sv
-add_files -norecurse $FPGA_RTL/pad_functional_xilinx.sv
-add_files -norecurse $FPGA_RTL/pulp_clock_gating_xilinx.sv
-
-
-# set pulpissimo as top
-set_property top xilinx_pulpissimo [current_fileset]; #
-
-# needed only if used in batch mode
-update_compile_order -fileset sources_1
-
-# Add constraints
-add_files -fileset constrs_1 -norecurse $CONSTRS/genesys2.xdc
-
-# Elaborate design
-synth_design -rtl -name rtl_1 -sfcu;# sfcu -> run synthesis in single file compilation unit mode
-
-
-
-# launch synthesis
-set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY none [get_runs synth_1]
-set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value -sfcu -objects [get_runs synth_1] ;# Use single file compilation unit mode to prevent issues with import pkg::* statements in the codebase
-launch_runs synth_1 -jobs 8
-wait_on_run synth_1
-open_run synth_1 -name netlist_1
-set_property needs_refresh false [get_runs synth_1]
-
-# Remove unused IOBUF cells in padframe (they are not optimized away since the
-# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i
-# )
-remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel
-
-
-# Launch Implementation
-
-# set for RuntimeOptimized implementation
-set_property "steps.opt_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
-set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
-set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
-
-set_property STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE true [get_runs impl_1]
-set_property config_mode SPIx4 [current_design]
-
-launch_runs impl_1 -jobs 8
-wait_on_run impl_1
-launch_runs impl_1 -to_step write_bitstream
-wait_on_run impl_1
-
-open_run impl_1
-
-# Generate reports
-exec mkdir -p reports/
-exec rm -rf reports/*
-check_timing                                                              -file reports/${project}.check_timing.rpt
-report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack   -file reports/${project}.timing_WORST_100.rpt
-report_timing -nworst 1 -delay_type max -sort_by group                    -file reports/${project}.timing.rpt
-report_utilization -hierarchical                                          -file reports/${project}.utilization.rpt
diff --git a/fpga/pulpissimo-nexys_video/.gitignore b/fpga/pulpissimo-nexys_video/.gitignore
deleted file mode 100644
index 58cd8944..00000000
--- a/fpga/pulpissimo-nexys_video/.gitignore
+++ /dev/null
@@ -1,22 +0,0 @@
-#Ignore vivado project files generated by the tcl script
-**/.Xil/*
-**/reports/*
-**/*.cache/*
-**/*.hw/*
-**/*.ip_user_files/*
-**/*.runs/*
-**/*.sim/*
-**/*.srcs/*
-*.edf
-*.xpr
-*.jou
-*.log
-
-.cxl.*
-
-*_stub.v
-gmon.out
-
-/pulpissimo-nexys_video/**/pulpissimo.bit
-
-**/xdc/constraints.xdc
diff --git a/fpga/pulpissimo-nexys_video/Makefile b/fpga/pulpissimo-nexys_video/Makefile
deleted file mode 100644
index 5b436097..00000000
--- a/fpga/pulpissimo-nexys_video/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-PROJECT:=pulpissimo-nexys_video
-VIVADO ?= vivado
-VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
-
-include fpga-settings.mk
-
-.DEFAULT_GOAL:=help
-
-.PHONY: help all gui ips clean-ips clk clean-clk ram clean-ram clean
-
-all: ips ## Generate the bitstream for pulpissimo with vivado in batch mode. The vivado invocation command may be overriden with the env variable VIVADO.
-	$(VIVADO) -mode batch -source tcl/run.tcl
-
-gui: ips ## Generates the bitstream for pulpissimo with vivado in GUI mode. The vivado invocation command may be overriden with the env variable VIVADO.
-	$(VIVADO) -mode gui -source tcl/run.tcl &
-
-ips: clk ram ## Synthesizes necessary xilinx IP
-
-clean-ips: clean-clk clean-ram ## Clean all IPs
-
-clk: ## Synthesizes the Xilinx Clocking Manager IPs
-	cd ips/xilinx_clk_mngr; make all
-	cd ips/xilinx_slow_clk_mngr; make all
-
-clean-clk: ## Removes all Clocking Wizard IP outputs
-	cd ips/xilinx_clk_mngr; make clean
-	cd ips/xilinx_slow_clk_mngr; make clean
-
-ram: ## Synthesizes the Xilinx Block Memory Generator IPs for PULPissimo's L2 Ram
-	cd ips/xilinx_interleaved_ram; make all
-	cd ips/xilinx_private_ram; make all
-
-clean-ram: ## Removes all Block Ram IP outputs related to l2 ram
-	cd ips/xilinx_interleaved_ram; make clean
-	cd ips/xilinx_private_ram; make clean
-
-clean: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*)
-	rm -rf ${PROJECT}.*[^'bit']
-	rm -rf ${PROJECT}.*[^'bin']
-	rm -rf *.log
-	rm -rf vivado*
-
-help:
-	@grep -E -h '^[a-zA-Z_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'
diff --git a/fpga/pulpissimo-nexys_video/README.md b/fpga/pulpissimo-nexys_video/README.md
deleted file mode 100644
index 354967f5..00000000
--- a/fpga/pulpissimo-nexys_video/README.md
+++ /dev/null
@@ -1,55 +0,0 @@
-# PULPissimo on the Digilent Nexys Video Board
-[\[Documentation\]](https://reference.digilentinc.com/reference/programmable-logic/nexys-video/start)
-
-## Bitstream Generation
-In the fpga folder, run
-```Shell
-make nexys_video
-```
-which will generate `pulpissimo_nexys_video.bit`.
-Use Vivado to load it into the FPGA.
-
-## Default SoC and Core Frequencies
-
-By default the clock generating IPs are synthesized to provide the following frequencies to PULPissimo:
-
-| Clock Domain   | Default Frequency on Nexys Video board |
-|----------------|----------------------------------------|
-| Core Frequency | 10 MHz                                 |
-| SoC Frequency  |  5 MHz                                 |
-
-
-## Peripherals
-PULPissimo is connected to the following board peripherals:
-
-
-| PULPissimo Pin | Mapped Board Peripheral                             |
-|----------------|-----------------------------------------------------|
-| `SPIM0` pins   | QSPI Flash                                          |
-| `I2C0` pins    | I2C Bus (connects to the ADAU1761 audio codec)      |
-| `spim_csn1`    | LED0                                                |
-| `cam_pclk`     | LED1                                                |
-| `cam_hsync`    | LED2                                                |
-| `cam_data0`    | LED3                                                |
-| `cam_data1`    | Switch 0                                            |
-| `cam_data2`    | Switch 1                                            |
-| `cam_data3`    | Button C                                            |
-| `cam_data4`    | Button D                                            |
-| `cam_data5`    | Button L                                            |
-| `cam_data6`    | Button R                                            |
-| `cam_data7`    | Button U                                            |
-
-### Reset Button
-The CPU RESET button (G4) resets the RISC-V CPU.
-
-### UART
-PULPissimo's UART port is mapped to the onboard FTDI FT232R USB-UART bridge and thus accessible through the UART micro-USB connector (J13).
-
-### JTAG
-PULPIssimo's JTAG plug is connected to Channel 0 of the onboard FTDI USB JTAG programmer.
-Therefore we can attach OpenOCD withouth the need of an external JTAG programmer.
-Just attach a micro-USB cable to the PROG micro-USB connector (J12) and use the provided OpenOCD configuration file:
-
-```Shell
-$OPENOCD/bin/openocd -f pulpissimo/fpga/pulpissimo-nexys_video/openocd-nexys_video.cfg
-```
diff --git a/fpga/pulpissimo-nexys_video/constraints/nexys_video.xdc b/fpga/pulpissimo-nexys_video/constraints/nexys_video.xdc
deleted file mode 100644
index b0e8e841..00000000
--- a/fpga/pulpissimo-nexys_video/constraints/nexys_video.xdc
+++ /dev/null
@@ -1,138 +0,0 @@
-#######################################
-#  _______ _           _              #
-# |__   __(_)         (_)             #
-#    | |   _ _ __ ___  _ _ __   __ _  #
-#    | |  | | '_ ` _ \| | '_ \ / _` | #
-#    | |  | | | | | | | | | | | (_| | #
-#    |_|  |_|_| |_| |_|_|_| |_|\__, | #
-#                               __/ | #
-#                              |___/  #
-#######################################
-
-
-#Create constraint for the clock input of the nexys video board
-create_clock -period 10.000 -name ref_clk [get_ports sys_clk]
-
-#I2S and CAM interface are not used in this FPGA port. Set constraints to
-#disable the clock
-set_case_analysis 0 i_pulpissimo/safe_domain_i/cam_pclk_o
-set_case_analysis 0 i_pulpissimo/safe_domain_i/i2s_slave_sck_o
-#set_input_jitter tck 1.000
-
-## JTAG
-create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_jtag_tck]
-set_input_jitter tck 1.000
-
-
-# minimize routing delay
-set_input_delay -clock tck -clock_fall 5.000 [get_ports pad_jtag_tdi]
-set_input_delay -clock tck -clock_fall 5.000 [get_ports pad_jtag_tms]
-set_output_delay -clock tck 5.000 [get_ports pad_jtag_tdo]
-set_false_path -from [get_ports pad_jtag_trst]
-
-set_max_delay -to [get_ports pad_jtag_tdo] 20.000
-set_max_delay -from [get_ports pad_jtag_tms] 20.000
-set_max_delay -from [get_ports pad_jtag_tdi] 20.000
-set_max_delay -from [get_ports pad_jtag_trst] 20.000
-
-set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000
-set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000
-set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000
-
-
-# reset signal
-set_false_path -from [get_ports pad_reset_n]
-
-# Set ASYNC_REG attribute for ff synchronizers to place them closer together and
-# increase MTBF
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/apb_adv_timer_i/u_tim0/u_in_stage/r_ls_clk_sync_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/apb_adv_timer_i/u_tim1/u_in_stage/r_ls_clk_sync_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/apb_adv_timer_i/u_tim2/u_in_stage/r_ls_clk_sync_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/apb_adv_timer_i/u_tim3/u_in_stage/r_ls_clk_sync_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*]
-
-# Create asynchronous clock group between slow-clk and SoC clock. Those clocks
-# are considered asynchronously and proper synchronization regs are in place
-set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/safe_domain_i/i_slow_clk_gen/i_slow_clk_mngr/inst/mmcm_adv_inst/CLKOUT0]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fpga_clk_gen/i_clk_manager/inst/mmcm_adv_inst/CLKOUT0]]
-
-
-#############################################################
-#  _____ ____         _____      _   _   _                  #
-# |_   _/ __ \       / ____|    | | | | (_)                 #
-#   | || |  | |_____| (___   ___| |_| |_ _ _ __   __ _ ___  #
-#   | || |  | |______\___ \ / _ \ __| __| | '_ \ / _` / __| #
-#  _| || |__| |      ____) |  __/ |_| |_| | | | | (_| \__ \ #
-# |_____\____/      |_____/ \___|\__|\__|_|_| |_|\__, |___/ #
-#                                                 __/ |     #
-#                                                |___/      #
-#############################################################
-
-## Sys clock
-set_property -dict {PACKAGE_PIN R4  IOSTANDARD LVCMOS33} [get_ports sys_clk]
-
-## Buttons
-set_property -dict {PACKAGE_PIN G4  IOSTANDARD LVCMOS15} [get_ports pad_reset_n]
-set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS12} [get_ports btnc_i]
-set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS12} [get_ports btnd_i]
-set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS12} [get_ports btnl_i]
-set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS12} [get_ports btnr_i]
-set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS12} [get_ports btnu_i]
-
-## To use FTDI FT2232 JTAG
-set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports pad_jtag_trst]
-set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tck]
-set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tdi]
-set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tdo]
-set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tms]
-
-## UART
-set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports pad_uart_tx]
-set_property -dict {PACKAGE_PIN V18  IOSTANDARD LVCMOS33} [get_ports pad_uart_rx]
-
-## LEDs
-set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports led0_o]
-set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports led1_o]
-set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports led2_o]
-set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS25} [get_ports led3_o]
-
-## Switches
-set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS12} [get_ports switch0_i]
-set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS12} [get_ports switch1_i]
-
-## I2C Bus
-set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS33} [get_ports pad_i2c0_scl]
-set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports pad_i2c0_sda]
-
-## QSPI Flash
-set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports pad_spim_csn0]
-#set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS33} [get_ports { pad_spim_sdio0 }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
-set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports pad_spim_sdio1]
-set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports pad_spim_sdio2]
-set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS33} [get_ports pad_spim_sdio3]
-
-## OLED Display
-set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports oled_dc_o]
-set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports oled_rst_o]
-set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports oled_spim_sck_o]
-set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS33} [get_ports oled_spim_mosi_o]
-set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports oled_vbat_o]
-set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports oled_vdd_o]
-
-## SD Card
-set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports pad_sdio_clk]
-#set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports { sd_cd }]; #IO_L20N_T3_A07_D23_14 Sch=sd_cd
-set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports pad_sdio_cmd]
-set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports pad_sdio_data0]
-set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports pad_sdio_data1]
-set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports pad_sdio_data2]
-set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports pad_sdio_data3]
-set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports sdio_reset_o]
-
-# Nexys Video has a quad SPI flash
-set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
-
-# Configuration options, can be used for all designs
-set_property CONFIG_VOLTAGE 3.3 [current_design]
-set_property CFGBVS VCCO [current_design]
diff --git a/fpga/pulpissimo-nexys_video/elf_run.gdb b/fpga/pulpissimo-nexys_video/elf_run.gdb
deleted file mode 100644
index cba53bd0..00000000
--- a/fpga/pulpissimo-nexys_video/elf_run.gdb
+++ /dev/null
@@ -1,4 +0,0 @@
-target remote localhost:3333
-monitor reset halt
-load
-continue
\ No newline at end of file
diff --git a/fpga/pulpissimo-nexys_video/elf_run.sh b/fpga/pulpissimo-nexys_video/elf_run.sh
deleted file mode 100755
index a17ade42..00000000
--- a/fpga/pulpissimo-nexys_video/elf_run.sh
+++ /dev/null
@@ -1,15 +0,0 @@
-#!/bin/bash
-
-trap "exit" INT TERM
-trap "kill 0" EXIT
-
-
-SCRIPTDIR=$(dirname $0)
-
-#Execute gdb and connect to openocd via pipe
-$OPENOCD/bin/openocd -f $SCRIPTDIR/openocd-nexys_video.cfg &
-$PULP_RISCV_GCC_TOOLCHAIN_CI/bin/riscv32-unknown-elf-gdb -x $SCRIPTDIR/elf_run.gdb $1 &
-sleep 3
-minicom -D /dev/ttyUSB0 -b 115200
-
-
diff --git a/fpga/pulpissimo-nexys_video/fpga-settings.mk b/fpga/pulpissimo-nexys_video/fpga-settings.mk
deleted file mode 100644
index 1b30bc93..00000000
--- a/fpga/pulpissimo-nexys_video/fpga-settings.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-export BOARD=nexys_video
-export XILINX_PART=xc7a200tsbg484-1
-export XILINX_BOARD=digilentinc.com:nexys_video:1.1
-export FC_CLK_PERIOD_NS=100
-export PER_CLK_PERIOD_NS=200
-export SLOW_CLK_PERIOD_NS=30517
-#Must also change the localparam 'L2_BANK_SIZE' in pulp_soc.sv accordingly
-export INTERLEAVED_BANK_SIZE=28672
-#Must also change the localparam 'L2_BANK_SIZE_PRI' in pulp_soc.sv accordingly
-export PRIVATE_BANK_SIZE=8192
-$(info Setting environment variables for $(BOARD) board)
diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/.gitignore b/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/.gitignore
deleted file mode 100644
index 5099fe9c..00000000
--- a/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/.gitignore
+++ /dev/null
@@ -1,21 +0,0 @@
-#Ignore vivado project files generated by the tcl script
-**/.Xil/*
-**/reports/*
-**/*.cache/*
-**/*.hw/*
-**/*.ip_user_files/*
-**/*.runs/*
-**/*.sim/*
-**/*.srcs/*
-*.edf
-*.xpr
-*.jou
-*.log
-
-.cxl.*
-
-*ip
-
-*_stub.v
-gmon.out
-
diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/Makefile b/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/Makefile
deleted file mode 100644
index 978b9cee..00000000
--- a/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/Makefile
+++ /dev/null
@@ -1,37 +0,0 @@
-PROJECT:=xilinx_clk_mngr
-VIVADO ?= vivado
-VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
-MODE=batch
-
-include ../../fpga-settings.mk
-
-.DEFAULT_GOAL:=help
-
-.PHONY: help all gui clean
-
-all: MODE=batch ## Create and synthesize the IP in batch mode.
-
-gui: MODE=gui  ## Create and synthesize the IP in GUI mode.
-
-all gui: $(PROJECT).xpr
-
-$(PROJECT).xpr: ../../fpga-settings.mk tcl/run.tcl
-	make clean
-	$(VIVADO) -mode $(MODE) -source tcl/run.tcl
-	mkdir -p ip
-	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
-	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
-
-clean: ## Remove all build products
-	rm -rf ip/*
-	mkdir -p ip
-	rm -rf ${PROJECT}.*
-	rm -rf component.xml
-	rm -rf vivado*.jou
-	rm -rf vivado*.log
-	rm -rf vivado*.str
-	rm -rf xgui
-	rm -rf .Xil
-
-help: ## Shows this help message
-	@grep -E -h '^[a-zA-Z0-9_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'
diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/tcl/run.tcl b/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/tcl/run.tcl
deleted file mode 100644
index a6b3d9ea..00000000
--- a/fpga/pulpissimo-nexys_video/ips/xilinx_clk_mngr/tcl/run.tcl
+++ /dev/null
@@ -1,49 +0,0 @@
-set partNumber $::env(XILINX_PART)
-
-if [info exists ::env(BOARD)] {
-    set BOARD $::env(BOARD)
-} else {
-    error "BOARD is not defined. Please source the sourceme.sh file."
-    exit
-}
-if [info exists ::env(XILINX_BOARD)] {
-	set boardName  $::env(XILINX_BOARD)
-}
-
-# detect target clock
-if [info exists ::env(FC_CLK_PERIOD_NS)] {
-    set FC_CLK_PERIOD_NS $::env(FC_CLK_PERIOD_NS)
-} else {
-    set FC_CLK_PERIOD_NS 10.000
-}
-if [info exists ::env(PER_CLK_PERIOD_NS)] {
-    set PER_CLK_PERIOD_NS $::env(PER_CLK_PERIOD_NS)
-} else {
-    set PER_CLK_PERIOD_NS 20.000
-}
-
-
-set FC_CLK_FREQ_MHZ [expr 1000 / $FC_CLK_PERIOD_NS]
-set PER_CLK_FREQ_MHZ [expr 1000 / $PER_CLK_PERIOD_NS]
-
-set ipName xilinx_clk_mngr
-
-create_project $ipName . -part $partNumber
-set_property board_part $boardName [current_project]
-
-create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
-
-set_property -dict [eval list CONFIG.PRIM_IN_FREQ {100.000} \
-                        CONFIG.NUM_OUT_CLKS {2} \
-                        CONFIG.CLKOUT2_USED {true} \
-                        CONFIG.RESET_TYPE {ACTIVE_LOW} \
-                        CONFIG.RESET_PORT {resetn} \
-                        CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {$FC_CLK_FREQ_MHZ} \
-                        CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {$PER_CLK_FREQ_MHZ} \
-                        CONFIG.CLKIN1_JITTER_PS {50.0} \
-                       ] [get_ips $ipName]
-
-generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_interleaved_ram/.gitignore b/fpga/pulpissimo-nexys_video/ips/xilinx_interleaved_ram/.gitignore
deleted file mode 100644
index 5099fe9c..00000000
--- a/fpga/pulpissimo-nexys_video/ips/xilinx_interleaved_ram/.gitignore
+++ /dev/null
@@ -1,21 +0,0 @@
-#Ignore vivado project files generated by the tcl script
-**/.Xil/*
-**/reports/*
-**/*.cache/*
-**/*.hw/*
-**/*.ip_user_files/*
-**/*.runs/*
-**/*.sim/*
-**/*.srcs/*
-*.edf
-*.xpr
-*.jou
-*.log
-
-.cxl.*
-
-*ip
-
-*_stub.v
-gmon.out
-
diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_interleaved_ram/Makefile b/fpga/pulpissimo-nexys_video/ips/xilinx_interleaved_ram/Makefile
deleted file mode 100644
index 08752831..00000000
--- a/fpga/pulpissimo-nexys_video/ips/xilinx_interleaved_ram/Makefile
+++ /dev/null
@@ -1,37 +0,0 @@
-PROJECT:=xilinx_interleaved_ram
-VIVADO ?= vivado
-VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
-MODE=batch
-
-include ../../fpga-settings.mk
-
-.DEFAULT_GOAL:=help
-
-.PHONY: help all gui clean
-
-all: MODE=batch ## Create and synthesize the IP in batch mode.
-
-gui: MODE=gui  ## Create and synthesize the IP in GUI mode.
-
-all gui: $(PROJECT).xpr
-
-$(PROJECT).xpr: ../../fpga-settings.mk tcl/run.tcl
-	make clean
-	$(VIVADO) -mode $(MODE) -source tcl/run.tcl
-	mkdir -p ip
-	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
-	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
-
-clean: ## Remove all build products
-	rm -rf ip/*
-	mkdir -p ip
-	rm -rf ${PROJECT}.*
-	rm -rf component.xml
-	rm -rf vivado*.jou
-	rm -rf vivado*.log
-	rm -rf vivado*.str
-	rm -rf xgui
-	rm -rf .Xil
-
-help: ## Shows this help message
-	@grep -E -h '^[a-zA-Z0-9_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'
diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_interleaved_ram/tcl/run.tcl b/fpga/pulpissimo-nexys_video/ips/xilinx_interleaved_ram/tcl/run.tcl
deleted file mode 100644
index a2e84f23..00000000
--- a/fpga/pulpissimo-nexys_video/ips/xilinx_interleaved_ram/tcl/run.tcl
+++ /dev/null
@@ -1,38 +0,0 @@
-set partNumber $::env(XILINX_PART)
-
-if [info exists ::env(BOARD)] {
-    set BOARD $::env(BOARD)
-} else {
-    error "BOARD is not defined. Please source the sourceme.sh file."
-    exit
-}
-if [info exists ::env(XILINX_BOARD)] {
-	set boardName  $::env(XILINX_BOARD)
-}
-
-# detect target ram size
-if [info exists ::env(INTERLEAVED_BANK_SIZE)] {
-    set INTERLEAVED_BANK_SIZE $::env(INTERLEAVED_BANK_SIZE)
-} else {
-    set INTERLEAVED_BANK_SIZE 4096
-}
-
-set ipName xilinx_interleaved_ram
-
-create_project $ipName . -part $partNumber
-set_property board_part $boardName [current_project]
-
-create_ip -name blk_mem_gen -vendor xilinx.com -library ip -module_name $ipName
-
-set_property -dict [eval list CONFIG.Use_Byte_Write_Enable {true} \
-                     CONFIG.Byte_Size {8} \
-                     CONFIG.Write_Width_A {32} \
-                     CONFIG.Write_Depth_A {$INTERLEAVED_BANK_SIZE} \
-                     CONFIG.Read_Width_A {32} \
-                     CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
-                    ] [get_ips $ipName]
-
-generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_private_ram/.gitignore b/fpga/pulpissimo-nexys_video/ips/xilinx_private_ram/.gitignore
deleted file mode 100644
index 5099fe9c..00000000
--- a/fpga/pulpissimo-nexys_video/ips/xilinx_private_ram/.gitignore
+++ /dev/null
@@ -1,21 +0,0 @@
-#Ignore vivado project files generated by the tcl script
-**/.Xil/*
-**/reports/*
-**/*.cache/*
-**/*.hw/*
-**/*.ip_user_files/*
-**/*.runs/*
-**/*.sim/*
-**/*.srcs/*
-*.edf
-*.xpr
-*.jou
-*.log
-
-.cxl.*
-
-*ip
-
-*_stub.v
-gmon.out
-
diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_private_ram/Makefile b/fpga/pulpissimo-nexys_video/ips/xilinx_private_ram/Makefile
deleted file mode 100644
index 4734e7ad..00000000
--- a/fpga/pulpissimo-nexys_video/ips/xilinx_private_ram/Makefile
+++ /dev/null
@@ -1,37 +0,0 @@
-PROJECT:=xilinx_private_ram
-VIVADO ?= vivado
-VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
-MODE=batch
-
-include ../../fpga-settings.mk
-
-.DEFAULT_GOAL:=help
-
-.PHONY: help all gui clean
-
-all: MODE=batch ## Create and synthesize the IP in batch mode.
-
-gui: MODE=gui  ## Create and synthesize the IP in GUI mode.
-
-all gui: $(PROJECT).xpr
-
-$(PROJECT).xpr: ../../fpga-settings.mk tcl/run.tcl
-	make clean
-	$(VIVADO) -mode $(MODE) -source tcl/run.tcl
-	mkdir -p ip
-	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
-	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
-
-clean: ## Remove all build products
-	rm -rf ip/*
-	mkdir -p ip
-	rm -rf ${PROJECT}.*
-	rm -rf component.xml
-	rm -rf vivado*.jou
-	rm -rf vivado*.log
-	rm -rf vivado*.str
-	rm -rf xgui
-	rm -rf .Xil
-
-help: ## Shows this help message
-	@grep -E -h '^[a-zA-Z0-9_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'
diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_private_ram/tcl/run.tcl b/fpga/pulpissimo-nexys_video/ips/xilinx_private_ram/tcl/run.tcl
deleted file mode 100644
index 78493b37..00000000
--- a/fpga/pulpissimo-nexys_video/ips/xilinx_private_ram/tcl/run.tcl
+++ /dev/null
@@ -1,38 +0,0 @@
-set partNumber $::env(XILINX_PART)
-
-if [info exists ::env(BOARD)] {
-    set BOARD $::env(BOARD)
-} else {
-    error "BOARD is not defined. Please source the sourceme.sh file."
-    exit
-}
-if [info exists ::env(XILINX_BOARD)] {
-	set boardName  $::env(XILINX_BOARD)
-}
-
-# detect target ram size
-if [info exists ::env(PRIVATE_BANK_SIZE)] {
-    set PRIVATE_BANK_SIZE $::env(PRIVATE_BANK_SIZE)
-} else {
-    set PRIVATE_BANK_SIZE 4096
-}
-
-set ipName xilinx_private_ram
-
-create_project $ipName . -part $partNumber
-set_property board_part $boardName [current_project]
-
-create_ip -name blk_mem_gen -vendor xilinx.com -library ip -module_name $ipName
-
-set_property -dict [eval list CONFIG.Use_Byte_Write_Enable {true} \
-                     CONFIG.Byte_Size {8} \
-                     CONFIG.Write_Width_A {32} \
-                     CONFIG.Write_Depth_A {$PRIVATE_BANK_SIZE} \
-                     CONFIG.Read_Width_A {32} \
-                     CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
-                    ] [get_ips $ipName]
-
-generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/.gitignore b/fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/.gitignore
deleted file mode 100644
index 5099fe9c..00000000
--- a/fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/.gitignore
+++ /dev/null
@@ -1,21 +0,0 @@
-#Ignore vivado project files generated by the tcl script
-**/.Xil/*
-**/reports/*
-**/*.cache/*
-**/*.hw/*
-**/*.ip_user_files/*
-**/*.runs/*
-**/*.sim/*
-**/*.srcs/*
-*.edf
-*.xpr
-*.jou
-*.log
-
-.cxl.*
-
-*ip
-
-*_stub.v
-gmon.out
-
diff --git a/fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/tcl/run.tcl b/fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/tcl/run.tcl
deleted file mode 100644
index 1f96dc03..00000000
--- a/fpga/pulpissimo-nexys_video/ips/xilinx_slow_clk_mngr/tcl/run.tcl
+++ /dev/null
@@ -1,45 +0,0 @@
-set partNumber $::env(XILINX_PART)
-
-if [info exists ::env(BOARD)] {
-    set BOARD $::env(BOARD)
-} else {
-    error "BOARD is not defined. Please source the sourceme.sh file."
-    exit
-}
-if [info exists ::env(XILINX_BOARD)] {
-	set boardName  $::env(XILINX_BOARD)
-}
-
-# detect target clock
-if [info exists ::env(SLOW_CLK_PERIOD_NS)] {
-    set SLOW_CLK_PERIOD_NS $::env(SLOW_CLK_PERIOD_NS)
-} else {
-    set SLOW_CLK_PERIOD_NS 30517
-}
-
-# Multiply frequency by 250 as there is a clock divider (by 250) after the
-# slow_clk_mngr since the MMCMs do not support clocks slower then 4.69 MHz.
-set SLOW_CLK_FREQ_MHZ [expr 1000 * 256 / $SLOW_CLK_PERIOD_NS]
-
-set ipName xilinx_slow_clk_mngr
-
-create_project $ipName . -part $partNumber
-set_property board_part $boardName [current_project]
-
-create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
-
-set_property -dict [eval list CONFIG.PRIM_IN_FREQ {100.000} \
-                        CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {$SLOW_CLK_FREQ_MHZ} \
-                        CONFIG.USE_SAFE_CLOCK_STARTUP {true} \
-                        CONFIG.USE_LOCKED {false} \
-                        CONFIG.RESET_TYPE {ACTIVE_LOW} \
-                        CONFIG.CLKIN1_JITTER_PS {50.0} \
-                        CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \
-                        CONFIG.RESET_PORT {resetn} \
-                       ] [get_ips $ipName]
-
-
-generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
diff --git a/fpga/pulpissimo-nexys_video/openocd-nexys_video.cfg b/fpga/pulpissimo-nexys_video/openocd-nexys_video.cfg
deleted file mode 100644
index b0de8583..00000000
--- a/fpga/pulpissimo-nexys_video/openocd-nexys_video.cfg
+++ /dev/null
@@ -1,46 +0,0 @@
-adapter_khz     1000
-
-interface ftdi
-ftdi_vid_pid 0x0403 0x6010
-
-# Channel 1 is taken by Xilinx JTAG
-ftdi_channel 0
-
-# links:
-# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html
-# 
-# Bit  MPSSE     FT2232    JTAG    Type   Description
-# Bit0 TCK       ADBUS0    TCK     Out    Clock Signal Output
-# Bit1 TDI       ADBUS1    TDI     Out    Serial Data Out
-# Bit2 TDO       ADBUS2    TDO     In     Serial Data In
-# Bit3 TMS       ADBUS3    TMS     Out    Select Signal Out
-# Bit4 GPIOL0    ADBUS4    nTRST   In/Out General Purpose I/O 
-# this corresponds to the following in/out layout, with TMS initially set to 1
-ftdi_layout_init 0x0018 0x001b
-# we only have to specify nTRST, the others are assigned correctly by default
-ftdi_layout_signal nTRST -ndata 0x0010
-
-set _CHIPNAME riscv
-
-jtag newtap $_CHIPNAME unknown0 -irlen 5 -expected-id 0x10102001
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x249511C3
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0x3e0
-
-gdb_report_data_abort enable
-gdb_report_register_access_error enable
-
-riscv set_reset_timeout_sec 120
-riscv set_command_timeout_sec 120
-
-# prefer to use sba for system bus access
-riscv set_prefer_sba on
-
-# dump jtag chain
-scan_chain
-
-
-init
-halt
-echo "Ready for Remote Connections"
diff --git a/fpga/pulpissimo-nexys_video/rtl/fpga_bootrom.sv b/fpga/pulpissimo-nexys_video/rtl/fpga_bootrom.sv
deleted file mode 100644
index 79d78b3f..00000000
--- a/fpga/pulpissimo-nexys_video/rtl/fpga_bootrom.sv
+++ /dev/null
@@ -1,36 +0,0 @@
-//-----------------------------------------------------------------------------
-// Title         : FPGA Bootrom for PULPissimo
-//-----------------------------------------------------------------------------
-// File          : fpga_bootrom.sv
-// Author        : Manuel Eggimann  <meggimann@iis.ee.ethz.ch>
-// Created       : 29.05.2019
-//-----------------------------------------------------------------------------
-// Description :
-// Mockup bootrom that keeps returning jal x0,0 to trap the core in an infinite
-// loop until the debug module takes over control.
-//-----------------------------------------------------------------------------
-// Copyright (C) 2013-2019 ETH Zurich, University of Bologna
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License. You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-//-----------------------------------------------------------------------------
-
-
-module fpga_bootrom
-  #(
-    parameter ADDR_WIDTH=32,
-    parameter DATA_WIDTH=32
-    )
-  (
-   input logic                   CLK,
-   input logic                   CEN,
-   input logic [ADDR_WIDTH-1:0]  A,
-   output logic [DATA_WIDTH-1:0] Q
-   );
-  assign Q = 32'h0000006f; //jal x0,0
-endmodule : fpga_bootrom
diff --git a/fpga/pulpissimo-nexys_video/rtl/fpga_clk_gen.sv b/fpga/pulpissimo-nexys_video/rtl/fpga_clk_gen.sv
deleted file mode 100644
index 2ad9a8eb..00000000
--- a/fpga/pulpissimo-nexys_video/rtl/fpga_clk_gen.sv
+++ /dev/null
@@ -1,74 +0,0 @@
-//-----------------------------------------------------------------------------
-// Title : FPGA CLK Gen for PULPissimo
-// -----------------------------------------------------------------------------
-// File : fpga_clk_gen.sv Author : Manuel Eggimann <meggimann@iis.ee.ethz.ch>
-// Created : 17.05.2019
-// -----------------------------------------------------------------------------
-// Description : Instantiates Xilinx clocking wizard IP to generate 2 output
-// clocks. Currently, the clock is not dynamicly reconfigurable and all
-// configuration requests are acknowledged without any effect.
-// -----------------------------------------------------------------------------
-// Copyright (C) 2013-2019 ETH Zurich, University of Bologna Copyright and
-// related rights are licensed under the Solderpad Hardware License, Version
-// 0.51 (the "License"); you may not use this file except in compliance with the
-// License. You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law or
-// agreed to in writing, software, hardware and materials distributed under this
-// License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
-// OF ANY KIND, either express or implied. See the License for the specific
-// language governing permissions and limitations under the License.
-// -----------------------------------------------------------------------------
-
-
-module fpga_clk_gen (
-                     input logic         ref_clk_i,
-                     input logic         rstn_glob_i,
-                     input logic         test_mode_i,
-                     input logic         shift_enable_i,
-                     output logic        soc_clk_o,
-                     output logic        per_clk_o,
-                     output logic        cluster_clk_o,
-                     output logic        soc_cfg_lock_o,
-                     input logic         soc_cfg_req_i,
-                     output logic        soc_cfg_ack_o,
-                     input logic [1:0]   soc_cfg_add_i,
-                     input logic [31:0]  soc_cfg_data_i,
-                     output logic [31:0] soc_cfg_r_data_o,
-                     input logic         soc_cfg_wrn_i,
-                     output logic        per_cfg_lock_o,
-                     input logic         per_cfg_req_i,
-                     output logic        per_cfg_ack_o,
-                     input logic [1:0]   per_cfg_add_i,
-                     input logic [31:0]  per_cfg_data_i,
-                     output logic [31:0] per_cfg_r_data_o,
-                     input logic         per_cfg_wrn_i,
-                     output logic        cluster_cfg_lock_o,
-                     input logic         cluster_cfg_req_i,
-                     output logic        cluster_cfg_ack_o,
-                     input logic [1:0]   cluster_cfg_add_i,
-                     input logic [31:0]  cluster_cfg_data_i,
-                     output logic [31:0] cluster_cfg_r_data_o,
-                     input logic         cluster_cfg_wrn_i
-                     );
-
-  logic                                  s_locked;
-
-  xilinx_clk_mngr i_clk_manager
-    (
-     .resetn(rstn_glob_i),
-     .clk_in1(ref_clk_i),
-     .clk_out1(soc_clk_o),
-     .clk_out2(per_clk_o),
-     .locked(s_locked)
-     );
-
-  assign soc_cfg_lock_o = s_locked;
-  assign per_cfg_lock_o = s_locked;
-
-  assign soc_cfg_ack_o = 1'b1; //Always acknowledge without doing anything for now
-  assign per_cfg_ack_o = 1'b1;
-
-  assign soc_cfg_r_data_o = 32'hdeadda7a;
-  assign per_cfg_r_data_o = 32'hdeadda7a;
-
-endmodule : fpga_clk_gen
diff --git a/fpga/pulpissimo-nexys_video/rtl/fpga_interleaved_ram.sv b/fpga/pulpissimo-nexys_video/rtl/fpga_interleaved_ram.sv
deleted file mode 100644
index 7d52e5d8..00000000
--- a/fpga/pulpissimo-nexys_video/rtl/fpga_interleaved_ram.sv
+++ /dev/null
@@ -1,57 +0,0 @@
-//-----------------------------------------------------------------------------
-// Title : FPGA Interleaved RAM Bank for PULPissimo
-// -----------------------------------------------------------------------------
-// File : fpga_interleaved_ram.sv Author : Manuel Eggimann
-// <meggimann@iis.ee.ethz.ch> Created : 20.05.2019
-// -----------------------------------------------------------------------------
-// Description : Instantiated block ram generator IP to replace the SRAM banks
-// in the interleaved region of L2. Since Xilinx LogicoreIP are not customizable
-// via parameters, the bank size selected in l2_ram_multibank must match the one
-// used in the TCL script for IP generation.
-// -----------------------------------------------------------------------------
-// Copyright (C) 2013-2019 ETH Zurich, University of Bologna Copyright and
-// related rights are licensed under the Solderpad Hardware License, Version
-// 0.51 (the "License"); you may not use this file except in compliance with the
-// License. You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law or
-// agreed to in writing, software, hardware and materials distributed under this
-// License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
-// OF ANY KIND, either express or implied. See the License for the specific
-// language governing permissions and limitations under the License.
-// -----------------------------------------------------------------------------
-
-module fpga_interleaved_ram
-  #(
-    parameter ADDR_WIDTH=12
-    ) (
-       input logic                  clk_i,
-       input logic                  rst_ni,
-       input logic                  csn_i,
-       input logic                  wen_i,
-       input logic [3:0]            be_i,
-       input logic [ADDR_WIDTH-1:0] addr_i,
-       input logic [31:0]           wdata_i,
-       output logic [31:0]          rdata_o
-   );
-
-  logic [3:0]                       wea;
-
-  always_comb begin
-    if (wen_i == 1'b0) begin
-      wea = be_i;
-    end else begin
-      wea = '0;
-    end
-  end
-
-  xilinx_interleaved_ram i_xilinx_interleaved_ram
-    (
-     .clka(clk_i),
-     .ena(~csn_i),
-     .wea(wea),
-     .addra(addr_i),
-     .dina(wdata_i),
-     .douta(rdata_o)
-     );
-
-endmodule : fpga_interleaved_ram
diff --git a/fpga/pulpissimo-nexys_video/rtl/fpga_private_ram.sv b/fpga/pulpissimo-nexys_video/rtl/fpga_private_ram.sv
deleted file mode 100644
index 05244931..00000000
--- a/fpga/pulpissimo-nexys_video/rtl/fpga_private_ram.sv
+++ /dev/null
@@ -1,57 +0,0 @@
-//-----------------------------------------------------------------------------
-// Title : FPGA Private RAM Bank for PULPissimo
-// -----------------------------------------------------------------------------
-// File : fpga_private_ram.sv Author : Manuel Eggimann
-// <meggimann@iis.ee.ethz.ch> Created : 20.05.2019
-// -----------------------------------------------------------------------------
-// Description : Instantiated block ram generator IP to replace the SRAM banks
-// in the private region of L2. Since Xilinx LogicoreIP are not customizable
-// via parameters, the bank size selected in l2_ram_multibank must match the one
-// used in the TCL script for IP generation.
-// -----------------------------------------------------------------------------
-// Copyright (C) 2013-2019 ETH Zurich, University of Bologna Copyright and
-// related rights are licensed under the Solderpad Hardware License, Version
-// 0.51 (the "License"); you may not use this file except in compliance with the
-// License. You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law or
-// agreed to in writing, software, hardware and materials distributed under this
-// License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
-// OF ANY KIND, either express or implied. See the License for the specific
-// language governing permissions and limitations under the License.
-// -----------------------------------------------------------------------------
-
-module fpga_private_ram
-  #(
-    parameter ADDR_WIDTH=12
-    ) (
-       input logic                  clk_i,
-       input logic                  rst_ni,
-       input logic                  csn_i,
-       input logic                  wen_i,
-       input logic [3:0]            be_i,
-       input logic [ADDR_WIDTH-1:0] addr_i,
-       input logic [31:0]           wdata_i,
-       output logic [31:0]          rdata_o
-   );
-
-  logic [3:0]                       wea;
-
-  always_comb begin
-    if (wen_i == 1'b0) begin
-      wea = be_i;
-    end else begin
-      wea = '0;
-    end
-  end
-
-  xilinx_private_ram i_xilinx_private_ram
-    (
-     .clka(clk_i),
-     .ena(~csn_i),
-     .wea(wea),
-     .addra(addr_i),
-     .dina(wdata_i),
-     .douta(rdata_o)
-     );
-
-endmodule : fpga_private_ram
diff --git a/fpga/pulpissimo-nexys_video/rtl/fpga_slow_clk_gen.sv b/fpga/pulpissimo-nexys_video/rtl/fpga_slow_clk_gen.sv
deleted file mode 100644
index f3db58f4..00000000
--- a/fpga/pulpissimo-nexys_video/rtl/fpga_slow_clk_gen.sv
+++ /dev/null
@@ -1,82 +0,0 @@
-//-----------------------------------------------------------------------------
-// Title         : FPGA slow clk generator for PULPissimo
-//-----------------------------------------------------------------------------
-// File          : fpga_slow_clk_gen.sv
-// Author        : Manuel Eggimann  <meggimann@iis.ee.ethz.ch>
-// Created       : 20.05.2019
-//-----------------------------------------------------------------------------
-// Description : Instantiates Xilinx Clocking Wizard IP to generate the slow_clk
-// signal since for certain boards the available clock sources are to fast to
-// use directly.
-//-----------------------------------------------------------------------------
-// Copyright (C) 2013-2019 ETH Zurich, University of Bologna
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License. You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-//-----------------------------------------------------------------------------
-
-
-module fpga_slow_clk_gen
-  #(
-    parameter CLK_DIV_VALUE = 256 //The xilinx_slow_clk_mngr is supposed to
-                                  //generate an 8.3886MHz clock. We need to divide it
-                                  //by 256 to arrive to a 32.768kHz clock
-    )
-  (input logic ref_clk_i,
-   input logic rst_ni,
-   output logic slow_clk_o
-   );
-
-
-
-  localparam COUNTER_WIDTH = $clog2(CLK_DIV_VALUE);
-
-
-  //Create clock divider using BUFGCE cells as the PLL/MMCM cannot generate clocks
-  //slower than 4.69 MHz and we need 32.768kHz
-
-  logic [COUNTER_WIDTH-1:0] clk_counter_d, clk_counter_q;
-  logic                     clock_gate_en;
-
-  logic                     intermmediate_clock;
-
-  xilinx_slow_clk_mngr i_slow_clk_mngr
-    (
-     .resetn(rst_ni),
-     .clk_in1(ref_clk_i),
-     .clk_out1(intermmediate_clock)
-     );
-
-
-
-  always_comb begin
-    if (clk_counter_q == CLK_DIV_VALUE-1) begin
-      clk_counter_d = '0;
-      clock_gate_en = 1'b1;
-    end else begin
-      clk_counter_d = clk_counter_q + 1;
-      clock_gate_en = 1'b0;
-    end
-  end
-
-  always_ff @(posedge intermmediate_clock, negedge rst_ni) begin
-    if (!rst_ni) begin
-      clk_counter_q <= '0;
-    end else begin
-      clk_counter_q <= clk_counter_d;
-    end
-  end
-
-  BUFGCE i_clock_gate
-    (
-      .I(intermmediate_clock),
-      .CE(clock_gate_en),
-      .O(slow_clk_o)
-     );
-
-endmodule : fpga_slow_clk_gen
diff --git a/fpga/pulpissimo-nexys_video/rtl/pad_functional_xilinx.sv b/fpga/pulpissimo-nexys_video/rtl/pad_functional_xilinx.sv
deleted file mode 100644
index a3ca1cde..00000000
--- a/fpga/pulpissimo-nexys_video/rtl/pad_functional_xilinx.sv
+++ /dev/null
@@ -1,48 +0,0 @@
-// Copyright 2018 ETH Zurich and University of Bologna.
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License.  You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-
-
-module pad_functional_pd
-(
-   input  logic             OEN,
-   input  logic             I,
-   output logic             O,
-   input  logic             PEN,
-   inout  logic             PAD
-);
-
-  (* PULLDOWN = "YES" *)
-  IOBUF iobuf_i (
-    .T ( OEN ),
-    .I ( I    ),
-    .O ( O    ),
-    .IO( PAD  )
-  );
-
-endmodule
-
-module pad_functional_pu
-(
-   input  logic             OEN,
-   input  logic             I,
-   output logic             O,
-   input  logic             PEN,
-   inout  logic             PAD
-);
-
-  (* PULLUP = "YES" *)
-  IOBUF iobuf_i (
-    .T ( OEN ),
-    .I ( I    ),
-    .O ( O    ),
-    .IO( PAD  )
-  );
-
-endmodule
\ No newline at end of file
diff --git a/fpga/pulpissimo-nexys_video/rtl/pulp_clock_gating_xilinx.sv b/fpga/pulpissimo-nexys_video/rtl/pulp_clock_gating_xilinx.sv
deleted file mode 100644
index 1e2db2d1..00000000
--- a/fpga/pulpissimo-nexys_video/rtl/pulp_clock_gating_xilinx.sv
+++ /dev/null
@@ -1,21 +0,0 @@
-// Copyright 2018 ETH Zurich and University of Bologna.
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License. You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-
-module pulp_clock_gating
-  (
-   input  logic clk_i,
-   input  logic en_i,
-   input  logic test_en_i,
-   output logic clk_o
-   );
-
-   assign clk_o = clk_i;
-   
-endmodule
diff --git a/fpga/pulpissimo-nexys_video/rtl/xilinx_pulpissimo.v b/fpga/pulpissimo-nexys_video/rtl/xilinx_pulpissimo.v
deleted file mode 100644
index 8c9c4870..00000000
--- a/fpga/pulpissimo-nexys_video/rtl/xilinx_pulpissimo.v
+++ /dev/null
@@ -1,144 +0,0 @@
-//-----------------------------------------------------------------------------
-// Title         : PULPissimo Verilog Wrapper
-//-----------------------------------------------------------------------------
-// File          : xilinx_pulpissimo.v
-// Author        : Manuel Eggimann  <meggimann@iis.ee.ethz.ch>
-// Created       : 21.05.2019
-//-----------------------------------------------------------------------------
-// Description :
-// Verilog Wrapper of PULPissimo to use the module within Xilinx IP integrator.
-//-----------------------------------------------------------------------------
-// Copyright (C) 2013-2019 ETH Zurich, University of Bologna
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License. You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-//-----------------------------------------------------------------------------
-
-module xilinx_pulpissimo
-  (
-   input wire  sys_clk,
-
-//   inout wire  pad_spim_sdio0,
-   inout wire  pad_spim_sdio1,
-   inout wire  pad_spim_sdio2,
-   inout wire  pad_spim_sdio3,
-   inout wire  pad_spim_csn0,
-   inout wire  pad_spim_sck,
-
-   inout wire  pad_uart_rx,
-   inout wire  pad_uart_tx,
-
-   inout wire  led0_o, //Mapped to spim_csn1
-   inout wire  led1_o, //Mapped to cam_pclk
-   inout wire  led2_o, //Mapped to cam_hsync
-   inout wire  led3_o, //Mapped to cam_data0
-
-   inout wire  switch0_i, //Mapped to cam_data1
-   inout wire  switch1_i, //Mapped to cam_data2
-
-   inout wire  btnc_i, //Mapped to cam_data3
-   inout wire  btnd_i, //Mapped to cam_data4
-   inout wire  btnl_i, //Mapped to cam_data5
-   inout wire  btnr_i, //Mapped to cam_data6
-   inout wire  btnu_i, //Mapped to cam_data7
-
-   inout wire  oled_spim_sck_o, //Mapped to spim_sck
-   inout wire  oled_spim_mosi_o, //Mapped to spim_sdio0
-   inout wire  oled_rst_o, //Mapped to i2s0_sck
-   inout wire  oled_dc_o, //Mapped to i2s0_ws
-   inout wire  oled_vbat_o, // Mapped to i2s0_sdi
-   inout wire  oled_vdd_o, // Mapped to i2s1_sdi
-
-   inout wire  sdio_reset_o, //Reset signal for SD card need to be driven low to
-                             //power the onboard sd-card. Mapped to cam_vsync.
-   inout wire  pad_sdio_clk,
-   inout wire  pad_sdio_cmd,
-   inout wire  pad_sdio_data0,
-   inout wire  pad_sdio_data1,
-   inout wire  pad_sdio_data2,
-   inout wire  pad_sdio_data3,
-
-   inout wire  pad_i2c0_sda,
-   inout wire  pad_i2c0_scl,
-
-   input wire  pad_reset_n,
-   inout wire  pad_bootsel,
-
-   input wire  pad_jtag_tck,
-   input wire  pad_jtag_tdi,
-   output wire pad_jtag_tdo,
-   input wire  pad_jtag_tms,
-   input wire  pad_jtag_trst
- );
-
-  localparam CORE_TYPE = 0; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY)
-  localparam USE_FPU   = 1;
-  localparam USE_HWPE  = 0;
-
-  wire        ref_clk;
-
-  // Input clock buffer
-  IBUFG
-    #(
-      .IOSTANDARD("LVCMOS33"),
-      .IBUF_LOW_PWR("FALSE"))
-  i_sysclk_iobuf
-    (
-     .I(sys_clk),
-     .O(ref_clk)
-     );
-
-  pulpissimo
-    #(.CORE_TYPE(CORE_TYPE),
-      .USE_FPU(USE_FPU),
-      .USE_HWPE(USE_HWPE)
-      ) i_pulpissimo
-      (
-       .pad_spim_sdio0(oled_spim_mosi_o),
-       .pad_spim_sdio1(pad_spim_sdio1),
-       .pad_spim_sdio2(pad_spim_sdio2),
-       .pad_spim_sdio3(pad_spim_sdio3),
-       .pad_spim_csn0(pad_spim_csn0),
-       .pad_spim_csn1(led0_o),
-       .pad_spim_sck(oled_spim_sck_o),
-       .pad_uart_rx(pad_uart_rx),
-       .pad_uart_tx(pad_uart_tx),
-       .pad_cam_pclk(led1_o),
-       .pad_cam_hsync(led2_o),
-       .pad_cam_data0(led3_o),
-       .pad_cam_data1(switch0_i),
-       .pad_cam_data2(switch1_i),
-       .pad_cam_data3(btnc_i),
-       .pad_cam_data4(btnd_i),
-       .pad_cam_data5(btnl_i),
-       .pad_cam_data6(btnr_i),
-       .pad_cam_data7(btnu_i),
-       .pad_cam_vsync(sdio_reset_o),
-       .pad_sdio_clk(pad_sdio_clk),
-       .pad_sdio_cmd(pad_sdio_cmd),
-       .pad_sdio_data0(pad_sdio_data0),
-       .pad_sdio_data1(pad_sdio_data1),
-       .pad_sdio_data2(pad_sdio_data2),
-       .pad_sdio_data3(pad_sdio_data3),
-       .pad_i2c0_sda(pad_i2c0_sda),
-       .pad_i2c0_scl(pad_i2c0_scl),
-       .pad_i2s0_sck(oled_rst_o),
-       .pad_i2s0_ws(oled_dc_o),
-       .pad_i2s0_sdi(oled_vbat_o),
-       .pad_i2s1_sdi(oled_vdd_o),
-       .pad_reset_n(pad_reset_n),
-       .pad_jtag_tck(pad_jtag_tck),
-       .pad_jtag_tdi(pad_jtag_tdi),
-       .pad_jtag_tdo(pad_jtag_tdo),
-       .pad_jtag_tms(pad_jtag_tms),
-       .pad_jtag_trst(pad_jtag_trst),
-       .pad_xtal_in(ref_clk),
-       .pad_bootsel()
-       );
-
-endmodule
diff --git a/fpga/pulpissimo-nexys_video/tcl/.gitignore b/fpga/pulpissimo-nexys_video/tcl/.gitignore
deleted file mode 100644
index 587a0fa6..00000000
--- a/fpga/pulpissimo-nexys_video/tcl/.gitignore
+++ /dev/null
@@ -1,6 +0,0 @@
-#Ignore tcl files generated by ipstools
-ips_add_files.tcl
-ips_inc_dirs.tcl
-ips_src_files.tcl
-rtl_add_files.tcl
-rtl_src_files.tcl
\ No newline at end of file
diff --git a/fpga/pulpissimo-nexys_video/tcl/messages.tcl b/fpga/pulpissimo-nexys_video/tcl/messages.tcl
deleted file mode 100644
index e8bfaf90..00000000
--- a/fpga/pulpissimo-nexys_video/tcl/messages.tcl
+++ /dev/null
@@ -1,13 +0,0 @@
-# sets up Vivado messages in a more sensible way
-
-set_msg_config -id {[Synth 8-3352]}         -new_severity "critical warning"
-set_msg_config -id {[Synth 8-350]}          -new_severity "critical warning"
-set_msg_config -id {[Synth 8-2490]}         -new_severity "warning"
-set_msg_config -id {[Synth 8-2306]}         -new_severity "info"
-set_msg_config -id {[Synth 8-3331]}         -new_severity "critical warning"
-set_msg_config -id {[Synth 8-3332]}         -new_severity "info"
-set_msg_config -id {[Synth 8-2715]}         -new_severity "error"
-set_msg_config -id {[Opt 31-35]}            -new_severity "info"
-set_msg_config -id {[Opt 31-32]}            -new_severity "info"
-set_msg_config -id {[Shape Builder 18-119]} -new_severity "warning"
-set_msg_config -id {[Filemgmt 20-742]}      -new_severity "error"
diff --git a/fpga/pulpissimo-nexys_video/tcl/run.tcl b/fpga/pulpissimo-nexys_video/tcl/run.tcl
deleted file mode 100644
index 88b044ca..00000000
--- a/fpga/pulpissimo-nexys_video/tcl/run.tcl
+++ /dev/null
@@ -1,126 +0,0 @@
-# detect board
-if [info exists ::env(BOARD)] {
-    set BOARD $::env(BOARD)
-} else {
-    puts "Please include 'fpga-settings.mk' in your Makefile to setup necessary environment variables."
-    exit
-}
-if [info exists ::env(XILINX_BOARD)] {
-    set XILINX_BOARD $::env(XILINX_BOARD)
-}
-
-set PROJECT pulpissimo-$BOARD
-set RTL ../../../rtl
-set IPS ../../../ips
-set CONSTRS constraints
-
-# create project
-create_project $PROJECT . -force -part $::env(XILINX_PART)
-set_property board_part $XILINX_BOARD [current_project]
-
-# set up meaningfull errors
-source tcl/messages.tcl
-
-# set up includes
-source ../pulpissimo/tcl/ips_inc_dirs.tcl
-set_property include_dirs $INCLUDE_DIRS [current_fileset]
-set_property include_dirs $INCLUDE_DIRS [current_fileset -simset]
-
-# setup and add IP source files
-source ../pulpissimo/tcl/ips_src_files.tcl
-source ../pulpissimo/tcl/ips_add_files.tcl
-
-# setup and add RTL source files
-source ../pulpissimo/tcl/rtl_src_files.tcl
-source ../pulpissimo/tcl/rtl_add_files.tcl
-
-# Override IPSApprox default variables
-set FPGA_RTL rtl
-set FPGA_IPS ips
-
-# remove duplicate incompatible modules
-remove_files $IPS/pulp_soc/rtl/components/axi_slice_dc_slave_wrap.sv
-remove_file $IPS/pulp_soc/rtl/components/axi_slice_dc_master_wrap.sv
-remove_file $IPS/tech_cells_generic/pad_functional_xilinx.sv
-
-# Set Verilog Defines.
-set DEFINES "FPGA_TARGET_XILINX=1 PULP_FPGA_EMUL=1 AXI4_XCHECK_OFF=1"
-set_property verilog_define $DEFINES [current_fileset]
-
-# detect target clock
-if [info exists ::env(FC_CLK_PERIOD_NS)] {
-    set FC_CLK_PERIOD_NS $::env(FC_CLK_PERIOD_NS)
-} else {
-    set FC_CLK_PERIOD_NS 10.000
-}
-set CLK_HALFPERIOD_NS [expr ${FC_CLK_PERIOD_NS} / 2.0]
-
-# Add toplevel wrapper
-add_files -norecurse $FPGA_RTL/xilinx_pulpissimo.v
-
-# Add Xilinx IPs
-read_ip $FPGA_IPS/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci
-read_ip $FPGA_IPS/xilinx_slow_clk_mngr/ip/xilinx_slow_clk_mngr.xci
-read_ip $FPGA_IPS/xilinx_interleaved_ram/ip/xilinx_interleaved_ram.xci
-read_ip $FPGA_IPS/xilinx_private_ram/ip/xilinx_private_ram.xci
-
-# Add wrappers and xilinx specific techcells
-add_files -norecurse $FPGA_RTL/fpga_clk_gen.sv
-add_files -norecurse $FPGA_RTL/fpga_slow_clk_gen.sv
-add_files -norecurse $FPGA_RTL/fpga_interleaved_ram.sv
-add_files -norecurse $FPGA_RTL/fpga_private_ram.sv
-add_files -norecurse $FPGA_RTL/fpga_bootrom.sv
-add_files -norecurse $FPGA_RTL/pad_functional_xilinx.sv
-add_files -norecurse $FPGA_RTL/pulp_clock_gating_xilinx.sv
-
-
-# set pulpissimo as top
-set_property top xilinx_pulpissimo [current_fileset]; #
-
-# needed only if used in batch mode
-update_compile_order -fileset sources_1
-
-# Add constraints
-add_files -fileset constrs_1 -norecurse $CONSTRS/$BOARD.xdc
-
-# Elaborate design
-synth_design -rtl -name rtl_1 -sfcu;# sfcu -> run synthesis in single file compilation unit mode
-
-# Launch synthesis
-set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY none [get_runs synth_1]
-set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value -sfcu -objects [get_runs synth_1] ;# Use single file compilation unit mode to prevent issues with import pkg::* statements in the codebase
-launch_runs synth_1 -jobs 8
-wait_on_run synth_1
-open_run synth_1 -name netlist_1
-set_property needs_refresh false [get_runs synth_1]
-
-# Remove unused IOBUF cells in padframe (they are not optimized away since the
-# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i
-# )
-remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel
-
-
-# Launch Implementation
-
-# set for RuntimeOptimized implementation
-set_property "steps.opt_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
-set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
-set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
-
-set_property STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE true [get_runs impl_1]
-set_property config_mode SPIx4 [current_design]
-
-launch_runs impl_1 -jobs 8
-wait_on_run impl_1
-launch_runs impl_1 -to_step write_bitstream
-wait_on_run impl_1
-
-open_run impl_1
-
-# Generate reports
-exec mkdir -p reports/
-exec rm -rf reports/*
-check_timing                                                              -file reports/$PROJECT.check_timing.rpt
-report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack   -file reports/$PROJECT.timing_WORST_100.rpt
-report_timing -nworst 1 -delay_type max -sort_by group                    -file reports/$PROJECT.timing.rpt
-report_utilization -hierarchical                                          -file reports/$PROJECT.utilization.rpt
diff --git a/fpga/pulpissimo-zcu104/.gitignore b/fpga/pulpissimo-zcu104/.gitignore
deleted file mode 100644
index 3f35710f..00000000
--- a/fpga/pulpissimo-zcu104/.gitignore
+++ /dev/null
@@ -1,22 +0,0 @@
-#Ignore vivado project files generated by the tcl script
-**/.Xil/*
-**/reports/*
-**/*.cache/*
-**/*.hw/*
-**/*.ip_user_files/*
-**/*.runs/*
-**/*.sim/*
-**/*.srcs/*
-*.edf
-*.xpr
-*.jou
-*.log
-
-.cxl.*
-
-*_stub.v
-gmon.out
-
-/pulpissimo/**/pulpissimo.bit
-
-**/xdc/constraints.xdc
diff --git a/fpga/pulpissimo-zcu104/Makefile b/fpga/pulpissimo-zcu104/Makefile
deleted file mode 100644
index b18f05e8..00000000
--- a/fpga/pulpissimo-zcu104/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-PROJECT:=pulpissimo_zcu104
-VIVADO ?= vivado
-VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
-
-include fpga-settings.mk
-
-.DEFAULT_GOAL:=help
-
-.PHONY: help all gui ips clean-ips clk clean-clk ram clean-ram clean
-
-all: ips ## Generate the bitstream for pulpissimo with vivado in batch mode. The vivado invocation command may be overriden with the env variable VIVADO.
-	$(VIVADO) -mode batch -source tcl/run.tcl
-
-gui: ips ## Generates the bitstream for pulpissimo with vivado in GUI mode. The vivado invocation command may be overriden with the env variable VIVADO.
-	$(VIVADO) -mode gui -source tcl/run.tcl &
-
-ips: clk ram ## Synthesizes necessary xilinx IP
-
-clean-ips: clean-clk clean-ram ## Clean all IPs
-
-clk: ## Synthesizes the Xilinx Clocking Manager IPs
-	cd ips/xilinx_clk_mngr; make all
-	cd ips/xilinx_slow_clk_mngr; make all
-
-clean-clk: ## Removes all Clocking Wizard IP outputs
-	cd ips/xilinx_clk_mngr; make clean
-	cd ips/xilinx_slow_clk_mngr; make clean
-
-ram: ## Synthesizes the Xilinx Block Memory Generator IPs for PULPissimo's L2 Ram
-	cd ips/xilinx_interleaved_ram; make all
-	cd ips/xilinx_private_ram; make all
-
-clean-ram: ## Removes all Block Ram IP outputs related to l2 ram
-	cd ips/xilinx_interleaved_ram; make clean
-	cd ips/xilinx_private_ram; make clean
-
-clean: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*)
-	rm -rf ${PROJECT}.*[^'bit']
-	rm -rf ${PROJECT}.*[^'bin']
-	rm -rf *.log
-	rm -rf vivado*
-
-help:
-	@grep -E -h '^[a-zA-Z_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'
diff --git a/fpga/pulpissimo-zcu104/README.md b/fpga/pulpissimo-zcu104/README.md
deleted file mode 100644
index 02aa1fb0..00000000
--- a/fpga/pulpissimo-zcu104/README.md
+++ /dev/null
@@ -1,52 +0,0 @@
-# PULPissimo on the Xilinx ZCU104 Board
-[\[Datasheet\]](https://www.xilinx.com/support/documentation/boards_and_kits/zcu104/ug1267-zcu104-eval-bd.pdf)
-
-## Bitstream Generation
-In the fpga folder, run
-```Shell
-make zcu104
-```
-which will generate `pulpissimo_zcu104.bit`.
-Use Vivado to load it into the FPGA.
-
-## Default SoC and Core Frequencies
-
-By default the clock generating IPs are synthesized to provide the following frequencies to PULPissimo:
-
-| Clock Domain   | Default Frequency on ZCU104 board  |
-|----------------|------------------------------------|
-| Core Frequency | 20 MHz                             |
-| SoC Frequency  | 10 MHz                             |
-
-
-## Peripherals
-Most peripherals of are connected to the ARM processing system domain of the SoC and cannot be used from the programmable logic domain.
-The peripherals available to PULPissimo are thus very limited.
-
-### Reset Button
-The CPU RESET button (SW20) resets the RISC-V CPU.
-
-### UART
-PULPissimo's UART port is mapped to Channel D of the FT4232HL chip.
-When connecting the board to a computer using the USB/JTAG/UART micro-USB connector (J164), it is the last of the four detected serial devices.
-
-### JTAG
-Unfortunately, only one channel of the FT4232HL chip is connected to the programmable logic domain.
-Since we are using that channel for UART, the micro-USB connector on the board cannot be used to communicate with the RISC-V debug module over JTAG.
-Instead, you need to connect a separate JTAG adapter to the GPIO port (PMOD0 header) of the board:
-
-| JTAG Signal | FPGA Port | J55 Pin  |
-|-------------|-----------|----------|
-| tms         | PMOD0_0   | Pin 1    |
-| tdi         | PMOD0_1   | Pin 3    |
-| tdo         | PMOD0_2   | Pin 5    |
-| tck         | PMOD0_3   | Pin 7    |
-| gnd         | GND       | Pin 9    |
-| vdd         | 3V3       | Pin 11   |
-
-An OpenOCD configuration file for the Digilent JTAG-HS1 adapter is included.
-To use it, run
-
-```Shell
-$OPENOCD/bin/openocd -f pulpissimo/home/meggiman/projects/pulp/pulpissimo/fpga/pulpissimo-zcu104/openocd-zcu104-digilent-jtag-hs1.cfg
-```
diff --git a/fpga/pulpissimo-zcu104/constraints/zcu104.xdc b/fpga/pulpissimo-zcu104/constraints/zcu104.xdc
deleted file mode 100644
index 7ce80166..00000000
--- a/fpga/pulpissimo-zcu104/constraints/zcu104.xdc
+++ /dev/null
@@ -1,128 +0,0 @@
-#######################################
-#  _______ _           _              #
-# |__   __(_)         (_)             #
-#    | |   _ _ __ ___  _ _ __   __ _  #
-#    | |  | | '_ ` _ \| | '_ \ / _` | #
-#    | |  | | | | | | | | | | | (_| | #
-#    |_|  |_|_| |_| |_|_|_| |_|\__, | #
-#                               __/ | #
-#                              |___/  #
-#######################################
-
-
-#Create constraint for the clock input of the zcu104 board
-create_clock -period 8.000 -name ref_clk [get_ports ref_clk_p]
-
-#I2S and CAM interface are not used in this FPGA port. Set constraints to
-#disable the clock
-set_case_analysis 0 i_pulpissimo/safe_domain_i/cam_pclk_o
-set_case_analysis 0 i_pulpissimo/safe_domain_i/i2s_slave_sck_o
-#set_input_jitter tck 1.000
-
-## JTAG
-create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_jtag_tck]
-set_input_jitter tck 1.000
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_jtag_tck_IBUF_inst/O]
-
-
-# minimize routing delay
-set_input_delay -clock tck -clock_fall 5.000 [get_ports pad_jtag_tdi]
-set_input_delay -clock tck -clock_fall 5.000 [get_ports pad_jtag_tms]
-set_output_delay -clock tck 5.000 [get_ports pad_jtag_tdo]
-
-set_max_delay -to [get_ports pad_jtag_tdo] 20.000
-set_max_delay -from [get_ports pad_jtag_tms] 20.000
-set_max_delay -from [get_ports pad_jtag_tdi] 20.000
-
-set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000
-set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000
-set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000
-
-
-# reset signal
-set_false_path -from [get_ports pad_reset]
-
-# Set ASYNC_REG attribute for ff synchronizers to place them closer together and
-# increase MTBF
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/apb_adv_timer_i/u_tim0/u_in_stage/r_ls_clk_sync_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/apb_adv_timer_i/u_tim1/u_in_stage/r_ls_clk_sync_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/apb_adv_timer_i/u_tim2/u_in_stage/r_ls_clk_sync_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/apb_adv_timer_i/u_tim3/u_in_stage/r_ls_clk_sync_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*]
-
-# Create asynchronous clock group between slow-clk and SoC clock. Those clocks
-# are considered asynchronously and proper synchronization regs are in place
-set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/safe_domain_i/i_slow_clk_gen/slow_clk_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fpga_clk_gen/soc_clk_o]]
-
-
-#############################################################
-#  _____ ____         _____      _   _   _                  #
-# |_   _/ __ \       / ____|    | | | | (_)                 #
-#   | || |  | |_____| (___   ___| |_| |_ _ _ __   __ _ ___  #
-#   | || |  | |______\___ \ / _ \ __| __| | '_ \ / _` / __| #
-#  _| || |__| |      ____) |  __/ |_| |_| | | | | (_| \__ \ #
-# |_____\____/      |_____/ \___|\__|\__|_|_| |_|\__, |___/ #
-#                                                 __/ |     #
-#                                                |___/      #
-#############################################################
-
-## Sys clock
-set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVDS} [get_ports ref_clk_n]
-set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVDS} [get_ports ref_clk_p]
-
-## Reset
-set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS33} [get_ports pad_reset]
-
-## Buttons
-set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports btn0_i]
-set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports btn1_i]
-set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports btn2_i]
-set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS33} [get_ports btn3_i]
-
-## PMOD 0
-set_property -dict {PACKAGE_PIN G8 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tms]
-set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tdi]
-set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tdo]
-set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS33} [get_ports pad_jtag_tck]
-set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS33} [get_ports pad_pmod0_4]
-set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports pad_pmod0_5]
-set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS33} [get_ports pad_pmod0_6]
-set_property -dict {PACKAGE_PIN J7 IOSTANDARD LVCMOS33} [get_ports pad_pmod0_7]
-
-## PMOD 1
-set_property -dict {PACKAGE_PIN J9  IOSTANDARD LVCMOS33} [get_ports pad_pmod1_0]
-set_property -dict {PACKAGE_PIN K9  IOSTANDARD LVCMOS33} [get_ports pad_pmod1_1]
-set_property -dict {PACKAGE_PIN K8  IOSTANDARD LVCMOS33} [get_ports pad_pmod1_2]
-set_property -dict {PACKAGE_PIN L8  IOSTANDARD LVCMOS33} [get_ports pad_pmod1_3]
-set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS33} [get_ports pad_pmod1_4]
-set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS33} [get_ports pad_pmod1_5]
-set_property -dict {PACKAGE_PIN M8  IOSTANDARD LVCMOS33} [get_ports pad_pmod1_6]
-set_property -dict {PACKAGE_PIN M9  IOSTANDARD LVCMOS33} [get_ports pad_pmod1_7]
-
-## UART
-set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports pad_uart_rx]
-set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS18} [get_ports pad_uart_tx]
-set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS18} [get_ports pad_uart_rts]
-set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS18} [get_ports pad_uart_cts]
-
-## LEDs
-set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS33} [get_ports led0_o]
-set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS33} [get_ports led1_o]
-set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS33} [get_ports led2_o]
-set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS33} [get_ports led3_o]
-
-## Switches
-set_property -dict {PACKAGE_PIN E4 IOSTANDARD LVCMOS33} [get_ports switch0_i]
-set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports switch1_i]
-set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS33} [get_ports switch2_i]
-set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33} [get_ports switch3_i]
-
-## I2C Bus
-set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS33} [get_ports pad_i2c0_scl]
-set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS33} [get_ports pad_i2c0_sda]
-
-## HDMI CTL
-set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS33} [get_ports pad_hdmi_scl]
-set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports pad_hdmi_sda]
diff --git a/fpga/pulpissimo-zcu104/elf_run.gdb b/fpga/pulpissimo-zcu104/elf_run.gdb
deleted file mode 100644
index cba53bd0..00000000
--- a/fpga/pulpissimo-zcu104/elf_run.gdb
+++ /dev/null
@@ -1,4 +0,0 @@
-target remote localhost:3333
-monitor reset halt
-load
-continue
\ No newline at end of file
diff --git a/fpga/pulpissimo-zcu104/elf_run.sh b/fpga/pulpissimo-zcu104/elf_run.sh
deleted file mode 100755
index 9bd74f6a..00000000
--- a/fpga/pulpissimo-zcu104/elf_run.sh
+++ /dev/null
@@ -1,17 +0,0 @@
-#!/bin/bash
-
-trap "exit" INT TERM
-trap "kill 0" EXIT
-
-
-SCRIPTDIR=$(dirname $0)
-UART_TTY=${PULP_ZCU104_UART_TTY:=/dev/ttyUSB0}
-UART_BAUDRATE=${PULP_ZCU104_UART_BAUDRATE:=115200}
-
-#Execute gdb and connect to openocd via pipe
-$OPENOCD/bin/openocd -f $SCRIPTDIR/openocd-zcu104.cfg &
-$PULP_RISCV_GCC_TOOLCHAIN_CI/bin/riscv32-unknown-elf-gdb -x $SCRIPTDIR/elf_run.gdb $1 &
-sleep 3
-minicom -D $UART_TTY -b $UART_BAUDRATE
-
-
diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/.gitignore b/fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/.gitignore
deleted file mode 100644
index 5099fe9c..00000000
--- a/fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/.gitignore
+++ /dev/null
@@ -1,21 +0,0 @@
-#Ignore vivado project files generated by the tcl script
-**/.Xil/*
-**/reports/*
-**/*.cache/*
-**/*.hw/*
-**/*.ip_user_files/*
-**/*.runs/*
-**/*.sim/*
-**/*.srcs/*
-*.edf
-*.xpr
-*.jou
-*.log
-
-.cxl.*
-
-*ip
-
-*_stub.v
-gmon.out
-
diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/Makefile b/fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/Makefile
deleted file mode 100644
index 978b9cee..00000000
--- a/fpga/pulpissimo-zcu104/ips/xilinx_clk_mngr/Makefile
+++ /dev/null
@@ -1,37 +0,0 @@
-PROJECT:=xilinx_clk_mngr
-VIVADO ?= vivado
-VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
-MODE=batch
-
-include ../../fpga-settings.mk
-
-.DEFAULT_GOAL:=help
-
-.PHONY: help all gui clean
-
-all: MODE=batch ## Create and synthesize the IP in batch mode.
-
-gui: MODE=gui  ## Create and synthesize the IP in GUI mode.
-
-all gui: $(PROJECT).xpr
-
-$(PROJECT).xpr: ../../fpga-settings.mk tcl/run.tcl
-	make clean
-	$(VIVADO) -mode $(MODE) -source tcl/run.tcl
-	mkdir -p ip
-	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
-	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
-
-clean: ## Remove all build products
-	rm -rf ip/*
-	mkdir -p ip
-	rm -rf ${PROJECT}.*
-	rm -rf component.xml
-	rm -rf vivado*.jou
-	rm -rf vivado*.log
-	rm -rf vivado*.str
-	rm -rf xgui
-	rm -rf .Xil
-
-help: ## Shows this help message
-	@grep -E -h '^[a-zA-Z0-9_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'
diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_interleaved_ram/.gitignore b/fpga/pulpissimo-zcu104/ips/xilinx_interleaved_ram/.gitignore
deleted file mode 100644
index 5099fe9c..00000000
--- a/fpga/pulpissimo-zcu104/ips/xilinx_interleaved_ram/.gitignore
+++ /dev/null
@@ -1,21 +0,0 @@
-#Ignore vivado project files generated by the tcl script
-**/.Xil/*
-**/reports/*
-**/*.cache/*
-**/*.hw/*
-**/*.ip_user_files/*
-**/*.runs/*
-**/*.sim/*
-**/*.srcs/*
-*.edf
-*.xpr
-*.jou
-*.log
-
-.cxl.*
-
-*ip
-
-*_stub.v
-gmon.out
-
diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_interleaved_ram/Makefile b/fpga/pulpissimo-zcu104/ips/xilinx_interleaved_ram/Makefile
deleted file mode 100644
index 08752831..00000000
--- a/fpga/pulpissimo-zcu104/ips/xilinx_interleaved_ram/Makefile
+++ /dev/null
@@ -1,37 +0,0 @@
-PROJECT:=xilinx_interleaved_ram
-VIVADO ?= vivado
-VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
-MODE=batch
-
-include ../../fpga-settings.mk
-
-.DEFAULT_GOAL:=help
-
-.PHONY: help all gui clean
-
-all: MODE=batch ## Create and synthesize the IP in batch mode.
-
-gui: MODE=gui  ## Create and synthesize the IP in GUI mode.
-
-all gui: $(PROJECT).xpr
-
-$(PROJECT).xpr: ../../fpga-settings.mk tcl/run.tcl
-	make clean
-	$(VIVADO) -mode $(MODE) -source tcl/run.tcl
-	mkdir -p ip
-	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
-	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
-
-clean: ## Remove all build products
-	rm -rf ip/*
-	mkdir -p ip
-	rm -rf ${PROJECT}.*
-	rm -rf component.xml
-	rm -rf vivado*.jou
-	rm -rf vivado*.log
-	rm -rf vivado*.str
-	rm -rf xgui
-	rm -rf .Xil
-
-help: ## Shows this help message
-	@grep -E -h '^[a-zA-Z0-9_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'
diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_private_ram/.gitignore b/fpga/pulpissimo-zcu104/ips/xilinx_private_ram/.gitignore
deleted file mode 100644
index 5099fe9c..00000000
--- a/fpga/pulpissimo-zcu104/ips/xilinx_private_ram/.gitignore
+++ /dev/null
@@ -1,21 +0,0 @@
-#Ignore vivado project files generated by the tcl script
-**/.Xil/*
-**/reports/*
-**/*.cache/*
-**/*.hw/*
-**/*.ip_user_files/*
-**/*.runs/*
-**/*.sim/*
-**/*.srcs/*
-*.edf
-*.xpr
-*.jou
-*.log
-
-.cxl.*
-
-*ip
-
-*_stub.v
-gmon.out
-
diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_private_ram/Makefile b/fpga/pulpissimo-zcu104/ips/xilinx_private_ram/Makefile
deleted file mode 100644
index 4734e7ad..00000000
--- a/fpga/pulpissimo-zcu104/ips/xilinx_private_ram/Makefile
+++ /dev/null
@@ -1,37 +0,0 @@
-PROJECT:=xilinx_private_ram
-VIVADO ?= vivado
-VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
-MODE=batch
-
-include ../../fpga-settings.mk
-
-.DEFAULT_GOAL:=help
-
-.PHONY: help all gui clean
-
-all: MODE=batch ## Create and synthesize the IP in batch mode.
-
-gui: MODE=gui  ## Create and synthesize the IP in GUI mode.
-
-all gui: $(PROJECT).xpr
-
-$(PROJECT).xpr: ../../fpga-settings.mk tcl/run.tcl
-	make clean
-	$(VIVADO) -mode $(MODE) -source tcl/run.tcl
-	mkdir -p ip
-	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
-	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
-
-clean: ## Remove all build products
-	rm -rf ip/*
-	mkdir -p ip
-	rm -rf ${PROJECT}.*
-	rm -rf component.xml
-	rm -rf vivado*.jou
-	rm -rf vivado*.log
-	rm -rf vivado*.str
-	rm -rf xgui
-	rm -rf .Xil
-
-help: ## Shows this help message
-	@grep -E -h '^[a-zA-Z0-9_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'
diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_private_ram/tcl/run.tcl b/fpga/pulpissimo-zcu104/ips/xilinx_private_ram/tcl/run.tcl
deleted file mode 100644
index 78493b37..00000000
--- a/fpga/pulpissimo-zcu104/ips/xilinx_private_ram/tcl/run.tcl
+++ /dev/null
@@ -1,38 +0,0 @@
-set partNumber $::env(XILINX_PART)
-
-if [info exists ::env(BOARD)] {
-    set BOARD $::env(BOARD)
-} else {
-    error "BOARD is not defined. Please source the sourceme.sh file."
-    exit
-}
-if [info exists ::env(XILINX_BOARD)] {
-	set boardName  $::env(XILINX_BOARD)
-}
-
-# detect target ram size
-if [info exists ::env(PRIVATE_BANK_SIZE)] {
-    set PRIVATE_BANK_SIZE $::env(PRIVATE_BANK_SIZE)
-} else {
-    set PRIVATE_BANK_SIZE 4096
-}
-
-set ipName xilinx_private_ram
-
-create_project $ipName . -part $partNumber
-set_property board_part $boardName [current_project]
-
-create_ip -name blk_mem_gen -vendor xilinx.com -library ip -module_name $ipName
-
-set_property -dict [eval list CONFIG.Use_Byte_Write_Enable {true} \
-                     CONFIG.Byte_Size {8} \
-                     CONFIG.Write_Width_A {32} \
-                     CONFIG.Write_Depth_A {$PRIVATE_BANK_SIZE} \
-                     CONFIG.Read_Width_A {32} \
-                     CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
-                    ] [get_ips $ipName]
-
-generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
-launch_run -jobs 8 ${ipName}_synth_1
-wait_on_run ${ipName}_synth_1
diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/.gitignore b/fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/.gitignore
deleted file mode 100644
index 5099fe9c..00000000
--- a/fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/.gitignore
+++ /dev/null
@@ -1,21 +0,0 @@
-#Ignore vivado project files generated by the tcl script
-**/.Xil/*
-**/reports/*
-**/*.cache/*
-**/*.hw/*
-**/*.ip_user_files/*
-**/*.runs/*
-**/*.sim/*
-**/*.srcs/*
-*.edf
-*.xpr
-*.jou
-*.log
-
-.cxl.*
-
-*ip
-
-*_stub.v
-gmon.out
-
diff --git a/fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/Makefile b/fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/Makefile
deleted file mode 100644
index e3ba47bf..00000000
--- a/fpga/pulpissimo-zcu104/ips/xilinx_slow_clk_mngr/Makefile
+++ /dev/null
@@ -1,37 +0,0 @@
-PROJECT:=xilinx_slow_clk_mngr
-VIVADO ?= vivado
-VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
-MODE=batch
-
-include ../../fpga-settings.mk
-
-.DEFAULT_GOAL:=help
-
-.PHONY: help all gui clean
-
-all: MODE=batch ## Create and synthesize the IP in batch mode.
-
-gui: MODE=gui  ## Create and synthesize the IP in GUI mode.
-
-all gui: $(PROJECT).xpr
-
-$(PROJECT).xpr: ../../fpga-settings.mk tcl/run.tcl
-	make clean
-	$(VIVADO) -mode $(MODE) -source tcl/run.tcl
-	mkdir -p ip
-	cp -r ${PROJECT}.srcs/sources_1/ip/${PROJECT}/* ip/.
-	cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/.
-
-clean: ## Remove all build products
-	rm -rf ip/*
-	mkdir -p ip
-	rm -rf ${PROJECT}.*
-	rm -rf component.xml
-	rm -rf vivado*.jou
-	rm -rf vivado*.log
-	rm -rf vivado*.str
-	rm -rf xgui
-	rm -rf .Xil
-
-help: ## Shows this help message
-	@grep -E -h '^[a-zA-Z0-9_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'
diff --git a/fpga/pulpissimo-zcu104/openocd-zcu104-digilent-jtag-hs1.cfg b/fpga/pulpissimo-zcu104/openocd-zcu104-digilent-jtag-hs1.cfg
deleted file mode 100644
index fc453400..00000000
--- a/fpga/pulpissimo-zcu104/openocd-zcu104-digilent-jtag-hs1.cfg
+++ /dev/null
@@ -1,32 +0,0 @@
-adapter_khz     1000
-
-# Digilent JTAG-HS1
-interface ftdi
-ftdi_vid_pid 0x0403 0x6010
-ftdi_channel 0
-ftdi_layout_init 0x0088 0x008b
-
-set _CHIPNAME riscv
-
-jtag newtap $_CHIPNAME unknown0 -irlen 5 -expected-id 0x10102001
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x249511C3
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0x3e0
-
-gdb_report_data_abort enable
-gdb_report_register_access_error enable
-
-riscv set_reset_timeout_sec 120
-riscv set_command_timeout_sec 120
-
-# prefer to use sba for system bus access
-riscv set_prefer_sba on
-
-# dump jtag chain
-scan_chain
-
-
-init
-halt
-echo "Ready for Remote Connections"
diff --git a/fpga/pulpissimo-zcu104/rtl/fpga_bootrom.sv b/fpga/pulpissimo-zcu104/rtl/fpga_bootrom.sv
deleted file mode 100644
index 79d78b3f..00000000
--- a/fpga/pulpissimo-zcu104/rtl/fpga_bootrom.sv
+++ /dev/null
@@ -1,36 +0,0 @@
-//-----------------------------------------------------------------------------
-// Title         : FPGA Bootrom for PULPissimo
-//-----------------------------------------------------------------------------
-// File          : fpga_bootrom.sv
-// Author        : Manuel Eggimann  <meggimann@iis.ee.ethz.ch>
-// Created       : 29.05.2019
-//-----------------------------------------------------------------------------
-// Description :
-// Mockup bootrom that keeps returning jal x0,0 to trap the core in an infinite
-// loop until the debug module takes over control.
-//-----------------------------------------------------------------------------
-// Copyright (C) 2013-2019 ETH Zurich, University of Bologna
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License. You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-//-----------------------------------------------------------------------------
-
-
-module fpga_bootrom
-  #(
-    parameter ADDR_WIDTH=32,
-    parameter DATA_WIDTH=32
-    )
-  (
-   input logic                   CLK,
-   input logic                   CEN,
-   input logic [ADDR_WIDTH-1:0]  A,
-   output logic [DATA_WIDTH-1:0] Q
-   );
-  assign Q = 32'h0000006f; //jal x0,0
-endmodule : fpga_bootrom
diff --git a/fpga/pulpissimo-zcu104/rtl/fpga_clk_gen.sv b/fpga/pulpissimo-zcu104/rtl/fpga_clk_gen.sv
deleted file mode 100644
index 2ad9a8eb..00000000
--- a/fpga/pulpissimo-zcu104/rtl/fpga_clk_gen.sv
+++ /dev/null
@@ -1,74 +0,0 @@
-//-----------------------------------------------------------------------------
-// Title : FPGA CLK Gen for PULPissimo
-// -----------------------------------------------------------------------------
-// File : fpga_clk_gen.sv Author : Manuel Eggimann <meggimann@iis.ee.ethz.ch>
-// Created : 17.05.2019
-// -----------------------------------------------------------------------------
-// Description : Instantiates Xilinx clocking wizard IP to generate 2 output
-// clocks. Currently, the clock is not dynamicly reconfigurable and all
-// configuration requests are acknowledged without any effect.
-// -----------------------------------------------------------------------------
-// Copyright (C) 2013-2019 ETH Zurich, University of Bologna Copyright and
-// related rights are licensed under the Solderpad Hardware License, Version
-// 0.51 (the "License"); you may not use this file except in compliance with the
-// License. You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law or
-// agreed to in writing, software, hardware and materials distributed under this
-// License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
-// OF ANY KIND, either express or implied. See the License for the specific
-// language governing permissions and limitations under the License.
-// -----------------------------------------------------------------------------
-
-
-module fpga_clk_gen (
-                     input logic         ref_clk_i,
-                     input logic         rstn_glob_i,
-                     input logic         test_mode_i,
-                     input logic         shift_enable_i,
-                     output logic        soc_clk_o,
-                     output logic        per_clk_o,
-                     output logic        cluster_clk_o,
-                     output logic        soc_cfg_lock_o,
-                     input logic         soc_cfg_req_i,
-                     output logic        soc_cfg_ack_o,
-                     input logic [1:0]   soc_cfg_add_i,
-                     input logic [31:0]  soc_cfg_data_i,
-                     output logic [31:0] soc_cfg_r_data_o,
-                     input logic         soc_cfg_wrn_i,
-                     output logic        per_cfg_lock_o,
-                     input logic         per_cfg_req_i,
-                     output logic        per_cfg_ack_o,
-                     input logic [1:0]   per_cfg_add_i,
-                     input logic [31:0]  per_cfg_data_i,
-                     output logic [31:0] per_cfg_r_data_o,
-                     input logic         per_cfg_wrn_i,
-                     output logic        cluster_cfg_lock_o,
-                     input logic         cluster_cfg_req_i,
-                     output logic        cluster_cfg_ack_o,
-                     input logic [1:0]   cluster_cfg_add_i,
-                     input logic [31:0]  cluster_cfg_data_i,
-                     output logic [31:0] cluster_cfg_r_data_o,
-                     input logic         cluster_cfg_wrn_i
-                     );
-
-  logic                                  s_locked;
-
-  xilinx_clk_mngr i_clk_manager
-    (
-     .resetn(rstn_glob_i),
-     .clk_in1(ref_clk_i),
-     .clk_out1(soc_clk_o),
-     .clk_out2(per_clk_o),
-     .locked(s_locked)
-     );
-
-  assign soc_cfg_lock_o = s_locked;
-  assign per_cfg_lock_o = s_locked;
-
-  assign soc_cfg_ack_o = 1'b1; //Always acknowledge without doing anything for now
-  assign per_cfg_ack_o = 1'b1;
-
-  assign soc_cfg_r_data_o = 32'hdeadda7a;
-  assign per_cfg_r_data_o = 32'hdeadda7a;
-
-endmodule : fpga_clk_gen
diff --git a/fpga/pulpissimo-zcu104/rtl/fpga_interleaved_ram.sv b/fpga/pulpissimo-zcu104/rtl/fpga_interleaved_ram.sv
deleted file mode 100644
index 7d52e5d8..00000000
--- a/fpga/pulpissimo-zcu104/rtl/fpga_interleaved_ram.sv
+++ /dev/null
@@ -1,57 +0,0 @@
-//-----------------------------------------------------------------------------
-// Title : FPGA Interleaved RAM Bank for PULPissimo
-// -----------------------------------------------------------------------------
-// File : fpga_interleaved_ram.sv Author : Manuel Eggimann
-// <meggimann@iis.ee.ethz.ch> Created : 20.05.2019
-// -----------------------------------------------------------------------------
-// Description : Instantiated block ram generator IP to replace the SRAM banks
-// in the interleaved region of L2. Since Xilinx LogicoreIP are not customizable
-// via parameters, the bank size selected in l2_ram_multibank must match the one
-// used in the TCL script for IP generation.
-// -----------------------------------------------------------------------------
-// Copyright (C) 2013-2019 ETH Zurich, University of Bologna Copyright and
-// related rights are licensed under the Solderpad Hardware License, Version
-// 0.51 (the "License"); you may not use this file except in compliance with the
-// License. You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law or
-// agreed to in writing, software, hardware and materials distributed under this
-// License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
-// OF ANY KIND, either express or implied. See the License for the specific
-// language governing permissions and limitations under the License.
-// -----------------------------------------------------------------------------
-
-module fpga_interleaved_ram
-  #(
-    parameter ADDR_WIDTH=12
-    ) (
-       input logic                  clk_i,
-       input logic                  rst_ni,
-       input logic                  csn_i,
-       input logic                  wen_i,
-       input logic [3:0]            be_i,
-       input logic [ADDR_WIDTH-1:0] addr_i,
-       input logic [31:0]           wdata_i,
-       output logic [31:0]          rdata_o
-   );
-
-  logic [3:0]                       wea;
-
-  always_comb begin
-    if (wen_i == 1'b0) begin
-      wea = be_i;
-    end else begin
-      wea = '0;
-    end
-  end
-
-  xilinx_interleaved_ram i_xilinx_interleaved_ram
-    (
-     .clka(clk_i),
-     .ena(~csn_i),
-     .wea(wea),
-     .addra(addr_i),
-     .dina(wdata_i),
-     .douta(rdata_o)
-     );
-
-endmodule : fpga_interleaved_ram
diff --git a/fpga/pulpissimo-zcu104/rtl/fpga_private_ram.sv b/fpga/pulpissimo-zcu104/rtl/fpga_private_ram.sv
deleted file mode 100644
index 05244931..00000000
--- a/fpga/pulpissimo-zcu104/rtl/fpga_private_ram.sv
+++ /dev/null
@@ -1,57 +0,0 @@
-//-----------------------------------------------------------------------------
-// Title : FPGA Private RAM Bank for PULPissimo
-// -----------------------------------------------------------------------------
-// File : fpga_private_ram.sv Author : Manuel Eggimann
-// <meggimann@iis.ee.ethz.ch> Created : 20.05.2019
-// -----------------------------------------------------------------------------
-// Description : Instantiated block ram generator IP to replace the SRAM banks
-// in the private region of L2. Since Xilinx LogicoreIP are not customizable
-// via parameters, the bank size selected in l2_ram_multibank must match the one
-// used in the TCL script for IP generation.
-// -----------------------------------------------------------------------------
-// Copyright (C) 2013-2019 ETH Zurich, University of Bologna Copyright and
-// related rights are licensed under the Solderpad Hardware License, Version
-// 0.51 (the "License"); you may not use this file except in compliance with the
-// License. You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law or
-// agreed to in writing, software, hardware and materials distributed under this
-// License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
-// OF ANY KIND, either express or implied. See the License for the specific
-// language governing permissions and limitations under the License.
-// -----------------------------------------------------------------------------
-
-module fpga_private_ram
-  #(
-    parameter ADDR_WIDTH=12
-    ) (
-       input logic                  clk_i,
-       input logic                  rst_ni,
-       input logic                  csn_i,
-       input logic                  wen_i,
-       input logic [3:0]            be_i,
-       input logic [ADDR_WIDTH-1:0] addr_i,
-       input logic [31:0]           wdata_i,
-       output logic [31:0]          rdata_o
-   );
-
-  logic [3:0]                       wea;
-
-  always_comb begin
-    if (wen_i == 1'b0) begin
-      wea = be_i;
-    end else begin
-      wea = '0;
-    end
-  end
-
-  xilinx_private_ram i_xilinx_private_ram
-    (
-     .clka(clk_i),
-     .ena(~csn_i),
-     .wea(wea),
-     .addra(addr_i),
-     .dina(wdata_i),
-     .douta(rdata_o)
-     );
-
-endmodule : fpga_private_ram
diff --git a/fpga/pulpissimo-zcu104/rtl/fpga_slow_clk_gen.sv b/fpga/pulpissimo-zcu104/rtl/fpga_slow_clk_gen.sv
deleted file mode 100644
index f3db58f4..00000000
--- a/fpga/pulpissimo-zcu104/rtl/fpga_slow_clk_gen.sv
+++ /dev/null
@@ -1,82 +0,0 @@
-//-----------------------------------------------------------------------------
-// Title         : FPGA slow clk generator for PULPissimo
-//-----------------------------------------------------------------------------
-// File          : fpga_slow_clk_gen.sv
-// Author        : Manuel Eggimann  <meggimann@iis.ee.ethz.ch>
-// Created       : 20.05.2019
-//-----------------------------------------------------------------------------
-// Description : Instantiates Xilinx Clocking Wizard IP to generate the slow_clk
-// signal since for certain boards the available clock sources are to fast to
-// use directly.
-//-----------------------------------------------------------------------------
-// Copyright (C) 2013-2019 ETH Zurich, University of Bologna
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License. You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-//-----------------------------------------------------------------------------
-
-
-module fpga_slow_clk_gen
-  #(
-    parameter CLK_DIV_VALUE = 256 //The xilinx_slow_clk_mngr is supposed to
-                                  //generate an 8.3886MHz clock. We need to divide it
-                                  //by 256 to arrive to a 32.768kHz clock
-    )
-  (input logic ref_clk_i,
-   input logic rst_ni,
-   output logic slow_clk_o
-   );
-
-
-
-  localparam COUNTER_WIDTH = $clog2(CLK_DIV_VALUE);
-
-
-  //Create clock divider using BUFGCE cells as the PLL/MMCM cannot generate clocks
-  //slower than 4.69 MHz and we need 32.768kHz
-
-  logic [COUNTER_WIDTH-1:0] clk_counter_d, clk_counter_q;
-  logic                     clock_gate_en;
-
-  logic                     intermmediate_clock;
-
-  xilinx_slow_clk_mngr i_slow_clk_mngr
-    (
-     .resetn(rst_ni),
-     .clk_in1(ref_clk_i),
-     .clk_out1(intermmediate_clock)
-     );
-
-
-
-  always_comb begin
-    if (clk_counter_q == CLK_DIV_VALUE-1) begin
-      clk_counter_d = '0;
-      clock_gate_en = 1'b1;
-    end else begin
-      clk_counter_d = clk_counter_q + 1;
-      clock_gate_en = 1'b0;
-    end
-  end
-
-  always_ff @(posedge intermmediate_clock, negedge rst_ni) begin
-    if (!rst_ni) begin
-      clk_counter_q <= '0;
-    end else begin
-      clk_counter_q <= clk_counter_d;
-    end
-  end
-
-  BUFGCE i_clock_gate
-    (
-      .I(intermmediate_clock),
-      .CE(clock_gate_en),
-      .O(slow_clk_o)
-     );
-
-endmodule : fpga_slow_clk_gen
diff --git a/fpga/pulpissimo-zcu104/rtl/pad_functional_xilinx.sv b/fpga/pulpissimo-zcu104/rtl/pad_functional_xilinx.sv
deleted file mode 100644
index a3ca1cde..00000000
--- a/fpga/pulpissimo-zcu104/rtl/pad_functional_xilinx.sv
+++ /dev/null
@@ -1,48 +0,0 @@
-// Copyright 2018 ETH Zurich and University of Bologna.
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License.  You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-
-
-module pad_functional_pd
-(
-   input  logic             OEN,
-   input  logic             I,
-   output logic             O,
-   input  logic             PEN,
-   inout  logic             PAD
-);
-
-  (* PULLDOWN = "YES" *)
-  IOBUF iobuf_i (
-    .T ( OEN ),
-    .I ( I    ),
-    .O ( O    ),
-    .IO( PAD  )
-  );
-
-endmodule
-
-module pad_functional_pu
-(
-   input  logic             OEN,
-   input  logic             I,
-   output logic             O,
-   input  logic             PEN,
-   inout  logic             PAD
-);
-
-  (* PULLUP = "YES" *)
-  IOBUF iobuf_i (
-    .T ( OEN ),
-    .I ( I    ),
-    .O ( O    ),
-    .IO( PAD  )
-  );
-
-endmodule
\ No newline at end of file
diff --git a/fpga/pulpissimo-zcu104/rtl/pulp_clock_gating_xilinx.sv b/fpga/pulpissimo-zcu104/rtl/pulp_clock_gating_xilinx.sv
deleted file mode 100644
index 1e2db2d1..00000000
--- a/fpga/pulpissimo-zcu104/rtl/pulp_clock_gating_xilinx.sv
+++ /dev/null
@@ -1,21 +0,0 @@
-// Copyright 2018 ETH Zurich and University of Bologna.
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License. You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-
-module pulp_clock_gating
-  (
-   input  logic clk_i,
-   input  logic en_i,
-   input  logic test_en_i,
-   output logic clk_o
-   );
-
-   assign clk_o = clk_i;
-   
-endmodule
diff --git a/fpga/pulpissimo-zcu104/rtl/xilinx_pulpissimo.v b/fpga/pulpissimo-zcu104/rtl/xilinx_pulpissimo.v
deleted file mode 100644
index 46d58c73..00000000
--- a/fpga/pulpissimo-zcu104/rtl/xilinx_pulpissimo.v
+++ /dev/null
@@ -1,143 +0,0 @@
-//-----------------------------------------------------------------------------
-// Title         : PULPissimo Verilog Wrapper
-//-----------------------------------------------------------------------------
-// File          : xilinx_pulpissimo.v
-// Author        : Manuel Eggimann  <meggimann@iis.ee.ethz.ch>
-// Created       : 21.05.2019
-//-----------------------------------------------------------------------------
-// Description :
-// Verilog Wrapper of PULPissimo to use the module within Xilinx IP integrator.
-//-----------------------------------------------------------------------------
-// Copyright (C) 2013-2019 ETH Zurich, University of Bologna
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License. You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-//-----------------------------------------------------------------------------
-
-module xilinx_pulpissimo
-  (
-   input wire  ref_clk_p,
-   input wire  ref_clk_n,
-
-   inout wire  pad_uart_rx,
-   inout wire  pad_uart_tx,
-   inout wire  pad_uart_rts, //Mapped to spim_csn0
-   inout wire  pad_uart_cts, //Mapped to spim_sck
-
-   inout wire  led0_o, //Mapped to spim_csn1
-   inout wire  led1_o, //Mapped to cam_pclk
-   inout wire  led2_o, //Mapped to cam_hsync
-   inout wire  led3_o, //Mapped to cam_data0
-
-   inout wire  switch0_i, //Mapped to cam_data1
-   inout wire  switch1_i, //Mapped to cam_data2
-   inout wire  switch2_i, //Mapped to cam_data7
-   inout wire  switch3_i, //Mapped to cam_vsync
-
-   inout wire  btn0_i, //Mapped to cam_data3
-   inout wire  btn1_i, //Mapped to cam_data4
-   inout wire  btn2_i, //Mapped to cam_data5
-   inout wire  btn3_i, //Mapped to cam_data6
-
-   inout wire  pad_i2c0_sda,
-   inout wire  pad_i2c0_scl,
-
-   inout wire  pad_pmod0_4, //Mapped to spim_sdio0
-   inout wire  pad_pmod0_5, //Mapped to spim_sdio1
-   inout wire  pad_pmod0_6, //Mapped to spim_sdio2
-   inout wire  pad_pmod0_7, //Mapped to spim_sdio3
-
-   inout wire  pad_pmod1_0, //Mapped to sdio_data0
-   inout wire  pad_pmod1_1, //Mapped to sdio_data1
-   inout wire  pad_pmod1_2, //Mapped to sdio_data2
-   inout wire  pad_pmod1_3, //Mapped to sdio_data3
-   inout wire  pad_pmod1_4, //Mapped to i2s0_sck
-   inout wire  pad_pmod1_5, //Mapped to i2s0_ws
-   inout wire  pad_pmod1_6, //Mapped to i2s0_sdi
-   inout wire  pad_pmod1_7, //Mapped to i2s1_sdi
-
-   inout wire  pad_hdmi_scl, //Mapped to sdio_clk
-   inout wire  pad_hdmi_sda, //Mapped to sdio_cmd
-
-   input wire  pad_reset,
-
-   input wire  pad_jtag_tck,
-   input wire  pad_jtag_tdi,
-   output wire pad_jtag_tdo,
-   input wire  pad_jtag_tms
- );
-
-  localparam CORE_TYPE = 0; // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY)
-  localparam USE_FPU   = 1;
-  localparam USE_HWPE = 0;
-
-  wire        ref_clk;
-
-
-  //Differential to single ended clock conversion
-  IBUFGDS
-    #(
-      .IOSTANDARD("LVDS"),
-      .DIFF_TERM("FALSE"),
-      .IBUF_LOW_PWR("FALSE"))
-  i_sysclk_iobuf
-    (
-     .I(ref_clk_p),
-     .IB(ref_clk_n),
-     .O(ref_clk)
-     );
-
-  pulpissimo
-    #(.CORE_TYPE(CORE_TYPE),
-      .USE_FPU(USE_FPU),
-      .USE_HWPE(USE_HWPE)
-      ) i_pulpissimo
-      (
-       .pad_spim_sdio0(pad_pmod0_4),
-       .pad_spim_sdio1(pad_pmod0_5),
-       .pad_spim_sdio2(pad_pmod0_6),
-       .pad_spim_sdio3(pad_pmod0_7),
-       .pad_spim_csn0(pad_uart_rts),
-       .pad_spim_csn1(led0_o),
-       .pad_spim_sck(pad_uart_cts),
-       .pad_uart_rx(pad_uart_rx),
-       .pad_uart_tx(pad_uart_tx),
-       .pad_cam_pclk(led1_o),
-       .pad_cam_hsync(led2_o),
-       .pad_cam_data0(led3_o),
-       .pad_cam_data1(switch0_i),
-       .pad_cam_data2(switch1_i),
-       .pad_cam_data3(btn0_i),
-       .pad_cam_data4(btn1_i),
-       .pad_cam_data5(btn2_i),
-       .pad_cam_data6(btn3_i),
-       .pad_cam_data7(switch2_i),
-       .pad_cam_vsync(switch3_i),
-       .pad_sdio_clk(pad_hdmi_scl),
-       .pad_sdio_cmd(pad_hdmi_sda),
-       .pad_sdio_data0(pad_pmod1_0),
-       .pad_sdio_data1(pad_pmod1_1),
-       .pad_sdio_data2(pad_pmod1_2),
-       .pad_sdio_data3(pad_pmod1_3),
-       .pad_i2c0_sda(pad_i2c0_sda),
-       .pad_i2c0_scl(pad_i2c0_scl),
-       .pad_i2s0_sck(pad_pmod1_4),
-       .pad_i2s0_ws(pad_pmod1_5),
-       .pad_i2s0_sdi(pad_pmod1_6),
-       .pad_i2s1_sdi(pad_pmod1_7),
-       .pad_reset_n(~pad_reset),
-       .pad_jtag_tck(pad_jtag_tck),
-       .pad_jtag_tdi(pad_jtag_tdi),
-       .pad_jtag_tdo(pad_jtag_tdo),
-       .pad_jtag_tms(pad_jtag_tms),
-       .pad_jtag_trst(1'b1),
-       .pad_xtal_in(ref_clk),
-       .pad_bootsel()
-       );
-
-endmodule
diff --git a/fpga/pulpissimo-zcu104/tcl/.gitignore b/fpga/pulpissimo-zcu104/tcl/.gitignore
deleted file mode 100644
index 587a0fa6..00000000
--- a/fpga/pulpissimo-zcu104/tcl/.gitignore
+++ /dev/null
@@ -1,6 +0,0 @@
-#Ignore tcl files generated by ipstools
-ips_add_files.tcl
-ips_inc_dirs.tcl
-ips_src_files.tcl
-rtl_add_files.tcl
-rtl_src_files.tcl
\ No newline at end of file
diff --git a/fpga/pulpissimo-zcu104/tcl/messages.tcl b/fpga/pulpissimo-zcu104/tcl/messages.tcl
deleted file mode 100644
index e8bfaf90..00000000
--- a/fpga/pulpissimo-zcu104/tcl/messages.tcl
+++ /dev/null
@@ -1,13 +0,0 @@
-# sets up Vivado messages in a more sensible way
-
-set_msg_config -id {[Synth 8-3352]}         -new_severity "critical warning"
-set_msg_config -id {[Synth 8-350]}          -new_severity "critical warning"
-set_msg_config -id {[Synth 8-2490]}         -new_severity "warning"
-set_msg_config -id {[Synth 8-2306]}         -new_severity "info"
-set_msg_config -id {[Synth 8-3331]}         -new_severity "critical warning"
-set_msg_config -id {[Synth 8-3332]}         -new_severity "info"
-set_msg_config -id {[Synth 8-2715]}         -new_severity "error"
-set_msg_config -id {[Opt 31-35]}            -new_severity "info"
-set_msg_config -id {[Opt 31-32]}            -new_severity "info"
-set_msg_config -id {[Shape Builder 18-119]} -new_severity "warning"
-set_msg_config -id {[Filemgmt 20-742]}      -new_severity "error"
diff --git a/fpga/pulpissimo-zcu104/tcl/run.tcl b/fpga/pulpissimo-zcu104/tcl/run.tcl
deleted file mode 100644
index 8d138a3b..00000000
--- a/fpga/pulpissimo-zcu104/tcl/run.tcl
+++ /dev/null
@@ -1,135 +0,0 @@
-set project pulpissimo_zcu104
-set RTL ../../../rtl
-set IPS ../../../ips
-set CONSTRS constraints
-
-
-# detect board
-if [info exists ::env(BOARD)] {
-    set BOARD $::env(BOARD)
-} else {
-    puts "Please execute 'source ../sourceme.sh first before you start vivado in order to setup necessary environment variables."
-    exit
-}
-if [info exists ::env(XILINX_BOARD)] {
-    set XILINX_BOARD $::env(XILINX_BOARD)
-}
-
-# create project
-create_project $project . -force -part $::env(XILINX_PART)
-set_property board_part $XILINX_BOARD [current_project]
-
-# set up meaningfull errors
-source tcl/messages.tcl
-
-# set up includes
-source ../pulpissimo/tcl/ips_inc_dirs.tcl
-set_property include_dirs $INCLUDE_DIRS [current_fileset]
-set_property include_dirs $INCLUDE_DIRS [current_fileset -simset]
-
-# setup and add IP source files
-source ../pulpissimo/tcl/ips_src_files.tcl
-source ../pulpissimo/tcl/ips_add_files.tcl
-
-# setup and add RTL source files
-source ../pulpissimo/tcl/rtl_src_files.tcl
-source ../pulpissimo/tcl/rtl_add_files.tcl
-
-# Override IPSApprox default variables
-set FPGA_RTL rtl
-set FPGA_IPS ips
-
-# remove duplicate incompatible modules
-remove_files $IPS/pulp_soc/rtl/components/axi_slice_dc_slave_wrap.sv
-remove_file $IPS/pulp_soc/rtl/components/axi_slice_dc_master_wrap.sv
-remove_file $IPS/tech_cells_generic/pad_functional_xilinx.sv
-
-# Set Verilog Defines.
-set DEFINES "FPGA_TARGET_XILINX=1 PULP_FPGA_EMUL=1 AXI4_XCHECK_OFF=1"
-if { $BOARD == "zcu104" } {
-    set DEFINES "$DEFINES ZCU104=1"
-}
-set_property verilog_define $DEFINES [current_fileset]
-
-# detect target clock
-if [info exists ::env(FC_CLK_PERIOD_NS)] {
-    set FC_CLK_PERIOD_NS $::env(FC_CLK_PERIOD_NS)
-} else {
-    set FC_CLK_PERIOD_NS 10.000
-}
-set CLK_HALFPERIOD_NS [expr ${FC_CLK_PERIOD_NS} / 2.0]
-
-# Add toplevel wrapper
-add_files -norecurse $FPGA_RTL/xilinx_pulpissimo.v
-
-# Add Xilinx IPs
-read_ip $FPGA_IPS/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci
-read_ip $FPGA_IPS/xilinx_slow_clk_mngr/ip/xilinx_slow_clk_mngr.xci
-read_ip $FPGA_IPS/xilinx_interleaved_ram/ip/xilinx_interleaved_ram.xci
-read_ip $FPGA_IPS/xilinx_private_ram/ip/xilinx_private_ram.xci
-
-# Add wrappers and xilinx specific techcells
-add_files -norecurse $FPGA_RTL/fpga_clk_gen.sv
-add_files -norecurse $FPGA_RTL/fpga_slow_clk_gen.sv
-add_files -norecurse $FPGA_RTL/fpga_interleaved_ram.sv
-add_files -norecurse $FPGA_RTL/fpga_private_ram.sv
-add_files -norecurse $FPGA_RTL/fpga_bootrom.sv
-add_files -norecurse $FPGA_RTL/pad_functional_xilinx.sv
-add_files -norecurse $FPGA_RTL/pulp_clock_gating_xilinx.sv
-
-
-# set pulpissimo as top
-set_property top xilinx_pulpissimo [current_fileset]; #
-
-# needed only if used in batch mode
-update_compile_order -fileset sources_1
-
-# Add constraints
-add_files -fileset constrs_1 -norecurse $CONSTRS/zcu104.xdc
-
-# Elaborate design
-synth_design -rtl -name rtl_1 -sfcu;# sfcu -> run synthesis in single file compilation unit mode
-
-
-
-# launch synthesis
-set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY none [get_runs synth_1]
-set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value -sfcu -objects [get_runs synth_1] ;# Use single file compilation unit mode to prevent issues with import pkg::* statements in the codebase
-launch_runs synth_1 -jobs 8
-wait_on_run synth_1
-open_run synth_1 -name netlist_1
-set_property needs_refresh false [get_runs synth_1]
-
-# Remove unused IOBUF cells in padframe (they are not optimized away since the
-# pad driver also drives the input creating a datapath from pad_xy_o to pad_xy_i
-# )
-remove_cell i_pulpissimo/pad_frame_i/padinst_bootsel
-
-
-# Launch Implementation
-
-# set for RuntimeOptimized implementation
-set_property "steps.opt_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
-set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
-set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
-set_property "steps.phys_opt_design.args.is_enabled" true [get_runs impl_1]
-set_property "steps.phys_opt_design.args.directive" "ExploreWithHoldFix" [get_runs impl_1]
-set_property "steps.post_route_phys_opt_design.args.is_enabled" true [get_runs impl_1]
-set_property "steps.post_route_phys_opt_design.args.directive" "ExploreWithAggressiveHoldFix" [get_runs impl_1]
-
-set_property STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE true [get_runs impl_1]
-
-launch_runs impl_1 -jobs 8
-wait_on_run impl_1
-launch_runs impl_1 -to_step write_bitstream
-wait_on_run impl_1
-
-open_run impl_1
-
-# Generate reports
-exec mkdir -p reports/
-exec rm -rf reports/*
-check_timing                                                              -file reports/${project}.check_timing.rpt
-report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack   -file reports/${project}.timing_WORST_100.rpt
-report_timing -nworst 1 -delay_type max -sort_by group                    -file reports/${project}.timing.rpt
-report_utilization -hierarchical                                          -file reports/${project}.utilization.rpt
diff --git a/fpga/sim/.gitignore b/fpga/sim/.gitignore
new file mode 100644
index 00000000..b37fa9c4
--- /dev/null
+++ b/fpga/sim/.gitignore
@@ -0,0 +1,40 @@
+# ignore modelsim libraries
+modelsim_libs
+work
+xilinx_libs
+
+# ignore automatically generated stuff by modelsim
+transcript
+vsim.wlf
+wlft*
+vish_stacktrace.vstf
+stdout/uart
+CLUSTER_FLL.log  
+CORE*.txt  
+SOC_FLL.log 
+trace_core*
+stim.txt
+vsim_stacktrace.vstf
+
+CORE*_TCDM_DUMP.txt
+stdout/stdout*
+CORE*
+FETCH_CORE_*
+CLUSTER_FLL.log
+SOC_FLL.log
+core_state
+i2s_buffer.hex
+i2s_buffer_0.hex
+i2s_buffer_1.hex
+i2s_buffer_2.hex
+i2s_buffer_3.hex
+
+
+
+# ignore modelsim.ini
+modelsim.ini
+
+# ignore c build files
+slm_files
+simvectors
+vectors
diff --git a/fpga/sim/Makefile b/fpga/sim/Makefile
new file mode 100644
index 00000000..ba02faec
--- /dev/null
+++ b/fpga/sim/Makefile
@@ -0,0 +1,80 @@
+.PHONY: build lib clean sim simc
+
+mkfile_path := $(dir $(abspath $(firstword $(MAKEFILE_LIST))))
+
+VSIM        ?= vsim
+VSIM_FLAGS  = -gUSE_SDVT_SPI=0 -gUSE_SDVT_CPI=0 -gBAUDRATE=115200 \
+		-gENABLE_DEV_DPI=0 -gLOAD_L2=JTAG -gUSE_SDVT_I2S=0
+
+SVLIB	    =  ../../rtl/tb/remote_bitbang/librbs
+
+PULP_CLUSTER_NETLIST  = ../pulp_cluster/pulp_cluster_postsynt.v
+PULPEMU_TIME_NETLIST  = ../pulpemu/pulpemu_timesim.v
+PULPEMU_FUNC_NETLIST  = ../pulpemu/pulpemu_funcsim.v
+
+all: clean lib build opt
+
+sim:
+	$(VSIM) -64 -gui vopt_tb -L models_lib -L vip_lib \
+		-suppress vsim-3009 -suppress vsim-8683 \
+		+UVM_NO_RELNOTES -stats -t ps \
+		-sv_lib $(SVLIB) $(VSIM_FLAGS) \
+		-do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1"
+
+simc:
+	$(VSIM) -64 -c vopt_tb -L models_lib -L vip_lib \
+		-suppress vsim-3009 -suppress vsim-8683 \
+		+UVM_NO_RELNOTES -stats -t ps \
+		-sv_lib $(SVLIB) $(VSIM_FLAGS) \
+		-do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1" \
+		-do "run -all" \
+		-do "quit -code [examine -radix decimal sim:/tb_pulp/exit_status]"
+
+opt:
+	$(mkfile_path)/tcl_files/rtl_vopt.tcl
+
+build:
+	@make --no-print-directory -f $(mkfile_path)/vcompile/fpga.mk build
+	@make --no-print-directory -f $(mkfile_path)/vcompile/ips.mk build
+	@make --no-print-directory -f $(mkfile_path)/vcompile/rtl.mk build
+
+build_fpga_pulp_cluster:
+	@if [ ! -f $(PULP_CLUSTER_NETLIST) ]; then\
+	  echo "Can not find $(PULP_CLUSTER_NETLIST)! Please go to ../pulp_cluster and execute <python postsynth_names.py> to get netlist!";\
+	fi
+	@make --no-print-directory -f $(mkfile_path)/vcompile/fpga.mk build
+	@make --no-print-directory -f $(mkfile_path)/vcompile/ips.mk build
+	@make --no-print-directory -f $(mkfile_path)/vcompile/rtl.mk build
+	@vlog -quiet +define+PULP_FPGA_EMUL +define+PULP_FPGA_SIM -suppress 2583 -suppress 13314 -work modelsim_libs/pulp_cluster_lib $(PULP_CLUSTER_NETLIST)
+	@vlog -quiet -sv +incdir+../../rtl/includes +define+USE_CLUSTER_NETLIST \
+	 +define+PULP_FPGA_EMUL +define+PULP_FPGA_SIM -suppress 2583 -suppress 13314 \
+	-work modelsim_libs/pulp_lib ../../rtl/pulp/cluster_domain.sv
+
+build_fpga_pulpemu_function:
+	@make --no-print-directory -f $(mkfile_path)/vcompile/rtl/vip.mk build
+	@make --no-print-directory -f $(mkfile_path)/vcompile/rtl/tb.mk USE_NETLIST=1 build
+	@vlog -quiet -work modelsim_libs/pulpemu_lib $(PULPEMU_FUNC_NETLIST)
+
+build_fpga_pulpemu_timing:
+	@make --no-print-directory -f $(mkfile_path)/vcompile/rtl/vip.mk build
+	@make --no-print-directory -f $(mkfile_path)/vcompile/tb.mk USE_NETLIST=1 build
+	@vlog -quiet -work modelsim_libs/pulpemu_lib $(PULPEMU_TIME_NETLIST)
+
+lib:
+	@make --no-print-directory -f $(mkfile_path)/vcompile/ips.mk lib
+	@make --no-print-directory -f $(mkfile_path)/vcompile/rtl.mk lib
+
+xilinx:
+	vmap secureip xilinx_libs/secureip
+	vmap simprims_ver xilinx_libs/simprims_ver
+	vmap unifast xilinx_libs/unifast
+	vmap unifast_ver xilinx_libs/unifast_ver
+	vmap unimacro_ver xilinx_libs/unimacro_ver
+	vmap unisim xilinx_libs/unisim
+	vmap unisims_ver xilinx_libs/unisims_ver
+	vmap unimacro xilinx_libs/unimacro
+	vmap work modelsim_libs/work
+
+clean:
+	@make --no-print-directory -f $(mkfile_path)/vcompile/ips.mk clean
+	@make --no-print-directory -f $(mkfile_path)/vcompile/rtl.mk clean
diff --git a/fpga/sim/README.md b/fpga/sim/README.md
new file mode 100644
index 00000000..f79be9f6
--- /dev/null
+++ b/fpga/sim/README.md
@@ -0,0 +1,38 @@
+To do the compilation of RTL, Make sure the fpga IPs are already compiled, must source sourceme.sh
+
+
+1. Create xilinx_libs for modelsim simulation, please wait a few minutes.  
+   bash compile_simlibs.sh
+
+2. Use following command to compile your FPGA RTL platform  
+   make clean lib build opt  
+   clean  - clean all output including work  
+   lib    - create all modelsim_libs IP lib  
+   build  - build all rtl including testbench  
+   build_fpga_pulp_cluster      - build all rtl including testbench, replace pulp_cluster with netlist 
+   build_fpga_pulpemu_function  - build all rtl including testbench, replace pulpemu with functional netlist 
+   build_fpga_pulpemu_timing    - build all rtl including testbench, replace pulpemu with timing netlist 
+   opt    - modelsim optimization  
+
+3. ! For any sdk, do as usual, only change your VSIM_PATH to /Your/pulp/project/fpga/sim 
+   export VSIM_PATH=/Your/pulp/project/fpga/sim 
+
+4. (Only for gap_sdk) go to your SDK, source sourceme.sh, then go to your test, add < load=-l JTAG_DEV > in Makefile  
+   make clean all run/gui platform=fpga_rtl 
+
+
+RTL simualtion  
+Must do instruction 3. before continuing:  
+
+a. FPGA RTL simulation 
+make clean lib build opt 
+
+b. FPGA RTL pulp_cluster netlist simulation 
+make clean lib build_fpga_pulp_cluster opt 
+
+c. FPGA RTL pulpemu functional netlist simulation 
+make clean lib build_fpga_pulpemu_function opt 
+
+d. FPGA RTL pulpemu timing netlist simulation (need sdf) 
+make clean lib build_fpga_pulpemu_timing opt 
+
diff --git a/fpga/sim/boot b/fpga/sim/boot
new file mode 120000
index 00000000..6785301d
--- /dev/null
+++ b/fpga/sim/boot
@@ -0,0 +1 @@
+../../sim/vsim/boot/
\ No newline at end of file
diff --git a/fpga/sim/compile_simlibs.sh b/fpga/sim/compile_simlibs.sh
new file mode 100755
index 00000000..a3689e5a
--- /dev/null
+++ b/fpga/sim/compile_simlibs.sh
@@ -0,0 +1,3 @@
+#!/bin/bash
+vivado -mode batch -source compile_simlibs.tcl
+
diff --git a/fpga/sim/compile_simlibs.tcl b/fpga/sim/compile_simlibs.tcl
new file mode 100644
index 00000000..5c8901b8
--- /dev/null
+++ b/fpga/sim/compile_simlibs.tcl
@@ -0,0 +1,3 @@
+# to be wrapped by compile_simlibs.sh
+compile_simlib -simulator questa -directory ./xilinx_libs
+
diff --git a/fpga/sim/misc/glbl.v b/fpga/sim/misc/glbl.v
new file mode 100644
index 00000000..be642335
--- /dev/null
+++ b/fpga/sim/misc/glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/fpga/sim/tcl_files/config/.gitignore b/fpga/sim/tcl_files/config/.gitignore
new file mode 100644
index 00000000..6b9d01e9
--- /dev/null
+++ b/fpga/sim/tcl_files/config/.gitignore
@@ -0,0 +1,2 @@
+vsim_ips.tcl
+vsim_rtl.tcl
diff --git a/fpga/sim/tcl_files/config/export_all.tcl b/fpga/sim/tcl_files/config/export_all.tcl
new file mode 100755
index 00000000..dca8bede
--- /dev/null
+++ b/fpga/sim/tcl_files/config/export_all.tcl
@@ -0,0 +1,3 @@
+vcd file -compress export.vcd.gz
+vcd add -r -optcells -internal -ports {sim:/tb_pulp/i_dut/*}
+
diff --git a/fpga/sim/tcl_files/config/run_and_exit.tcl b/fpga/sim/tcl_files/config/run_and_exit.tcl
new file mode 100644
index 00000000..d417d543
--- /dev/null
+++ b/fpga/sim/tcl_files/config/run_and_exit.tcl
@@ -0,0 +1,10 @@
+# check exit status in tb and quit the simulation accordingly
+proc run_and_exit {} {
+    onElabError {quit -code 1}
+    onerror {quit -code 1}
+    if {[catch {run -all} ]} {
+      quit -code 1
+    }
+    quit -code [examine -radix decimal sim:/tb/tb_test_i/sim_manager_i/exit_status]
+}
+
diff --git a/fpga/sim/tcl_files/config/vsim.tcl b/fpga/sim/tcl_files/config/vsim.tcl
new file mode 100644
index 00000000..15bc73ce
--- /dev/null
+++ b/fpga/sim/tcl_files/config/vsim.tcl
@@ -0,0 +1,155 @@
+#######################################
+# Define vsim path and custom variables passed via make
+if {[info exists ::env(VSIM_PATH)]} {
+    quietly set VSIM_SCRIPTS_PATH $::env(VSIM_PATH)
+} {
+    quietly set VSIM_SCRIPTS_PATH ./
+}
+
+if {[info exists ::env(TB_PATH)]} {
+    quietly set TB_PATH_TCL $::env(TB_PATH)
+} {
+    quietly set TB_PATH_TCL "$VSIM_SCRIPTS_PATH/../../fe/tb/"
+}
+
+if {[info exists ::env(VSIM_FLAGS)]} {
+    quietly set VSIM_FLAGS_TCL $::env(VSIM_FLAGS)
+} {
+    quietly set VSIM_FLAGS_TCL ""
+}
+
+if {[info exists ::env(VSIM_RUNNER_FLAGS)]} {
+    quietly set VSIM_FLAGS_TCL "$VSIM_FLAGS_TCL $::env(VSIM_RUNNER_FLAGS)"
+}
+
+quietly set VSIM_TB_PATH $VSIM_SCRIPTS_PATH/../tb
+#######################################
+#######################################
+quietly source $VSIM_SCRIPTS_PATH/tcl_files/config/vsim_ips.tcl
+
+quietly source $VSIM_SCRIPTS_PATH/tcl_files/config/vsim_sdvt.tcl
+quietly source $VSIM_SCRIPTS_PATH/tcl_files/config/vsim_custom.tcl
+
+quietly set design_libs "\
+  "
+
+set sdkLib ""
+
+if {[info exists ::env(PULP_SIMCHECKER)]} {
+  set sdkLib "-sv_lib $::env(PULP_SDK_HOME)/install/ws/lib/libri5cyv2sim $sdkLib"
+}
+
+quietly set warning_args "\
+  +nowarnTRAN \
+  +nowarnTSCALE \
+  +nowarnTFMPC \
+  "
+
+quietly set define_args "\
+  +TB_PATH=$TB_PATH_TCL \
+  +UVM_NO_RELNOTES \
+  "
+
+quietly set common_args "\
+  $design_libs \
+  $warning_args \
+  $define_args \
+  "
+
+quietly set custom_args "\
+  $VSIM_FLAGS_TCL \
+  $uart_drv_mon \
+  $use_dev_dpi \
+  $sdkLib \
+  "
+
+quietly set common_sdvt_args "\
+  $sdvt_debug_level \
+  $use_sdvt_cpi \
+  $sdvt_cpi_test \
+  $sdvt_cpi_cmds \
+  $sdvt_cpi_checker_ena \
+  $sdvt_cpi_hres \
+  $sdvt_cpi_vres \
+  $use_sdvt_i2s \
+  $sdvt_i2s_test \
+  $sdvt_i2s_cmds \
+  $use_sdvt_spi \
+  $sdvt_spi_test \
+  $sdvt_spi_cmds \
+  "
+
+quietly set vsim_custom_args "\
+  $vsim_record_wlf \
+  $vsim_do_files \
+  $use_sdvt \
+  +VSIM_PATH=$::env(VSIM_PATH) \
+  "
+
+quietly set vopt_args ""
+if {$vopt_acc_ena == "YES"} {
+  #+ quietly append vopt_args $vopt_args "+acc=abflmnprstv"
+  quietly append vopt_args $vopt_args "+acc=mnprv \
+                                       -assertdebug \
+                                       -bitscalars \
+                                       -fsmdebug \
+                                       -linedebug"
+}
+if {[info exists vopt_cov]} {
+  quietly append vopt_args $vopt_args $vopt_cov
+}
+if {$vopt_args != ""} {
+  quietly set vsim_vopt_args "-voptargs=\"$vopt_args\""
+} {
+  quietly set vsim_vopt_args ""
+}
+
+quietly set vopt_cmd "vopt -quiet tb \
+              $common_args \
+              $custom_args \
+              $common_sdvt_args \
+              $vopt_args \
+              -o pulp_opt -work work"
+
+if {[info exists ::env(VOPT_FLOW)]} {
+    onElabError {quit -code 1}
+    onerror {quit -code 1}
+    quietly eval $vopt_cmd
+    quietly eval "quit"
+
+
+} {
+  set vsim_cmd "vsim -c -quiet $TB \
+                -t ps \
+                $vsim_cov \
+                $common_args \
+                $custom_args \
+                $common_sdvt_args \
+                $vsim_custom_args \
+                $vsim_vopt_args \
+                "
+
+    eval $vsim_cmd
+    eval $vsimcmd_test_path
+    eval $vsimcmd_testname
+
+    # Added these variables to avoid dummy warnings in the FLL
+    set StdArithNoWarnings 1
+    set NumericStdNoWarnings 1
+
+    # check exit status in tb and quit the simulation accordingly
+    proc run_and_exit {} {
+        run -all
+	if {[info exists ::env(VSIM_EXIT_SIGNAL)]} {
+	    quit -code [examine -radix decimal sim:$::env(VSIM_EXIT_SIGNAL)]
+	} else {
+	    quit -code [examine -radix decimal sim:/tb_pulp/exit_status]
+	}
+    }
+
+    #+ set StdArithNoWarnings 1
+    #+ set NumericStdNoWarnings 1
+    #+ run 1ps
+    #+ set StdArithNoWarnings 0
+    #+ set NumericStdNoWarnings 0
+}
diff --git a/fpga/sim/tcl_files/config/vsim_custom.tcl b/fpga/sim/tcl_files/config/vsim_custom.tcl
new file mode 100644
index 00000000..b78475a7
--- /dev/null
+++ b/fpga/sim/tcl_files/config/vsim_custom.tcl
@@ -0,0 +1,81 @@
+
+#######################################
+quietly set testname_uid "dummy_testname"
+
+quietly set vsim_testname "dummy_testname"
+if {[info exists ::env(PLPTEST_NAME)]} {
+    quietly set vsim_testname $::env(PLPTEST_NAME)
+    quietly regsub -all {\.} $vsim_testname _ testname_uid
+}  {
+  if {[info exists ::env(TESTNAME)]} {
+    quietly set testname_uid "$::env(TESTNAME)"
+  }
+}
+quietly set vsimcmd_testname "coverage attribute -test $testname_uid -name TESTNAME_PLP -value $vsim_testname"
+
+# vsim UID testname
+#+ if {[info exists ::env(PLPTEST_RUN_ID)]} {
+#+   #+ quietly set testname_uid "$::env(PLPTEST_RUN_ID)"
+#+ } {
+#+ }
+quietly set vsim_testname_uid "-testname $testname_uid"
+
+quietly set vsim_test_path "dummy_testpath"
+if {[info exists ::env(PLPTEST_PATH)]} {
+    quietly set vsim_test_path $::env(PLPTEST_PATH)
+} 
+quietly set vsimcmd_test_path "coverage attribute -test $testname_uid -name TESTPATH -value $vsim_test_path"
+
+# vsim coverage enable
+quietly set vsim_cov ""
+if {[info exists ::env(VSIM_COV)]} {
+  if {$::env(VSIM_COV) == "YES"} {
+    quietly set vsim_cov "-coverage -coverstore $GAP_PATH_TCL/fe/sim/cov $vsim_testname_uid"
+    quietly set vopt_cov "+cover+pulp_chip."
+    #+ quietly set vopt_cov "+cover+pulp_chip. -coveropt 1"
+  } 
+} 
+#######################################
+#######################################
+# enable access control in vopt when vsim gui mode activated
+quietly set vopt_acc_ena ""
+if {[info exists ::env(VOPT_ACC_ENA)]} {
+  if {$::env(VOPT_ACC_ENA) == "YES"} {
+    quietly set vopt_acc_ena "YES"
+  } 
+} 
+
+#######################################
+# Enable DPI use in tb
+#######################################
+quietly set use_dev_dpi "-gENABLE_DEV_DPI=0"
+if {[info exists ::env(PLP_DEVICES)]} {
+  quietly set use_dev_dpi "-gENABLE_DEV_DPI=1"
+} 
+
+#######################################
+# record wlf
+quietly set vsim_record_wlf ""
+if {[info exists ::env(RECORD_WLF)]} {
+  if {$::env(RECORD_WLF) == "YES"} {
+    # enable access control in vopt when recordwlf mode activated
+    quietly set vopt_acc_ena "YES"
+    quietly set vsim_record_wlf "-wlf \"gap.wlf\""
+  } 
+} 
+
+# select do file for waveform selection
+quietly set vsim_do_files ""
+if {[info exists ::env(DO_FILES)]} {
+    quietly set vsim_do_files $::env(DO_FILES)
+} 
+#######################################
+#######################################
+# UART tb or VIP select
+quietly set uart_drv_mon ""
+if {[info exists ::env(UART_DRV_MON)]} {
+  if {$::env(UART_DRV_MON) == "VIP"} {
+    quietly set uart_drv_mon "+uart_drv_mon=$::env(UART_DRV_MON)"
+  } 
+} 
+#######################################
diff --git a/fpga/sim/tcl_files/config/vsim_fpga.tcl b/fpga/sim/tcl_files/config/vsim_fpga.tcl
new file mode 100644
index 00000000..a310ec6d
--- /dev/null
+++ b/fpga/sim/tcl_files/config/vsim_fpga.tcl
@@ -0,0 +1,15 @@
+set VSIM_FPGA_LIBS " \
+  -L fpga_lib \
+  -L secureip \
+  -L simprims_ver \
+  -L unifast \
+  -L unifast_ver \
+  -L unimacro \
+  -L unimacro_ver \
+  -L unisim \
+  -L unisims_ver \
+  +nowarnTRAN \
+  +nowarnTSCALE \
+  +nowarnTFMPC \
+  glbl \
+"
diff --git a/fpga/sim/tcl_files/config/vsim_sdvt.tcl b/fpga/sim/tcl_files/config/vsim_sdvt.tcl
new file mode 100644
index 00000000..8d749cae
--- /dev/null
+++ b/fpga/sim/tcl_files/config/vsim_sdvt.tcl
@@ -0,0 +1,98 @@
+
+#######################################
+# SDVT support
+if {[info exists ::env(SMARTDV_HOME)]} {
+    quietly set SMARTDV_HOME $::env(SMARTDV_HOME)
+} {
+    quietly set SMARTDV_HOME ./
+}
+
+quietly set use_sdvt ""
+if {[info exists ::env(USE_SDVT)]} {
+  if {$::env(USE_SDVT) == "YES"} {
+    quietly set use_sdvt "-pli $VSIM_TB_PATH/smartdv_vip_models/sdvt_license_fl_mti_64.so"
+  } 
+} 
+
+# SMARTDV  Debug level 1 - verbose, 2 - debug, 3 - info, 4 - warning, 5 - error
+quietly set sdvt_debug_level ""
+if {[info exists ::env(SDVT_DEBUG_LEVEL)]} {
+  quietly set sdvt_debug_level "+sdvt_debug=$::env(SDVT_DEBUG_LEVEL)"
+} 
+
+#######################################
+#### SDVT CPI support
+quietly set use_sdvt_cpi "-gUSE_SDVT_CPI=0"
+if {[info exists ::env(SDVT_CPI)]} {
+  if {$::env(SDVT_CPI) == "YES"} {
+    quietly set use_sdvt_cpi "-gUSE_SDVT_CPI=1"
+  } 
+} 
+
+quietly set sdvt_cpi_test "" 
+if {[info exists ::env(SDVT_CPI_TEST)]} {
+  quietly set sdvt_cpi_test "+sdvt_cpi_test=$::env(SDVT_CPI_TEST)"
+} 
+
+## camera number of images to be transmitted
+quietly set sdvt_cpi_cmds "" 
+if {[info exists ::env(SDVT_CPI_CMDS)]} {
+  quietly set sdvt_cpi_cmds "+sdvt_cpi_cmds=$::env(SDVT_CPI_CMDS)"
+} 
+
+quietly set sdvt_cpi_checker_ena ""
+if {[info exists ::env(SDVT_CPI_CHECKER_ENA)]} {
+  if {$::env(SDVT_CPI_CHECKER_ENA) == "YES"} {
+    quietly set sdvt_cpi_checker_ena "+SDVT_CPI_CHECKER_ENA"
+  } 
+} 
+
+quietly set sdvt_cpi_hres "" 
+if {[info exists ::env(SDVT_CPI_H_RES)]} {
+  quietly set sdvt_cpi_hres "+sdvt_cpi_hres=$::env(SDVT_CPI_H_RES)"
+} 
+
+quietly set sdvt_cpi_vres "" 
+if {[info exists ::env(SDVT_CPI_V_RES)]} {
+  quietly set sdvt_cpi_vres "+sdvt_cpi_vres=$::env(SDVT_CPI_V_RES)"
+} 
+#######################################
+#### SDVT I2S support
+quietly set use_sdvt_i2s "-gUSE_SDVT_I2S=0"
+if {[info exists ::env(SDVT_I2S)]} {
+  if {$::env(SDVT_I2S) == "YES"} {
+    quietly set use_sdvt_i2s "-gUSE_SDVT_I2S=1"
+  } 
+} 
+
+quietly set sdvt_i2s_test "" 
+if {[info exists ::env(SDVT_I2S_TEST)]} {
+  quietly set sdvt_i2s_test "+sdvt_i2s_test=$::env(SDVT_I2S_TEST)"
+} 
+
+## camera number of images to be transmitted
+quietly set sdvt_i2s_cmds "" 
+if {[info exists ::env(SDVT_I2S_CMDS)]} {
+  quietly set sdvt_i2s_cmds "+sdvt_i2s_cmds=$::env(SDVT_I2S_CMDS)"
+} 
+
+#######################################
+#### SDVT SPI support
+quietly set use_sdvt_spi "-gUSE_SDVT_SPI=0"
+if {[info exists ::env(SDVT_SPI)]} {
+  if {$::env(SDVT_SPI) == "YES"} {
+    quietly set use_sdvt_spi "-gUSE_SDVT_SPI=1"
+  } 
+} 
+
+quietly set sdvt_spi_test "" 
+if {[info exists ::env(SDVT_SPI_TEST)]} {
+  quietly set sdvt_spi_test "+sdvt_spi_test=$::env(SDVT_SPI_TEST)"
+} 
+
+## camera number of images to be transmitted
+quietly set sdvt_spi_cmds "" 
+if {[info exists ::env(SDVT_SPI_CMDS)]} {
+  quietly set sdvt_spi_cmds "+sdvt_spi_cmds=$::env(SDVT_SPI_CMDS)"
+} 
+
diff --git a/fpga/sim/tcl_files/export_run.tcl b/fpga/sim/tcl_files/export_run.tcl
new file mode 100755
index 00000000..1fb87948
--- /dev/null
+++ b/fpga/sim/tcl_files/export_run.tcl
@@ -0,0 +1,7 @@
+#!/bin/bash
+
+set TB "vopt_tb -L models_lib -L vip_lib"
+
+source ./tcl_files/config/vsim.tcl
+source ./tcl_files/config/export_all.tcl
+
diff --git a/fpga/sim/tcl_files/rtl_vopt.tcl b/fpga/sim/tcl_files/rtl_vopt.tcl
new file mode 100755
index 00000000..feacb1f2
--- /dev/null
+++ b/fpga/sim/tcl_files/rtl_vopt.tcl
@@ -0,0 +1,41 @@
+#!/usr/bin/env tclsh
+
+source ./tcl_files/config/vsim_ips.tcl
+source ./tcl_files/config/vsim_rtl.tcl
+source ./tcl_files/config/vsim_fpga.tcl
+
+
+proc color {foreground text} {
+    # tput is a little Unix utility that lets you use the termcap database
+    # *much* more easily...
+    return [exec tput setaf $foreground]$text[exec tput sgr0]
+}
+
+if {[catch {
+  info exists $::env(VSIM_PATH)
+}]} {
+  puts [concat [color 1 "ERROR"] ": VSIM_PATH should be defined before building the RTL platform."]
+  exit 1
+}
+eval exec vlib $::env(VSIM_PATH)/modelsim_libs/tb_lib
+eval exec vmap secureip xilinx_libs/secureip
+eval exec vmap simprims_ver xilinx_libs/simprims_ver
+eval exec vmap unifast xilinx_libs/unifast
+eval exec vmap unifast_ver xilinx_libs/unifast_ver
+eval exec vmap unimacro_ver xilinx_libs/unimacro_ver
+eval exec vmap unisim xilinx_libs/unisim
+eval exec vmap unisims_ver xilinx_libs/unisims_ver
+eval exec vmap unimacro xilinx_libs/unimacro
+
+eval exec vmap work $::env(VSIM_PATH)/modelsim_libs/tb_lib
+
+set sub_str "-L ${::env(VSIM_PATH)}/modelsim_libs/"
+set VSIM_IP_LIBS  [regsub -all -- "-L " $VSIM_IP_LIBS $sub_str]
+set VSIM_RTL_LIBS [regsub -all -- "-L " $VSIM_RTL_LIBS $sub_str]
+
+if {[info exists ::env(VSIM_PATH)]} {
+    eval exec >@stdout vopt +acc=mnpr -o vopt_tb tb_pulp -floatparameters+tb_pulp  $VSIM_FPGA_LIBS $VSIM_RTL_LIBS $VSIM_IP_LIBS -work work 
+} else {
+    eval exec >@stdout vopt +acc=mnpr -o vopt_pulp_chip pulp_chip $VSIM_FPGA_LIBS $VSIM_RTL_LIBS $VSIM_IP_LIBS -work pulpissimo_lib
+}
+
diff --git a/fpga/sim/tcl_files/run.tcl b/fpga/sim/tcl_files/run.tcl
new file mode 100755
index 00000000..f32d35de
--- /dev/null
+++ b/fpga/sim/tcl_files/run.tcl
@@ -0,0 +1,5 @@
+#!/bin/bash
+
+set TB "vopt_tb -L models_lib -L vip_lib"
+
+source ./tcl_files/config/vsim.tcl
diff --git a/fpga/sim/vcompile/.gitignore b/fpga/sim/vcompile/.gitignore
new file mode 100644
index 00000000..e6ddad4c
--- /dev/null
+++ b/fpga/sim/vcompile/.gitignore
@@ -0,0 +1,2 @@
+vcompile_ips.csh
+ips/
diff --git a/fpga/sim/vcompile/build.mk b/fpga/sim/vcompile/build.mk
new file mode 100644
index 00000000..18576dab
--- /dev/null
+++ b/fpga/sim/vcompile/build.mk
@@ -0,0 +1,63 @@
+#
+# Copyright (C) 2015 ETH Zurich, University of Bologna
+# All rights reserved.
+#
+# This software may be modified and distributed under the terms
+# of the BSD license.  See the LICENSE file for details.
+#
+
+# fix for colors on Ubuntu
+SHELL=/bin/bash
+
+# colors
+Green=\e[0;92m
+Yellow=\e[0;93m
+Red=\e[0;91m
+NC=\e[0;0m
+Blue=\e[0;94m
+
+# paths
+VSIM_PATH?=.
+PULP_PATH?=../..
+MSIM_LIBS_PATH=$(VSIM_PATH)/modelsim_libs
+IPS_PATH=../../ips
+RTL_PATH=../../rtl
+TB_PATH=../../tb
+LIB_PATH=$(MSIM_LIBS_PATH)/$(LIB_NAME)
+
+# commands
+ifndef VERBOSE
+	LIB_CREATE=@vlib
+	LIB_MAP=@vmap
+	SVLOG_CC=@vlog -quiet -sv
+	VLOG_CC=@vlog -quiet
+	VHDL_CC=@vcom -quiet
+	subip_echo=@echo -e "  $(NC)Building $(Yellow)$(IP)$(NC)/$(Yellow)$(1)$(NC)"
+	ip_echo=@echo -e "$(Green)Built$(NC) $(Yellow)$(IP)$(NC)"
+else
+	LIB_CREATE=vlib
+	LIB_MAP=vmap
+	SVLOG_CC=vlog -quiet -sv
+	VLOG_CC=vlog -quiet
+	VHDL_CC=vcom -quiet
+	subip_echo=@echo -e "\n$(NC)Building $(Yellow)$(IP)$(NC)/$(Yellow)$(1)$(NC)"
+	ip_echo=@echo -e "\n$(Green)Built$(NC) $(Yellow)$(IP)$(NC)"
+endif
+
+# rules
+.PHONY: build lib clean
+
+build: vcompile-$(IP)
+	@true
+
+lib: $(LIB_PATH)
+
+$(LIB_PATH): $(MSIM_LIBS_PATH)
+	$(LIB_CREATE) $(LIB_PATH)
+	$(LIB_MAP) $(LIB_NAME) $(LIB_PATH)
+
+$(MSIM_LIBS_PATH):
+	mkdir -p $(MSIM_LIBS_PATH)
+
+clean:
+	rm -rf $(LIB_PATH)
diff --git a/fpga/sim/vcompile/fpga.mk b/fpga/sim/vcompile/fpga.mk
new file mode 100644
index 00000000..85e0b1a8
--- /dev/null
+++ b/fpga/sim/vcompile/fpga.mk
@@ -0,0 +1,39 @@
+#
+# Copyright (C) 2016 ETH Zurich, University of Bologna
+# All rights reserved.
+#
+# This software may be modified and distributed under the terms
+# of the BSD license.  See the LICENSE file for details.
+#
+
+IP=fpga
+IP_PATH=../ips
+LIB_NAME=fpga_lib
+
+include vcompile/build.mk
+
+vcompile-$(IP): $(LIB_PATH)/_vmake
+
+$(LIB_PATH)/_vmake : | $(LIB_PATH)
+	@make --no-print-directory -f vcompile/fpga.mk vcompile-subip-fpga-mem vcompile-subip-fpga-zynq
+
+vcompile-subip-dummy:
+	@touch $(LIB_PATH)/_vmake
+
+vcompile-subip-fpga-mem: $(LIB_PATH)/fpga_mem.vmake
+
+$(LIB_PATH)/fpga_mem.vmake:
+	$(call subip_echo,fpga_mem)
+	$(SVLOG_CC) -work $(LIB_PATH) ../ips/xilinx_clk_mngr/ip/xilinx_clk_mngr_sim_netlist.v
+	$(SVLOG_CC) -work $(LIB_PATH) ../ips/xilinx_interleaved_ram/ip/xilinx_interleaved_ram_sim_netlist.v
+	$(SVLOG_CC) -work $(LIB_PATH) ../ips/xilinx_private_ram/ip/xilinx_private_ram_sim_netlist.v
+	$(SVLOG_CC) -work $(LIB_PATH) ../ips/xilinx_rom_bank_2048x32/ip/xilinx_rom_bank_2048x32_sim_netlist.v
+	$(SVLOG_CC) -work $(LIB_PATH) ../ips/xilinx_tcdm_bank_1024x32/ip/xilinx_tcdm_bank_1024x32_sim_netlist.v
+	@touch $(LIB_PATH)/fpga_mem.vmake
+
+vcompile-subip-fpga-zynq: $(LIB_PATH)/fpga_zynq.vmake
+
+$(LIB_PATH)/fpga_zynq.vmake:
+	$(call subip_echo,fpga_zynq)
+	$(SVLOG_CC) -work $(LIB_PATH) +define+PULP_FPGA_EMUL +define+PULP_FPGA_SIM -suppress 2583 -suppress 13314 +incdir+$(RTL_PATH)/includes ./misc/glbl.v
+	@touch $(LIB_PATH)/fpga_zynq.vmake
diff --git a/fpga/sim/vcompile/ips.mk b/fpga/sim/vcompile/ips.mk
new file mode 100644
index 00000000..fa81faf9
--- /dev/null
+++ b/fpga/sim/vcompile/ips.mk
@@ -0,0 +1,170 @@
+#
+# Copyright (C) 2016-2018 ETH Zurich, University of Bologna
+# All rights reserved.
+#
+# This software may be modified and distributed under the terms
+# of the BSD license.  See the LICENSE file for details.
+#
+
+mkfile_path := $(dir $(abspath $(firstword $(MAKEFILE_LIST))))
+
+.PHONY: build clean lib
+
+build:
+	@make --no-print-directory -f $(mkfile_path)/ips/L2_tcdm_hybrid_interco.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/adv_dbg_if.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/apb2per.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/apb_adv_timer.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/apb_fll_if.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/apb_gpio.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/apb_node.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/apb_interrupt_cntrl.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/axi.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/common_cells.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/axi_node.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/axi_slice.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/axi_slice_dc.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/timer_unit.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/fpu_div_sqrt_mvp.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/fpnew.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/jtag_pulp.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/riscv.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/ibex.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/scm.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/generic_FLL.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/tech_cells_generic.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_core.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_uart.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_i2c.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_i2s.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_qspi.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_sdio.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_camera.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_filter.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_external_per.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/hwpe-ctrl.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/hwpe-stream.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/hwpe-mac-engine.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/riscv-dbg.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/pulp_soc.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/axi2mem.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/axi2per.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/per2axi.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/axi_size_conv.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/cluster_interconnect.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/event_unit_flex.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/mchan.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/hier-icache.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/icache-intc.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/icache_mp_128_pf.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/icache_private.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/cluster_peripherals.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/fpu_interco.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/pulp_cluster.mk build
+	@make --no-print-directory -f $(mkfile_path)/ips/tbtools.mk build
+
+lib:
+	@make --no-print-directory -f $(mkfile_path)/ips/L2_tcdm_hybrid_interco.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/adv_dbg_if.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/apb2per.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/apb_adv_timer.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/apb_fll_if.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/apb_gpio.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/apb_node.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/apb_interrupt_cntrl.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/axi.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/common_cells.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/axi_node.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/axi_slice.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/axi_slice_dc.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/timer_unit.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/fpu_div_sqrt_mvp.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/fpnew.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/jtag_pulp.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/riscv.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/ibex.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/scm.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/generic_FLL.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/tech_cells_generic.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_core.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_uart.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_i2c.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_i2s.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_qspi.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_sdio.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_camera.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_filter.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_external_per.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/hwpe-ctrl.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/hwpe-stream.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/hwpe-mac-engine.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/riscv-dbg.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/pulp_soc.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/axi2mem.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/axi2per.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/per2axi.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/axi_size_conv.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/cluster_interconnect.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/event_unit_flex.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/mchan.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/hier-icache.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/icache-intc.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/icache_mp_128_pf.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/icache_private.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/cluster_peripherals.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/fpu_interco.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/pulp_cluster.mk lib
+	@make --no-print-directory -f $(mkfile_path)/ips/tbtools.mk lib
+
+clean:
+	@make --no-print-directory -f $(mkfile_path)/ips/L2_tcdm_hybrid_interco.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/adv_dbg_if.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/apb2per.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/apb_adv_timer.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/apb_fll_if.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/apb_gpio.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/apb_node.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/apb_interrupt_cntrl.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/axi.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/common_cells.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/axi_node.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/axi_slice.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/axi_slice_dc.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/timer_unit.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/fpu_div_sqrt_mvp.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/fpnew.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/jtag_pulp.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/riscv.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/ibex.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/scm.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/generic_FLL.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/tech_cells_generic.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_core.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_uart.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_i2c.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_i2s.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_qspi.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_sdio.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_camera.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_filter.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/udma_external_per.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/hwpe-ctrl.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/hwpe-stream.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/hwpe-mac-engine.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/riscv-dbg.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/pulp_soc.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/axi2mem.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/axi2per.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/per2axi.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/axi_size_conv.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/cluster_interconnect.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/event_unit_flex.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/mchan.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/hier-icache.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/icache-intc.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/icache_mp_128_pf.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/icache_private.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/cluster_peripherals.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/fpu_interco.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/pulp_cluster.mk clean
+	@make --no-print-directory -f $(mkfile_path)/ips/tbtools.mk clean
diff --git a/fpga/sim/vcompile/rtl.mk b/fpga/sim/vcompile/rtl.mk
new file mode 100644
index 00000000..61417693
--- /dev/null
+++ b/fpga/sim/vcompile/rtl.mk
@@ -0,0 +1,29 @@
+#
+# Copyright (C) 2016-2018 ETH Zurich, University of Bologna
+# All rights reserved.
+#
+# This software may be modified and distributed under the terms
+# of the BSD license.  See the LICENSE file for details.
+#
+
+mkfile_path := $(dir $(abspath $(firstword $(MAKEFILE_LIST))))
+
+.PHONY: build clean lib
+
+build:
+	@make --no-print-directory -f $(mkfile_path)/rtl/tb.mk build
+	@make --no-print-directory -f $(mkfile_path)/rtl/vip.mk build
+	@make --no-print-directory -f $(mkfile_path)/rtl/pulpemu.mk build
+	@make --no-print-directory -f $(mkfile_path)/rtl/pulp.mk build
+
+lib:
+	@make --no-print-directory -f $(mkfile_path)/rtl/tb.mk lib
+	@make --no-print-directory -f $(mkfile_path)/rtl/vip.mk lib
+	@make --no-print-directory -f $(mkfile_path)/rtl/pulpemu.mk lib
+	@make --no-print-directory -f $(mkfile_path)/rtl/pulp.mk lib
+
+clean:
+	@make --no-print-directory -f $(mkfile_path)/rtl/tb.mk clean
+	@make --no-print-directory -f $(mkfile_path)/rtl/vip.mk clean
+	@make --no-print-directory -f $(mkfile_path)/rtl/pulpemu.mk clean
+	@make --no-print-directory -f $(mkfile_path)/rtl/pulp.mk clean
diff --git a/fpga/sim/vcompile/tb.mk b/fpga/sim/vcompile/tb.mk
new file mode 100644
index 00000000..b4adab0d
--- /dev/null
+++ b/fpga/sim/vcompile/tb.mk
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2016 ETH Zurich, University of Bologna
+# All rights reserved.
+#
+# This software may be modified and distributed under the terms
+# of the BSD license.  See the LICENSE file for details.
+#
+
+IP=tb
+IP_PATH=$(RTL_PATH)/tb
+LIB_NAME=$(IP)_lib
+
+include vcompile/build.mk
+
+.PHONY: vcompile-$(IP) vcompile-subip-tb 
+
+vcompile-$(IP): $(LIB_PATH)/_vmake
+
+$(LIB_PATH)/_vmake : $(LIB_PATH)/tb.vmake 
+	@touch $(LIB_PATH)/_vmake
+
+ifdef USE_NETLIST
+$(info USE_NETLIST defined in tb)
+DEF_MODEL_LEVEL=+define+USE_NETLIST
+else
+DEF_MODEL_LEVEL=
+endif
+
+SRC_SVLOG_TB=\
+	$(IP_PATH)/../../ips/riscv-dbg/src/dm_pkg.sv\
+	$(IP_PATH)/riscv_pkg.sv\
+	$(IP_PATH)/jtag_pkg.sv\
+	$(IP_PATH)/pulp_tap_pkg.sv\
+	$(IP_PATH)/tb_clk_gen.sv\
+	$(IP_PATH)/tb_fs_handler.sv\
+	$(IP_PATH)/dpi_models/dpi_models.sv\
+	$(IP_PATH)/tb_driver/tb_driver.sv\
+	$(IP_PATH)/tb_pulp.sv\
+	$(IP_PATH)/SimJTAG.sv\
+	$(IP_PATH)/SimDTM.sv
+SRC_VHDL_TB=
+
+vcompile-subip-tb: $(LIB_PATH)/tb.vmake
+
+$(LIB_PATH)/tb.vmake: $(SRC_SVLOG_TB) $(SRC_VHDL_TB)
+	$(call subip_echo,tb)
+	$(SVLOG_CC) -work $(LIB_PATH)  -L riscv_dbg_lib +define+PULP_FPGA_EMUL +define+PULP_FPGA_SIM -suppress 2583 $(INCDIR_TB) $(SRC_SVLOG_TB) ${DEF_MODEL_LEVEL}
+	@touch $(LIB_PATH)/tb.vmake
+
diff --git a/fpga/sourceme.sh b/fpga/sourceme.sh
new file mode 100644
index 00000000..1f7fd130
--- /dev/null
+++ b/fpga/sourceme.sh
@@ -0,0 +1,28 @@
+#!/bin/bash
+
+export VIVADO_HOME=/opt/xilinx/Vivado/2018.2
+source $VIVADO_HOME/settings64.sh
+
+#VIVADO SETTINGS
+#Settings are board specific. Check FPGA board datasheet to add new target
+# either "vcu118" or "zcu102"
+
+if [ -z "$BOARD"  ]; then
+    read -p "Which board you want to use:  1-zcu102 2-vcu118: " BOARD
+
+    if [ "$BOARD" = "1" ]; then
+        export BOARD="zcu102"
+        export XILINX_PART="xczu9eg-ffvb1156-2-e"
+        export XILINX_BOARD="xilinx.com:zcu102:part0:3.2"
+    elif [ "$BOARD" = "2" ]; then
+        export BOARD="vcu118"
+        export XILINX_PART="xcvu9p-flga2104-2L-e"
+        export XILINX_BOARD="xilinx.com:vcu118:part0:2.0"
+    fi
+fi
+
+echo "$BOARD"
+echo "XILINX_PART=$XILINX_PART"
+echo "XILINX_BOARD=$XILINX_BOARD"
+
+export VSIM_PATH=$PWD/sim
diff --git a/fpga/tb b/fpga/tb
new file mode 120000
index 00000000..4145557e
--- /dev/null
+++ b/fpga/tb
@@ -0,0 +1 @@
+../rtl/tb
\ No newline at end of file
diff --git a/generate-scripts b/generate-scripts
index afb87880..79077f8c 100755
--- a/generate-scripts
+++ b/generate-scripts
@@ -35,8 +35,6 @@ execute("mkdir -p sim/vcompile/rtl")
 execute("rm -rf sim/vcompile/rtl/*")
 execute("mkdir -p sim/vcompile/tb")
 execute("rm -rf sim/vcompile/tb/*")
-execute("mkdir -p fpga/pulpissimo/tcl")
-execute("rm -rf fpga/pulpissimo/tcl/*")
 
 execute("mkdir -p sim/ncompile/ips")
 execute("rm -rf sim/ncompile/ips/*")
@@ -94,16 +92,16 @@ for line in fileinput.input("sim/ncompile/src_ips_files.f", inplace=True):
         print(line)
 
 
-# Generate FPGA scripts
-# generate Vivado src_files.tcl
-ipdb.export_vivado(script_path="fpga/pulpissimo/tcl/ips_src_files.tcl", domain='soc')
-ipdb.export_vivado(script_path="fpga/pulpissimo/tcl/rtl_src_files.tcl", domain='soc', source='rtl')
+# # Generate FPGA scripts
+# # generate Vivado src_files.tcl
+# ipdb.export_vivado(script_path="fpga/pulpissimo/tcl/ips_src_files.tcl", domain='soc')
+# ipdb.export_vivado(script_path="fpga/pulpissimo/tcl/rtl_src_files.tcl", domain='soc', source='rtl')
 
-# generate Vivado add_files.tcl
-ipdb.generate_vivado_add_files("fpga/pulpissimo/tcl/ips_add_files.tcl", domain='soc')
-ipdb.generate_vivado_add_files("fpga/pulpissimo/tcl/rtl_add_files.tcl", domain='soc', source='rtl')
+# # generate Vivado add_files.tcl
+# ipdb.generate_vivado_add_files("fpga/pulpissimo/tcl/ips_add_files.tcl", domain='soc')
+# ipdb.generate_vivado_add_files("fpga/pulpissimo/tcl/rtl_add_files.tcl", domain='soc', source='rtl')
 
-# generate Vivado inc_dirs.tcl
-ipdb.generate_vivado_inc_dirs("fpga/pulpissimo/tcl/ips_inc_dirs.tcl", domain='soc')
+# # generate Vivado inc_dirs.tcl
+# ipdb.generate_vivado_inc_dirs("fpga/pulpissimo/tcl/ips_inc_dirs.tcl", domain='soc')
 
 print(tcolors.OK + "Generated new scripts for IPs!" + tcolors.ENDC)
diff --git a/generate-scripts-fpga b/generate-scripts-fpga
new file mode 100755
index 00000000..67792c4f
--- /dev/null
+++ b/generate-scripts-fpga
@@ -0,0 +1,43 @@
+#!/usr/bin/env python
+# Francesco Conti <f.conti@unibo.it>
+#
+# Copyright (C) 2016 ETH Zurich, University of Bologna.
+# All rights reserved.
+
+from ipstools_cfg import *
+
+execute("mkdir -p fpga/sim/vcompile/ips")
+execute("rm -rf fpga/sim/vcompile/ips/*")
+execute("mkdir -p fpga/sim/vcompile/rtl")
+execute("rm -rf fpga/sim/vcompile/rtl/*")
+
+# creates an IPApproX database
+ipdb = ipstools.IPDatabase(rtl_dir='rtl', ips_dir='ips', vsim_dir='sim', load_cache=True)
+
+
+# do the same for FPGA platform simulation
+ipdb.export_make(script_path="fpga/sim/vcompile/ips", target_tech='xilinx')
+ipdb.export_make(script_path="fpga/sim/vcompile/rtl", target_tech='xilinx', source='rtl')
+ipdb.generate_vsim_tcl("fpga/sim/tcl_files/config/vsim_ips.tcl")
+ipdb.generate_vsim_tcl("fpga/sim/tcl_files/config/vsim_rtl.tcl", source='rtl')
+ipdb.generate_makefile("fpga/sim/vcompile/ips.mk", target_tech='xilinx')
+ipdb.generate_makefile("fpga/sim/vcompile/rtl.mk", target_tech='xilinx', source='rtl')
+
+# generate Vivado compilation scripts
+ipdb.export_vivado(script_path="fpga/pulp_cluster/tcl/ips_src_files.tcl", domain='cluster')
+ipdb.export_vivado(script_path="fpga/pulp_cluster/tcl/rtl_src_files.tcl", domain='cluster', source='rtl')
+ipdb.export_vivado(script_path="fpga/pulpemu/tcl/ips_src_files.tcl", domain='soc')
+ipdb.export_vivado(script_path="fpga/pulpemu/tcl/rtl_src_files.tcl", domain='soc', source='rtl')
+# generate Vivado add_files.tcl
+ipdb.generate_vivado_add_files("fpga/pulp_cluster/tcl/ips_add_files.tcl", domain='cluster')
+ipdb.generate_vivado_add_files("fpga/pulp_cluster/tcl/rtl_add_files.tcl", domain='cluster', source='rtl')
+ipdb.generate_vivado_add_files("fpga/pulpemu/tcl/ips_add_files.tcl", domain='soc')
+ipdb.generate_vivado_add_files("fpga/pulpemu/tcl/rtl_add_files.tcl", domain='soc', source='rtl')
+# generate Vivado inc_dirs.tcl
+ipdb.generate_vivado_inc_dirs("fpga/pulp_cluster/tcl/ips_inc_dirs.tcl", domain='cluster')
+ipdb.generate_vivado_inc_dirs("fpga/pulp_cluster/tcl/rtl_inc_dirs.tcl", domain='cluster', source='rtl')
+ipdb.generate_vivado_inc_dirs("fpga/pulpemu/tcl/ips_inc_dirs.tcl", domain='soc')
+ipdb.generate_vivado_inc_dirs("fpga/pulpemu/tcl/rtl_inc_dirs.tcl", domain='soc', source='rtl')
+
+print tcolors.OK + "Generated sim scripts for IPs!" + tcolors.ENDC
+
diff --git a/ips_list.yml b/ips_list.yml
index 0ebd3d14..fd7cf805 100644
--- a/ips_list.yml
+++ b/ips_list.yml
@@ -20,15 +20,18 @@
 
 pulp_soc:
   commit: v1.1.0
+  domain: [soc]
   server: https://github.com
   group:  pulp-platform
 
 pulp_cluster:
-  commit: pulp_cluster_v1.2
+  commit: pulp_cluster_v1.3
   server: https://github.com
   group:  pulp-platform
 
 tbtools:
   commit: v0.1
+  commit: master
+  domain: [soc]
   server: https://github.com
   group:  pulp-platform
diff --git a/rtl/pulp/cluster_domain.sv b/rtl/pulp/cluster_domain.sv
index 587152b4..e80dfca7 100644
--- a/rtl/pulp/cluster_domain.sv
+++ b/rtl/pulp/cluster_domain.sv
@@ -26,10 +26,11 @@ module cluster_domain
 #(
     //CLUSTER PARAMETERS
     parameter NB_CORES              = `NB_CORES,
+    parameter HWPE_PRESENT          = 0,
     parameter NB_HWPE_PORTS         = 4,
     parameter NB_DMAS               = 4,
 
-    parameter TCDM_SIZE             = 64*1024,                 // in Byte, POWER of 2
+    parameter TCDM_SIZE             = 128*1024,                 // in Byte, POWER of 2
     parameter NB_TCDM_BANKS         = 16,                      // POWER of 2
     parameter TCDM_BANK_SIZE        = TCDM_SIZE/NB_TCDM_BANKS, // eg 4096
     parameter TCDM_NUM_ROWS         = TCDM_BANK_SIZE/4,        // --> 4 byte, mem are 32 bit wide
@@ -253,6 +254,7 @@ module cluster_domain
 `ifndef USE_CLUSTER_NETLIST
     #(
         .NB_CORES                     ( NB_CORES                     ),
+        .HWPE_PRESENT                 ( HWPE_PRESENT                 ),
         .NB_HWPE_PORTS                ( NB_HWPE_PORTS                ),
         .NB_DMAS                      ( NB_DMAS                      ),
         .TCDM_SIZE                    ( TCDM_SIZE                    ),
diff --git a/rtl/pulp/pad_frame.sv b/rtl/pulp/pad_frame.sv
index c606ca89..9b677336 100644
--- a/rtl/pulp/pad_frame.sv
+++ b/rtl/pulp/pad_frame.sv
@@ -217,19 +217,19 @@ module pad_frame
     pad_functional_pu padinst_bootsel    (.OEN(1'b1            ), .I(                ), .O(bootsel_o      ), .PAD(pad_bootsel   ), .PEN(1'b1             ) );
 
 
-`ifndef PULP_FPGA_EMUL
-  pad_functional_pu padinst_ref_clk    (.OEN(1'b1            ), .I(                ), .O(ref_clk_o      ), .PAD(pad_xtal_in   ), .PEN(1'b1             ) );
-  pad_functional_pu padinst_reset_n    (.OEN(1'b1            ), .I(                ), .O(rstn_o         ), .PAD(pad_reset_n   ), .PEN(1'b1             ) );
-  pad_functional_pu padinst_jtag_tck   (.OEN(1'b1            ), .I(                ), .O(jtag_tck_o     ), .PAD(pad_jtag_tck  ), .PEN(1'b1             ) );
-  pad_functional_pu padinst_jtag_tms   (.OEN(1'b1            ), .I(                ), .O(jtag_tms_o     ), .PAD(pad_jtag_tms  ), .PEN(1'b1             ) );
-  pad_functional_pu padinst_jtag_tdi   (.OEN(1'b1            ), .I(                ), .O(jtag_tdi_o     ), .PAD(pad_jtag_tdi  ), .PEN(1'b1             ) );
-  pad_functional_pu padinst_jtag_trstn (.OEN(1'b1            ), .I(                ), .O(jtag_trst_o    ), .PAD(pad_jtag_trst ), .PEN(1'b1             ) );
-  pad_functional_pd padinst_jtag_tdo   (.OEN(1'b0            ), .I(jtag_tdo_i      ), .O(               ), .PAD(pad_jtag_tdo  ), .PEN(1'b1             ) );
-
+`ifndef PULP_FPGA_EMUL   
+    pad_functional_pu padinst_reset_n    (.OEN(1'b1            ), .I(                ), .O(rstn_o         ), .PAD(pad_reset_n   ), .PEN(1'b1             ) );
+    pad_functional_pu padinst_jtag_tck   (.OEN(1'b1            ), .I(                ), .O(jtag_tck_o     ), .PAD(pad_jtag_tck  ), .PEN(1'b1             ) );
+    pad_functional_pu padinst_jtag_tms   (.OEN(1'b1            ), .I(                ), .O(jtag_tms_o     ), .PAD(pad_jtag_tms  ), .PEN(1'b1             ) );
+    pad_functional_pu padinst_jtag_tdi   (.OEN(1'b1            ), .I(                ), .O(jtag_tdi_o     ), .PAD(pad_jtag_tdi  ), .PEN(1'b1             ) );
+    pad_functional_pu padinst_jtag_trstn (.OEN(1'b1            ), .I(                ), .O(jtag_trst_o    ), .PAD(pad_jtag_trst ), .PEN(1'b1             ) );
+    pad_functional_pd padinst_jtag_tdo   (.OEN(1'b0            ), .I(jtag_tdo_i      ), .O(               ), .PAD(pad_jtag_tdo  ), .PEN(1'b1             ) );
+    pad_functional_pu padinst_ref_clk    (.OEN(1'b1            ), .I(                ), .O(ref_clk_o      ), .PAD(pad_xtal_in   ), .PEN(1'b1             ) );
+  
 `else
   assign ref_clk_o = pad_xtal_in;
   assign rstn_o = pad_reset_n;
-
+  
   //JTAG signals
   assign pad_jtag_tdo = jtag_tdo_i;
   assign jtag_trst_o = pad_jtag_trst;
diff --git a/rtl/pulp/pulp.sv b/rtl/pulp/pulp.sv
index 92a9f92c..6ecb9874 100644
--- a/rtl/pulp/pulp.sv
+++ b/rtl/pulp/pulp.sv
@@ -13,10 +13,16 @@
 module pulp
 #(
   parameter CORE_TYPE   = 0, // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY)
-  parameter USE_FPU     = 1,
-  parameter USE_HWPE    = 1
+  parameter USE_FPU     = 0,
+  parameter USE_HWPE    = 0
 )
 (
+`ifdef PULP_FPGA_EMUL
+  // input  logic       zynq_clk_i,
+  // input  logic       zynq_soc_clk_i,
+  // input  logic       zynq_cluster_clk_i,
+  // input  logic       zynq_per_clk_i,
+`endif
 
    inout  wire        pad_spim_sdio0,
    inout  wire        pad_spim_sdio1,
@@ -465,11 +471,16 @@ module pulp
   //***********************************************************
   //********** PAD FRAME **************************************
   //***********************************************************
+`ifdef PULP_FPGA_EMUL
+   //assign s_ref_clk = zynq_clk_i;
+`endif
 
   pad_frame pad_frame_i
   (
         .pad_cfg_i             ( s_pad_cfg              ),
+//`ifndef PULP_FPGA_EMUL
         .ref_clk_o             ( s_ref_clk              ),
+//`endif
         .rstn_o                ( s_rstn                 ),
         .jtag_tdo_i            ( s_jtag_tdo             ),
         .jtag_tck_o            ( s_jtag_tck             ),
@@ -628,7 +639,7 @@ module pulp
    safe_domain safe_domain_i (
 
         .ref_clk_i                  ( s_ref_clk                   ),
-        .slow_clk_o                 ( s_slow_clk                  ),
+        .slow_clk_o                 ( s_slow_clk                 ),
         .rst_ni                     ( s_rstn                     ),
 
         .rst_no                     ( s_rstn_por                  ),
@@ -849,6 +860,11 @@ module pulp
         .test_clk_i                   ( s_test_clk                       ),
 
         .rstn_glob_i                  ( s_rstn_por                       ),
+    `ifdef PULP_FPGA_EMUL
+        //.zynq_soc_clk_i               ( zynq_soc_clk_i      ),
+        //.zynq_cluster_clk_i           ( zynq_cluster_clk_i  ),
+        //.zynq_per_clk_i               ( zynq_per_clk_i      ),
+    `endif
 
         .mode_select_i                ( s_mode_select                    ),
         .dft_cg_enable_i              ( s_dft_cg_enable                  ),
diff --git a/rtl/pulp/safe_domain.sv b/rtl/pulp/safe_domain.sv
index 8ed6537c..bb9ceb6e 100644
--- a/rtl/pulp/safe_domain.sv
+++ b/rtl/pulp/safe_domain.sv
@@ -15,212 +15,212 @@ module safe_domain
         parameter FLL_ADDR_WIDTH = 32
     )
     (
-        input  logic             ref_clk_i            ,
-        output logic             slow_clk_o           ,
-        input  logic             rst_ni               ,
-        output logic             rst_no               ,
+        input logic              ref_clk_i ,
+        output logic             slow_clk_o,
+        input logic              rst_ni ,
+        output logic             rst_no ,
 
-        output logic             test_clk_o           ,
-        output logic             test_mode_o          ,
-        output logic             mode_select_o        ,
-        output logic             dft_cg_enable_o      ,
+        output logic             test_clk_o ,
+        output logic             test_mode_o ,
+        output logic             mode_select_o ,
+        output logic             dft_cg_enable_o ,
 
         //**********************************************************
         //*** PERIPHERALS SIGNALS **********************************
         //**********************************************************
 
         // PAD CONTROL REGISTER
-        input  logic [127:0]     pad_mux_i            ,
-        input  logic [383:0]     pad_cfg_i            ,
+        input logic [127:0]      pad_mux_i ,
+        input logic [383:0]      pad_cfg_i ,
 
-        output logic [47:0][5:0] pad_cfg_o            ,
+        output logic [47:0][5:0] pad_cfg_o ,
 
         // GPIOS
-        input  logic [31:0]      gpio_out_i           ,
-        output logic [31:0]      gpio_in_o            ,
-        input  logic [31:0]      gpio_dir_i           ,
-        input  logic [191:0]     gpio_cfg_i           ,
+        input logic [31:0]       gpio_out_i ,
+        output logic [31:0]      gpio_in_o ,
+        input logic [31:0]       gpio_dir_i ,
+        input logic [191:0]      gpio_cfg_i ,
 
         // UART
-        input  logic             uart_tx_i            ,
-        output logic             uart_rx_o            ,
+        input logic              uart_tx_i ,
+        output logic             uart_rx_o ,
 
         // I2C0
-        input  logic             i2c0_scl_out_i       ,
-        output logic             i2c0_scl_in_o        ,
-        input  logic             i2c0_scl_oe_i        ,
-        input  logic             i2c0_sda_out_i       ,
-        output logic             i2c0_sda_in_o        ,
-        input  logic             i2c0_sda_oe_i        ,
+        input logic              i2c0_scl_out_i ,
+        output logic             i2c0_scl_in_o ,
+        input logic              i2c0_scl_oe_i ,
+        input logic              i2c0_sda_out_i ,
+        output logic             i2c0_sda_in_o ,
+        input logic              i2c0_sda_oe_i ,
 
         // I2C1
-        input  logic             i2c1_scl_out_i       ,
-        output logic             i2c1_scl_in_o        ,
-        input  logic             i2c1_scl_oe_i        ,
-        input  logic             i2c1_sda_out_i       ,
-        output logic             i2c1_sda_in_o        ,
-        input  logic             i2c1_sda_oe_i        ,
+        input logic              i2c1_scl_out_i ,
+        output logic             i2c1_scl_in_o ,
+        input logic              i2c1_scl_oe_i ,
+        input logic              i2c1_sda_out_i ,
+        output logic             i2c1_sda_in_o ,
+        input logic              i2c1_sda_oe_i ,
 
         // I2S
-        output logic             i2s_slave_sd0_o      ,
-        output logic             i2s_slave_sd1_o      ,
-        output logic             i2s_slave_ws_o       ,
-        input  logic             i2s_slave_ws_i       ,
-        input  logic             i2s_slave_ws_oe      ,
-        output logic             i2s_slave_sck_o      ,
-        input  logic             i2s_slave_sck_i      ,
-        input  logic             i2s_slave_sck_oe     ,
+        output logic             i2s_slave_sd0_o ,
+        output logic             i2s_slave_sd1_o ,
+        output logic             i2s_slave_ws_o ,
+        input logic              i2s_slave_ws_i ,
+        input logic              i2s_slave_ws_oe ,
+        output logic             i2s_slave_sck_o ,
+        input logic              i2s_slave_sck_i ,
+        input logic              i2s_slave_sck_oe ,
 
         // SPI MASTER
-        input  logic             spi_master0_csn0_i   ,
-        input  logic             spi_master0_csn1_i   ,
-        input  logic             spi_master0_sck_i    ,
-        output logic             spi_master0_sdi0_o   ,
-        output logic             spi_master0_sdi1_o   ,
-        output logic             spi_master0_sdi2_o   ,
-        output logic             spi_master0_sdi3_o   ,
-        input  logic             spi_master0_sdo0_i   ,
-        input  logic             spi_master0_sdo1_i   ,
-        input  logic             spi_master0_sdo2_i   ,
-        input  logic             spi_master0_sdo3_i   ,
-        input  logic             spi_master0_oen0_i   ,
-        input  logic             spi_master0_oen1_i   ,
-        input  logic             spi_master0_oen2_i   ,
-        input  logic             spi_master0_oen3_i   ,
-
-        input  logic             spi_master1_csn0_i   ,
-        input  logic             spi_master1_csn1_i   ,
-        input  logic             spi_master1_sck_i    ,
-        output logic             spi_master1_sdi_o    ,
-        input  logic             spi_master1_sdo_i    ,
-        input  logic [1:0]       spi_master1_mode_i,
-
-
-        input  logic             sdio_clk_i,
-        input  logic             sdio_cmd_i,
+        input logic              spi_master0_csn0_i ,
+        input logic              spi_master0_csn1_i ,
+        input logic              spi_master0_sck_i ,
+        output logic             spi_master0_sdi0_o ,
+        output logic             spi_master0_sdi1_o ,
+        output logic             spi_master0_sdi2_o ,
+        output logic             spi_master0_sdi3_o ,
+        input logic              spi_master0_sdo0_i ,
+        input logic              spi_master0_sdo1_i ,
+        input logic              spi_master0_sdo2_i ,
+        input logic              spi_master0_sdo3_i ,
+        input logic              spi_master0_oen0_i ,
+        input logic              spi_master0_oen1_i ,
+        input logic              spi_master0_oen2_i ,
+        input logic              spi_master0_oen3_i ,
+
+        input logic              spi_master1_csn0_i ,
+        input logic              spi_master1_csn1_i ,
+        input logic              spi_master1_sck_i ,
+        output logic             spi_master1_sdi_o ,
+        input logic              spi_master1_sdo_i ,
+        input logic [1:0]        spi_master1_mode_i,
+
+
+        input logic              sdio_clk_i,
+        input logic              sdio_cmd_i,
         output logic             sdio_cmd_o,
-        input  logic             sdio_cmd_oen_i,
-        input  logic [3:0]       sdio_data_i,
+        input logic              sdio_cmd_oen_i,
+        input logic [3:0]        sdio_data_i,
         output logic [3:0]       sdio_data_o,
-        input  logic [3:0]       sdio_data_oen_i,
+        input logic [3:0]        sdio_data_oen_i,
 
         // CAMERA INTERFACE
-        output logic             cam_pclk_o           ,
-        output logic [7:0]       cam_data_o           ,
-        output logic             cam_hsync_o          ,
-        output logic             cam_vsync_o          ,
+        output logic             cam_pclk_o ,
+        output logic [7:0]       cam_data_o ,
+        output logic             cam_hsync_o ,
+        output logic             cam_vsync_o ,
 
         // TIMER
-        input  logic [3:0]       timer0_i             ,
-        input  logic [3:0]       timer1_i             ,
-        input  logic [3:0]       timer2_i             ,
-        input  logic [3:0]       timer3_i             ,
+        input logic [3:0]        timer0_i ,
+        input logic [3:0]        timer1_i ,
+        input logic [3:0]        timer2_i ,
+        input logic [3:0]        timer3_i ,
 
         //**********************************************************
         //*** PAD FRAME SIGNALS ************************************
         //**********************************************************
 
         // PADS OUTPUTS
-        output logic             out_spim_sdio0_o     ,
-        output logic             out_spim_sdio1_o     ,
-        output logic             out_spim_sdio2_o     ,
-        output logic             out_spim_sdio3_o     ,
-        output logic             out_spim_csn0_o      ,
-        output logic             out_spim_csn1_o      ,
-        output logic             out_spim_sck_o       ,
-        output logic             out_sdio_clk_o       ,
-        output logic             out_sdio_cmd_o       ,
-        output logic             out_sdio_data0_o     ,
-        output logic             out_sdio_data1_o     ,
-        output logic             out_sdio_data2_o     ,
-        output logic             out_sdio_data3_o     ,
-        output logic             out_uart_rx_o        ,
-        output logic             out_uart_tx_o        ,
-        output logic             out_cam_pclk_o       ,
-        output logic             out_cam_hsync_o      ,
-        output logic             out_cam_data0_o      ,
-        output logic             out_cam_data1_o      ,
-        output logic             out_cam_data2_o      ,
-        output logic             out_cam_data3_o      ,
-        output logic             out_cam_data4_o      ,
-        output logic             out_cam_data5_o      ,
-        output logic             out_cam_data6_o      ,
-        output logic             out_cam_data7_o      ,
-        output logic             out_cam_vsync_o      ,
-        output logic             out_i2c0_sda_o       ,
-        output logic             out_i2c0_scl_o       ,
-        output logic             out_i2s0_sck_o       ,
-        output logic             out_i2s0_ws_o        ,
-        output logic             out_i2s0_sdi_o       ,
-        output logic             out_i2s1_sdi_o       ,
+        output logic             out_spim_sdio0_o ,
+        output logic             out_spim_sdio1_o ,
+        output logic             out_spim_sdio2_o ,
+        output logic             out_spim_sdio3_o ,
+        output logic             out_spim_csn0_o ,
+        output logic             out_spim_csn1_o ,
+        output logic             out_spim_sck_o ,
+        output logic             out_sdio_clk_o ,
+        output logic             out_sdio_cmd_o ,
+        output logic             out_sdio_data0_o ,
+        output logic             out_sdio_data1_o ,
+        output logic             out_sdio_data2_o ,
+        output logic             out_sdio_data3_o ,
+        output logic             out_uart_rx_o ,
+        output logic             out_uart_tx_o ,
+        output logic             out_cam_pclk_o ,
+        output logic             out_cam_hsync_o ,
+        output logic             out_cam_data0_o ,
+        output logic             out_cam_data1_o ,
+        output logic             out_cam_data2_o ,
+        output logic             out_cam_data3_o ,
+        output logic             out_cam_data4_o ,
+        output logic             out_cam_data5_o ,
+        output logic             out_cam_data6_o ,
+        output logic             out_cam_data7_o ,
+        output logic             out_cam_vsync_o ,
+        output logic             out_i2c0_sda_o ,
+        output logic             out_i2c0_scl_o ,
+        output logic             out_i2s0_sck_o ,
+        output logic             out_i2s0_ws_o ,
+        output logic             out_i2s0_sdi_o ,
+        output logic             out_i2s1_sdi_o ,
 
 
         // PAD INPUTS
-        input logic              in_spim_sdio0_i      ,
-        input logic              in_spim_sdio1_i      ,
-        input logic              in_spim_sdio2_i      ,
-        input logic              in_spim_sdio3_i      ,
-        input logic              in_spim_csn0_i       ,
-        input logic              in_spim_csn1_i       ,
-        input logic              in_spim_sck_i        ,
-        input logic              in_sdio_clk_i        ,
-        input logic              in_sdio_cmd_i        ,
-        input logic              in_sdio_data0_i      ,
-        input logic              in_sdio_data1_i      ,
-        input logic              in_sdio_data2_i      ,
-        input logic              in_sdio_data3_i      ,
-        input logic              in_uart_rx_i         ,
-        input logic              in_uart_tx_i         ,
-        input logic              in_cam_pclk_i        ,
-        input logic              in_cam_hsync_i       ,
-        input logic              in_cam_data0_i       ,
-        input logic              in_cam_data1_i       ,
-        input logic              in_cam_data2_i       ,
-        input logic              in_cam_data3_i       ,
-        input logic              in_cam_data4_i       ,
-        input logic              in_cam_data5_i       ,
-        input logic              in_cam_data6_i       ,
-        input logic              in_cam_data7_i       ,
-        input logic              in_cam_vsync_i       ,
-        input logic              in_i2c0_sda_i        ,
-        input logic              in_i2c0_scl_i        ,
-        input logic              in_i2s0_sck_i        ,
-        input logic              in_i2s0_ws_i         ,
-        input logic              in_i2s0_sdi_i        ,
-        input logic              in_i2s1_sdi_i        ,
+        input logic              in_spim_sdio0_i ,
+        input logic              in_spim_sdio1_i ,
+        input logic              in_spim_sdio2_i ,
+        input logic              in_spim_sdio3_i ,
+        input logic              in_spim_csn0_i ,
+        input logic              in_spim_csn1_i ,
+        input logic              in_spim_sck_i ,
+        input logic              in_sdio_clk_i ,
+        input logic              in_sdio_cmd_i ,
+        input logic              in_sdio_data0_i ,
+        input logic              in_sdio_data1_i ,
+        input logic              in_sdio_data2_i ,
+        input logic              in_sdio_data3_i ,
+        input logic              in_uart_rx_i ,
+        input logic              in_uart_tx_i ,
+        input logic              in_cam_pclk_i ,
+        input logic              in_cam_hsync_i ,
+        input logic              in_cam_data0_i ,
+        input logic              in_cam_data1_i ,
+        input logic              in_cam_data2_i ,
+        input logic              in_cam_data3_i ,
+        input logic              in_cam_data4_i ,
+        input logic              in_cam_data5_i ,
+        input logic              in_cam_data6_i ,
+        input logic              in_cam_data7_i ,
+        input logic              in_cam_vsync_i ,
+        input logic              in_i2c0_sda_i ,
+        input logic              in_i2c0_scl_i ,
+        input logic              in_i2s0_sck_i ,
+        input logic              in_i2s0_ws_i ,
+        input logic              in_i2s0_sdi_i ,
+        input logic              in_i2s1_sdi_i ,
 
         // OUTPUT ENABLE
-        output logic             oe_spim_sdio0_o      ,
-        output logic             oe_spim_sdio1_o      ,
-        output logic             oe_spim_sdio2_o      ,
-        output logic             oe_spim_sdio3_o      ,
-        output logic             oe_spim_csn0_o       ,
-        output logic             oe_spim_csn1_o       ,
-        output logic             oe_spim_sck_o        ,
-        output logic             oe_sdio_clk_o        ,
-        output logic             oe_sdio_cmd_o        ,
-        output logic             oe_sdio_data0_o      ,
-        output logic             oe_sdio_data1_o      ,
-        output logic             oe_sdio_data2_o      ,
-        output logic             oe_sdio_data3_o      ,
-        output logic             oe_uart_rx_o         ,
-        output logic             oe_uart_tx_o         ,
-        output logic             oe_cam_pclk_o        ,
-        output logic             oe_cam_hsync_o       ,
-        output logic             oe_cam_data0_o       ,
-        output logic             oe_cam_data1_o       ,
-        output logic             oe_cam_data2_o       ,
-        output logic             oe_cam_data3_o       ,
-        output logic             oe_cam_data4_o       ,
-        output logic             oe_cam_data5_o       ,
-        output logic             oe_cam_data6_o       ,
-        output logic             oe_cam_data7_o       ,
-        output logic             oe_cam_vsync_o       ,
-        output logic             oe_i2c0_sda_o        ,
-        output logic             oe_i2c0_scl_o        ,
-        output logic             oe_i2s0_sck_o        ,
-        output logic             oe_i2s0_ws_o         ,
-        output logic             oe_i2s0_sdi_o        ,
+        output logic             oe_spim_sdio0_o ,
+        output logic             oe_spim_sdio1_o ,
+        output logic             oe_spim_sdio2_o ,
+        output logic             oe_spim_sdio3_o ,
+        output logic             oe_spim_csn0_o ,
+        output logic             oe_spim_csn1_o ,
+        output logic             oe_spim_sck_o ,
+        output logic             oe_sdio_clk_o ,
+        output logic             oe_sdio_cmd_o ,
+        output logic             oe_sdio_data0_o ,
+        output logic             oe_sdio_data1_o ,
+        output logic             oe_sdio_data2_o ,
+        output logic             oe_sdio_data3_o ,
+        output logic             oe_uart_rx_o ,
+        output logic             oe_uart_tx_o ,
+        output logic             oe_cam_pclk_o ,
+        output logic             oe_cam_hsync_o ,
+        output logic             oe_cam_data0_o ,
+        output logic             oe_cam_data1_o ,
+        output logic             oe_cam_data2_o ,
+        output logic             oe_cam_data3_o ,
+        output logic             oe_cam_data4_o ,
+        output logic             oe_cam_data5_o ,
+        output logic             oe_cam_data6_o ,
+        output logic             oe_cam_data7_o ,
+        output logic             oe_cam_vsync_o ,
+        output logic             oe_i2c0_sda_o ,
+        output logic             oe_i2c0_scl_o ,
+        output logic             oe_i2s0_sck_o ,
+        output logic             oe_i2s0_ws_o ,
+        output logic             oe_i2s0_sdi_o ,
         output logic             oe_i2s1_sdi_o
     );
 
@@ -417,7 +417,6 @@ module safe_domain
         .*
     );
 
-
 `ifndef PULP_FPGA_EMUL
     rstgen i_rstgen
     (
@@ -428,10 +427,10 @@ module safe_domain
         .init_no     (             )  //not used
     );
 
-  assign slow_clk_o = ref_clk_i;
+   assign slow_clk_o = ref_clk_i;
 
-`else
-  assign s_rstn_sync = s_rstn;
+`else // !`ifndef PULP_FPGA_EMUL
+     assign s_rstn_sync = s_rstn;
   //Don't use the supplied clock directly for the FPGA target. On some boards
   //the reference clock is a very fast (e.g. 200MHz) clock that cannot be used
   //directly as the "slow_clk". Therefore we slow it down if a FPGA/board
@@ -447,9 +446,9 @@ module safe_domain
      .ref_clk_i(ref_clk_i),
      .slow_clk_o(slow_clk_o)
      );
-`endif
-
+`endif // !`ifndef PULP_FPGA_EMUL
 
+   
     assign s_rstn          = rst_ni;
     assign rst_no          = s_rstn;
 
diff --git a/rtl/pulp/soc_domain.sv b/rtl/pulp/soc_domain.sv
index 33d62721..3c756425 100644
--- a/rtl/pulp/soc_domain.sv
+++ b/rtl/pulp/soc_domain.sv
@@ -28,222 +28,227 @@ module soc_domain #(
     parameter EVNT_WIDTH           = 8
 )(
 
-    input logic                              ref_clk_i,
-    input logic                              slow_clk_i,
-    input logic                              test_clk_i,
-
-    input  logic                             rstn_glob_i,
-
-    input  logic                             dft_test_mode_i,
-    input  logic                             dft_cg_enable_i,
-
-    input  logic                             mode_select_i,
-
-    input logic                              bootsel_i,
-
-    input  logic                             jtag_tck_i,
-    input  logic                             jtag_trst_ni,
-    input  logic                             jtag_tms_i,
-    input  logic                             jtag_tdi_i,
-    output logic                             jtag_tdo_o,
-
-    output logic [`NB_CORES-1:0]             dbg_irq_valid_o,
-
-    input  logic [31:0]                      gpio_in_i,
-    output logic [31:0]                      gpio_out_o,
-    output logic [31:0]                      gpio_dir_o,
-    output logic [191:0]                     gpio_cfg_o,
-
-    output logic [127:0]                     pad_mux_o,
-    output logic [383:0]                     pad_cfg_o,
-
-    output logic                             uart_tx_o,
-    input  logic                             uart_rx_i,
-
-    input  logic                             cam_clk_i,
-    input  logic [7:0]                       cam_data_i,
-    input  logic                             cam_hsync_i,
-    input  logic                             cam_vsync_i,
-
-    output logic [3:0]                       timer_ch0_o,
-    output logic [3:0]                       timer_ch1_o,
-    output logic [3:0]                       timer_ch2_o,
-    output logic [3:0]                       timer_ch3_o,
-
-    input  logic                             i2c0_scl_i,
-    output logic                             i2c0_scl_o,
-    output logic                             i2c0_scl_oe_o,
-    input  logic                             i2c0_sda_i,
-    output logic                             i2c0_sda_o,
-    output logic                             i2c0_sda_oe_o,
-
-    input  logic                             i2c1_scl_i,
-    output logic                             i2c1_scl_o,
-    output logic                             i2c1_scl_oe_o,
-    input  logic                             i2c1_sda_i,
-    output logic                             i2c1_sda_o,
-    output logic                             i2c1_sda_oe_o,
-
-    input  logic                             i2s_slave_sd0_i,
-    input  logic                             i2s_slave_sd1_i,
-    input  logic                             i2s_slave_ws_i,
-    output logic                             i2s_slave_ws_o,
-    output logic                             i2s_slave_ws_oe,
-    input  logic                             i2s_slave_sck_i,
-    output logic                             i2s_slave_sck_o,
-    output logic                             i2s_slave_sck_oe,
-
-    output logic                             spi_master0_clk_o,
-    output logic                             spi_master0_csn0_o,
-    output logic                             spi_master0_csn1_o,
-    output logic                             spi_master0_oen0_o,
-    output logic                             spi_master0_oen1_o,
-    output logic                             spi_master0_oen2_o,
-    output logic                             spi_master0_oen3_o,
-    output logic                             spi_master0_sdo0_o,
-    output logic                             spi_master0_sdo1_o,
-    output logic                             spi_master0_sdo2_o,
-    output logic                             spi_master0_sdo3_o,
-    input  logic                             spi_master0_sdi0_i,
-    input  logic                             spi_master0_sdi1_i,
-    input  logic                             spi_master0_sdi2_i,
-    input  logic                             spi_master0_sdi3_i,
-
-    output logic                             sdio_clk_o,
-    output logic                             sdio_cmd_o,
-    input  logic                             sdio_cmd_i,
-    output logic                             sdio_cmd_oen_o,
-    output logic                       [3:0] sdio_data_o,
-    input  logic                       [3:0] sdio_data_i,
-    output logic                       [3:0] sdio_data_oen_o
-
-    ,
+    input logic                           ref_clk_i,
+    input logic                           test_clk_i,
+    input logic                           slow_clk_i,
+
+    input logic                           rstn_glob_i,
+    `ifdef PULP_FPGA_EMUL
+    //input logic                           zynq_soc_clk_i,
+    //input logic                           zynq_cluster_clk_i,
+    //input logic                           zynq_per_clk_i,
+    `endif
+
+    input logic                           dft_test_mode_i,
+    input logic                           dft_cg_enable_i,
+
+    input logic                           mode_select_i,
+
+    input logic                           bootsel_i,
+
+    input logic                           jtag_tck_i,
+    input logic                           jtag_trst_ni,
+    input logic                           jtag_tms_i,
+    input logic                           jtag_tdi_i,
+    output logic                          jtag_tdo_o,
+
+    output logic [`NB_CORES-1:0]          dbg_irq_valid_o,
+
+    input logic [31:0]                    gpio_in_i,
+    output logic [31:0]                   gpio_out_o,
+    output logic [31:0]                   gpio_dir_o,
+    output logic [191:0]                  gpio_cfg_o,
+
+    output logic [127:0]                  pad_mux_o,
+    output logic [383:0]                  pad_cfg_o,
+
+    output logic                          uart_tx_o,
+    input logic                           uart_rx_i,
+
+    input logic                           cam_clk_i,
+    input logic [7:0]                     cam_data_i,
+    input logic                           cam_hsync_i,
+    input logic                           cam_vsync_i,
+
+    output logic [3:0]                    timer_ch0_o,
+    output logic [3:0]                    timer_ch1_o,
+    output logic [3:0]                    timer_ch2_o,
+    output logic [3:0]                    timer_ch3_o,
+
+    input logic                           i2c0_scl_i,
+    output logic                          i2c0_scl_o,
+    output logic                          i2c0_scl_oe_o,
+    input logic                           i2c0_sda_i,
+    output logic                          i2c0_sda_o,
+    output logic                          i2c0_sda_oe_o,
+
+    input logic                           i2c1_scl_i,
+    output logic                          i2c1_scl_o,
+    output logic                          i2c1_scl_oe_o,
+    input logic                           i2c1_sda_i,
+    output logic                          i2c1_sda_o,
+    output logic                          i2c1_sda_oe_o,
+
+    input logic                           i2s_slave_sd0_i,
+    input logic                           i2s_slave_sd1_i,
+    input logic                           i2s_slave_ws_i,
+    output logic                          i2s_slave_ws_o,
+    output logic                          i2s_slave_ws_oe,
+    input logic                           i2s_slave_sck_i,
+    output logic                          i2s_slave_sck_o,
+    output logic                          i2s_slave_sck_oe,
+
+    output logic                          spi_master0_clk_o,
+    output logic                          spi_master0_csn0_o,
+    output logic                          spi_master0_csn1_o,
+    output logic                          spi_master0_oen0_o,
+    output logic                          spi_master0_oen1_o,
+    output logic                          spi_master0_oen2_o,
+    output logic                          spi_master0_oen3_o,
+    output logic                          spi_master0_sdo0_o,
+    output logic                          spi_master0_sdo1_o,
+    output logic                          spi_master0_sdo2_o,
+    output logic                          spi_master0_sdo3_o,
+    input logic                           spi_master0_sdi0_i,
+    input logic                           spi_master0_sdi1_i,
+    input logic                           spi_master0_sdi2_i,
+    input logic                           spi_master0_sdi3_i,
+
+    output logic                          sdio_clk_o,
+    output logic                          sdio_cmd_o,
+    input logic                           sdio_cmd_i,
+    output logic                          sdio_cmd_oen_o,
+    output logic [3:0]                    sdio_data_o,
+    input logic [3:0]                     sdio_data_i,
+    output logic [3:0]                    sdio_data_oen_o
+                                          
+                                          ,
     // CLUSTER
-    output logic                             cluster_clk_o,
-    output logic                             cluster_rstn_o,
-    input  logic                             cluster_busy_i,
-    output logic                             cluster_irq_o,
-
-    output logic                             cluster_rtc_o,
-    output logic                             cluster_fetch_enable_o,
-    output logic [63:0]                      cluster_boot_addr_o,
-    output logic                             cluster_test_en_o,
-    output logic                             cluster_pow_o,
-    output logic                             cluster_byp_o,
+    output logic                          cluster_clk_o,
+    output logic                          cluster_rstn_o,
+    input logic                           cluster_busy_i,
+    output logic                          cluster_irq_o,
+
+    output logic                          cluster_rtc_o,
+    output logic                          cluster_fetch_enable_o,
+    output logic [63:0]                   cluster_boot_addr_o,
+    output logic                          cluster_test_en_o,
+    output logic                          cluster_pow_o,
+    output logic                          cluster_byp_o,
 
     // EVENT BUS
-    output logic [BUFFER_WIDTH-1:0]          cluster_events_wt_o,
-    input  logic [BUFFER_WIDTH-1:0]          cluster_events_rp_i,
-    output logic [EVNT_WIDTH-1:0]            cluster_events_da_o,
+    output logic [BUFFER_WIDTH-1:0]       cluster_events_wt_o,
+    input logic [BUFFER_WIDTH-1:0]        cluster_events_rp_i,
+    output logic [EVNT_WIDTH-1:0]         cluster_events_da_o,
 
-    output logic                             dma_pe_evt_ack_o,
-    input  logic                             dma_pe_evt_valid_i,
+    output logic                          dma_pe_evt_ack_o,
+    input logic                           dma_pe_evt_valid_i,
 
-    output logic                             dma_pe_irq_ack_o,
-    input  logic                             dma_pe_irq_valid_i,
+    output logic                          dma_pe_irq_ack_o,
+    input logic                           dma_pe_irq_valid_i,
 
-    output logic                             pf_evt_ack_o,
-    input logic                              pf_evt_valid_i,
+    output logic                          pf_evt_ack_o,
+    input logic                           pf_evt_valid_i,
 
     // AXI4 SLAVE
-    input  logic [7:0]                       data_slave_aw_writetoken_i,
-    input  logic [AXI_ADDR_WIDTH-1:0]        data_slave_aw_addr_i,
-    input  logic [2:0]                       data_slave_aw_prot_i,
-    input  logic [3:0]                       data_slave_aw_region_i,
-    input  logic [7:0]                       data_slave_aw_len_i,
-    input  logic [2:0]                       data_slave_aw_size_i,
-    input  logic [1:0]                       data_slave_aw_burst_i,
-    input  logic                             data_slave_aw_lock_i,
-    input  logic [3:0]                       data_slave_aw_cache_i,
-    input  logic [3:0]                       data_slave_aw_qos_i,
-    input  logic [AXI_ID_IN_WIDTH-1:0]       data_slave_aw_id_i,
-    input  logic [AXI_USER_WIDTH-1:0]        data_slave_aw_user_i,
-    output logic [7:0]                       data_slave_aw_readpointer_o,
-
-    input  logic [7:0]                       data_slave_ar_writetoken_i,
-    input  logic [AXI_ADDR_WIDTH-1:0]        data_slave_ar_addr_i,
-    input  logic [2:0]                       data_slave_ar_prot_i,
-    input  logic [3:0]                       data_slave_ar_region_i,
-    input  logic [7:0]                       data_slave_ar_len_i,
-    input  logic [2:0]                       data_slave_ar_size_i,
-    input  logic [1:0]                       data_slave_ar_burst_i,
-    input  logic                             data_slave_ar_lock_i,
-    input  logic [3:0]                       data_slave_ar_cache_i,
-    input  logic [3:0]                       data_slave_ar_qos_i,
-    input  logic [AXI_ID_IN_WIDTH-1:0]       data_slave_ar_id_i,
-    input  logic [AXI_USER_WIDTH-1:0]        data_slave_ar_user_i,
-    output logic [7:0]                       data_slave_ar_readpointer_o,
-
-    input  logic [7:0]                       data_slave_w_writetoken_i,
-    input  logic [AXI_DATA_IN_WIDTH-1:0]     data_slave_w_data_i,
-    input  logic [AXI_STRB_IN_WIDTH-1:0]     data_slave_w_strb_i,
-    input  logic [AXI_USER_WIDTH-1:0]        data_slave_w_user_i,
-    input  logic                             data_slave_w_last_i,
-    output logic [7:0]                       data_slave_w_readpointer_o,
-
-    output logic [7:0]                       data_slave_r_writetoken_o,
-    output logic [AXI_DATA_IN_WIDTH-1:0]     data_slave_r_data_o,
-    output logic [1:0]                       data_slave_r_resp_o,
-    output logic                             data_slave_r_last_o,
-    output logic [AXI_ID_IN_WIDTH-1:0]       data_slave_r_id_o,
-    output logic [AXI_USER_WIDTH-1:0]        data_slave_r_user_o,
-    input  logic [7:0]                       data_slave_r_readpointer_i,
-
-    output logic [7:0]                       data_slave_b_writetoken_o,
-    output logic [1:0]                       data_slave_b_resp_o,
-    output logic [AXI_ID_IN_WIDTH-1:0]       data_slave_b_id_o,
-    output logic [AXI_USER_WIDTH-1:0]        data_slave_b_user_o,
-    input  logic [7:0]                       data_slave_b_readpointer_i,
+    input logic [7:0]                     data_slave_aw_writetoken_i,
+    input logic [AXI_ADDR_WIDTH-1:0]      data_slave_aw_addr_i,
+    input logic [2:0]                     data_slave_aw_prot_i,
+    input logic [3:0]                     data_slave_aw_region_i,
+    input logic [7:0]                     data_slave_aw_len_i,
+    input logic [2:0]                     data_slave_aw_size_i,
+    input logic [1:0]                     data_slave_aw_burst_i,
+    input logic                           data_slave_aw_lock_i,
+    input logic [3:0]                     data_slave_aw_cache_i,
+    input logic [3:0]                     data_slave_aw_qos_i,
+    input logic [AXI_ID_IN_WIDTH-1:0]     data_slave_aw_id_i,
+    input logic [AXI_USER_WIDTH-1:0]      data_slave_aw_user_i,
+    output logic [7:0]                    data_slave_aw_readpointer_o,
+
+    input logic [7:0]                     data_slave_ar_writetoken_i,
+    input logic [AXI_ADDR_WIDTH-1:0]      data_slave_ar_addr_i,
+    input logic [2:0]                     data_slave_ar_prot_i,
+    input logic [3:0]                     data_slave_ar_region_i,
+    input logic [7:0]                     data_slave_ar_len_i,
+    input logic [2:0]                     data_slave_ar_size_i,
+    input logic [1:0]                     data_slave_ar_burst_i,
+    input logic                           data_slave_ar_lock_i,
+    input logic [3:0]                     data_slave_ar_cache_i,
+    input logic [3:0]                     data_slave_ar_qos_i,
+    input logic [AXI_ID_IN_WIDTH-1:0]     data_slave_ar_id_i,
+    input logic [AXI_USER_WIDTH-1:0]      data_slave_ar_user_i,
+    output logic [7:0]                    data_slave_ar_readpointer_o,
+
+    input logic [7:0]                     data_slave_w_writetoken_i,
+    input logic [AXI_DATA_IN_WIDTH-1:0]   data_slave_w_data_i,
+    input logic [AXI_STRB_IN_WIDTH-1:0]   data_slave_w_strb_i,
+    input logic [AXI_USER_WIDTH-1:0]      data_slave_w_user_i,
+    input logic                           data_slave_w_last_i,
+    output logic [7:0]                    data_slave_w_readpointer_o,
+
+    output logic [7:0]                    data_slave_r_writetoken_o,
+    output logic [AXI_DATA_IN_WIDTH-1:0]  data_slave_r_data_o,
+    output logic [1:0]                    data_slave_r_resp_o,
+    output logic                          data_slave_r_last_o,
+    output logic [AXI_ID_IN_WIDTH-1:0]    data_slave_r_id_o,
+    output logic [AXI_USER_WIDTH-1:0]     data_slave_r_user_o,
+    input logic [7:0]                     data_slave_r_readpointer_i,
+
+    output logic [7:0]                    data_slave_b_writetoken_o,
+    output logic [1:0]                    data_slave_b_resp_o,
+    output logic [AXI_ID_IN_WIDTH-1:0]    data_slave_b_id_o,
+    output logic [AXI_USER_WIDTH-1:0]     data_slave_b_user_o,
+    input logic [7:0]                     data_slave_b_readpointer_i,
 
     // AXI4 MASTER
-    output logic [7:0]                       data_master_aw_writetoken_o,
-    output logic [AXI_ADDR_WIDTH-1:0]        data_master_aw_addr_o,
-    output logic [2:0]                       data_master_aw_prot_o,
-    output logic [3:0]                       data_master_aw_region_o,
-    output logic [7:0]                       data_master_aw_len_o,
-    output logic [2:0]                       data_master_aw_size_o,
-    output logic [1:0]                       data_master_aw_burst_o,
-    output logic                             data_master_aw_lock_o,
-    output logic [3:0]                       data_master_aw_cache_o,
-    output logic [3:0]                       data_master_aw_qos_o,
-    output logic [AXI_ID_OUT_WIDTH-1:0]      data_master_aw_id_o,
-    output logic [AXI_USER_WIDTH-1:0]        data_master_aw_user_o,
-    input  logic [7:0]                       data_master_aw_readpointer_i,
-
-    output logic [7:0]                       data_master_ar_writetoken_o,
-    output logic [AXI_ADDR_WIDTH-1:0]        data_master_ar_addr_o,
-    output logic [2:0]                       data_master_ar_prot_o,
-    output logic [3:0]                       data_master_ar_region_o,
-    output logic [7:0]                       data_master_ar_len_o,
-    output logic [2:0]                       data_master_ar_size_o,
-    output logic [1:0]                       data_master_ar_burst_o,
-    output logic                             data_master_ar_lock_o,
-    output logic [3:0]                       data_master_ar_cache_o,
-    output logic [3:0]                       data_master_ar_qos_o,
-    output logic [AXI_ID_OUT_WIDTH-1:0]      data_master_ar_id_o,
-    output logic [AXI_USER_WIDTH-1:0]        data_master_ar_user_o,
-    input  logic [7:0]                       data_master_ar_readpointer_i,
-
-    output logic [7:0]                       data_master_w_writetoken_o,
-    output logic [AXI_DATA_OUT_WIDTH-1:0]    data_master_w_data_o,
-    output logic [AXI_STRB_OUT_WIDTH-1:0]    data_master_w_strb_o,
-    output logic [AXI_USER_WIDTH-1:0]        data_master_w_user_o,
-    output logic                             data_master_w_last_o,
-    input  logic [7:0]                       data_master_w_readpointer_i,
-
-    input  logic [7:0]                       data_master_r_writetoken_i,
-    input  logic [AXI_DATA_OUT_WIDTH-1:0]    data_master_r_data_i,
-    input  logic [1:0]                       data_master_r_resp_i,
-    input  logic                             data_master_r_last_i,
-    input  logic [AXI_ID_OUT_WIDTH-1:0]      data_master_r_id_i,
-    input  logic [AXI_USER_WIDTH-1:0]        data_master_r_user_i,
-    output logic [7:0]                       data_master_r_readpointer_o,
-
-    input  logic [7:0]                       data_master_b_writetoken_i,
-    input  logic [1:0]                       data_master_b_resp_i,
-    input  logic [AXI_ID_OUT_WIDTH-1:0]      data_master_b_id_i,
-    input  logic [AXI_USER_WIDTH-1:0]        data_master_b_user_i,
-    output logic [7:0]                       data_master_b_readpointer_o
+    output logic [7:0]                    data_master_aw_writetoken_o,
+    output logic [AXI_ADDR_WIDTH-1:0]     data_master_aw_addr_o,
+    output logic [2:0]                    data_master_aw_prot_o,
+    output logic [3:0]                    data_master_aw_region_o,
+    output logic [7:0]                    data_master_aw_len_o,
+    output logic [2:0]                    data_master_aw_size_o,
+    output logic [1:0]                    data_master_aw_burst_o,
+    output logic                          data_master_aw_lock_o,
+    output logic [3:0]                    data_master_aw_cache_o,
+    output logic [3:0]                    data_master_aw_qos_o,
+    output logic [AXI_ID_OUT_WIDTH-1:0]   data_master_aw_id_o,
+    output logic [AXI_USER_WIDTH-1:0]     data_master_aw_user_o,
+    input logic [7:0]                     data_master_aw_readpointer_i,
+
+    output logic [7:0]                    data_master_ar_writetoken_o,
+    output logic [AXI_ADDR_WIDTH-1:0]     data_master_ar_addr_o,
+    output logic [2:0]                    data_master_ar_prot_o,
+    output logic [3:0]                    data_master_ar_region_o,
+    output logic [7:0]                    data_master_ar_len_o,
+    output logic [2:0]                    data_master_ar_size_o,
+    output logic [1:0]                    data_master_ar_burst_o,
+    output logic                          data_master_ar_lock_o,
+    output logic [3:0]                    data_master_ar_cache_o,
+    output logic [3:0]                    data_master_ar_qos_o,
+    output logic [AXI_ID_OUT_WIDTH-1:0]   data_master_ar_id_o,
+    output logic [AXI_USER_WIDTH-1:0]     data_master_ar_user_o,
+    input logic [7:0]                     data_master_ar_readpointer_i,
+
+    output logic [7:0]                    data_master_w_writetoken_o,
+    output logic [AXI_DATA_OUT_WIDTH-1:0] data_master_w_data_o,
+    output logic [AXI_STRB_OUT_WIDTH-1:0] data_master_w_strb_o,
+    output logic [AXI_USER_WIDTH-1:0]     data_master_w_user_o,
+    output logic                          data_master_w_last_o,
+    input logic [7:0]                     data_master_w_readpointer_i,
+
+    input logic [7:0]                     data_master_r_writetoken_i,
+    input logic [AXI_DATA_OUT_WIDTH-1:0]  data_master_r_data_i,
+    input logic [1:0]                     data_master_r_resp_i,
+    input logic                           data_master_r_last_i,
+    input logic [AXI_ID_OUT_WIDTH-1:0]    data_master_r_id_i,
+    input logic [AXI_USER_WIDTH-1:0]      data_master_r_user_i,
+    output logic [7:0]                    data_master_r_readpointer_o,
+
+    input logic [7:0]                     data_master_b_writetoken_i,
+    input logic [1:0]                     data_master_b_resp_i,
+    input logic [AXI_ID_OUT_WIDTH-1:0]    data_master_b_id_i,
+    input logic [AXI_USER_WIDTH-1:0]      data_master_b_user_i,
+    output logic [7:0]                    data_master_b_readpointer_o
     );
 
     pulp_soc
diff --git a/fpga/pulpissimo-genesys2/rtl/fpga_bootrom.sv b/rtl/pulpemu/fpga_bootrom.sv
similarity index 56%
rename from fpga/pulpissimo-genesys2/rtl/fpga_bootrom.sv
rename to rtl/pulpemu/fpga_bootrom.sv
index 79d78b3f..d7b9b0b3 100644
--- a/fpga/pulpissimo-genesys2/rtl/fpga_bootrom.sv
+++ b/rtl/pulpemu/fpga_bootrom.sv
@@ -1,13 +1,12 @@
 //-----------------------------------------------------------------------------
-// Title         : FPGA Bootrom for PULPissimo
+// Title         : FPGA Bootrom for PULP
 //-----------------------------------------------------------------------------
 // File          : fpga_bootrom.sv
-// Author        : Manuel Eggimann  <meggimann@iis.ee.ethz.ch>
-// Created       : 29.05.2019
+// Author        : Jie Chen  <owenchj@gmail.com>
+// Created       : 23.10.2019
 //-----------------------------------------------------------------------------
 // Description :
-// Mockup bootrom that keeps returning jal x0,0 to trap the core in an infinite
-// loop until the debug module takes over control.
+// Real boot with jtag reaction.
 //-----------------------------------------------------------------------------
 // Copyright (C) 2013-2019 ETH Zurich, University of Bologna
 // Copyright and related rights are licensed under the Solderpad Hardware
@@ -26,11 +25,28 @@ module fpga_bootrom
     parameter ADDR_WIDTH=32,
     parameter DATA_WIDTH=32
     )
-  (
-   input logic                   CLK,
-   input logic                   CEN,
-   input logic [ADDR_WIDTH-1:0]  A,
-   output logic [DATA_WIDTH-1:0] Q
-   );
-  assign Q = 32'h0000006f; //jal x0,0
+   (
+    input logic                   CLK,
+    input logic                   RSTN,
+    input logic                   CEN,
+    input logic [ADDR_WIDTH-1:0]  A,
+    output logic [DATA_WIDTH-1:0] Q
+    );
+
+   logic [3:0]                    wea;
+   logic [31:0]                   dina;
+
+   assign wea  = 4'b0000;
+   assign dina = 32'h0000_0000;
+
+   xilinx_rom_bank_2048x32 rom_mem_i (
+                                      .clka  (CLK),
+                                      .rsta  (~RSTN),
+                                      .ena   (~CEN),
+                                      .wea   (wea),
+                                      .addra (A),
+                                      .dina  (dina),
+                                      .douta (Q)
+                                      );
+
 endmodule : fpga_bootrom
diff --git a/fpga/pulpissimo-genesys2/rtl/fpga_clk_gen.sv b/rtl/pulpemu/fpga_clk_gen.sv
similarity index 84%
rename from fpga/pulpissimo-genesys2/rtl/fpga_clk_gen.sv
rename to rtl/pulpemu/fpga_clk_gen.sv
index 2ad9a8eb..1cca5b60 100644
--- a/fpga/pulpissimo-genesys2/rtl/fpga_clk_gen.sv
+++ b/rtl/pulpemu/fpga_clk_gen.sv
@@ -52,23 +52,34 @@ module fpga_clk_gen (
                      );
 
   logic                                  s_locked;
+  logic                                  s_clk;
 
   xilinx_clk_mngr i_clk_manager
     (
      .resetn(rstn_glob_i),
      .clk_in1(ref_clk_i),
-     .clk_out1(soc_clk_o),
+     .clk_out1(s_clk),
      .clk_out2(per_clk_o),
+     //.clk_out3(cluster_clk_o),
      .locked(s_locked)
      );
 
-  assign soc_cfg_lock_o = s_locked;
-  assign per_cfg_lock_o = s_locked;
+  assign soc_clk_o     = s_clk;
+  assign cluster_clk_o = s_clk;
+  
+  assign soc_cfg_lock_o      = s_locked;
+  assign per_cfg_lock_o      = s_locked;
+  assign cluster_cfg_lock_o  = s_locked;
+   
 
-  assign soc_cfg_ack_o = 1'b1; //Always acknowledge without doing anything for now
-  assign per_cfg_ack_o = 1'b1;
+  assign soc_cfg_ack_o     = 1'b1; //Always acknowledge without doing anything for now
+  assign per_cfg_ack_o     = 1'b1;
+  assign cluster_cfg_ack_o = 1'b1;
+   
 
-  assign soc_cfg_r_data_o = 32'hdeadda7a;
-  assign per_cfg_r_data_o = 32'hdeadda7a;
+  assign soc_cfg_r_data_o     = 32'hdeadda7a;
+  assign per_cfg_r_data_o     = 32'hdeadda7a;
+  assign cluster_cfg_r_data_o = 32'hdeadda7a;
+   
 
 endmodule : fpga_clk_gen
diff --git a/fpga/pulpissimo-genesys2/rtl/fpga_interleaved_ram.sv b/rtl/pulpemu/fpga_interleaved_ram.sv
similarity index 100%
rename from fpga/pulpissimo-genesys2/rtl/fpga_interleaved_ram.sv
rename to rtl/pulpemu/fpga_interleaved_ram.sv
diff --git a/fpga/pulpissimo-genesys2/rtl/fpga_private_ram.sv b/rtl/pulpemu/fpga_private_ram.sv
similarity index 100%
rename from fpga/pulpissimo-genesys2/rtl/fpga_private_ram.sv
rename to rtl/pulpemu/fpga_private_ram.sv
diff --git a/fpga/pulpissimo-genesys2/rtl/fpga_slow_clk_gen.sv b/rtl/pulpemu/fpga_slow_clk_gen.sv
similarity index 100%
rename from fpga/pulpissimo-genesys2/rtl/fpga_slow_clk_gen.sv
rename to rtl/pulpemu/fpga_slow_clk_gen.sv
diff --git a/fpga/pulpissimo-genesys2/rtl/pad_functional_xilinx.sv b/rtl/pulpemu/pad_functional_xilinx.sv
similarity index 99%
rename from fpga/pulpissimo-genesys2/rtl/pad_functional_xilinx.sv
rename to rtl/pulpemu/pad_functional_xilinx.sv
index a3ca1cde..0d69b35f 100644
--- a/fpga/pulpissimo-genesys2/rtl/pad_functional_xilinx.sv
+++ b/rtl/pulpemu/pad_functional_xilinx.sv
@@ -17,7 +17,7 @@ module pad_functional_pd
    input  logic             PEN,
    inout  logic             PAD
 );
-
+  
   (* PULLDOWN = "YES" *)
   IOBUF iobuf_i (
     .T ( OEN ),
@@ -45,4 +45,4 @@ module pad_functional_pu
     .IO( PAD  )
   );
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/fpga/pulpissimo-genesys2/rtl/pulp_clock_gating_xilinx.sv b/rtl/pulpemu/pulp_clock_gating_xilinx.sv
similarity index 100%
rename from fpga/pulpissimo-genesys2/rtl/pulp_clock_gating_xilinx.sv
rename to rtl/pulpemu/pulp_clock_gating_xilinx.sv
diff --git a/rtl/pulpemu/pulpemu.sv b/rtl/pulpemu/pulpemu.sv
new file mode 100644
index 00000000..5a9f4cbc
--- /dev/null
+++ b/rtl/pulpemu/pulpemu.sv
@@ -0,0 +1,156 @@
+//-----------------------------------------------------------------------------
+// Title         : PULPissimo Verilog Wrapper
+//-----------------------------------------------------------------------------
+// File          : xilinx_pulpissimo.v
+// Author        : Manuel Eggimann  <meggimann@iis.ee.ethz.ch>
+// Created       : 21.05.2019
+//-----------------------------------------------------------------------------
+// Description :
+// Verilog Wrapper of PULPissimo to use the module within Xilinx IP integrator.
+//-----------------------------------------------------------------------------
+// Copyright (C) 2013-2019 ETH Zurich, University of Bologna
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+//-----------------------------------------------------------------------------
+
+module pulpemu
+  (
+   input wire  ref_clk_p,
+   input wire  ref_clk_n,
+
+   inout wire  pad_uart_rx,
+   inout wire  pad_uart_tx,
+  
+   inout       FMC_sdio_data0,
+   inout       FMC_sdio_data1,
+   inout       FMC_sdio_data2,
+   inout       FMC_sdio_data3,
+   inout       FMC_sdio_cmd,
+   inout       FMC_sdio_sck,
+  
+
+   inout       FMC_qspi_sdio0,
+   inout       FMC_qspi_sdio1,
+   inout       FMC_qspi_sdio2,
+   inout       FMC_qspi_sdio3,
+   inout       FMC_qspi_csn0,
+   inout       FMC_qspi_csn1,
+   inout       FMC_qspi_sck,
+
+   inout       FMC_i2c0_sda,
+   inout       FMC_i2c0_scl,
+
+   inout       FMC_i2s0_sck,
+   inout       FMC_i2s0_ws,
+   inout       FMC_i2s0_sdi,
+   inout       FMC_i2s1_sdi,
+  
+  
+   inout       FMC_cam_pclk,
+   inout       FMC_cam_hsync,
+   inout       FMC_cam_data0,
+   inout       FMC_cam_data1,
+   inout       FMC_cam_data2,
+   inout       FMC_cam_data3,
+   inout       FMC_cam_data4,
+   inout       FMC_cam_data5,
+   inout       FMC_cam_data6,
+   inout       FMC_cam_data7,
+   inout       FMC_cam_vsync,
+
+   input wire  pad_reset,
+
+   input wire  pad_jtag_tck,
+   input wire  pad_jtag_tdi,
+   output wire pad_jtag_tdo,
+   input wire  pad_jtag_tms
+ );
+
+   localparam CORE_TYPE = 0; // 0 for RISCY, 1 for ZERORISCY, 2 for MICRORISCY
+   localparam USE_FPU   = 1;
+   localparam USE_HWPE = 1;
+
+   wire        ref_clk;
+
+   logic       reset_n;
+
+   assign reset_n = ~pad_reset & pad_jtag_trst;
+
+
+   //Differential to single ended clock conversion
+   IBUFGDS
+     #(
+       .IOSTANDARD("LVDS"),
+       .DIFF_TERM("FALSE"),
+       .IBUF_LOW_PWR("FALSE"))
+   i_sysclk_iobuf
+     (
+      .I(ref_clk_p),
+      .IB(ref_clk_n),
+      .O(ref_clk)
+      );
+
+   pulp
+     #(.CORE_TYPE(CORE_TYPE),
+       .USE_FPU(USE_FPU),
+       .USE_HWPE(USE_HWPE)
+       ) i_pulp
+       (
+
+        .pad_spim_sdio0(FMC_qspi_sdio0),
+        .pad_spim_sdio1(FMC_qspi_sdio1),
+        .pad_spim_sdio2(FMC_qspi_sdio2),
+        .pad_spim_sdio3(FMC_qspi_sdio3),
+        .pad_spim_csn0(FMC_qspi_csn0),
+        .pad_spim_csn1(FMC_qspi_csn1),
+        .pad_spim_sck(FMC_qspi_sck),
+        
+        .pad_uart_rx(pad_uart_rx),   //keep
+        .pad_uart_tx(pad_uart_tx),   //keep
+        
+        .pad_cam_pclk(FMC_cam_pclk),
+        .pad_cam_hsync(FMC_cam_hsync),
+        .pad_cam_data0(FMC_cam_data0),
+        .pad_cam_data1(FMC_cam_data1),
+        .pad_cam_data2(FMC_cam_data2),
+        .pad_cam_data3(FMC_cam_data3),
+        .pad_cam_data4(FMC_cam_data4),
+        .pad_cam_data5(FMC_cam_data5),
+        .pad_cam_data6(FMC_cam_data6),
+        .pad_cam_data7(FMC_cam_data7),
+        .pad_cam_vsync(FMC_cam_vsync),
+        
+        
+        .pad_sdio_clk(FMC_sdio_sck),
+        .pad_sdio_cmd(FMC_sdio_cmd),
+        .pad_sdio_data0(FMC_sdio_data0),
+        .pad_sdio_data1(FMC_sdio_data1),
+        .pad_sdio_data2(FMC_sdio_data2),
+        .pad_sdio_data3(FMC_sdio_data3),
+        
+        .pad_i2c0_sda(FMC_i2c0_sda),
+        .pad_i2c0_scl(FMC_i2c0_scl),
+        .pad_i2s0_sck(FMC_i2s0_sck),
+        .pad_i2s0_ws(FMC_i2s0_ws),
+        .pad_i2s0_sdi(FMC_i2s0_sdi),
+        .pad_i2s1_sdi(FMC_i2s1_sdi),
+        
+        .pad_reset_n(reset_n),
+        
+        .pad_jtag_tck(pad_jtag_tck), //keep
+        .pad_jtag_tdi(pad_jtag_tdi), //keep
+        .pad_jtag_tdo(pad_jtag_tdo), //keep
+        .pad_jtag_tms(pad_jtag_tms), //keep
+        .pad_jtag_trst(1'b1),        //keep
+        
+        .pad_xtal_in(ref_clk),       //keep
+        .pad_bootsel()               //keep
+        );
+
+endmodule
diff --git a/rtl/pulpemu/pulpemu_ref_clk_div.sv b/rtl/pulpemu/pulpemu_ref_clk_div.sv
new file mode 100644
index 00000000..49f627f9
--- /dev/null
+++ b/rtl/pulpemu/pulpemu_ref_clk_div.sv
@@ -0,0 +1,37 @@
+
+module pulpemu_ref_clk_div
+  #(
+    parameter DIVISOR = 256
+    )
+   (
+    input logic  clk_i,
+    input logic  rstn_i,
+    output logic ref_clk_o
+    );
+
+   logic [($clog2(DIVISOR) - 1):0]   counter;
+
+   always_ff @(posedge clk_i, negedge rstn_i)
+     begin
+        if(!rstn_i)
+          begin
+             counter <= '0;
+          end
+        else
+          begin
+             if(counter >= (DIVISOR-1))
+               counter <= '0;
+             else
+               counter <= counter + 1;
+          end // else: !if(!rstn_i)
+     end
+
+   // The frequency of the output clk_out
+   //  = The frequency of the input clk_in divided by DIVISOR
+   // For example: clk_i = 8.388608 Mhz, if you want to get 32768 Hz signal to be reference clock
+   // You will modify the DIVISOR parameter value to 256
+   // Then the frequency of the output clk_out = 8.388608 Mhz/ 256 = 32768 Hz
+
+   assign ref_clk_o = (counter < DIVISOR / 2 ) ? 1'b0 : 1'b1;
+
+endmodule
diff --git a/rtl/pulpemu/src_files.yml b/rtl/pulpemu/src_files.yml
new file mode 100644
index 00000000..8d435759
--- /dev/null
+++ b/rtl/pulpemu/src_files.yml
@@ -0,0 +1,19 @@
+pulpemu:
+  incdirs: [
+    ../includes,
+    .,
+  ]
+  targets: [
+    xilinx,
+  ]
+  files: [
+    fpga_clk_gen.sv,
+    fpga_slow_clk_gen.sv,
+    pad_functional_xilinx.sv,
+    fpga_bootrom.sv,
+    fpga_interleaved_ram.sv,
+    fpga_private_ram.sv,
+    pulpemu.sv,
+    pulpemu_ref_clk_div.sv,
+    pulp_clock_gating_xilinx.sv
+  ]
diff --git a/rtl/tb/src_files.yml b/rtl/tb/src_files.yml
index a1d66dcb..249bdf10 100644
--- a/rtl/tb/src_files.yml
+++ b/rtl/tb/src_files.yml
@@ -3,6 +3,7 @@ tb:
     rtl
   ]
   files: [
+    ../../ips/riscv-dbg/src/dm_pkg.sv,
     riscv_pkg.sv,
     jtag_pkg.sv,
     pulp_tap_pkg.sv,
diff --git a/rtl/tb/tb_pulp.sv b/rtl/tb/tb_pulp.sv
index 20ba68c6..2cf25fcd 100644
--- a/rtl/tb/tb_pulp.sv
+++ b/rtl/tb/tb_pulp.sv
@@ -45,6 +45,11 @@ module tb_pulp;
    // period of the external reference clock (32.769kHz)
    parameter  REF_CLK_PERIOD = 30517ns;
 
+   
+   `ifdef PULP_FPGA_EMUL
+   parameter  SYSTEM_CLK_PERIOD = 8ns;
+   `endif
+   
    // how L2 is loaded. valid values are "JTAG" or "STANDALONE", the latter works only when USE_S25FS256S_MODEL is 1
    parameter  LOAD_L2 = "JTAG";
 
@@ -120,6 +125,7 @@ module tb_pulp;
    /* system wires */
    // the w_/s_ prefixes are used to mean wire/tri-type and logic-type (respectively)
 
+   logic                 s_cpu_rst = 1'b1;
    logic                 s_rst_n = 1'b0;
    logic                 s_rst_dpi_n;
    wire                  w_rst_n;
@@ -534,6 +540,9 @@ module tb_pulp;
 
 
    // PULP chip (design under test)
+   `ifndef PULP_FPGA_EMUL
+   `define PULP_INST i_dut
+
    pulp #(
       .CORE_TYPE ( CORE_TYPE ),
       .USE_FPU   ( RISCY_FPU )
@@ -589,6 +598,75 @@ module tb_pulp;
       .pad_xtal_in        ( w_clk_ref          )
    );
 
+   `else // !`ifndef PULP_FPGA_EMU
+
+   `define PULP_INST i_dut.pulp_chip_i
+
+   logic s_clk_125;
+   tb_clk_gen #( .CLK_PERIOD(SYSTEM_CLK_PERIOD) ) i_system_clk_gen (.clk_o(s_clk_125) );
+
+   pulpemu
+   `ifndef USE_NETLIST
+         #(
+	  .CORE_TYPE ( 0 ),
+	  .USE_FPU   ( 1 ),
+	  .USE_HWPE  ( 0 )
+	  )
+   `endif
+   i_dut (
+	  .clk_125_p          ( s_clk_125          ),
+	  .clk_125_n          ( ~s_clk_125         ),
+          .cpu_reset          ( s_cpu_rst          ),
+
+	  .FMC_qspi_sdio0     ( w_spi_master_sdio0 ),
+	  .FMC_qspi_sdio1     ( w_spi_master_sdio1 ),
+	  .FMC_qspi_sdio2     ( w_spi_master_sdio2 ),
+	  .FMC_qspi_sdio3     ( w_spi_master_sdio3 ),
+	  .FMC_qspi_csn0      ( w_spi_master_csn0  ),
+	  .FMC_qspi_csn1      ( w_spi_master_csn1  ),
+	  .FMC_qspi_sck       ( w_spi_master_sck   ),
+
+	  .FMC_uart_rx        ( w_uart_tx          ),
+	  .FMC_uart_tx        ( w_uart_rx          ),
+
+	  .FMC_cam_pclk       ( w_cam_pclk         ),
+	  .FMC_cam_hsync      ( w_cam_hsync        ),
+	  .FMC_cam_data0      ( w_cam_data[0]      ),
+	  .FMC_cam_data1      ( w_cam_data[1]      ),
+	  .FMC_cam_data2      ( w_cam_data[2]      ),
+	  .FMC_cam_data3      ( w_cam_data[3]      ),
+	  .FMC_cam_data4      ( w_cam_data[4]      ),
+	  .FMC_cam_data5      ( w_cam_data[5]      ),
+	  .FMC_cam_data6      ( w_cam_data[6]      ),
+	  .FMC_cam_data7      ( w_cam_data[7]      ),
+	  .FMC_cam_vsync      ( w_cam_vsync        ),
+
+	  .FMC_sdio_sck       (                    ),
+	  .FMC_sdio_cmd       (                    ),
+	  .FMC_sdio_data0     ( w_sdio_data0       ),
+	  .FMC_sdio_data1     (                    ),
+	  .FMC_sdio_data2     (                    ),
+	  .FMC_sdio_data3     (                    ),
+
+	  .FMC_i2c0_sda       ( w_i2c0_sda         ),
+	  .FMC_i2c0_scl       ( w_i2c0_scl         ),
+
+	  .FMC_i2s0_sck       ( w_i2s0_sck         ),
+	  .FMC_i2s0_ws        ( w_i2s0_ws          ),
+	  .FMC_i2s0_sdi       ( w_i2s0_sdi         ),
+	  .FMC_i2s1_sdi       ( w_i2s1_sdi         ),
+
+	  .FMC_reset_n        ( w_rst_n            ),
+	  .FMC_bootmode        ( w_bootsel          ),
+
+	  .FMC_jtag_tck       ( w_tck              ),
+	  .FMC_jtag_tdi       ( w_tdi              ),
+	  .FMC_jtag_tdo       ( w_tdo              ),
+	  .FMC_jtag_tms       ( w_tms              ),
+	  .FMC_jtag_trst      ( w_trstn            )
+	  );
+   `endif
+
    tb_clk_gen #( .CLK_PERIOD(REF_CLK_PERIOD) ) i_ref_clk_gen (.clk_o(s_clk_ref) );
 
     initial begin: timing_format
@@ -621,7 +699,13 @@ module tb_pulp;
 
          $display("[TB] %t - Asserting hard reset", $realtime);
          s_rst_n = 1'b0;
-
+   `ifdef PULP_FPGA_EMUL
+         $display("[TB] %t - Asserting CPU reset", $realtime);
+         s_cpu_rst = 1'b1;
+         #1us;
+         $display("[TB] %t - Releasing CPU reset", $realtime);
+         s_cpu_rst = 1'b0;
+   `endif
          #1ns
 
          uart_tb_rx_en  = 1'b1; // enable uart rx in testbench
@@ -807,8 +891,7 @@ module tb_pulp;
 
          end
       end
-
-
+   
    `ifndef USE_NETLIST
       /* File System access */
       logic r_stdout_pready;
@@ -822,26 +905,26 @@ module tb_pulp;
       logic [31:0] fs_wdata;
       logic [31:0] fs_rdata;
 
-      assign fs_clk = i_dut.soc_domain_i.pulp_soc_i.s_soc_clk;
-      assign fs_rst_n = i_dut.soc_domain_i.pulp_soc_i.s_soc_rstn;
+      assign fs_clk = `PULP_INST.soc_domain_i.pulp_soc_i.s_soc_clk;
+      assign fs_rst_n = `PULP_INST.soc_domain_i.pulp_soc_i.s_soc_rstn;
 
-      assign fs_csn   = ~(i_dut.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.psel &
-         i_dut.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.penable &
+      assign fs_csn   = ~(`PULP_INST.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.psel &
+         `PULP_INST.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.penable &
          r_stdout_pready);
-      assign fs_wen   = ~i_dut.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.pwrite;
-      assign fs_add   = i_dut.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.paddr;
-      assign fs_wdata = i_dut.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.pwdata;
+      assign fs_wen   = ~`PULP_INST.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.pwrite;
+      assign fs_add   = `PULP_INST.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.paddr;
+      assign fs_wdata = `PULP_INST.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.pwdata;
       assign fs_be    = 4'hF;
-      assign i_dut.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.pready  = r_stdout_pready;
-      assign i_dut.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.pslverr = 1'b0;
-      assign i_dut.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.prdata  = fs_rdata;
+      assign `PULP_INST.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.pready  = r_stdout_pready;
+      assign `PULP_INST.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.pslverr = 1'b0;
+      assign `PULP_INST.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.prdata  = fs_rdata;
 
       always_ff @(posedge fs_clk or negedge fs_rst_n) begin
          if(~fs_rst_n) begin
             r_stdout_pready <= 0;
          end
          else begin
-            r_stdout_pready <= (i_dut.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.psel & i_dut.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.penable);
+            r_stdout_pready <= (`PULP_INST.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.psel & `PULP_INST.soc_domain_i.pulp_soc_i.soc_peripherals_i.s_stdout_bus.penable);
          end
       end
 
diff --git a/rtl_list.yml b/rtl_list.yml
index 6af3b2f2..2412f823 100644
--- a/rtl_list.yml
+++ b/rtl_list.yml
@@ -8,8 +8,14 @@
 
 tb:
   path: tb
+  domain: [soc]
 vip:
   path: vip
+  domain: [soc]
+pulpemu:
+  path: pulpemu
+  domain: [soc]
 pulp:
   path: pulp
+  domain: [soc]