From 2cd911a9b9d358255a51584c18f67e90117ac30b Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Mon, 16 Feb 2026 21:50:43 +0530 Subject: [PATCH 01/16] Revert "Merge remote-tracking branch tech/all/dt/glymur into qcom-next" This reverts commit 523e555741acc68e7abdf9fdc55dfcf190bb2a5d, reversing changes made to afa3f7dac73c814635c77d34461c91a41e385f06. Signed-off-by: Pradyot Kumar Nayak --- .../devicetree/bindings/arm/qcom.yaml | 5 - arch/arm64/boot/dts/qcom/Makefile | 1 - arch/arm64/boot/dts/qcom/glymur-crd.dts | 895 -- arch/arm64/boot/dts/qcom/glymur.dtsi | 7997 ----------------- arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 187 - arch/arm64/boot/dts/qcom/pmh0101.dtsi | 68 - arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 144 - arch/arm64/boot/dts/qcom/pmk8850.dtsi | 70 - arch/arm64/boot/dts/qcom/smb2370.dtsi | 45 - 9 files changed, 9412 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/glymur-crd.dts delete mode 100644 arch/arm64/boot/dts/qcom/glymur.dtsi delete mode 100644 arch/arm64/boot/dts/qcom/pmcx0102.dtsi delete mode 100644 arch/arm64/boot/dts/qcom/pmh0101.dtsi delete mode 100644 arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi delete mode 100644 arch/arm64/boot/dts/qcom/pmk8850.dtsi delete mode 100644 arch/arm64/boot/dts/qcom/smb2370.dtsi diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index b6398bc8c588..d84bd3bca201 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -61,11 +61,6 @@ properties: - qcom,apq8084-sbc - const: qcom,apq8084 - - items: - - enum: - - qcom,glymur-crd - - const: qcom,glymur - - items: - enum: - microsoft,dempsey diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6ff911cca06c..6f34d5ed331c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -13,7 +13,6 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb -dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts deleted file mode 100644 index 130bb9f801b5..000000000000 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ /dev/null @@ -1,895 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -/dts-v1/; - -#include "glymur.dtsi" -#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ -#include "pmh0101.dtsi" /* SPMI0: SID-1 */ -#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */ -#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */ -#include "pmk8850.dtsi" /* SPMI0: SID-0 */ -#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ - -/ { - model = "Qualcomm Technologies, Inc. Glymur CRD"; - compatible = "qcom,glymur-crd", "qcom,glymur"; - - aliases { - serial0 = &uart21; - serial1 = &uart14; - i2c0 = &i2c0; - i2c1 = &i2c4; - i2c2 = &i2c5; - spi0 = &spi18; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - clock-frequency = <38400000>; - #clock-cells = <0>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&key_vol_up_default>; - pinctrl-names = "default"; - - key-volume-up { - label = "Volume Up"; - linux,code = ; - gpios = <&pmh0101_gpios 6 GPIO_ACTIVE_LOW>; - debounce-interval = <15>; - linux,can-disable; - wakeup-source; - }; - }; - - pmic-glink { - compatible = "qcom,glymur-pmic-glink"; - #address-cells = <1>; - #size-cells = <0>; - - connector@0 { - compatible = "usb-c-connector"; - reg = <0>; - - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_hs_in: endpoint { - remote-endpoint = <&usb1_ss0_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss_in: endpoint { - remote-endpoint = <&usb1_ss0_qmpphy_out>; - }; - }; - }; - }; - - connector@1 { - compatible = "usb-c-connector"; - reg = <1>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_hs_in1: endpoint { - remote-endpoint = <&usb1_ss1_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss_in1: endpoint { - remote-endpoint = <&usb1_ss1_qmpphy_out>; - }; - }; - }; - }; - - connector@2 { - compatible = "usb-c-connector"; - reg = <2>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_hs_in2: endpoint { - remote-endpoint = <&usb1_ss2_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss_in2: endpoint { - remote-endpoint = <&usb1_ss2_qmpphy_out>; - }; - }; - }; - }; - }; - - vreg_nvme: regulator-nvme { - compatible = "regulator-fixed"; - - regulator-name = "VREG_NVME_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&nvme_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_nvmesec: regulator-nvmesec { - compatible = "regulator-fixed"; - - regulator-name = "VREG_NVME_SEC_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pmh0110_f_e1_gpios 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&nvme_sec_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_wlan: regulator-wlan { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WLAN_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&wlan_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_wwan: regulator-wwan { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WWAN_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 246 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&wwan_reg_en>; - pinctrl-names = "default"; - }; -}; - -&apps_rsc { - regulators-0 { - compatible = "qcom,pmh0101-rpmh-regulators"; - qcom,pmic-id = "B_E0"; - - vreg_bob1_e0: bob1 { - regulator-name = "vreg_bob1_e0"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <4224000>; - regulator-initial-mode = ; - }; - - vreg_bob2_e0: bob2 { - regulator-name = "vreg_bob2_e0"; - regulator-min-microvolt = <2540000>; - regulator-max-microvolt = <3600000>; - regulator-initial-mode = ; - }; - - vreg_l1b_e0_1p8: ldo1 { - regulator-name = "vreg_l1b_e0_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l2b_e0_2p9: ldo2 { - regulator-name = "vreg_l2b_e0_2p9"; - regulator-min-microvolt = <2904000>; - regulator-max-microvolt = <2904000>; - regulator-initial-mode = ; - }; - - vreg_l7b_e0_2p79: ldo7 { - regulator-name = "vreg_l7b_e0_2p79"; - regulator-min-microvolt = <2790000>; - regulator-max-microvolt = <2792000>; - regulator-initial-mode = ; - }; - - vreg_l8b_e0_1p50: ldo8 { - regulator-name = "vreg_l8b_e0_1p50"; - regulator-min-microvolt = <1504000>; - regulator-max-microvolt = <1504000>; - regulator-initial-mode = ; - }; - - vreg_l9b_e0_2p7: ldo9 { - regulator-name = "vreg_l9b_e0_2p7"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - vreg_l10b_e0_1p8: ldo10 { - regulator-name = "vreg_l10b_e0_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l11b_e0_1p2: ldo11 { - regulator-name = "vreg_l11b_e0_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l12b_e0_1p14: ldo12 { - regulator-name = "vreg_l12b_e0_1p14"; - regulator-min-microvolt = <1144000>; - regulator-max-microvolt = <1144000>; - regulator-initial-mode = ; - }; - - vreg_l15b_e0_1p8: ldo15 { - regulator-name = "vreg_l15b_e0_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l17b_e0_2p4: ldo17 { - regulator-name = "vreg_l17b_e0_2p4"; - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <2700000>; - regulator-initial-mode = ; - }; - - vreg_l18b_e0_1p2: ldo18 { - regulator-name = "vreg_l18b_e0_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - }; - - regulators-1 { - compatible = "qcom,pmcx0102-rpmh-regulators"; - qcom,pmic-id = "C_E1"; - - vreg_l1c_e1_0p82: ldo1 { - regulator-name = "vreg_l1c_e1_0p82"; - regulator-min-microvolt = <832000>; - regulator-max-microvolt = <832000>; - regulator-initial-mode = ; - }; - - vreg_l2c_e1_1p14: ldo2 { - regulator-name = "vreg_l2c_e1_1p14"; - regulator-min-microvolt = <1144000>; - regulator-max-microvolt = <1144000>; - regulator-initial-mode = ; - }; - - vreg_l3c_e1_0p89: ldo3 { - regulator-name = "vreg_l3c_e1_0p89"; - regulator-min-microvolt = <890000>; - regulator-max-microvolt = <980000>; - regulator-initial-mode = ; - }; - - vreg_l4c_e1_0p72: ldo4 { - regulator-name = "vreg_l4c_e1_0p72"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <720000>; - regulator-initial-mode = ; - }; - }; - - regulators-2 { - compatible = "qcom,pmh0110-rpmh-regulators"; - qcom,pmic-id = "F_E0"; - - vreg_s7f_e0_1p32: smps7 { - regulator-name = "vreg_s7f_e0_1p32"; - regulator-min-microvolt = <1320000>; - regulator-max-microvolt = <1352000>; - regulator-initial-mode = ; - }; - - vreg_s8f_e0_0p95: smps8 { - regulator-name = "vreg_s8f_e0_0p95"; - regulator-min-microvolt = <952000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_s9f_e0_1p9: smps9 { - regulator-name = "vreg_s9f_e0_1p9"; - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - vreg_l2f_e0_0p82: ldo2 { - regulator-name = "vreg_l2f_e0_0p82"; - regulator-min-microvolt = <832000>; - regulator-max-microvolt = <832000>; - regulator-initial-mode = ; - }; - - vreg_l3f_e0_0p72: ldo3 { - regulator-name = "vreg_l3f_e0_0p72"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <720000>; - regulator-initial-mode = ; - }; - - vreg_l4f_e0_0p3: ldo4 { - regulator-name = "vreg_l4f_e0_0p3"; - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - }; - - regulators-3 { - compatible = "qcom,pmh0110-rpmh-regulators"; - qcom,pmic-id = "F_E1"; - - vreg_s7f_e1_0p3: smps7 { - regulator-name = "vreg_s7f_e1_0p3"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l1f_e1_0p82: ldo1 { - regulator-name = "vreg_l1f_e1_0p82"; - regulator-min-microvolt = <832000>; - regulator-max-microvolt = <832000>; - regulator-initial-mode = ; - }; - - vreg_l2f_e1_0p83: ldo2 { - regulator-name = "vreg_l2f_e1_0p83"; - regulator-min-microvolt = <832000>; - regulator-max-microvolt = <832000>; - regulator-initial-mode = ; - }; - - vreg_l4f_e1_1p08: ldo4 { - regulator-name = "vreg_l4f_e1_1p08"; - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1320000>; - regulator-initial-mode = ; - }; - }; - - regulators-4 { - compatible = "qcom,pmh0110-rpmh-regulators"; - qcom,pmic-id = "H_E0"; - - vreg_l1h_e0_0p89: ldo1 { - regulator-name = "vreg_l1h_e0_0p89"; - regulator-min-microvolt = <832000>; - regulator-max-microvolt = <832000>; - regulator-initial-mode = ; - }; - - vreg_l2h_e0_0p72: ldo2 { - regulator-name = "vreg_l2h_e0_0p72"; - regulator-min-microvolt = <832000>; - regulator-max-microvolt = <832000>; - regulator-initial-mode = ; - }; - - vreg_l3h_e0_0p32: ldo3 { - regulator-name = "vreg_l3h_e0_0p32"; - regulator-min-microvolt = <320000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - vreg_l4h_e0_1p2: ldo4 { - regulator-name = "vreg_l4h_e0_1p2"; - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1320000>; - regulator-initial-mode = ; - }; - }; -}; - -&i2c5 { - clock-frequency = <400000>; - - status = "okay"; - - ptn3222_0: redriver@43 { - compatible = "nxp,ptn3222"; - reg = <0x43>; - - reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; - - vdd3v3-supply = <&vreg_l8b_e0_1p50>; - vdd1v8-supply = <&vreg_l15b_e0_1p8>; - - #phy-cells = <0>; - }; - - ptn3222_1: redriver@4f { - compatible = "nxp,ptn3222"; - reg = <0x4f>; - - reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; - - vdd3v3-supply = <&vreg_l8b_e0_1p50>; - vdd1v8-supply = <&vreg_l15b_e0_1p8>; - - #phy-cells = <0>; - }; - - ptn3222_2: redriver@47 { - compatible = "nxp,ptn3222"; - reg = <0x47>; - - reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; - - vdd3v3-supply = <&vreg_l8b_e0_1p50>; - vdd1v8-supply = <&vreg_l15b_e0_1p8>; - - #phy-cells = <0>; - }; -}; - -&pcie3b { - vddpe-3v3-supply = <&vreg_nvmesec>; - - pinctrl-0 = <&pcie3b_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie3b_phy { - vdda-phy-supply = <&vreg_l3c_e1_0p89>; - vdda-pll-supply = <&vreg_l2c_e1_1p14>; - - status = "okay"; -}; - -&pcie3b_port0 { - reset-gpios = <&tlmm 155 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 157 GPIO_ACTIVE_LOW>; -}; - -&pcie4 { - vddpe-3v3-supply = <&vreg_wlan>; - - pinctrl-0 = <&pcie4_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie4_phy { - vdda-phy-supply = <&vreg_l1c_e1_0p82>; - vdda-pll-supply = <&vreg_l4f_e1_1p08>; - - status = "okay"; -}; - -&pcie4_port0 { - reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; -}; - -&pcie5 { - vddpe-3v3-supply = <&vreg_nvme>; - - pinctrl-0 = <&pcie5_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie5_phy { - vdda-phy-supply = <&vreg_l2f_e0_0p82>; - vdda-pll-supply = <&vreg_l4h_e0_1p2>; - - status = "okay"; -}; - -&pcie5_port0 { - reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; -}; - -&pcie6 { - vddpe-3v3-supply = <&vreg_wwan>; - - pinctrl-0 = <&pcie6_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie6_phy { - vdda-phy-supply = <&vreg_l1c_e1_0p82>; - vdda-pll-supply = <&vreg_l4f_e1_1p08>; - - status = "okay"; -}; - -&pcie6_port0 { - reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; -}; - -&pmh0101_gpios { - nvme_reg_en: nvme-reg-en-state { - pins = "gpio14"; - function = "normal"; - bias-disable; - }; -}; - -&pmh0110_f_e1_gpios { - nvme_sec_reg_en: nvme-reg-en-state { - pins = "gpio14"; - function = "normal"; - bias-disable; - }; -}; - -&pmh0101_gpios { - key_vol_up_default: key-vol-up-default-state { - pins = "gpio6"; - function = "normal"; - output-disable; - bias-pull-up; - }; -}; - -&pmk8850_rtc { - qcom,no-alarm; -}; - -&pon_resin { - linux,code = ; - status = "okay"; -}; - -&smb2370_j_e2_eusb2_repeater { - vdd18-supply = <&vreg_l15b_e0_1p8>; - vdd3-supply = <&vreg_l7b_e0_2p79>; -}; - -&smb2370_k_e2_eusb2_repeater { - vdd18-supply = <&vreg_l15b_e0_1p8>; - vdd3-supply = <&vreg_l7b_e0_2p79>; -}; - -&smb2370_l_e2_eusb2_repeater { - vdd18-supply = <&vreg_l15b_e0_1p8>; - vdd3-supply = <&vreg_l7b_e0_2p79>; -}; - -&remoteproc_adsp { - firmware-name = "qcom/glymur/adsp.mbn", - "qcom/glymur/adsp_dtb.mbn"; - - status = "okay"; -}; - -&remoteproc_cdsp { - firmware-name = "qcom/glymur/cdsp.mbn", - "qcom/glymur/cdsp_dtb.mbn"; - - status = "okay"; -}; - -&tlmm { - gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ - <10 2>, /* OOB UART */ - <44 4>; /* Security SPI (TPM) */ - - pcie4_default: pcie4-default-state { - clkreq-n-pins { - pins = "gpio147"; - function = "pcie4_clk_req_n"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio146"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio148"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie5_default: pcie5-default-state { - clkreq-n-pins { - pins = "gpio153"; - function = "pcie5_clk_req_n"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio152"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio154"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie6_default: pcie6-default-state { - clkreq-n-pins { - pins = "gpio150"; - function = "pcie6_clk_req_n"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio149"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio151"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie3b_default: pcie3b-default-state { - clkreq-n-pins { - pins = "gpio156"; - function = "pcie3b_clk"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio155"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio157"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - wlan_reg_en: wlan-reg-en-state { - pins = "gpio94"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wwan_reg_en: wwan-reg-en-state { - pins = "gpio246"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; -}; - -&usb1_ss0_hsphy { - vdd-supply = <&vreg_l3f_e0_0p72>; - vdda12-supply = <&vreg_l4h_e0_1p2>; - - phys = <&smb2370_j_e2_eusb2_repeater>; - - status = "okay"; -}; - -&usb1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l3f_e0_0p72>; - refgen-supply = <&vreg_l2f_e0_0p82>; - - status = "okay"; -}; - -&usb1_ss0_qmpphy_out { - remote-endpoint = <&pmic_glink_ss_in>; -}; - -&usb1_ss0_dwc3_hs { - remote-endpoint = <&pmic_glink_hs_in>; -}; - -&usb1_ss0 { - status = "okay"; -}; - -&usb1_ss1_qmpphy_out { - remote-endpoint = <&pmic_glink_ss_in1>; -}; - -&usb1_ss1_dwc3_hs { - remote-endpoint = <&pmic_glink_hs_in1>; -}; - -&usb1_ss1_hsphy { - vdd-supply = <&vreg_l3f_e0_0p72>; - vdda12-supply = <&vreg_l4h_e0_1p2>; - - phys = <&smb2370_k_e2_eusb2_repeater>; - - status = "okay"; -}; - -&usb1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l1h_e0_0p89>; - refgen-supply = <&vreg_l2f_e0_0p82>; - - status = "okay"; -}; - -&usb1_ss1 { - status = "okay"; -}; - -&usb1_ss2_qmpphy_out { - remote-endpoint = <&pmic_glink_ss_in2>; -}; - -&usb1_ss2_dwc3_hs { - remote-endpoint = <&pmic_glink_hs_in2>; -}; - -&usb1_ss2_hsphy { - vdd-supply = <&vreg_l4c_e1_0p72>; - vdda12-supply = <&vreg_l4f_e1_1p08>; - - phys = <&smb2370_l_e2_eusb2_repeater>; - - status = "okay"; -}; - -&usb1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l4f_e1_1p08>; - vdda-pll-supply = <&vreg_l4c_e1_0p72>; - refgen-supply = <&vreg_l1c_e1_0p82>; - - status = "okay"; -}; - -&usb1_ss2 { - status = "okay"; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_hsphy { - phys = <&ptn3222_2>; - - status = "okay"; -}; - -&usb_mp_hsphy0 { - vdd-supply = <&vreg_l2h_e0_0p72>; - vdda12-supply = <&vreg_l4h_e0_1p2>; - - phys = <&ptn3222_0>; - - status = "okay"; -}; - -&usb_mp_hsphy1 { - vdd-supply = <&vreg_l2h_e0_0p72>; - vdda12-supply = <&vreg_l4h_e0_1p2>; - - phys = <&ptn3222_1>; - - status = "okay"; -}; - -&usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l2h_e0_0p72>; - refgen-supply = <&vreg_l4f_e1_1p08>; - - status = "okay"; -}; - -&usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l2h_e0_0p72>; - refgen-supply = <&vreg_l4f_e1_1p08>; - - status = "okay"; -}; - -&usb_mp { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi deleted file mode 100644 index d775352f2393..000000000000 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ /dev/null @@ -1,7997 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "glymur-ipcc.h" - -/ { - interrupt-parent = <&intc>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x0>; - enable-method = "psci"; - power-domains = <&cpu_pd0>, <&scmi_perf 0>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_0>; - - l2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - cpu1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x100>; - enable-method = "psci"; - power-domains = <&cpu_pd1>, <&scmi_perf 0>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_0>; - }; - - cpu2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x200>; - enable-method = "psci"; - power-domains = <&cpu_pd2>, <&scmi_perf 0>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_0>; - }; - - cpu3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x300>; - enable-method = "psci"; - power-domains = <&cpu_pd3>, <&scmi_perf 0>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_0>; - }; - - cpu4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x400>; - enable-method = "psci"; - power-domains = <&cpu_pd4>, <&scmi_perf 0>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_0>; - }; - - cpu5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x500>; - enable-method = "psci"; - power-domains = <&cpu_pd5>, <&scmi_perf 0>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_0>; - }; - - cpu6: cpu@10000 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x10000>; - enable-method = "psci"; - power-domains = <&cpu_pd6>, <&scmi_perf 1>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_1>; - - l2_1: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - cpu7: cpu@10100 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x10100>; - enable-method = "psci"; - power-domains = <&cpu_pd7>, <&scmi_perf 1>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_1>; - }; - - cpu8: cpu@10200 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x10200>; - enable-method = "psci"; - power-domains = <&cpu_pd8>, <&scmi_perf 1>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_1>; - }; - - cpu9: cpu@10300 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x10300>; - enable-method = "psci"; - power-domains = <&cpu_pd9>, <&scmi_perf 1>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_1>; - }; - - cpu10: cpu@10400 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x10400>; - enable-method = "psci"; - power-domains = <&cpu_pd10>, <&scmi_perf 1>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_1>; - }; - - cpu11: cpu@10500 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x10500>; - enable-method = "psci"; - power-domains = <&cpu_pd11>, <&scmi_perf 1>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_1>; - }; - - cpu12: cpu@20000 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x20000>; - enable-method = "psci"; - power-domains = <&cpu_pd12>, <&scmi_perf 2>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_2>; - - l2_2: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - }; - }; - - cpu13: cpu@20100 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x20100>; - enable-method = "psci"; - power-domains = <&cpu_pd13>, <&scmi_perf 2>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_2>; - }; - - cpu14: cpu@20200 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x20200>; - enable-method = "psci"; - power-domains = <&cpu_pd14>, <&scmi_perf 2>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_2>; - }; - - cpu15: cpu@20300 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x20300>; - enable-method = "psci"; - power-domains = <&cpu_pd15>, <&scmi_perf 2>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_2>; - }; - - cpu16: cpu@20400 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x20400>; - enable-method = "psci"; - power-domains = <&cpu_pd16>, <&scmi_perf 2>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_2>; - }; - - cpu17: cpu@20500 { - device_type = "cpu"; - compatible = "qcom,oryon"; - reg = <0x0 0x20500>; - enable-method = "psci"; - power-domains = <&cpu_pd17>, <&scmi_perf 2>; - power-domain-names = "psci", "perf"; - next-level-cache = <&l2_2>; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - - core2 { - cpu = <&cpu2>; - }; - - core3 { - cpu = <&cpu3>; - }; - - core4 { - cpu = <&cpu4>; - }; - - core5 { - cpu = <&cpu5>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu6>; - }; - - core1 { - cpu = <&cpu7>; - }; - - core2 { - cpu = <&cpu8>; - }; - - core3 { - cpu = <&cpu9>; - }; - - core4 { - cpu = <&cpu10>; - }; - - core5 { - cpu = <&cpu11>; - }; - }; - - cluster2 { - core0 { - cpu = <&cpu12>; - }; - - core1 { - cpu = <&cpu13>; - }; - - core2 { - cpu = <&cpu14>; - }; - - core3 { - cpu = <&cpu15>; - }; - - core4 { - cpu = <&cpu16>; - }; - - core5 { - cpu = <&cpu17>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - cpu_c4: cpu-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "ret"; - arm,psci-suspend-param = <0x00000004>; - entry-latency-us = <180>; - exit-latency-us = <320>; - min-residency-us = <1000>; - }; - }; - - domain-idle-states { - cluster_cl5: cluster-sleep-0 { - compatible = "domain-idle-state"; - arm,psci-suspend-param = <0x01000054>; - entry-latency-us = <2000>; - exit-latency-us = <2000>; - min-residency-us = <9000>; - }; - - domain_ss3: domain-sleep-0 { - compatible = "domain-idle-state"; - arm,psci-suspend-param = <0x0200c354>; - entry-latency-us = <2800>; - exit-latency-us = <4400>; - min-residency-us = <10150>; - }; - }; - }; - - dummy-sink { - compatible = "arm,coresight-dummy-sink"; - - in-ports { - port { - eud_in: endpoint { - remote-endpoint = <&swao_rep_out1>; - }; - }; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-glymur", "qcom,scm"; - qcom,dload-mode = <&tcsr 0x4000>; - interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - }; - - scmi { - compatible = "arm,scmi"; - mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>; - mbox-names = "tx", "rx"; - shmem = <&cpu_scp_lpri1>, <&cpu_scp_lpri0>; - - #address-cells = <1>; - #size-cells = <0>; - - scmi_perf: protocol@13 { - reg = <0x13>; - #power-domain-cells = <1>; - }; - }; - }; - - clk_virt: interconnect-0 { - compatible = "qcom,glymur-clk-virt"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mc_virt: interconnect-1 { - compatible = "qcom,glymur-mc-virt"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - - cpu_pd0: power-domain-cpu0 { - #power-domain-cells = <0>; - power-domains = <&cluster0_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cpu_pd1: power-domain-cpu1 { - #power-domain-cells = <0>; - power-domains = <&cluster0_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cpu_pd2: power-domain-cpu2 { - #power-domain-cells = <0>; - power-domains = <&cluster0_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cpu_pd3: power-domain-cpu3 { - #power-domain-cells = <0>; - power-domains = <&cluster0_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cpu_pd4: power-domain-cpu4 { - #power-domain-cells = <0>; - power-domains = <&cluster0_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cpu_pd5: power-domain-cpu5 { - #power-domain-cells = <0>; - power-domains = <&cluster0_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cpu_pd6: power-domain-cpu6 { - #power-domain-cells = <0>; - power-domains = <&cluster1_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cpu_pd7: power-domain-cpu7 { - #power-domain-cells = <0>; - power-domains = <&cluster1_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cpu_pd8: power-domain-cpu8 { - #power-domain-cells = <0>; - power-domains = <&cluster1_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cpu_pd9: power-domain-cpu9 { - #power-domain-cells = <0>; - power-domains = <&cluster1_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cpu_pd10: power-domain-cpu10 { - #power-domain-cells = <0>; - power-domains = <&cluster1_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cpu_pd11: power-domain-cpu11 { - #power-domain-cells = <0>; - power-domains = <&cluster1_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cpu_pd12: power-domain-cpu12 { - #power-domain-cells = <0>; - power-domains = <&cluster2_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cpu_pd13: power-domain-cpu13 { - #power-domain-cells = <0>; - power-domains = <&cluster2_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cpu_pd14: power-domain-cpu14 { - #power-domain-cells = <0>; - power-domains = <&cluster2_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cpu_pd15: power-domain-cpu15 { - #power-domain-cells = <0>; - power-domains = <&cluster2_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cpu_pd16: power-domain-cpu16 { - #power-domain-cells = <0>; - power-domains = <&cluster2_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cpu_pd17: power-domain-cpu17 { - #power-domain-cells = <0>; - power-domains = <&cluster2_pd>; - domain-idle-states = <&cpu_c4>; - }; - - cluster0_pd: power-domain-cpu-cluster0 { - #power-domain-cells = <0>; - power-domains = <&system_pd>; - domain-idle-states = <&cluster_cl5>; - }; - - cluster1_pd: power-domain-cpu-cluster1 { - #power-domain-cells = <0>; - power-domains = <&system_pd>; - domain-idle-states = <&cluster_cl5>; - }; - - cluster2_pd: power-domain-cpu-cluster2 { - #power-domain-cells = <0>; - power-domains = <&system_pd>; - domain-idle-states = <&cluster_cl5>; - }; - - system_pd: power-domain-system { - #power-domain-cells = <0>; - domain-idle-states = <&domain_ss3>; - }; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - pdp_mem: pdp@81400000 { - reg = <0x0 0x81400000 0x0 0x100000>; - no-map; - }; - - aop_cmd_db_mem: aop-cmd-db@81c60000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x81c60000 0x0 0x20000>; - no-map; - }; - - pdp_ns_shared_mem: pdp-ns-shared@81e00000 { - reg = <0x0 0x81e00000 0x0 0x200000>; - no-map; - }; - - oobdaretag_mem: oobdaretag@86e10000 { - reg = <0x0 0x86e10000 0x0 0x360000>; - no-map; - }; - - oob_secure_mem: oob-secure@87170000 { - reg = <0x0 0x87170000 0x0 0xbc0000>; - no-map; - }; - - oobdtbqc_mem: oobdtbqc@87d30000 { - reg = <0x0 0x87d30000 0x0 0x20000>; - no-map; - }; - - oobdtboem_mem: oobdtboem@87d50000 { - reg = <0x0 0x87d50000 0x0 0x20000>; - no-map; - }; - - oob_nonsecure_mem: oob-nonsecure@87e00000 { - reg = <0x0 0x87e00000 0x0 0xc00000>; - no-map; - }; - - spss_region_mem: spss@88a00000 { - reg = <0x0 0x88a00000 0x0 0x400000>; - no-map; - }; - - soccpdtb_mem: soccpdtb@892e0000 { - reg = <0x0 0x892e0000 0x0 0x20000>; - no-map; - }; - - soccp_mem: soccp@89300000 { - reg = <0x0 0x89300000 0x0 0x400000>; - no-map; - }; - - cvp_mem: cvp@89700000 { - reg = <0x0 0x89700000 0x0 0x700000>; - no-map; - }; - - adspslpi_mem: adspslpi@89e00000 { - reg = <0x0 0x89e00000 0x0 0x3a00000>; - no-map; - }; - - q6_adsp_dtb_mem: q6-adsp-dtb@8d800000 { - reg = <0x0 0x8d800000 0x0 0x80000>; - no-map; - }; - - cdsp_mem: cdsp@8d900000 { - reg = <0x0 0x8d900000 0x0 0x4000000>; - no-map; - }; - - q6_cdsp_dtb_mem: q6-cdsp-dtb@91900000 { - reg = <0x0 0x91900000 0x0 0x80000>; - no-map; - }; - - gpu_microcode_mem: gpu-microcode@919fe000 { - reg = <0x0 0x919fe000 0x0 0x2000>; - no-map; - }; - - camera_mem: camera@91a00000 { - reg = <0x0 0x91a00000 0x0 0x800000>; - no-map; - }; - - av1_encoder_mem: av1-encoder@92200000 { - reg = <0x0 0x92200000 0x0 0x700000>; - no-map; - }; - - video_mem: video@92900000 { - reg = <0x0 0x92900000 0x0 0xc00000>; - no-map; - }; - - smem_mem: smem@ffe00000 { - compatible = "qcom,smem"; - reg = <0x0 0xffe00000 0x0 0x200000>; - hwlocks = <&tcsr_mutex 3>; - no-map; - }; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - - interrupts-extended = <&ipcc IPCC_MPROC_LPASS - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - - mboxes = <&ipcc IPCC_MPROC_LPASS IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,smem = <443>, <429>; - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - smp2p_adsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_adsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - - interrupts-extended = <&ipcc IPCC_MPROC_CDSP - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - - mboxes = <&ipcc IPCC_MPROC_CDSP IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,smem = <94>, <432>; - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - smp2p_cdsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_cdsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-soccp { - compatible = "qcom,smp2p"; - - interrupts-extended = <&ipcc IPCC_MPROC_SOCCP - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - - mboxes = <&ipcc IPCC_MPROC_SOCCP - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,smem = <617>, <616>; - qcom,local-pid = <0>; - qcom,remote-pid = <19>; - - soccp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - soccp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; - dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; - - gcc: clock-controller@100000 { - compatible = "qcom,glymur-gcc"; - reg = <0x0 0x00100000 0x0 0x1f9000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, /* Board XO source */ - <&rpmhcc RPMH_CXO_CLK_A>, /* Board XO_A source */ - <&sleep_clk>, /* Sleep */ - <0>, /* USB 0 Phy DP0 GMUX */ - <0>, /* USB 0 Phy DP1 GMUX */ - <0>, /* USB 0 Phy PCIE PIPEGMUX */ - <0>, /* USB 0 Phy PIPEGMUX */ - <0>, /* USB 0 Phy SYS PCIE PIPEGMUX */ - <0>, /* USB 1 Phy DP0 GMUX 2 */ - <0>, /* USB 1 Phy DP1 GMUX 2 */ - <0>, /* USB 1 Phy PCIE PIPEGMUX */ - <0>, /* USB 1 Phy PIPEGMUX */ - <0>, /* USB 1 Phy SYS PCIE PIPEGMUX */ - <0>, /* USB 2 Phy DP0 GMUX 2 */ - <0>, /* USB 2 Phy DP1 GMUX 2 */ - <0>, /* USB 2 Phy PCIE PIPEGMUX */ - <0>, /* USB 2 Phy PIPEGMUX */ - <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ - <0>, /* PCIe 3a */ - <&pcie3b_phy>, /* PCIe 3b */ - <&pcie4_phy>, /* PCIe 4 */ - <&pcie5_phy>, /* PCIe 5 */ - <&pcie6_phy>, /* PCIe 6 */ - <0>, /* QUSB4 0 PHY RX 0 */ - <0>, /* QUSB4 0 PHY RX 1 */ - <0>, /* QUSB4 1 PHY RX 0 */ - <0>, /* QUSB4 1 PHY RX 1 */ - <0>, /* QUSB4 2 PHY RX 0 */ - <0>, /* QUSB4 2 PHY RX 1 */ - <0>, /* UFS PHY RX Symbol 0 */ - <0>, /* UFS PHY RX Symbol 1 */ - <0>, /* UFS PHY TX Symbol 0 */ - <&usb1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, - <&usb1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, - <&usb1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, - <&usb_mp_qmpphy0 QMP_USB43DP_USB3_PIPE_CLK>, - <&usb_mp_qmpphy1 QMP_USB43DP_USB3_PIPE_CLK>, - <0>, /* USB4 PHY 0 pcie pipe */ - <0>, /* USB4 PHY 0 Max pipe */ - <0>, /* USB4 PHY 1 pcie pipe */ - <0>, /* USB4 PHY 1 Max pipe */ - <0>, /* USB4 PHY 2 pcie */ - <0>; /* USB4 PHY 2 Max */ - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - gpi_dma2: dma-controller@800000 { - compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; - reg = <0x0 0x00800000 0x0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <16>; - dma-channel-mask = <0x3f>; - #dma-cells = <3>; - iommus = <&apps_smmu 0xd76 0x0>; - }; - - qupv3_2: geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x008c0000 0x0 0x3000>; - clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; - clock-names = "m-ahb", - "s-ahb"; - iommus = <&apps_smmu 0xd63 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - i2c16: i2c@880000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00880000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, - <&gpi_dma2 1 0 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c16_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi16: spi@880000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00880000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, - <&gpi_dma2 1 0 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c17: i2c@884000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00884000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, - <&gpi_dma2 1 1 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c17_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi17: spi@884000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00884000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, - <&gpi_dma2 1 1 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c18: i2c@888000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00888000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, - <&gpi_dma2 1 2 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c18_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi18: spi@888000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00888000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, - <&gpi_dma2 1 2 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c19: i2c@88c000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x0088c000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, - <&gpi_dma2 1 3 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c19_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi19: spi@88c000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x0088c000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, - <&gpi_dma2 1 3 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - uart19: serial@88c000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x0088c000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config"; - pinctrl-0 = <&qup_uart19_default>; - pinctrl-names = "default"; - - status = "disabled"; - }; - - i2c20: i2c@890000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00890000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, - <&gpi_dma2 1 4 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c20_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi20: spi@890000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00890000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, - <&gpi_dma2 1 4 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c21: i2c@894000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00894000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, - <&gpi_dma2 1 5 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c21_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi21: spi@894000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00894000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, - <&gpi_dma2 1 5 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - uart21: serial@894000 { - compatible = "qcom,geni-debug-uart"; - reg = <0x0 0x00894000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config"; - pinctrl-0 = <&qup_uart21_default>; - pinctrl-names = "default"; - }; - - i2c22: i2c@898000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00898000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, - <&gpi_dma2 1 6 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c22_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi22: spi@898000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00898000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, - <&gpi_dma2 1 6 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - uart22: serial@898000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x00898000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config"; - pinctrl-0 = <&qup_uart22_default>; - pinctrl-names = "default"; - - status = "disabled"; - }; - - i2c23: i2c@89c000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x0089c000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, - <&gpi_dma2 1 7 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c23_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi23: spi@89c000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x0089c000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, - <&gpi_dma2 1 7 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - }; - - gpi_dma1: dma-controller@a00000 { - compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; - reg = <0x0 0x00a00000 0x0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <16>; - dma-channel-mask = <0x3f>; - #dma-cells = <3>; - iommus = <&apps_smmu 0xcb6 0x0>; - }; - - qupv3_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x3000>; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - clock-names = "m-ahb", - "s-ahb"; - iommus = <&apps_smmu 0xca3 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - i2c8: i2c@a80000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00a80000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, - <&gpi_dma1 1 0 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c8_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi8: spi@a80000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00a80000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, - <&gpi_dma1 1 0 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c9: i2c@a84000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00a84000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, - <&gpi_dma1 1 1 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c9_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi9: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00a84000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, - <&gpi_dma1 1 1 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c10: i2c@a88000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00a88000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, - <&gpi_dma1 1 2 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c10_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi10: spi@a88000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00a88000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, - <&gpi_dma1 1 2 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c11: i2c@a8c000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00a8c000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, - <&gpi_dma1 1 3 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c11_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi11: spi@a8c000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00a8c000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, - <&gpi_dma1 1 3 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c12: i2c@a90000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00a90000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, - <&gpi_dma1 1 4 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c12_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi12: spi@a90000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00a90000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, - <&gpi_dma1 1 4 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c13: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00a94000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, - <&gpi_dma1 1 5 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c13_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi13: spi@a94000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00a94000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, - <&gpi_dma1 1 5 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c14: i2c@a98000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00a98000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, - <&gpi_dma1 1 6 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c14_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi14: spi@a98000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00a98000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, - <&gpi_dma1 1 6 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - uart14: serial@a98000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x00a98000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config"; - pinctrl-0 = <&qup_uart14_default>; - pinctrl-names = "default"; - - status = "disabled"; - }; - - i2c15: i2c@a9c000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00a9c000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, - <&gpi_dma1 1 7 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c15_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi15: spi@a9c000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00a9c000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, - <&gpi_dma1 1 7 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - }; - - gpi_dma0: dma-controller@b00000 { - compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; - reg = <0x0 0x00b00000 0x0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - dma-channels = <16>; - dma-channel-mask = <0x3f>; - #dma-cells = <3>; - iommus = <&apps_smmu 0xd36 0x0>; - }; - - qupv3_0: geniqup@bc0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00bc0000 0x0 0x3000>; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - clock-names = "m-ahb", - "s-ahb"; - iommus = <&apps_smmu 0xd23 0x0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - i2c0: i2c@b80000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00b80000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, - <&gpi_dma0 1 0 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c0_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi0: spi@b80000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00b80000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, - <&gpi_dma0 1 0 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c1: i2c@b84000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00b84000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, - <&gpi_dma0 1 1 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c1_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi1: spi@b84000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00b84000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, - <&gpi_dma0 1 1 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c2: i2c@b88000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00b88000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, - <&gpi_dma0 1 2 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c2_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi2: spi@b88000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00b88000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, - <&gpi_dma0 1 2 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - uart2: serial@b88000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x00b88000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config"; - pinctrl-0 = <&qup_uart2_default>; - pinctrl-names = "default"; - - status = "disabled"; - }; - - i2c3: i2c@b8c000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00b8c000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, - <&gpi_dma0 1 3 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c3_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi3: spi@b8c000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00b8c000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, - <&gpi_dma0 1 3 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c4: i2c@b90000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00b90000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, - <&gpi_dma0 1 4 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c4_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi4: spi@b90000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00b90000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, - <&gpi_dma0 1 4 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c5: i2c@b94000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00b94000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, - <&gpi_dma0 1 5 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c5_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi5: spi@b94000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00b94000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, - <&gpi_dma0 1 5 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c6: i2c@b98000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00b98000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, - <&gpi_dma0 1 6 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c6_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi6: spi@b98000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00b98000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, - <&gpi_dma0 1 6 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - i2c7: i2c@b9c000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x00b9c000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, - <&gpi_dma0 1 7 QCOM_GPI_I2C>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_i2c7_data_clk>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi7: spi@b9c000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x00b9c000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, - <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, - <&gpi_dma0 1 7 QCOM_GPI_SPI>; - dma-names = "tx", - "rx"; - pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - }; - - usb_mp_hsphy0: phy@fa1000 { - compatible = "qcom,glymur-m31-eusb2-phy", - "qcom,sm8750-m31-eusb2-phy"; - - reg = <0 0x00fa1000 0 0x29c>; - #phy-cells = <0>; - - clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; - - status = "disabled"; - }; - - usb_mp_hsphy1: phy@fa2000 { - compatible = "qcom,glymur-m31-eusb2-phy", - "qcom,sm8750-m31-eusb2-phy"; - - reg = <0 0x00fa2000 0 0x29c>; - #phy-cells = <0>; - - clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; - - status = "disabled"; - }; - - usb_mp_qmpphy0: phy@fa3000 { - compatible = "qcom,glymur-qmp-usb3-uni-phy"; - reg = <0 0x00fa3000 0 0x2000>; - - clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, - <&tcsr TCSR_USB3_0_CLKREF_EN>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; - clock-names = "aux", - "clkref", - "ref", - "com_aux", - "pipe"; - - power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; - - resets = <&gcc GCC_USB3_MP_SS0_PHY_BCR>, - <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; - reset-names = "phy", - "phy_phy"; - - clock-output-names = "usb3_uni_phy_0_pipe_clk_src"; - #clock-cells = <0>; - #phy-cells = <0>; - - status = "disabled"; - }; - - usb_mp_qmpphy1: phy@fa5000 { - compatible = "qcom,glymur-qmp-usb3-uni-phy"; - reg = <0 0x00fa5000 0 0x2000>; - - clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, - <&tcsr TCSR_USB3_1_CLKREF_EN>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; - clock-names = "aux", - "clkref", - "ref", - "com_aux", - "pipe"; - - power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; - - resets = <&gcc GCC_USB3_MP_SS1_PHY_BCR>, - <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; - reset-names = "phy", - "phy_phy"; - - clock-output-names = "usb3_uni_phy_1_pipe_clk_src"; - - #clock-cells = <0>; - #phy-cells = <0>; - - status = "disabled"; - }; - - usb1_ss0_hsphy: phy@fd3000 { - compatible = "qcom,glymur-m31-eusb2-phy", - "qcom,sm8750-m31-eusb2-phy"; - - reg = <0 0x00fd3000 0 0x29c>; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - - status = "disabled"; - }; - - usb1_ss0_qmpphy: phy@fd5000 { - compatible = "qcom,glymur-qmp-usb3-dp-phy"; - reg = <0 0x00fd5000 0 0x8000>; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "aux", - "ref", - "com_aux", - "usb3_pipe"; - - resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, - <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; - - reset-names = "phy", - "common"; - - power-domains = <&gcc GCC_USB_0_PHY_GDSC>; - - #clock-cells = <1>; - #phy-cells = <1>; - - mode-switch; - orientation-switch; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb1_ss0_qmpphy_out: endpoint { - }; - }; - - port@1 { - reg = <1>; - - usb1_ss0_qmpphy_usb_ss_in: endpoint { - remote-endpoint = <&usb1_ss0_dwc3_ss>; - }; - }; - - port@2 { - reg = <2>; - - usb_dp_qmpphy_dp_in: endpoint { - }; - }; - }; - }; - - usb1_ss1_hsphy: phy@fdd000 { - compatible = "qcom,glymur-m31-eusb2-phy", - "qcom,sm8750-m31-eusb2-phy"; - - reg = <0 0x00fdd000 0 0x29c>; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; - - status = "disabled"; - }; - - usb1_ss1_qmpphy: phy@fde000 { - compatible = "qcom,glymur-qmp-usb3-dp-phy"; - reg = <0 0x00fde000 0 0x8000>; - - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, - <&tcsr TCSR_USB4_1_CLKREF_EN>; - clock-names = "aux", - "ref", - "com_aux", - "usb3_pipe", - "clkref"; - - power-domains = <&gcc GCC_USB_1_PHY_GDSC>; - - resets = <&gcc GCC_USB3_PHY_SEC_BCR>, - <&gcc GCC_USB3PHY_PHY_SEC_BCR>; - reset-names = "phy", - "common"; - - #clock-cells = <1>; - #phy-cells = <1>; - - mode-switch; - orientation-switch; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb1_ss1_qmpphy_out: endpoint { - }; - }; - - port@1 { - reg = <1>; - - usb1_ss1_qmpphy_usb_ss_in: endpoint { - remote-endpoint = <&usb1_ss1_dwc3_ss>; - }; - }; - - port@2 { - reg = <2>; - - usb1_ss1_qmpphy_dp_in: endpoint { - }; - }; - }; - }; - - usb_2_hsphy: phy@fa0000 { - compatible = "qcom,glymur-m31-eusb2-phy", - "qcom,sm8750-m31-eusb2-phy"; - reg = <0 0x00fa0000 0 0x154>; - #phy-cells = <0>; - - clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; - - status = "disabled"; - }; - - - cnoc_main: interconnect@1500000 { - compatible = "qcom,glymur-cnoc-main"; - reg = <0x0 0x01500000 0x0 0x17080>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - - config_noc: interconnect@1600000 { - compatible = "qcom,glymur-cnoc-cfg"; - reg = <0x0 0x01600000 0x0 0x6600>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - - system_noc: interconnect@1680000 { - compatible = "qcom,glymur-system-noc"; - reg = <0x0 0x01680000 0x0 0x1c080>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - - pcie_west_anoc: interconnect@16c0000 { - compatible = "qcom,glymur-pcie-west-anoc"; - reg = <0x0 0x016c0000 0x0 0xf580>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - clocks = <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; - }; - - pcie_east_anoc: interconnect@16d0000 { - compatible = "qcom,glymur-pcie-east-anoc"; - reg = <0x0 0x016d0000 0x0 0xf300>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - clocks = <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,glymur-aggre1-noc"; - reg = <0x0 0x016e0000 0x0 0x14400>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - - aggre2_noc: interconnect@1720000 { - compatible = "qcom,glymur-aggre2-noc"; - reg = <0x0 0x01720000 0x0 0x14400>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - clocks = <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, - <&gcc GCC_AGGRE_USB4_2_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; - }; - - aggre3_noc: interconnect@1700000 { - compatible = "qcom,glymur-aggre3-noc"; - reg = <0x0 0x01700000 0x0 0x1d400>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - - aggre4_noc: interconnect@1740000 { - compatible = "qcom,glymur-aggre4-noc"; - reg = <0x0 0x01740000 0x0 0x14400>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, - <&gcc GCC_AGGRE_USB4_0_AXI_CLK>, - <&gcc GCC_AGGRE_USB4_1_AXI_CLK>; - }; - - mmss_noc: interconnect@1780000 { - compatible = "qcom,glymur-mmss-noc"; - reg = <0x0 0x01780000 0x0 0x5b800>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - - pcie_east_slv_noc: interconnect@1900000 { - compatible = "qcom,glymur-pcie-east-slv-noc"; - reg = <0x0 0x01900000 0x0 0xe080>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - - pcie_west_slv_noc: interconnect@1920000 { - compatible = "qcom,glymur-pcie-west-slv-noc"; - reg = <0x0 0x01920000 0x0 0xf180>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - - pcie4: pci@1bf0000 { - device_type = "pci"; - compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; - reg = <0x0 0x01bf0000 0x0 0x3000>, - <0x0 0x78000000 0x0 0xf20>, - <0x0 0x78000f40 0x0 0xa8>, - <0x0 0x78001000 0x0 0x4000>, - <0x0 0x78005000 0x0 0x100000>, - <0x0 0x01bf3000 0x0 0x1000>; - reg-names = "parf", - "dbi", - "elbi", - "atu", - "config", - "mhi"; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0x78105000 0x0 0x100000>, - <0x02000000 0x0 0x78205000 0x0 0x78205000 0x0 0x1dfb000>, - <0x03000000 0x7 0x80000000 0x7 0x80000000 0x0 0x20000000>; - bus-range = <0x00 0xff>; - - dma-coherent; - - linux,pci-domain = <4>; - num-lanes = <2>; - - operating-points-v2 = <&pcie4_opp_table>; - - msi-map = <0x0 &gic_its 0xc0000 0x10000>; - iommu-map = <0x0 &pcie_smmu 0x40000 0x10000>; - - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "msi0", - "msi1", - "msi2", - "msi3", - "msi4", - "msi5", - "msi6", - "msi7", - "global"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 513 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 514 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 515 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 516 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc GCC_PCIE_4_AUX_CLK>, - <&gcc GCC_PCIE_4_CFG_AHB_CLK>, - <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_4_SLV_AXI_CLK>, - <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>; - clock-names = "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "noc_aggr"; - - assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; - assigned-clock-rates = <19200000>; - - interconnects = <&pcie_west_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &pcie_west_slv_noc SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "pcie-mem", - "cpu-pcie"; - - resets = <&gcc GCC_PCIE_4_BCR>, - <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; - reset-names = "pci", - "link_down"; - - power-domains = <&gcc GCC_PCIE_4_GDSC>; - - eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; - eq-presets-16gts = /bits/ 8 <0x55 0x55>; - - status = "disabled"; - - pcie4_opp_table: opp-table { - compatible = "operating-points-v2"; - - /* GEN 1 x1 */ - opp-2500000-1 { - opp-hz = /bits/ 64 <2500000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <250000 1>; - opp-level = <1>; - }; - - /* GEN 1 x2 */ - opp-5000000-1 { - opp-hz = /bits/ 64 <5000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <500000 1>; - opp-level = <1>; - }; - - /* GEN 2 x1 */ - opp-5000000-2 { - opp-hz = /bits/ 64 <5000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <500000 1>; - opp-level = <2>; - }; - - /* GEN 2 x2 */ - opp-10000000-2 { - opp-hz = /bits/ 64 <10000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <1000000 1>; - opp-level = <2>; - }; - - /* GEN 3 x1 */ - opp-8000000-3 { - opp-hz = /bits/ 64 <8000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <984500 1>; - opp-level = <3>; - }; - - /* GEN 3 x2 */ - opp-16000000-3 { - opp-hz = /bits/ 64 <16000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <1969000 1>; - opp-level = <3>; - }; - - /* GEN 4 x1 */ - opp-16000000-4 { - opp-hz = /bits/ 64 <16000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <1969000 1>; - opp-level = <4>; - }; - - /* GEN 4 x2 */ - opp-32000000-4 { - opp-hz = /bits/ 64 <32000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <3938000 1>; - opp-level = <4>; - }; - - }; - - pcie4_port0: pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - bus-range = <0x01 0xff>; - - phys = <&pcie4_phy>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - }; - }; - - pcie4_phy: phy@1bf6000 { - compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; - reg = <0x0 0x01bf6000 0x0 0x2000>; - - clocks = <&gcc GCC_PCIE_PHY_4_AUX_CLK>, - <&gcc GCC_PCIE_4_CFG_AHB_CLK>, - <&tcsr TCSR_PCIE_2_CLKREF_EN>, - <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_4_PIPE_CLK>, - <&gcc GCC_PCIE_4_PIPE_DIV2_CLK>; - clock-names = "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe", - "pipediv2"; - - resets = <&gcc GCC_PCIE_4_PHY_BCR>, - <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; - reset-names = "phy", - "phy_nocsr"; - - assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; - - #clock-cells = <0>; - clock-output-names = "pcie4_pipe_clk"; - - #phy-cells = <0>; - - status = "disabled"; - }; - - pcie5: pci@1b40000 { - device_type = "pci"; - compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; - reg = <0x0 0x01b40000 0x0 0x3000>, - <0x0 0x7a000000 0x0 0xf20>, - <0x0 0x7a000f40 0x0 0xa8>, - <0x0 0x7a001000 0x0 0x4000>, - <0x0 0x7a100000 0x0 0x100000>, - <0x0 0x01b43000 0x0 0x1000>; - reg-names = "parf", - "dbi", - "elbi", - "atu", - "config", - "mhi"; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0x7a200000 0x0 0x100000>, - <0x02000000 0x0 0x7a300000 0x0 0x7a300000 0x0 0x3d00000>, - <0x03000000 0x7 0xa0000000 0x7 0xa0000000 0x0 0x40000000>; - bus-range = <0x00 0xff>; - - dma-coherent; - - linux,pci-domain = <5>; - num-lanes = <4>; - - operating-points-v2 = <&pcie5_opp_table>; - - msi-map = <0x0 &gic_its 0xd0000 0x10000>; - iommu-map = <0x0 &pcie_smmu 0x50000 0x10000>; - - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "msi0", - "msi1", - "msi2", - "msi3", - "msi4", - "msi5", - "msi6", - "msi7", - "global"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 526 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 428 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 429 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc GCC_PCIE_5_AUX_CLK>, - <&gcc GCC_PCIE_5_CFG_AHB_CLK>, - <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_5_SLV_AXI_CLK>, - <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; - clock-names = "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "noc_aggr"; - - assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; - assigned-clock-rates = <19200000>; - - interconnects = <&pcie_east_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &pcie_east_slv_noc SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "pcie-mem", - "cpu-pcie"; - - resets = <&gcc GCC_PCIE_5_BCR>, - <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; - reset-names = "pci", - "link_down"; - - power-domains = <&gcc GCC_PCIE_5_GDSC>; - - eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; - eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; - eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; - - status = "disabled"; - - pcie5_opp_table: opp-table { - compatible = "operating-points-v2"; - - /* GEN 1 x1 */ - opp-2500000-1 { - opp-hz = /bits/ 64 <2500000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <250000 1>; - opp-level = <1>; - }; - - /* GEN 1 x2 */ - opp-5000000-1 { - opp-hz = /bits/ 64 <5000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <500000 1>; - opp-level = <1>; - }; - - /* GEN 1 x4 */ - opp-10000000-1 { - opp-hz = /bits/ 64 <10000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <1000000 1>; - opp-level = <1>; - }; - - /* GEN 2 x1 */ - opp-5000000-2 { - opp-hz = /bits/ 64 <5000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <500000 1>; - opp-level = <2>; - }; - - /* GEN 2 x2 */ - opp-10000000-2 { - opp-hz = /bits/ 64 <10000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <1000000 1>; - opp-level = <2>; - }; - - /* GEN 2 x4 */ - opp-20000000-2 { - opp-hz = /bits/ 64 <20000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <2000000 1>; - opp-level = <2>; - }; - - /* GEN 3 x1 */ - opp-8000000-3 { - opp-hz = /bits/ 64 <8000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <984500 1>; - opp-level = <3>; - }; - - /* GEN 3 x2 */ - opp-16000000-3 { - opp-hz = /bits/ 64 <16000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <1969000 1>; - opp-level = <3>; - }; - - /* GEN 3 x4 */ - opp-32000000-3 { - opp-hz = /bits/ 64 <32000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <3938000 1>; - opp-level = <3>; - }; - - /* GEN 4 x1 */ - opp-16000000-4 { - opp-hz = /bits/ 64 <16000000>; - required-opps = <&rpmhpd_opp_svs>; - opp-peak-kBps = <1969000 1>; - opp-level = <4>; - }; - - /* GEN 4 x2 */ - opp-32000000-4 { - opp-hz = /bits/ 64 <32000000>; - required-opps = <&rpmhpd_opp_svs>; - opp-peak-kBps = <3938000 1>; - opp-level = <4>; - }; - - /* GEN 4 x4 */ - opp-64000000-4 { - opp-hz = /bits/ 64 <64000000>; - required-opps = <&rpmhpd_opp_svs>; - opp-peak-kBps = <7876000 1>; - opp-level = <4>; - }; - - /* GEN 5 x1 */ - opp-32000000-5 { - opp-hz = /bits/ 64 <32000000>; - required-opps = <&rpmhpd_opp_nom>; - opp-peak-kBps = <3938000 1>; - opp-level = <5>; - }; - - /* GEN 5 x2 */ - opp-64000000-5 { - opp-hz = /bits/ 64 <64000000>; - required-opps = <&rpmhpd_opp_nom>; - opp-peak-kBps = <7876000 1>; - opp-level = <5>; - }; - - /* GEN 5 x4 */ - opp-128000000-5 { - opp-hz = /bits/ 64 <128000000>; - required-opps = <&rpmhpd_opp_nom>; - opp-peak-kBps = <15753000 1>; - opp-level = <5>; - }; - }; - - pcie5_port0: pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - bus-range = <0x01 0xff>; - - phys = <&pcie5_phy>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - }; - }; - - pcie5_phy: phy@1b50000 { - compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; - reg = <0x0 0x01b50000 0x0 0x10000>; - - clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>, - <&gcc GCC_PCIE_5_CFG_AHB_CLK>, - <&tcsr TCSR_PCIE_1_CLKREF_EN>, - <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_5_PIPE_CLK>, - <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; - clock-names = "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe", - "pipediv2"; - - resets = <&gcc GCC_PCIE_5_PHY_BCR>, - <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; - reset-names = "phy", - "phy_nocsr"; - - assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; - - #clock-cells = <0>; - clock-output-names = "pcie5_pipe_clk"; - - #phy-cells = <0>; - - status = "disabled"; - }; - - pcie6: pci@1c00000 { - device_type = "pci"; - compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; - reg = <0x0 0x01c00000 0x0 0x3000>, - <0x0 0x7e000000 0x0 0xf20>, - <0x0 0x7e000f40 0x0 0xa8>, - <0x0 0x7e001000 0x0 0x4000>, - <0x0 0x7e100000 0x0 0x100000>, - <0x0 0x01c03000 0x0 0x1000>; - reg-names = "parf", - "dbi", - "elbi", - "atu", - "config", - "mhi"; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, - <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>, - <0x03000000 0x7 0xe0000000 0x7 0xe0000000 0x0 0x20000000>; - bus-range = <0x00 0xff>; - - dma-coherent; - - linux,pci-domain = <6>; - num-lanes = <2>; - - operating-points-v2 = <&pcie6_opp_table>; - - msi-map = <0x0 &gic_its 0xe0000 0x10000>; - iommu-map = <0x0 &pcie_smmu 0x60000 0x10000>; - - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "msi0", - "msi1", - "msi2", - "msi3", - "msi4", - "msi5", - "msi6", - "msi7", - "global"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 472 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 473 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 474 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 475 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc GCC_PCIE_6_AUX_CLK>, - <&gcc GCC_PCIE_6_CFG_AHB_CLK>, - <&gcc GCC_PCIE_6_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_6_SLV_AXI_CLK>, - <&gcc GCC_PCIE_6_SLV_Q2A_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; - clock-names = "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "noc_aggr"; - - assigned-clocks = <&gcc GCC_PCIE_6_AUX_CLK>; - assigned-clock-rates = <19200000>; - - interconnects = <&pcie_west_anoc MASTER_PCIE_6 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &pcie_west_slv_noc SLAVE_PCIE_6 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "pcie-mem", - "cpu-pcie"; - - resets = <&gcc GCC_PCIE_6_BCR>, - <&gcc GCC_PCIE_6_LINK_DOWN_BCR>; - reset-names = "pci", - "link_down"; - - power-domains = <&gcc GCC_PCIE_6_GDSC>; - - eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; - eq-presets-16gts = /bits/ 8 <0x55 0x55>; - - status = "disabled"; - - pcie6_opp_table: opp-table { - compatible = "operating-points-v2"; - - /* GEN 1 x1 */ - opp-2500000-1 { - opp-hz = /bits/ 64 <2500000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <250000 1>; - opp-level = <1>; - }; - - /* GEN 1 x2 */ - opp-5000000-1 { - opp-hz = /bits/ 64 <5000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <500000 1>; - opp-level = <1>; - }; - - /* GEN 2 x1 */ - opp-5000000-2 { - opp-hz = /bits/ 64 <5000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <500000 1>; - opp-level = <2>; - }; - - /* GEN 2 x2 */ - opp-10000000-2 { - opp-hz = /bits/ 64 <10000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <1000000 1>; - opp-level = <2>; - }; - - /* GEN 3 x1 */ - opp-8000000-3 { - opp-hz = /bits/ 64 <8000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <984500 1>; - opp-level = <3>; - }; - - /* GEN 3 x2 */ - opp-16000000-3 { - opp-hz = /bits/ 64 <16000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <1969000 1>; - opp-level = <3>; - }; - - /* GEN 4 x1 */ - opp-16000000-4 { - opp-hz = /bits/ 64 <16000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <1969000 1>; - opp-level = <4>; - }; - - /* GEN 4 x2 */ - opp-32000000-4 { - opp-hz = /bits/ 64 <32000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <3938000 1>; - opp-level = <4>; - }; - - }; - - pcie6_port0: pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - bus-range = <0x01 0xff>; - - phys = <&pcie6_phy>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - }; - }; - - pcie6_phy: phy@1c06000 { - compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; - reg = <0x0 0x01c06000 0x0 0x2000>; - - clocks = <&gcc GCC_PCIE_PHY_6_AUX_CLK>, - <&gcc GCC_PCIE_6_CFG_AHB_CLK>, - <&tcsr TCSR_PCIE_4_CLKREF_EN>, - <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_6_PIPE_CLK>, - <&gcc GCC_PCIE_6_PIPE_DIV2_CLK>; - clock-names = "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe", - "pipediv2"; - - resets = <&gcc GCC_PCIE_6_PHY_BCR>, - <&gcc GCC_PCIE_6_NOCSR_COM_PHY_BCR>; - reset-names = "phy", - "phy_nocsr"; - - assigned-clocks = <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; - - #clock-cells = <0>; - clock-output-names = "pcie6_pipe_clk"; - - #phy-cells = <0>; - - status = "disabled"; - }; - - pcie3b: pci@1b80000 { - device_type = "pci"; - compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; - reg = <0x0 0x01b80000 0x0 0x3000>, - <0x0 0x74000000 0x0 0xf20>, - <0x0 0x74000f40 0x0 0xa8>, - <0x0 0x74001000 0x0 0x4000>, - <0x0 0x74100000 0x0 0x100000>, - <0x0 0x01b83000 0x0 0x1000>; - reg-names = "parf", - "dbi", - "elbi", - "atu", - "config", - "mhi"; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0x74200000 0x0 0x100000>, - <0x02000000 0x0 0x74300000 0x0 0x74300000 0x0 0x3d00000>, - <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; - bus-range = <0x00 0xff>; - - dma-coherent; - - linux,pci-domain = <7>; - num-lanes = <4>; - - operating-points-v2 = <&pcie3b_opp_table>; - - msi-map = <0x0 &gic_its 0xf0000 0x10000>; - iommu-map = <0x0 &pcie_smmu 0x70000 0x10000>; - - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "msi0", - "msi1", - "msi2", - "msi3", - "msi4", - "msi5", - "msi6", - "msi7", - "global"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 831 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 832 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 833 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 834 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, - <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, - <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, - <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>; - clock-names = "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "noc_aggr"; - - assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; - assigned-clock-rates = <19200000>; - - interconnects = <&pcie_west_anoc MASTER_PCIE_3B QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &pcie_west_slv_noc SLAVE_PCIE_3B QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "pcie-mem", - "cpu-pcie"; - - resets = <&gcc GCC_PCIE_3B_BCR>, - <&gcc GCC_PCIE_3B_LINK_DOWN_BCR>; - reset-names = "pci", - "link_down"; - - power-domains = <&gcc GCC_PCIE_3B_GDSC>; - - eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; - eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; - eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; - - status = "disabled"; - - pcie3b_opp_table: opp-table { - compatible = "operating-points-v2"; - - /* GEN 1 x1 */ - opp-2500000-1 { - opp-hz = /bits/ 64 <2500000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <250000 1>; - opp-level = <1>; - }; - - /* GEN 1 x2 */ - opp-5000000-1 { - opp-hz = /bits/ 64 <5000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <500000 1>; - opp-level = <1>; - }; - - /* GEN 1 x4 */ - opp-10000000-1 { - opp-hz = /bits/ 64 <10000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <1000000 1>; - opp-level = <1>; - }; - - /* GEN 2 x1 */ - opp-5000000-2 { - opp-hz = /bits/ 64 <5000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <500000 1>; - opp-level = <2>; - }; - - /* GEN 2 x2 */ - opp-10000000-2 { - opp-hz = /bits/ 64 <10000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <1000000 1>; - opp-level = <2>; - }; - - /* GEN 2 x4 */ - opp-20000000-2 { - opp-hz = /bits/ 64 <20000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <2000000 1>; - opp-level = <2>; - }; - - /* GEN 3 x1 */ - opp-8000000-3 { - opp-hz = /bits/ 64 <8000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <984500 1>; - opp-level = <3>; - }; - - /* GEN 3 x2 */ - opp-16000000-3 { - opp-hz = /bits/ 64 <16000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <1969000 1>; - opp-level = <3>; - }; - - /* GEN 3 x4 */ - opp-32000000-3 { - opp-hz = /bits/ 64 <32000000>; - required-opps = <&rpmhpd_opp_low_svs>; - opp-peak-kBps = <3938000 1>; - opp-level = <3>; - }; - - /* GEN 4 x1 */ - opp-16000000-4 { - opp-hz = /bits/ 64 <16000000>; - required-opps = <&rpmhpd_opp_svs>; - opp-peak-kBps = <1969000 1>; - opp-level = <4>; - }; - - /* GEN 4 x2 */ - opp-32000000-4 { - opp-hz = /bits/ 64 <32000000>; - required-opps = <&rpmhpd_opp_svs>; - opp-peak-kBps = <3938000 1>; - opp-level = <4>; - }; - - /* GEN 4 x4 */ - opp-64000000-4 { - opp-hz = /bits/ 64 <64000000>; - required-opps = <&rpmhpd_opp_svs>; - opp-peak-kBps = <7876000 1>; - opp-level = <4>; - }; - - /* GEN 5 x1 */ - opp-32000000-5 { - opp-hz = /bits/ 64 <32000000>; - required-opps = <&rpmhpd_opp_nom>; - opp-peak-kBps = <3938000 1>; - opp-level = <5>; - }; - - /* GEN 5 x2 */ - opp-64000000-5 { - opp-hz = /bits/ 64 <64000000>; - required-opps = <&rpmhpd_opp_nom>; - opp-peak-kBps = <7876000 1>; - opp-level = <5>; - }; - - /* GEN 5 x4 */ - opp-128000000-5 { - opp-hz = /bits/ 64 <128000000>; - required-opps = <&rpmhpd_opp_nom>; - opp-peak-kBps = <15753000 1>; - opp-level = <5>; - }; - }; - - pcie3b_port0: pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - bus-range = <0x01 0xff>; - - phys = <&pcie3b_phy>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - }; - }; - - pcie3b_phy: phy@f10000 { - compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; - reg = <0x0 0x00f10000 0x0 0x10000>; - - clocks = <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, - <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, - <&tcsr TCSR_PCIE_3_CLKREF_EN>, - <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_3B_PIPE_CLK>, - <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; - clock-names = "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe", - "pipediv2"; - - resets = <&gcc GCC_PCIE_3B_PHY_BCR>, - <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; - reset-names = "phy", - "phy_nocsr"; - - assigned-clocks = <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - power-domains = <&gcc GCC_PCIE_3B_PHY_GDSC>; - - #clock-cells = <0>; - clock-output-names = "pcie3b_pipe_clk"; - - #phy-cells = <0>; - - status = "disabled"; - }; - - tcsr_mutex: hwlock@1f40000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x0 0x01f40000 0x0 0x20000>; - - #hwlock-cells = <1>; - }; - - tcsr: clock-controller@1fd5000 { - compatible = "qcom,glymur-tcsr", - "syscon"; - reg = <0x0 0x1fd5000 0x0 0x21000>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - hsc_noc: interconnect@2000000 { - compatible = "qcom,glymur-hscnoc"; - reg = <0x0 0x02000000 0x0 0x93a080>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - - ipcc: mailbox@3e04000 { - compatible = "qcom,glymur-ipcc", "qcom,ipcc"; - reg = <0x0 0x03e04000 0x0 0x1000>; - - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - - #mbox-cells = <2>; - }; - - remoteproc_adsp: remoteproc@6800000 { - compatible = "qcom,glymur-adsp-pas", "qcom,sm8550-adsp-pas"; - reg = <0x0 0x06800000 0x0 0x10000>; - - iommus = <&apps_smmu 0x1000 0x0>; - - interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", - "fatal", - "ready", - "handover", - "stop-ack", - "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - - power-domains = <&rpmhpd RPMHPD_LCX>, - <&rpmhpd RPMHPD_LMX>; - power-domain-names = "lcx", - "lmx"; - - memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_adsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - remoteproc_adsp_glink: glink-edge { - interrupts-extended = <&ipcc IPCC_MPROC_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - - mboxes = <&ipcc IPCC_MPROC_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - qcom,remote-pid = <2>; - - label = "lpass"; - - fastrpc { - compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - - iommus = <&apps_smmu 0x1003 0x80>, - <&apps_smmu 0x1043 0x20>; - dma-coherent; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - - iommus = <&apps_smmu 0x1004 0x80>, - <&apps_smmu 0x1044 0x20>; - dma-coherent; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - - iommus = <&apps_smmu 0x1005 0x80>, - <&apps_smmu 0x1045 0x20>; - dma-coherent; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - - iommus = <&apps_smmu 0x1006 0x80>, - <&apps_smmu 0x1046 0x20>; - dma-coherent; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - - iommus = <&apps_smmu 0x1007 0x40>, - <&apps_smmu 0x1067 0x0>, - <&apps_smmu 0x1087 0x0>; - dma-coherent; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - - iommus = <&apps_smmu 0x1008 0x80>, - <&apps_smmu 0x1048 0x20>; - dma-coherent; - }; - }; - }; - }; - - lpass_lpiaon_noc: interconnect@7400000 { - compatible = "qcom,glymur-lpass-lpiaon-noc"; - reg = <0x0 0x07400000 0x0 0x19080>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - - lpass_lpicx_noc: interconnect@7420000 { - compatible = "qcom,glymur-lpass-lpicx-noc"; - reg = <0x0 0x07420000 0x0 0x44080>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - - lpass_ag_noc: interconnect@7e40000 { - compatible = "qcom,glymur-lpass-ag-noc"; - reg = <0x0 0x07e40000 0x0 0xe080>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - - usb1_ss2_hsphy: phy@88e0000 { - compatible = "qcom,glymur-m31-eusb2-phy", - "qcom,sm8750-m31-eusb2-phy"; - - reg = <0 0x088e0000 0 0x29c>; - #phy-cells = <0>; - - clocks = <&tcsr TCSR_USB2_4_CLKREF_EN>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; - - status = "disabled"; - }; - - usb1_ss2_qmpphy: phy@88e1000 { - compatible = "qcom,glymur-qmp-usb3-dp-phy"; - reg = <0 0x088e1000 0 0x8000>; - - clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>, - <&tcsr TCSR_USB4_2_CLKREF_EN>; - clock-names = "aux", - "ref", - "com_aux", - "usb3_pipe", - "clkref"; - - power-domains = <&gcc GCC_USB_2_PHY_GDSC>; - - resets = <&gcc GCC_USB3_PHY_TERT_BCR>, - <&gcc GCC_USB3PHY_PHY_TERT_BCR>; - reset-names = "phy", - "common"; - - #clock-cells = <1>; - #phy-cells = <1>; - - mode-switch; - orientation-switch; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb1_ss2_qmpphy_out: endpoint { - }; - }; - - port@1 { - reg = <1>; - - usb1_ss2_qmpphy_usb_ss_in: endpoint { - remote-endpoint = <&usb1_ss2_dwc3_ss>; - }; - }; - - port@2 { - reg = <2>; - - usb1_ss2_qmpphy_dp_in: endpoint { - }; - }; - }; - }; - - usb1_ss0: usb@a600000 { - compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; - reg = <0 0x0a600000 0 0xfc100>; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, - <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; - clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi", - "noc_aggr_north", - "noc_aggr_south"; - - interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 90 IRQ_TYPE_EDGE_BOTH>, - <&pdc 60 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "dwc_usb3", - "pwr_event", - "dp_hs_phy_irq", - "dm_hs_phy_irq", - "ss_phy_irq"; - - power-domains = <&gcc GCC_USB30_PRIM_GDSC>; - resets = <&gcc GCC_USB30_PRIM_BCR>; - - iommus = <&apps_smmu 0x1420 0x0>; - phys = <&usb1_ss0_hsphy>, - <&usb1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names = "usb2-phy", - "usb3-phy"; - - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,dis_u3_susphy_quirk; - snps,usb2-lpm-disable; - - usb-role-switch; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb1_ss0_dwc3_hs: endpoint { - }; - }; - - port@1 { - reg = <1>; - - usb1_ss0_dwc3_ss: endpoint { - remote-endpoint = <&usb1_ss0_qmpphy_usb_ss_in>; - }; - }; - }; - }; - - usb1_ss1: usb@a800000 { - compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; - reg = <0 0x0a800000 0 0xfc100>; - - clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_SLEEP_CLK>, - <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, - <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; - clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi", - "noc_aggr_north", - "noc_aggr_south"; - - interrupts-extended = <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 88 IRQ_TYPE_EDGE_BOTH>, - <&pdc 87 IRQ_TYPE_EDGE_BOTH>, - <&pdc 76 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "dwc_usb3", - "pwr_event", - "dp_hs_phy_irq", - "dm_hs_phy_irq", - "ss_phy_irq"; - - resets = <&gcc GCC_USB30_SEC_BCR>; - power-domains = <&gcc GCC_USB30_SEC_GDSC>; - - iommus = <&apps_smmu 0x1460 0x0>; - - phys = <&usb1_ss1_hsphy>, - <&usb1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names = "usb2-phy", - "usb3-phy"; - - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,dis_u3_susphy_quirk; - snps,usb2-lpm-disable; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb1_ss1_dwc3_hs: endpoint { - }; - }; - - port@1 { - reg = <1>; - - usb1_ss1_dwc3_ss: endpoint { - remote-endpoint = <&usb1_ss1_qmpphy_usb_ss_in>; - }; - }; - }; - }; - - usb1_ss2: usb@a000000 { - compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; - reg = <0 0x0a000000 0 0xfc100>; - - clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, - <&gcc GCC_USB30_TERT_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, - <&gcc GCC_USB30_TERT_SLEEP_CLK>, - <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, - <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, - <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; - clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi", - "noc_aggr_north", - "noc_aggr_south"; - - interrupts-extended = <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 89 IRQ_TYPE_EDGE_BOTH>, - <&pdc 81 IRQ_TYPE_EDGE_BOTH>, - <&pdc 75 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "dwc_usb3", - "pwr_event", - "dp_hs_phy_irq", - "dm_hs_phy_irq", - "ss_phy_irq"; - - resets = <&gcc GCC_USB30_TERT_BCR>; - power-domains = <&gcc GCC_USB30_TERT_GDSC>; - - iommus = <&apps_smmu 0x420 0x0>; - - phys = <&usb1_ss2_hsphy>, - <&usb1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names = "usb2-phy", - "usb3-phy"; - - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,dis_u3_susphy_quirk; - snps,usb2-lpm-disable; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb1_ss2_dwc3_hs: endpoint { - }; - }; - - port@1 { - reg = <1>; - - usb1_ss2_dwc3_ss: endpoint { - remote-endpoint = <&usb1_ss2_qmpphy_usb_ss_in>; - }; - }; - }; - }; - - usb_2: usb@a2f8800 { - compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; - reg = <0 0x0a200000 0 0xfc100>; - - clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, - <&gcc GCC_USB20_MASTER_CLK>, - <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, - <&gcc GCC_USB20_SLEEP_CLK>, - <&gcc GCC_USB20_MOCK_UTMI_CLK>, - <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, - <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; - clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi", - "noc_aggr_north", - "noc_aggr_south"; - - assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, - <&gcc GCC_USB20_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 92 IRQ_TYPE_EDGE_BOTH>, - <&pdc 57 IRQ_TYPE_EDGE_BOTH>, - <&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "dwc_usb3", - "pwr_event", - "dp_hs_phy_irq", - "dm_hs_phy_irq", - "hs_phy_irq"; - - resets = <&gcc GCC_USB20_PRIM_BCR>; - - power-domains = <&gcc GCC_USB20_PRIM_GDSC>; - required-opps = <&rpmhpd_opp_nom>; - - iommus = <&apps_smmu 0x0ce0 0x0>; - - interconnects = <&aggre3_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "usb-ddr", - "apps-usb"; - - phys = <&usb_2_hsphy>; - phy-names = "usb2-phy"; - - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,dis_enblslpm_quirk; - - dr_mode = "host"; - - maximum-speed = "high-speed"; - - status = "disabled"; - }; - - usb_mp: usb@a400000 { - compatible = "qcom,glymur-dwc3-mp", "qcom,snps-dwc3"; - reg = <0 0x0a400000 0 0xfc100>; - - clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, - <&gcc GCC_USB30_MP_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, - <&gcc GCC_USB30_MP_SLEEP_CLK>, - <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, - <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, - <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; - clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi", - "noc_aggr_north", - "noc_aggr_south"; - - interrupts-extended = <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 12 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 11 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 13 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 78 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 77 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "dwc_usb3", - "pwr_event_1", - "pwr_event_2", - "hs_phy_1", - "hs_phy_2", - "dp_hs_phy_1", - "dm_hs_phy_1", - "dp_hs_phy_2", - "dm_hs_phy_2", - "ss_phy_1", - "ss_phy_2"; - - resets = <&gcc GCC_USB30_MP_BCR>; - power-domains = <&gcc GCC_USB30_MP_GDSC>; - - iommus = <&apps_smmu 0xda0 0x0>; - - phys = <&usb_mp_hsphy0>, - <&usb_mp_qmpphy0>, - <&usb_mp_hsphy1>, - <&usb_mp_qmpphy1>; - phy-names = "usb2-0", - "usb3-0", - "usb2-1", - "usb3-1"; - - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,usb3_lpm_capable; - snps,dis_u3_susphy_quirk; - snps,usb2-lpm-disable; - - dr_mode = "host"; - - status = "disabled"; - }; - - - dispcc: clock-controller@af00000 { - compatible = "qcom,glymur-dispcc"; - reg = <0x0 0x0af00000 0x0 0x20000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>, - <0>, /* dp0 */ - <0>, - <0>, /* dp1 */ - <0>, - <0>, /* dp2 */ - <0>, - <0>, /* dp3 */ - <0>, - <0>, /* dsi0 */ - <0>, - <0>, /* dsi1 */ - <0>, - <0>, - <0>, - <0>, - <0>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - pdc: interrupt-controller@b220000 { - compatible = "qcom,glymur-pdc", "qcom,pdc"; - reg = <0x0 0x0b220000 0x0 0x10000>; - qcom,pdc-ranges = <0 745 51>, - <51 527 47>, - <98 609 32>, - <130 717 12>, - <142 251 5>, - <147 796 16>, - <171 4104 36>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - tsens0: thermal-sensor@c22c000 { - compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; - reg = <0x0 0x0c22c000 0x0 0x1000>, - <0x0 0x0c222000 0x0 0x1000>; - - interrupts = , - ; - interrupt-names = "uplow", - "critical"; - - #qcom,sensors = <13>; - - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c22d000 { - compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; - reg = <0x0 0x0c22d000 0x0 0x1000>, - <0x0 0x0c223000 0x0 0x1000>; - - interrupts = , - ; - interrupt-names = "uplow", - "critical"; - - #qcom,sensors = <9>; - - #thermal-sensor-cells = <1>; - }; - - tsens2: thermal-sensor@c22e000 { - compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; - reg = <0x0 0x0c22e000 0x0 0x1000>, - <0x0 0x0c224000 0x0 0x1000>; - - interrupts = , - ; - interrupt-names = "uplow", - "critical"; - - #qcom,sensors = <13>; - - #thermal-sensor-cells = <1>; - }; - - tsens3: thermal-sensor@c22f000 { - compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; - reg = <0x0 0x0c22f000 0x0 0x1000>, - <0x0 0x0c225000 0x0 0x1000>; - - interrupts = , - ; - interrupt-names = "uplow", - "critical"; - - #qcom,sensors = <8>; - - #thermal-sensor-cells = <1>; - }; - - tsens4: thermal-sensor@c230000 { - compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; - reg = <0x0 0x0c230000 0x0 0x1000>, - <0x0 0x0c226000 0x0 0x1000>; - - interrupts = , - ; - interrupt-names = "uplow", - "critical"; - - #qcom,sensors = <13>; - - #thermal-sensor-cells = <1>; - }; - - tsens5: thermal-sensor@c231000 { - compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; - reg = <0x0 0x0c231000 0x0 0x1000>, - <0x0 0x0c227000 0x0 0x1000>; - - interrupts = , - ; - interrupt-names = "uplow", - "critical"; - - #qcom,sensors = <8>; - - #thermal-sensor-cells = <1>; - }; - - tsens6: thermal-sensor@c232000 { - compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; - reg = <0x0 0x0c232000 0x0 0x1000>, - <0x0 0x0c228000 0x0 0x1000>; - - interrupts = , - ; - interrupt-names = "uplow", - "critical"; - - #qcom,sensors = <13>; - - #thermal-sensor-cells = <1>; - }; - - tsens7: thermal-sensor@c233000 { - compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; - reg = <0x0 0x0c233000 0x0 0x1000>, - <0x0 0x0c229000 0x0 0x1000>; - - interrupts = , - ; - interrupt-names = "uplow", - "critical"; - - #qcom,sensors = <15>; - - #thermal-sensor-cells = <1>; - }; - - aoss_qmp: power-management@c300000 { - compatible = "qcom,glymur-aoss-qmp", "qcom,aoss-qmp"; - reg = <0x0 0x0c300000 0x0 0x400>; - interrupt-parent = <&ipcc>; - interrupts-extended = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; - - #clock-cells = <0>; - }; - - sram@c30f000 { - compatible = "qcom,rpmh-stats"; - reg = <0x0 0x0c30f000 0x0 0x400>; - }; - - arbiter@c400000 { - compatible = "qcom,glymur-spmi-pmic-arb"; - reg = <0x0 0x0c400000 0x0 0x3000>, - <0x0 0x0c900000 0x0 0x400000>, - <0x0 0x0c4c0000 0x0 0x400000>, - <0x0 0x0c403000 0x0 0x8000>; - reg-names = "core", - "chnls", - "obsrvr", - "chnl_map"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - qcom,channel = <0>; - qcom,ee = <0>; - - spmi_bus0: spmi@c426000 { - reg = <0x0 0x0c426000 0x0 0x4000>, - <0x0 0x0c8c0000 0x0 0x10000>, - <0x0 0x0c42a000 0x0 0x8000>; - reg-names = "cnfg", - "intr", - "chnl_owner"; - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "periph_irq"; - interrupt-controller; - #interrupt-cells = <4>; - #address-cells = <2>; - #size-cells = <0>; - }; - - spmi_bus1: spmi@c437000 { - reg = <0x0 0x0c437000 0x0 0x4000>, - <0x0 0x0c8d0000 0x0 0x10000>, - <0x0 0x0c43b000 0x0 0x8000>; - reg-names = "cnfg", - "intr", - "chnl_owner"; - interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "periph_irq"; - interrupt-controller; - #interrupt-cells = <4>; - #address-cells = <2>; - #size-cells = <0>; - }; - - spmi_bus2: spmi@c48000 { - reg = <0x0 0x0c448000 0x0 0x4000>, - <0x0 0x0c8e0000 0x0 0x10000>, - <0x0 0x0c44c000 0x0 0x8000>; - reg-names = "cnfg", - "intr", - "chnl_owner"; - interrupts-extended = <&pdc 72 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "periph_irq"; - interrupt-controller; - #interrupt-cells = <4>; - #address-cells = <2>; - #size-cells = <0>; - }; - }; - - tlmm: pinctrl@f100000 { - compatible = "qcom,glymur-tlmm"; - reg = <0x0 0x0f100000 0x0 0xf00000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 249>; - wakeup-parent = <&pdc>; - - qup_i2c0_data_clk: qup-i2c0-data-clk-state { - /* SDA, SCL */ - pins = "gpio0", "gpio1"; - function = "qup0_se0"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c1_data_clk: qup-i2c1-data-clk-state { - /* SDA, SCL */ - pins = "gpio4", "gpio5"; - function = "qup0_se1"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c2_data_clk: qup-i2c2-data-clk-state { - /* SDA, SCL */ - pins = "gpio8", "gpio9"; - function = "qup0_se2"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c3_data_clk: qup-i2c3-data-clk-state { - /* SDA, SCL */ - pins = "gpio12", "gpio13"; - function = "qup0_se3"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c4_data_clk: qup-i2c4-data-clk-state { - /* SDA, SCL */ - pins = "gpio16", "gpio17"; - function = "qup0_se4"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c5_data_clk: qup-i2c5-data-clk-state { - /* SDA, SCL */ - pins = "gpio20", "gpio21"; - function = "qup0_se5"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c6_data_clk: qup-i2c6-data-clk-state { - /* SDA, SCL */ - pins = "gpio6", "gpio7"; - function = "qup0_se6"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c7_data_clk: qup-i2c7-data-clk-state { - /* SDA, SCL */ - pins = "gpio14", "gpio15"; - function = "qup0_se7"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c8_data_clk: qup-i2c8-data-clk-state { - /* SDA, SCL */ - pins = "gpio32", "gpio33"; - function = "qup1_se0"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c9_data_clk: qup-i2c9-data-clk-state { - /* SDA, SCL */ - pins = "gpio36", "gpio37"; - function = "qup1_se1"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c10_data_clk: qup-i2c10-data-clk-state { - /* SDA, SCL */ - pins = "gpio40", "gpio41"; - function = "qup1_se2"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c11_data_clk: qup-i2c11-data-clk-state { - /* SDA, SCL */ - pins = "gpio44", "gpio45"; - function = "qup1_se3"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c12_data_clk: qup-i2c12-data-clk-state { - /* SDA, SCL */ - pins = "gpio48", "gpio49"; - function = "qup1_se4"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c13_data_clk: qup-i2c13-data-clk-state { - /* SDA, SCL */ - pins = "gpio52", "gpio53"; - function = "qup1_se5"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c14_data_clk: qup-i2c14-data-clk-state { - /* SDA, SCL */ - pins = "gpio56", "gpio57"; - function = "qup1_se6"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c15_data_clk: qup-i2c15-data-clk-state { - /* SDA, SCL */ - pins = "gpio54", "gpio55"; - function = "qup1_se7"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c16_data_clk: qup-i2c16-data-clk-state { - /* SDA, SCL */ - pins = "gpio64", "gpio65"; - function = "qup2_se0"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c17_data_clk: qup-i2c17-data-clk-state { - /* SDA, SCL */ - pins = "gpio68", "gpio69"; - function = "qup2_se1"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c18_data_clk: qup-i2c18-data-clk-state { - /* SDA, SCL */ - pins = "gpio72", "gpio73"; - function = "qup2_se2"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c19_data_clk: qup-i2c19-data-clk-state { - /* SDA, SCL */ - pins = "gpio76", "gpio77"; - function = "qup2_se3"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c20_data_clk: qup-i2c20-data-clk-state { - /* SDA, SCL */ - pins = "gpio80", "gpio81"; - function = "qup2_se4"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c21_data_clk: qup-i2c21-data-clk-state { - /* SDA, SCL */ - pins = "gpio84", "gpio85"; - function = "qup2_se5"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c22_data_clk: qup-i2c22-data-clk-state { - /* SDA, SCL */ - pins = "gpio88", "gpio89"; - function = "qup2_se6"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_i2c23_data_clk: qup-i2c23-data-clk-state { - /* SDA, SCL */ - pins = "gpio80", "gpio81"; - function = "qup2_se7"; - drive-strength = <2>; - bias-pull-up = <2200>; - }; - - qup_spi0_cs: qup-spi0-cs-state { - pins = "gpio3"; - function = "qup0_se0"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi0_data_clk: qup-spi0-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio0", "gpio1", "gpio2"; - function = "qup0_se0"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi1_cs: qup-spi1-cs-state { - pins = "gpio7"; - function = "qup0_se1"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi1_data_clk: qup-spi1-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio4", "gpio5", "gpio6"; - function = "qup0_se1"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi2_cs: qup-spi2-cs-state { - pins = "gpio11"; - function = "qup0_se2"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi2_data_clk: qup-spi2-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio8", "gpio9", "gpio10"; - function = "qup0_se2"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi3_cs: qup-spi3-cs-state { - pins = "gpio15"; - function = "qup0_se3"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi3_data_clk: qup-spi3-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio12", "gpio13", "gpio14"; - function = "qup0_se3"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi4_cs: qup-spi4-cs-state { - pins = "gpio19"; - function = "qup0_se4"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi4_data_clk: qup-spi4-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio16", "gpio17", "gpio18"; - function = "qup0_se4"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi5_cs: qup-spi5-cs-state { - pins = "gpio23"; - function = "qup0_se5"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi5_data_clk: qup-spi5-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio20", "gpio21", "gpio22"; - function = "qup0_se5"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi6_cs: qup-spi6-cs-state { - pins = "gpio5"; - function = "qup0_se6"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi6_data_clk: qup-spi6-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio6", "gpio7", "gpio4"; - function = "qup0_se6"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi7_cs: qup-spi7-cs-state { - pins = "gpio13"; - function = "qup0_se7"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi7_data_clk: qup-spi7-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio14", "gpio15", "gpio12"; - function = "qup0_se7"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi8_cs: qup-spi8-cs-state { - pins = "gpio35"; - function = "qup1_se0"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi8_data_clk: qup-spi8-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio32", "gpio33", "gpio34"; - function = "qup1_se0"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi9_cs: qup-spi9-cs-state { - pins = "gpio39"; - function = "qup1_se1"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi9_data_clk: qup-spi9-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio36", "gpio37", "gpio38"; - function = "qup1_se1"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi10_cs: qup-spi10-cs-state { - pins = "gpio43"; - function = "qup1_se2"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi10_data_clk: qup-spi10-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio40", "gpio41", "gpio42"; - function = "qup1_se2"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi11_cs: qup-spi11-cs-state { - pins = "gpio47"; - function = "qup1_se3"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi11_data_clk: qup-spi11-data-clk-state { - pins = "gpio44", "gpio45", "gpio46"; - function = "qup1_se3"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi12_cs: qup-spi12-cs-state { - pins = "gpio51"; - function = "qup1_se4"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi12_data_clk: qup-spi12-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio48", "gpio49", "gpio50"; - function = "qup1_se4"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi13_cs: qup-spi13-cs-state { - pins = "gpio55"; - function = "qup1_se5"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi13_data_clk: qup-spi13-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio52", "gpio53", "gpio54"; - function = "qup1_se5"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi14_cs: qup-spi14-cs-state { - pins = "gpio59"; - function = "qup1_se6"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi14_data_clk: qup-spi14-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio56", "gpio57", "gpio58"; - function = "qup1_se6"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi15_cs: qup-spi15-cs-state { - pins = "gpio53"; - function = "qup1_se7"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi15_data_clk: qup-spi15-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio54", "gpio55", "gpio52"; - function = "qup1_se7"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi16_cs: qup-spi16-cs-state { - pins = "gpio67"; - function = "qup2_se0"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi16_data_clk: qup-spi16-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio64", "gpio65", "gpio66"; - function = "qup2_se0"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi17_cs: qup-spi17-cs-state { - pins = "gpio71"; - function = "qup2_se1"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi17_data_clk: qup-spi17-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio68", "gpio69", "gpio70"; - function = "qup2_se1"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi18_cs: qup-spi18-cs-state { - pins = "gpio75"; - function = "qup2_se2"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi18_data_clk: qup-spi18-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio72", "gpio73", "gpio74"; - function = "qup2_se2"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi19_cs: qup-spi19-cs-state { - pins = "gpio79"; - function = "qup2_se3"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi19_data_clk: qup-spi19-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio76", "gpio77", "gpio78"; - function = "qup2_se3"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi20_cs: qup-spi20-cs-state { - pins = "gpio83"; - function = "qup2_se4"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi20_data_clk: qup-spi20-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio80", "gpio81", "gpio82"; - function = "qup2_se4"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi21_cs: qup-spi21-cs-state { - pins = "gpio87"; - function = "qup2_se5"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi21_data_clk: qup-spi21-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio84", "gpio85", "gpio86"; - function = "qup2_se5"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi22_cs: qup-spi22-cs-state { - pins = "gpio91"; - function = "qup2_se6"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi22_data_clk: qup-spi22-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio88", "gpio89", "gpio90"; - function = "qup2_se6"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi23_cs: qup-spi23-cs-state { - pins = "gpio83"; - function = "qup2_se7"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi23_data_clk: qup-spi23-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio80", "gpio81", "gpio82"; - function = "qup2_se7"; - drive-strength = <6>; - bias-disable; - }; - - qup_uart2_default: qup-uart2-default-state { - tx-pins { - pins = "gpio10"; - function = "qup0_se2"; - drive-strength = <2>; - bias-disable; - }; - - rx-pins { - pins = "gpio11"; - function = "qup0_se2"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_uart14_default: qup-uart14-default-state { - cts-pins { - pins = "gpio56"; - function = "qup1_se6"; - drive-strength = <2>; - bias-disable; - }; - - rts-pins { - pins = "gpio57"; - function = "qup1_se6"; - drive-strength = <2>; - bias-disable; - }; - - tx-pins { - pins = "gpio58"; - function = "qup1_se6"; - drive-strength = <2>; - bias-disable; - }; - - rx-pins { - pins = "gpio59"; - function = "qup1_se6"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_uart19_default: qup-uart19-default-state { - cts-pins { - pins = "gpio76"; - function = "qup2_se3"; - drive-strength = <2>; - bias-disable; - }; - - rts-pins { - pins = "gpio77"; - function = "qup2_se3"; - drive-strength = <2>; - bias-disable; - }; - - tx-pins { - pins = "gpio78"; - function = "qup2_se3"; - drive-strength = <2>; - bias-disable; - }; - - rx-pins { - pins = "gpio79"; - function = "qup2_se3"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_uart21_default: qup-uart21-default-state { - tx-pins { - pins = "gpio86"; - function = "qup2_se5"; - drive-strength = <2>; - bias-disable; - }; - - rx-pins { - pins = "gpio87"; - function = "qup2_se5"; - drive-strength = <2>; - bias-disable; - }; - }; - - qup_uart22_default: qup-uart22-default-state { - tx-pins { - pins = "gpio90"; - function = "qup2_se6"; - drive-strength = <2>; - bias-disable; - }; - - rx-pins { - pins = "gpio91"; - function = "qup2_se6"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - - stm: stm@10002000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0x0 0x10002000 0x0 0x1000>, - <0x0 0x16280000 0x0 0x180000>; - reg-names = "stm-base", - "stm-stimulus-base"; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - stm_out: endpoint { - remote-endpoint = <&funnel0_in7>; - }; - }; - }; - }; - - tpda@10004000 { - compatible = "qcom,coresight-tpda", "arm,primecell"; - reg = <0x0 0x10004000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - qdss_tpda_in1: endpoint { - remote-endpoint = <&spdm_tpdm_out>; - }; - }; - }; - - out-ports { - port { - qdss_tpda_out: endpoint { - remote-endpoint = <&funnel0_in6>; - }; - }; - }; - }; - - tpdm@1000f000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1000f000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <32>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - spdm_tpdm_out: endpoint { - remote-endpoint = <&qdss_tpda_in1>; - }; - }; - }; - }; - - funnel@10041000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x0 0x10041000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - funnel0_in0: endpoint { - remote-endpoint = <&tn_ag_out>; - }; - }; - - port@6 { - reg = <6>; - - funnel0_in6: endpoint { - remote-endpoint = <&qdss_tpda_out>; - }; - }; - - port@7 { - reg = <7>; - - funnel0_in7: endpoint { - remote-endpoint = <&stm_out>; - }; - }; - }; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = <&aoss_funnel_in6>; - }; - }; - }; - }; - - tpdm@1102c000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1102c000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - gcc_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in36>; - }; - }; - }; - }; - - cti@11161000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0 0x11161000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - }; - - cti@11162000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0 0x11162000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - }; - - tpdm@11180000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11180000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-element-bits = <32>; - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - cdsp_tpdm_out: endpoint { - remote-endpoint = <&cdsp_tpda_in0>; - }; - }; - }; - }; - - tpdm@11183000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11183000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <32>; - qcom,cmb-msrs-num = <32>; - qcom,dsb-element-bits = <32>; - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - cdsp_cmsr_tpdm_out: endpoint { - remote-endpoint = <&cdsp_tpda_in3>; - }; - }; - }; - }; - - tpdm@11184000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11184000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <32>; - qcom,cmb-msrs-num = <32>; - qcom,dsb-element-bits = <32>; - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - cdsp_cmsr2_tpdm_out: endpoint { - remote-endpoint = <&cdsp_tpda_in4>; - }; - }; - }; - }; - - tpdm@11185000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11185000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <64>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - cdsp_dpm1_tpdm_out: endpoint { - remote-endpoint = <&cdsp_tpda_in5>; - }; - }; - }; - }; - - tpdm@11186000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11186000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <64>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - cdsp_dpm2_tpdm_out: endpoint { - remote-endpoint = <&cdsp_tpda_in6>; - }; - }; - }; - }; - - tpda@11188000 { - compatible = "qcom,coresight-tpda", "arm,primecell"; - reg = <0x0 0x11188000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - cdsp_tpda_in0: endpoint { - remote-endpoint = <&cdsp_tpdm_out>; - }; - }; - - port@1 { - reg = <1>; - - cdsp_tpda_in1: endpoint { - remote-endpoint = <&cdsp_llm_tpdm_out>; - }; - }; - - port@2 { - reg = <2>; - - cdsp_tpda_in2: endpoint { - remote-endpoint = <&cdsp_llm2_tpdm_out>; - }; - }; - - port@3 { - reg = <3>; - - cdsp_tpda_in3: endpoint { - remote-endpoint = <&cdsp_cmsr_tpdm_out>; - }; - }; - - port@4 { - reg = <4>; - - cdsp_tpda_in4: endpoint { - remote-endpoint = <&cdsp_cmsr2_tpdm_out>; - }; - }; - - port@5 { - reg = <5>; - - cdsp_tpda_in5: endpoint { - remote-endpoint = <&cdsp_dpm1_tpdm_out>; - }; - }; - - port@6 { - reg = <6>; - - cdsp_tpda_in6: endpoint { - remote-endpoint = <&cdsp_dpm2_tpdm_out>; - }; - }; - }; - - out-ports { - port { - cdsp_tpda_out: endpoint { - remote-endpoint = <&cdsp_funnel_in0>; - }; - }; - }; - }; - - funnel@11189000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x0 0x11189000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - port { - cdsp_funnel_in0: endpoint { - remote-endpoint = <&cdsp_tpda_out>; - }; - }; - }; - - out-ports { - port { - cdsp_funnel_out: endpoint { - remote-endpoint = <&tn_ag_in53>; - }; - }; - }; - }; - - cti@11193000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0 0x11193000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - }; - - cti@111ab000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0 0x111ab000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - }; - - tpdm@111d0000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x111d0000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - qm_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in35>; - }; - }; - }; - }; - - tn@11200000 { - compatible = "qcom,coresight-tnoc", "arm,primecell"; - reg = <0x0 0x11200000 0x0 0x4200>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@6 { - reg = <6>; - - tn_ag_in6: endpoint { - remote-endpoint = <&mm_dsb_tpdm_out>; - }; - }; - - port@10 { - reg = <0x10>; - - tn_ag_in16: endpoint { - remote-endpoint = <&east_dsb_tpdm_out>; - }; - }; - - port@21 { - reg = <0x21>; - - tn_ag_in33: endpoint { - remote-endpoint = <&west_dsb_tpdm_out>; - }; - }; - - port@23 { - reg = <0x23>; - - tn_ag_in35: endpoint { - remote-endpoint = <&qm_tpdm_out>; - }; - }; - - port@24 { - reg = <0x24>; - - tn_ag_in36: endpoint { - remote-endpoint = <&gcc_tpdm_out>; - }; - }; - - port@32 { - reg = <0x32>; - - tn_ag_in50: endpoint { - remote-endpoint = <&pcie_rscc_tpda_out>; - }; - }; - - port@35 { - reg = <0x35>; - - tn_ag_in53: endpoint { - remote-endpoint = <&cdsp_funnel_out>; - }; - }; - - port@3f { - reg = <0x3f>; - - tn_ag_in63: endpoint { - remote-endpoint = <¢er_dsb_tpdm_out>; - }; - }; - - port@40 { - reg = <0x40>; - - tn_ag_in64: endpoint { - remote-endpoint = <&ipcc_cmb_tpdm_out>; - }; - }; - - port@41 { - reg = <0x41>; - - tn_ag_in65: endpoint { - remote-endpoint = <&qrng_tpdm_out>; - }; - }; - - port@42 { - reg = <0x42>; - - tn_ag_in66: endpoint { - remote-endpoint = <&pmu_tpdm_out>; - }; - }; - - port@43 { - reg = <0x43>; - - tn_ag_in67: endpoint { - remote-endpoint = <&rdpm_west_cmb0_tpdm_out>; - }; - }; - - port@44 { - reg = <0x44>; - - tn_ag_in68: endpoint { - remote-endpoint = <&rdpm_west_cmb1_tpdm_out>; - }; - }; - - port@45 { - reg = <0x45>; - - tn_ag_in69: endpoint { - remote-endpoint = <&rdpm_west_cmb2_tpdm_out>; - }; - }; - - port@4b { - reg = <0x4b>; - - tn_ag_in75: endpoint { - remote-endpoint = <&south_dsb2_tpdm_out>; - }; - }; - - port@52 { - reg = <0x52>; - - tn_ag_in82: endpoint { - remote-endpoint = <&south_dsb_tpdm_out>; - }; - }; - - port@53 { - reg = <0x53>; - - tn_ag_in83: endpoint { - remote-endpoint = <¢er_dsb1_tpdm_out>; - }; - }; - }; - - out-ports { - port { - tn_ag_out: endpoint { - remote-endpoint = <&funnel0_in0>; - }; - }; - }; - }; - - tpdm@11207000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11207000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - mm_dsb_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in6>; - }; - }; - }; - }; - - tpdm@1120b000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1120b000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - east_dsb_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in16>; - }; - }; - }; - }; - - tpdm@11213000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11213000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - west_dsb_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in33>; - }; - }; - }; - }; - - tpdm@11219000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11219000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - center_dsb_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in63>; - }; - }; - }; - }; - - tpdm@1121a000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1121a000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - ipcc_cmb_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in64>; - }; - }; - }; - }; - - tpdm@1121b000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1121b000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - qrng_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in65>; - }; - }; - }; - }; - - tpdm@1121c000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1121c000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - pmu_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in66>; - }; - }; - }; - }; - - tpdm@1121d000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1121d000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - rdpm_west_cmb0_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in67>; - }; - }; - }; - }; - - tpdm@1121e000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1121e000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - rdpm_west_cmb1_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in68>; - }; - }; - }; - }; - - tpdm@1121f000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1121f000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - rdpm_west_cmb2_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in69>; - }; - }; - }; - }; - - tpdm@11220000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11220000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - center_dsb1_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in83>; - }; - }; - }; - }; - - tpdm@11224000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11224000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - south_dsb2_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in75>; - }; - }; - }; - }; - - tpdm@11228000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11228000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - south_dsb_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in82>; - }; - }; - }; - }; - - tpdm@11470000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11470000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <32>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - pcie_rscc_tpdm_out: endpoint { - remote-endpoint = <&pcie_rscc_tpda_in0>; - }; - }; - }; - }; - - tpda@11471000 { - compatible = "qcom,coresight-tpda", "arm,primecell"; - reg = <0x0 0x11471000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - port { - pcie_rscc_tpda_in0: endpoint { - remote-endpoint = <&pcie_rscc_tpdm_out>; - }; - }; - }; - - out-ports { - port { - pcie_rscc_tpda_out: endpoint { - remote-endpoint = <&tn_ag_in50>; - }; - }; - }; - }; - - tpdm@11c03000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11c03000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <64>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - swao_prio4_tpdm_out: endpoint { - remote-endpoint = <&aoss_tpda_in4>; - }; - }; - }; - }; - - funnel@11c04000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x0 0x11c04000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@5 { - reg = <5>; - - aoss_funnel_in5: endpoint { - remote-endpoint = <&aoss_tpda_out>; - }; - }; - - port@6 { - reg = <6>; - - aoss_funnel_in6: endpoint { - remote-endpoint = <&funnel0_out>; - }; - }; - }; - - out-ports { - port { - aoss_funnel_out: endpoint { - remote-endpoint = <&etf0_in>; - }; - }; - }; - }; - - tmc_etf: tmc@11c05000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x0 0x11c05000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - port { - etf0_in: endpoint { - remote-endpoint = <&aoss_funnel_out>; - }; - }; - }; - - out-ports { - port { - etf0_out: endpoint { - remote-endpoint = <&swao_rep_in>; - }; - }; - }; - }; - - replicator@11c06000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0x0 0x11c06000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - port { - swao_rep_in: endpoint { - remote-endpoint = <&etf0_out>; - }; - }; - }; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - swao_rep_out1: endpoint { - remote-endpoint = <&eud_in>; - }; - }; - }; - }; - - tpda@11c08000 { - compatible = "qcom,coresight-tpda", "arm,primecell"; - reg = <0x0 0x11c08000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - aoss_tpda_in0: endpoint { - remote-endpoint = <&swao_prio0_tpdm_out>; - }; - }; - - port@1 { - reg = <1>; - - aoss_tpda_in1: endpoint { - remote-endpoint = <&swao_prio1_tpdm_out>; - }; - }; - - port@2 { - reg = <2>; - - aoss_tpda_in2: endpoint { - remote-endpoint = <&swao_prio2_tpdm_out>; - }; - }; - - port@3 { - reg = <3>; - - aoss_tpda_in3: endpoint { - remote-endpoint = <&swao_prio3_tpdm_out>; - }; - }; - - port@4 { - reg = <4>; - - aoss_tpda_in4: endpoint { - remote-endpoint = <&swao_prio4_tpdm_out>; - }; - }; - - port@5 { - reg = <5>; - - aoss_tpda_in5: endpoint { - remote-endpoint = <&swao_tpdm_out>; - }; - }; - }; - - out-ports { - port { - aoss_tpda_out: endpoint { - remote-endpoint = <&aoss_funnel_in5>; - }; - }; - }; - }; - - tpdm@11c09000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11c09000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <64>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - swao_prio0_tpdm_out: endpoint { - remote-endpoint = <&aoss_tpda_in0>; - }; - }; - }; - }; - - tpdm@11c0a000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11c0a000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <64>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - swao_prio1_tpdm_out: endpoint { - remote-endpoint = <&aoss_tpda_in1>; - }; - }; - }; - }; - - tpdm@11c0b000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11c0b000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <64>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - swao_prio2_tpdm_out: endpoint { - remote-endpoint = <&aoss_tpda_in2>; - }; - }; - }; - }; - - tpdm@11c0c000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11c0c000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <64>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - swao_prio3_tpdm_out: endpoint { - remote-endpoint = <&aoss_tpda_in3>; - }; - }; - }; - }; - - cti@11c42000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0 0x11c42000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - }; - - cti@11c4b000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0 0x11c4b000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - }; - - tpdm@11c0d000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11c0d000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-element-bits = <32>; - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - swao_tpdm_out: endpoint { - remote-endpoint = <&aoss_tpda_in5>; - }; - }; - }; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,glymur-smmu-500", - "qcom,smmu-500", - "arm,mmu-500"; - reg = <0x0 0x15000000 0x0 0x100000>; - - #iommu-cells = <2>; - #global-interrupts = <1>; - - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - - dma-coherent; - }; - - pcie_smmu: iommu@15480000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0x15480000 0x0 0x20000>; - interrupts = , - , - ; - interrupt-names = "eventq", "cmdq-sync", "gerror"; - dma-coherent; - #iommu-cells = <1>; - }; - - intc: interrupt-controller@17000000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x17000000 0x0 0x10000>, - <0x0 0x17080000 0x0 0x480000>; - - interrupts = ; - - #interrupt-cells = <3>; - interrupt-controller; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gic_its: msi-controller@17040000 { - compatible = "arm,gic-v3-its"; - reg = <0x0 0x17040000 0x0 0x40000>; - - msi-controller; - #msi-cells = <1>; - }; - }; - - watchdog@17600000 { - compatible = "qcom,apss-wdt-glymur", "qcom,kpss-wdt"; - reg = <0x0 0x17600000 0x0 0x1000>; - clocks = <&sleep_clk>; - interrupts = ; - }; - - pdp0_mbox: mailbox@17610000 { - compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; - reg = <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; - interrupts = ; - #mbox-cells = <1>; - }; - - timer@17810000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x17810000 0x0 0x1000>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x0 0x20000000>; - - frame@17811000 { - reg = <0x0 0x17811000 0x1000>, - <0x0 0x17812000 0x1000>; - - interrupts = , - ; - - frame-number = <0>; - }; - - frame@17813000 { - reg = <0x0 0x17813000 0x1000>; - - interrupts = ; - - frame-number = <1>; - - status = "disabled"; - }; - - frame@17815000 { - reg = <0x0 0x17815000 0x1000>; - - interrupts = ; - - frame-number = <2>; - - status = "disabled"; - }; - - frame@17817000 { - reg = <0x0 0x17817000 0x1000>; - - interrupts = ; - - frame-number = <3>; - - status = "disabled"; - }; - - frame@17819000 { - reg = <0x0 0x17819000 0x1000>; - - interrupts = ; - - frame-number = <4>; - - status = "disabled"; - }; - - frame@1781b000 { - reg = <0x0 0x1781b000 0x1000>; - - interrupts = ; - - frame-number = <5>; - - status = "disabled"; - }; - - frame@1781d000 { - reg = <0x0 0x1781d000 0x1000>; - - interrupts = ; - - frame-number = <6>; - - status = "disabled"; - }; - }; - - apps_rsc: rsc@18900000 { - compatible = "qcom,rpmh-rsc"; - label = "apps_rsc"; - reg = <0x0 0x18900000 0x0 0x10000>, - <0x0 0x18910000 0x0 0x10000>, - <0x0 0x18920000 0x0 0x10000>; - reg-names = "drv-0", - "drv-1", - "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - power-domains = <&system_pd>; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible = "qcom,glymur-rpmh-clk"; - - clocks = <&xo_board>; - clock-names = "xo"; - - #clock-cells = <1>; - }; - - rpmhpd: power-controller { - compatible = "qcom,glymur-rpmhpd"; - - operating-points-v2 = <&rpmhpd_opp_table>; - - #power-domain-cells = <1>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp-16 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp-48 { - opp-level = ; - }; - - rpmhpd_opp_low_svs_d2: opp-52 { - opp-level = ; - }; - - rpmhpd_opp_low_svs_d1: opp-56 { - opp-level = ; - }; - - rpmhpd_opp_low_svs_d0: opp-60 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp-64 { - opp-level = ; - }; - - rpmhpd_opp_low_svs_l1: opp-80 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp-128 { - opp-level = ; - }; - - rpmhpd_opp_svs_l0: opp-144 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp-192 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp-256 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp-320 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp-336 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp-384 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp-416 { - opp-level = ; - }; - }; - }; - }; - - nsi_noc: interconnect@1d600000 { - compatible = "qcom,glymur-nsinoc"; - reg = <0x0 0x1d600000 0x0 0x14080>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - - oobm_ss_noc: interconnect@1f300000 { - compatible = "qcom,glymur-oobm-ss-noc"; - reg = <0x0 0x1f300000 0x0 0x49a00>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - - system-cache-controller@20400000 { - compatible = "qcom,glymur-llcc"; - reg = <0x0 0x21800000 0x0 0x100000>, - <0x0 0x21a00000 0x0 0x100000>, - <0x0 0x21c00000 0x0 0x100000>, - <0x0 0x21e00000 0x0 0x100000>, - <0x0 0x22800000 0x0 0x100000>, - <0x0 0x22a00000 0x0 0x100000>, - <0x0 0x22c00000 0x0 0x100000>, - <0x0 0x22e00000 0x0 0x100000>, - <0x0 0x23800000 0x0 0x100000>, - <0x0 0x23a00000 0x0 0x100000>, - <0x0 0x23c00000 0x0 0x100000>, - <0x0 0x23e00000 0x0 0x100000>, - <0x0 0x20400000 0x0 0x100000>, - <0x0 0x20600000 0x0 0x100000>; - reg-names = "llcc0_base", - "llcc1_base", - "llcc2_base", - "llcc3_base", - "llcc4_base", - "llcc5_base", - "llcc6_base", - "llcc7_base", - "llcc8_base", - "llcc9_base", - "llcc10_base", - "llcc11_base", - "llcc_broadcast_base", - "llcc_broadcast_and_base"; - - interrupts = ; - }; - - nsp_noc: interconnect@320c0000 { - compatible = "qcom,glymur-nsp-noc"; - reg = <0x0 0x320c0000 0x0 0x21280>; - qcom,bcm-voters = <&apps_bcm_voter>; - #interconnect-cells = <2>; - }; - - remoteproc_cdsp: remoteproc@32300000 { - compatible = "qcom,glymur-cdsp-pas", "qcom,sm8550-cdsp-pas"; - reg = <0x0 0x32300000 0x0 0x10000>; - - iommus = <&apps_smmu 0x2000 0x400>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", - "fatal", - "ready", - "handover", - "stop-ack", - "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - - power-domains = <&rpmhpd RPMHPD_CX>, - <&rpmhpd RPMHPD_MXC>, - <&rpmhpd RPMHPD_NSP>; - power-domain-names = "cx", - "mxc", - "nsp"; - - memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; - qcom,qmp = <&aoss_qmp>; - qcom,smem-states = <&smp2p_cdsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_MPROC_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_MPROC_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP>; - qcom,remote-pid = <5>; - label = "cdsp"; - - fastrpc { - compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "cdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - - iommus = <&apps_smmu 0x2001 0x440>, - <&apps_smmu 0x1961 0x0>, - <&apps_smmu 0x19c1 0x0>; - dma-coherent; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - - iommus = <&apps_smmu 0x2002 0x440>, - <&apps_smmu 0x1962 0x0>, - <&apps_smmu 0x19c2 0x0>; - dma-coherent; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - - iommus = <&apps_smmu 0x2003 0x440>, - <&apps_smmu 0x1963 0x0>, - <&apps_smmu 0x19c3 0x0>; - dma-coherent; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - - iommus = <&apps_smmu 0x2004 0x440>, - <&apps_smmu 0x1964 0x0>, - <&apps_smmu 0x19c4 0x0>; - dma-coherent; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - - iommus = <&apps_smmu 0x2005 0x440>, - <&apps_smmu 0x1965 0x0>, - <&apps_smmu 0x19c5 0x0>; - dma-coherent; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - - iommus = <&apps_smmu 0x2006 0x440>, - <&apps_smmu 0x1966 0x0>, - <&apps_smmu 0x19c6 0x0>; - dma-coherent; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - - iommus = <&apps_smmu 0x2007 0x440>, - <&apps_smmu 0x1967 0x0>, - <&apps_smmu 0x19c7 0x0>; - dma-coherent; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - - iommus = <&apps_smmu 0x2008 0x440>, - <&apps_smmu 0x1968 0x0>, - <&apps_smmu 0x19c8 0x0>; - dma-coherent; - }; - - /* note: compute-cb@9 is secure */ - - compute-cb@10 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <10>; - - iommus = <&apps_smmu 0x200c 0x440>, - <&apps_smmu 0x196c 0x0>, - <&apps_smmu 0x19cc 0x0>; - dma-coherent; - }; - - compute-cb@11 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <11>; - - iommus = <&apps_smmu 0x200d 0x440>, - <&apps_smmu 0x196d 0x0>, - <&apps_smmu 0x19cd 0x0>; - dma-coherent; - }; - - compute-cb@12 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <12>; - - iommus = <&apps_smmu 0x200e 0x440>, - <&apps_smmu 0x196e 0x0>, - <&apps_smmu 0x19ce 0x0>; - dma-coherent; - }; - }; - }; - }; - - imem: sram@81e08000 { - compatible = "mmio-sram"; - reg = <0x0 0x81e08600 0x0 0x300>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x81e08600 0x300>; - - cpu_scp_lpri0: scp-sram-section@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x180>; - }; - - cpu_scp_lpri1: scp-sram-section@180 { - compatible = "arm,scmi-shmem"; - reg = <0x180 0x180>; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - , - ; - }; - - thermal_zones: thermal-zones { - aoss-0-thermal { - thermal-sensors = <&tsens0 0>; - - trips { - aoss-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-0-0-0-thermal { - thermal-sensors = <&tsens0 1>; - - trips { - cpu-0-0-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-0-0-1-thermal { - thermal-sensors = <&tsens0 2>; - - trips { - cpu-0-0-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-0-1-0-thermal { - thermal-sensors = <&tsens0 3>; - - trips { - cpu-0-1-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-0-1-1-thermal { - thermal-sensors = <&tsens0 4>; - - trips { - cpu-0-1-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-0-2-0-thermal { - thermal-sensors = <&tsens0 5>; - - trips { - cpu-0-2-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-0-2-1-thermal { - thermal-sensors = <&tsens0 6>; - - trips { - cpu-0-2-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-0-3-0-thermal { - thermal-sensors = <&tsens0 7>; - - trips { - cpu-0-3-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-0-3-1-thermal { - thermal-sensors = <&tsens0 8>; - - trips { - cpu-0-3-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-0-4-0-thermal { - thermal-sensors = <&tsens0 9>; - - trips { - cpu-0-4-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-0-4-1-thermal { - thermal-sensors = <&tsens0 10>; - - trips { - cpu-0-4-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-0-5-0-thermal { - thermal-sensors = <&tsens0 11>; - - trips { - cpu-0-5-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-0-5-1-thermal { - thermal-sensors = <&tsens0 12>; - - trips { - cpu-0-5-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - aoss-1-thermal { - thermal-sensors = <&tsens1 0>; - - trips { - aoss-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpullc-0-0-thermal { - thermal-sensors = <&tsens1 1>; - - trips { - cpullc-0-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpullc-0-1-thermal { - thermal-sensors = <&tsens1 2>; - - trips { - cpullc-0-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - qmx-0-0-thermal { - thermal-sensors = <&tsens1 3>; - - trips { - qmx-0-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - qmx-0-1-thermal { - thermal-sensors = <&tsens1 4>; - - trips { - qmx-0-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - qmx-0-2-thermal { - thermal-sensors = <&tsens1 5>; - - trips { - qmx-0-2-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - ddr-0-thermal { - thermal-sensors = <&tsens1 6>; - - trips { - ddr-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - video-0-thermal { - thermal-sensors = <&tsens1 7>; - - trips { - video-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - video-1-thermal { - thermal-sensors = <&tsens1 8>; - - trips { - video-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - aoss-2-thermal { - thermal-sensors = <&tsens2 0>; - - trips { - aoss-2-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-1-0-0-thermal { - thermal-sensors = <&tsens2 1>; - - trips { - cpu-1-0-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-1-0-1-thermal { - thermal-sensors = <&tsens2 2>; - - trips { - cpu-1-0-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-1-1-0-thermal { - thermal-sensors = <&tsens2 3>; - - trips { - cpu-1-1-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-1-1-1-thermal { - thermal-sensors = <&tsens2 4>; - - trips { - cpu-1-1-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-1-2-0-thermal { - thermal-sensors = <&tsens2 5>; - - trips { - cpu-1-2-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-1-2-1-thermal { - thermal-sensors = <&tsens2 6>; - - trips { - cpu-1-2-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-1-3-0-thermal { - thermal-sensors = <&tsens2 7>; - - trips { - cpu-1-3-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-1-3-1-thermal { - thermal-sensors = <&tsens2 8>; - - trips { - cpu-1-3-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-1-4-0-thermal { - thermal-sensors = <&tsens2 9>; - - trips { - cpu-1-4-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-1-4-1-thermal { - thermal-sensors = <&tsens2 10>; - - trips { - cpu-1-4-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-1-5-0-thermal { - thermal-sensors = <&tsens2 11>; - - trips { - cpu-1-5-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-1-5-1-thermal { - thermal-sensors = <&tsens2 12>; - - trips { - cpu-1-5-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - aoss-3-thermal { - thermal-sensors = <&tsens3 0>; - - trips { - aoss-3-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpullc-1-0-thermal { - thermal-sensors = <&tsens3 1>; - - trips { - cpullc-1-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpullc-1-1-thermal { - thermal-sensors = <&tsens3 2>; - - trips { - cpullc-1-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - qmx-1-0-thermal { - thermal-sensors = <&tsens3 3>; - - trips { - qmx-1-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - qmx-1-1-thermal { - thermal-sensors = <&tsens3 4>; - - trips { - qmx-1-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - qmx-1-2-thermal { - thermal-sensors = <&tsens3 5>; - - trips { - qmx-1-2-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - qmx-1-3-thermal { - thermal-sensors = <&tsens3 6>; - - trips { - qmx-1-3-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - qmx-1-4-thermal { - thermal-sensors = <&tsens3 7>; - - trips { - qmx-1-4-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - aoss-4-thermal { - thermal-sensors = <&tsens4 0>; - - trips { - aoss-4-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-2-0-0-thermal { - thermal-sensors = <&tsens4 1>; - - trips { - cpu-2-0-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-2-0-1-thermal { - thermal-sensors = <&tsens4 2>; - - trips { - cpu-2-0-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-2-1-0-thermal { - thermal-sensors = <&tsens4 3>; - - trips { - cpu-2-1-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-2-1-1-thermal { - thermal-sensors = <&tsens4 4>; - - trips { - cpu-2-1-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-2-2-0-thermal { - thermal-sensors = <&tsens4 5>; - - trips { - cpu-2-2-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-2-2-1-thermal { - thermal-sensors = <&tsens4 6>; - - trips { - cpu-2-2-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-2-3-0-thermal { - thermal-sensors = <&tsens4 7>; - - trips { - cpu-2-3-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-2-3-1-thermal { - thermal-sensors = <&tsens4 8>; - - trips { - cpu-2-3-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-2-4-0-thermal { - thermal-sensors = <&tsens4 9>; - - trips { - cpu-2-4-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-2-4-1-thermal { - thermal-sensors = <&tsens4 10>; - - trips { - cpu-2-4-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-2-5-0-thermal { - thermal-sensors = <&tsens4 11>; - - trips { - cpu-2-5-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu-2-5-1-thermal { - thermal-sensors = <&tsens4 12>; - - trips { - cpu-2-5-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - aoss-5-thermal { - thermal-sensors = <&tsens5 0>; - - trips { - aoss-5-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpullc-2-0-thermal { - thermal-sensors = <&tsens5 1>; - - trips { - cpullc-2-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpuillc-2-1-thermal { - thermal-sensors = <&tsens5 2>; - - trips { - cpullc-2-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - qmx-2-0-thermal { - thermal-sensors = <&tsens5 3>; - - trips { - qmx-2-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - qmx-2-1-thermal { - thermal-sensors = <&tsens5 4>; - - trips { - qmx-2-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - qmx-2-2-thermal { - thermal-sensors = <&tsens5 5>; - - trips { - qmx-2-2-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - qmx-2-3-thermal { - thermal-sensors = <&tsens5 6>; - - trips { - qmx-2-3-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - qmx-2-4-thermal { - thermal-sensors = <&tsens5 7>; - - trips { - qmx-2-4-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - aoss-6-thermal { - thermal-sensors = <&tsens6 0>; - - trips { - aoss-6-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - nsphvx-0-thermal { - thermal-sensors = <&tsens6 1>; - - trips { - nsphvx-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - nsphvx-1-thermal { - thermal-sensors = <&tsens6 2>; - - trips { - nsphvx-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - nsphvx-2-thermal { - thermal-sensors = <&tsens6 3>; - - trips { - nsphvx-2-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - nsphvx-3-thermal { - thermal-sensors = <&tsens6 4>; - - trips { - nsphvx-3-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - nsphmx-0-thermal { - thermal-sensors = <&tsens6 5>; - - trips { - nsphmx-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - nsphmx-1-thermal { - thermal-sensors = <&tsens6 6>; - - trips { - nsphmx-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - nsphmx-2-thermal { - thermal-sensors = <&tsens6 7>; - - trips { - nsphmx-2-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - nsphmx-3-thermal { - thermal-sensors = <&tsens6 8>; - - trips { - nsphmx-3-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - camera-0-thermal { - thermal-sensors = <&tsens6 9>; - - trips { - camera-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - camera-1-thermal { - thermal-sensors = <&tsens6 10>; - - trips { - camera-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - ddr-1-thermal { - thermal-sensors = <&tsens6 11>; - - trips { - ddr-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - ddr-2-thermal { - thermal-sensors = <&tsens6 12>; - - trips { - ddr-2-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - aoss-7-thermal { - thermal-sensors = <&tsens7 0>; - - trips { - aoss-7-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpu-0-0-thermal { - thermal-sensors = <&tsens7 1>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; - }; - - gpu-0-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpu-0-1-thermal { - thermal-sensors = <&tsens7 2>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; - }; - - gpu-0-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpu-0-2-thermal { - thermal-sensors = <&tsens7 3>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; - }; - - gpu-0-2-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpu-1-0-thermal { - thermal-sensors = <&tsens7 4>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; - }; - - gpu-1-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpu-1-1-thermal { - thermal-sensors = <&tsens7 5>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; - }; - - gpu-1-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpu-1-2-thermal { - thermal-sensors = <&tsens7 6>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; - }; - - gpu-1-2-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpu-2-0-thermal { - thermal-sensors = <&tsens7 7>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; - }; - - gpu-2-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpu-2-1-thermal { - thermal-sensors = <&tsens7 8>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; - }; - - gpu-2-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpu-2-2-thermal { - thermal-sensors = <&tsens7 9>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; - }; - - gpu-2-2-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpu-3-0-thermal { - thermal-sensors = <&tsens7 10>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; - }; - - gpu-3-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpu-3-1-thermal { - thermal-sensors = <&tsens7 11>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; - }; - - gpu-3-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpu-3-2-thermal { - thermal-sensors = <&tsens7 12>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; - }; - - gpu-3-2-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpuss-0-thermal { - thermal-sensors = <&tsens7 13>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; - }; - - gpuss-0-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpuss-1-thermal { - thermal-sensors = <&tsens7 14>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; - }; - - gpuss-1-critical { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; - - tpdm-cdsp-llm { - compatible = "qcom,coresight-static-tpdm"; - qcom,cmb-element-bits = <32>; - - out-ports { - port { - cdsp_llm_tpdm_out: endpoint { - remote-endpoint = <&cdsp_tpda_in1>; - }; - }; - }; - }; - - tpdm-cdsp-llm2 { - compatible = "qcom,coresight-static-tpdm"; - qcom,cmb-element-bits = <32>; - - out-ports { - port { - cdsp_llm2_tpdm_out: endpoint { - remote-endpoint = <&cdsp_tpda_in2>; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi deleted file mode 100644 index c3ccd2b75609..000000000000 --- a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi +++ /dev/null @@ -1,187 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -#include -#include - -/ { - thermal-zones { - pmcx0102-c0-thermal { - polling-delay-passive = <100>; - thermal-sensors = <&pmcx0102_c_e0_temp_alarm>; - - trips { - trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - trip1 { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - pmcx0102-c1-thermal { - polling-delay-passive = <100>; - thermal-sensors = <&pmcx0102_c_e1_temp_alarm>; - - trips { - trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - trip1 { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - pmcx0102-d0-thermal { - polling-delay-passive = <100>; - thermal-sensors = <&pmcx0102_d_e0_temp_alarm>; - - trips { - trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - trip1 { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - pmcx0102-d1-thermal { - polling-delay-passive = <100>; - thermal-sensors = <&pmcx0102_d_e1_temp_alarm>; - - trips { - trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - trip1 { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; -}; - -&spmi_bus0 { - pmcx0102_c_e0: pmic@2 { - compatible = "qcom,pmcx0102", "qcom,spmi-pmic"; - reg = <0x2 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmcx0102_c_e0_temp_alarm: temp-alarm@a00 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0xa00>; - interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; - #thermal-sensor-cells = <0>; - }; - - pmcx0102_c_e0_gpios: gpio@8800 { - compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; - reg = <0x8800>; - gpio-controller; - gpio-ranges = <&pmcx0102_c_e0_gpios 0 0 14>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pmcx0102_d_e0: pmic@3 { - compatible = "qcom,pmcx0102", "qcom,spmi-pmic"; - reg = <0x3 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmcx0102_d_e0_temp_alarm: temp-alarm@a00 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0xa00>; - interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; - #thermal-sensor-cells = <0>; - }; - - pmcx0102_d_e0_gpios: gpio@8800 { - compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; - reg = <0x8800>; - gpio-controller; - gpio-ranges = <&pmcx0102_d_e0_gpios 0 0 14>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; - -&spmi_bus1 { - pmcx0102_c_e1: pmic@2 { - compatible = "qcom,pmcx0102", "qcom,spmi-pmic"; - reg = <0x2 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmcx0102_c_e1_temp_alarm: temp-alarm@a00 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0xa00>; - interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; - #thermal-sensor-cells = <0>; - }; - - pmcx0102_c_e1_gpios: gpio@8800 { - compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; - reg = <0x8800>; - gpio-controller; - gpio-ranges = <&pmcx0102_c_e1_gpios 0 0 14>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pmcx0102_d_e1: pmic@3 { - compatible = "qcom,pmcx0102", "qcom,spmi-pmic"; - reg = <0x3 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmcx0102_d_e1_temp_alarm: temp-alarm@a00 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0xa00>; - interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; - #thermal-sensor-cells = <0>; - }; - - pmcx0102_d_e1_gpios: gpio@8800 { - compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; - reg = <0x8800>; - gpio-controller; - gpio-ranges = <&pmcx0102_d_e1_gpios 0 0 14>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pmh0101.dtsi b/arch/arm64/boot/dts/qcom/pmh0101.dtsi deleted file mode 100644 index b1ec41325958..000000000000 --- a/arch/arm64/boot/dts/qcom/pmh0101.dtsi +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -#include -#include - -/ { - thermal-zones { - pmh0101-thermal { - polling-delay-passive = <100>; - thermal-sensors = <&pmh0101_temp_alarm>; - - trips { - trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - trip1 { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; -}; - -&spmi_bus0 { - pmic@1 { - compatible = "qcom,pmh0101", "qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmh0101_temp_alarm: temp-alarm@a00 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0xa00>; - interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; - #thermal-sensor-cells = <0>; - }; - - pmh0101_gpios: gpio@8800 { - compatible = "qcom,pmh0101-gpio", "qcom,spmi-gpio"; - reg = <0x8800>; - gpio-controller; - gpio-ranges = <&pmh0101_gpios 0 0 18>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pmh0101_flash: led-controller@ee00 { - compatible = "qcom,pmh0101-flash-led", "qcom,spmi-flash-led"; - reg = <0xee00>; - status = "disabled"; - }; - - pmh0101_pwm: pwm { - compatible = "qcom,pmh0101-pwm", "qcom,pm8350c-pwm"; - #pwm-cells = <2>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi deleted file mode 100644 index d89cceda53a3..000000000000 --- a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -#include -#include - -/{ - thermal_zones { - pmh0104-i0-thermal { - polling-delay-passive = <100>; - thermal-sensors = <&pmh0104_i_e0_temp_alarm>; - - trips { - trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - trip1 { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - pmh0104-j0-thermal { - polling-delay-passive = <100>; - thermal-sensors = <&pmh0104_j_e0_temp_alarm>; - - trips { - trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - trip1 { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - pmh0104-l1-thermal { - polling-delay-passive = <100>; - thermal-sensors = <&pmh0104_l_e1_temp_alarm>; - - trips { - trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - trip1 { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; -}; - -&spmi_bus0 { - pmh0104_i_e0: pmic@8 { - compatible = "qcom,pmh0104", "qcom,spmi-pmic"; - reg = <0x8 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmh0104_i_e0_temp_alarm: temp-alarm@a00 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0xa00>; - interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; - #thermal-sensor-cells = <0>; - }; - - pmh0104_i_e0_gpios: gpio@8800 { - compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio"; - reg = <0x8800>; - gpio-controller; - gpio-ranges = <&pmh0104_i_e0_gpios 0 0 8>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pmh0104_j_e0: pmic@9 { - compatible = "qcom,pmh0104", "qcom,spmi-pmic"; - reg = <0x9 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmh0104_j_e0_temp_alarm: temp-alarm@a00 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0xa00>; - interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; - #thermal-sensor-cells = <0>; - }; - - pmh0104_j_e0_gpios: gpio@8800 { - compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio"; - reg = <0x8800>; - gpio-controller; - gpio-ranges = <&pmh0104_j_e0_gpios 0 0 8>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; - -&spmi_bus1 { - pmh0104_l_e1: pmic@b { - compatible = "qcom,pmh0104", "qcom,spmi-pmic"; - reg = <0xb SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmh0104_l_e1_temp_alarm: temp-alarm@a00 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0xa00>; - interrupts = <0xb 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; - #thermal-sensor-cells = <0>; - }; - - pmh0104_l_e1_gpios: gpio@8800 { - compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio"; - reg = <0x8800>; - gpio-controller; - gpio-ranges = <&pmh0104_l_e1_gpios 0 0 8>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pmk8850.dtsi b/arch/arm64/boot/dts/qcom/pmk8850.dtsi deleted file mode 100644 index c7ba72fd48bc..000000000000 --- a/arch/arm64/boot/dts/qcom/pmk8850.dtsi +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -#include -#include -#include -#include - -&spmi_bus0 { - pmic@0 { - compatible = "qcom,pmk8850", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmk8850_pon: pon@1300 { - compatible = "qcom,pmk8350-pon"; - reg = <0x1300>, - <0x800>; - reg-names = "hlos", - "pbs"; - - pon_pwrkey: pwrkey { - compatible = "qcom,pmk8350-pwrkey"; - interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; - linux,code = ; - }; - - pon_resin: resin { - compatible = "qcom,pmk8350-resin"; - interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; - status = "disabled"; - }; - }; - - pmk8850_gpios: gpio@b800 { - compatible = "qcom,pmk8850-gpio", "qcom,spmi-gpio"; - reg = <0xb800>; - gpio-controller; - gpio-ranges = <&pmk8850_gpios 0 0 8>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pmk8850_rtc: rtc@6100 { - compatible = "qcom,pmk8350-rtc"; - reg = <0x6100>, - <0x6200>; - reg-names = "rtc", - "alarm"; - interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; - }; - - pmk8850_sdam_2: nvram@7100 { - compatible = "qcom,spmi-sdam"; - reg = <0x7100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x7100 0x100>; - - reboot_reason: reboot-reason@48 { - reg = <0x48 0x1>; - bits = <1 7>; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/smb2370.dtsi b/arch/arm64/boot/dts/qcom/smb2370.dtsi deleted file mode 100644 index 80f3fdae5705..000000000000 --- a/arch/arm64/boot/dts/qcom/smb2370.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -&spmi_bus2 { - smb2370_j_e2: pmic@9 { - compatible = "qcom,smb2370", "qcom,spmi-pmic"; - reg = <0x9 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - smb2370_j_e2_eusb2_repeater: phy@fd00 { - compatible = "qcom,smb2370-eusb2-repeater"; - reg = <0xfd00>; - #phy-cells = <0>; - }; - }; - - smb2370_k_e2: pmic@a { - compatible = "qcom,smb2370", "qcom,spmi-pmic"; - reg = <0xa SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - smb2370_k_e2_eusb2_repeater: phy@fd00 { - compatible = "qcom,smb2370-eusb2-repeater"; - reg = <0xfd00>; - #phy-cells = <0>; - }; - }; - - smb2370_l_e2: pmic@b { - compatible = "qcom,smb2370", "qcom,spmi-pmic"; - reg = <0xb SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - smb2370_l_e2_eusb2_repeater: phy@fd00 { - compatible = "qcom,smb2370-eusb2-repeater"; - reg = <0xfd00>; - #phy-cells = <0>; - }; - }; -}; From 71bf8772092819e58ba52de573a8b8092771212d Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Mon, 16 Feb 2026 22:29:46 +0530 Subject: [PATCH 02/16] cleaning up arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi | 144 ------------------- 1 file changed, 144 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi diff --git a/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi b/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi deleted file mode 100644 index 7655bc030348..000000000000 --- a/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -#include -#include - -/ { - thermal-zones { - pmh0110-f0-thermal { - polling-delay-passive = <100>; - thermal-sensors = <&pmh0110_f_e0_temp_alarm>; - - trips { - trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - trip1 { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - pmh0110-f1-thermal { - polling-delay-passive = <100>; - thermal-sensors = <&pmh0110_f_e1_temp_alarm>; - - trips { - trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - trip1 { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - pmh0110-h0-thermal { - polling-delay-passive = <100>; - thermal-sensors = <&pmh0110_h_e0_temp_alarm>; - - trips { - trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - trip1 { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - }; -}; - -&spmi_bus0 { - pmh0110_f_e0: pmic@5 { - compatible = "qcom,pmh0110", "qcom,spmi-pmic"; - reg = <0x5 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmh0110_f_e0_temp_alarm: temp-alarm@a00 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0xa00>; - interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; - #thermal-sensor-cells = <0>; - }; - - pmh0110_f_e0_gpios: gpio@8800 { - compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; - reg = <0x8800>; - gpio-controller; - gpio-ranges = <&pmh0110_f_e0_gpios 0 0 14>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pmh0110_h_e0: pmic@7 { - compatible = "qcom,pmh0110", "qcom,spmi-pmic"; - reg = <0x7 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmh0110_h_e0_temp_alarm: temp-alarm@a00 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0xa00>; - interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; - #thermal-sensor-cells = <0>; - }; - - pmh0110_h_e0_gpios: gpio@8800 { - compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; - reg = <0x8800>; - gpio-controller; - gpio-ranges = <&pmh0110_h_e0_gpios 0 0 14>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; - -&spmi_bus1 { - pmh0110_f_e1: pmic@5 { - compatible = "qcom,pmh0110", "qcom,spmi-pmic"; - reg = <0x5 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pmh0110_f_e1_temp_alarm: temp-alarm@a00 { - compatible = "qcom,spmi-temp-alarm"; - reg = <0xa00>; - interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; - #thermal-sensor-cells = <0>; - }; - - pmh0110_f_e1_gpios: gpio@8800 { - compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; - reg = <0x8800>; - gpio-controller; - gpio-ranges = <&pmh0110_f_e1_gpios 0 0 14>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; -}; From 28a167af963a38109039d0adce38729a813df21c Mon Sep 17 00:00:00 2001 From: Pankaj Patil Date: Thu, 25 Sep 2025 12:02:09 +0530 Subject: [PATCH 03/16] FROMLIST: dt-bindings: arm: qcom: Document Glymur SoC and board Document Glymur SoC bindings and Compute Reference Device (CRD) board id Link: https://lore.kernel.org/all/20260205-upstream_v3_glymur_introduction-v7-1-849e7a9e6888@oss.qualcomm.com/ Signed-off-by: Pankaj Patil Signed-off-by: Sibi Sankar Signed-off-by: Pradyot Kumar Nayak --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index d84bd3bca201..b6398bc8c588 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -61,6 +61,11 @@ properties: - qcom,apq8084-sbc - const: qcom,apq8084 + - items: + - enum: + - qcom,glymur-crd + - const: qcom,glymur + - items: - enum: - microsoft,dempsey From 023876c88163aa1f7a435bef1c000c4549039f15 Mon Sep 17 00:00:00 2001 From: Pankaj Patil Date: Thu, 25 Sep 2025 12:02:11 +0530 Subject: [PATCH 04/16] FROMLIST: arm64: dts: qcom: Introduce Glymur base dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce the base device tree support for Glymur – Qualcomm's next-generation compute SoC. The new glymur.dtsi describes the core SoC components, including: - CPUs and CPU topology - Interrupt controller and TLMM - GCC,DISPCC and RPMHCC clock controllers - Reserved memory and interconnects - APPS and PCIe SMMU and firmware SCM - Watchdog, RPMHPD, APPS RSC and SRAM - PSCI and PMU nodes - QUPv3 serial engines - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS - PDP0 mailbox, IPCC and AOSS - Display clock controller - SPMI PMIC arbiter with SPMI0/1/2 buses - SMP2P nodes - TSENS and thermal zones (8 instances, 92 sensors) Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104, PMH0110, PMIC's along with temp-alarm and GPIO nodes needed on Glymur Enabled PCIe controllers and associated PHY to support boot to shell with nvme storage, List of PCIe instances enabled: - PCIe3b - PCIe4 - PCIe5 - PCIe6 Link: https://lore.kernel.org/all/20260205-upstream_v3_glymur_introduction-v7-3-849e7a9e6888@oss.qualcomm.com/ Co-developed-by: Jyothi Kumar Seerapu Signed-off-by: Jyothi Kumar Seerapu Co-developed-by: Maulik Shah Signed-off-by: Maulik Shah Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Co-developed-by: Taniya Das Signed-off-by: Taniya Das Co-developed-by: Kamal Wadhwa Signed-off-by: Kamal Wadhwa Co-developed-by: Qiang Yu Signed-off-by: Qiang Yu Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa Co-developed-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Manaf Meethalavalappu Pallikunhi Co-developed-by: Jishnu Prakash Signed-off-by: Jishnu Prakash Signed-off-by: Pankaj Patil Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur.dtsi | 5913 ++++++++++++++++++ arch/arm64/boot/dts/qcom/pmcx0102.dtsi | 187 + arch/arm64/boot/dts/qcom/pmh0101.dtsi | 68 + arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 144 + arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi | 144 + arch/arm64/boot/dts/qcom/pmk8850.dtsi | 70 + arch/arm64/boot/dts/qcom/smb2370.dtsi | 45 + 7 files changed, 6571 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/glymur.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmcx0102.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmh0101.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmk8850.dtsi create mode 100644 arch/arm64/boot/dts/qcom/smb2370.dtsi diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi new file mode 100644 index 000000000000..e269cec7942c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -0,0 +1,5913 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "glymur-ipcc.h" + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x0>; + enable-method = "psci"; + power-domains = <&cpu_pd0>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x100>; + enable-method = "psci"; + power-domains = <&cpu_pd1>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x200>; + enable-method = "psci"; + power-domains = <&cpu_pd2>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x300>; + enable-method = "psci"; + power-domains = <&cpu_pd3>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x400>; + enable-method = "psci"; + power-domains = <&cpu_pd4>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x500>; + enable-method = "psci"; + power-domains = <&cpu_pd5>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + }; + + cpu6: cpu@10000 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x10000>; + enable-method = "psci"; + power-domains = <&cpu_pd6>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + + l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu7: cpu@10100 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x10100>; + enable-method = "psci"; + power-domains = <&cpu_pd7>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + }; + + cpu8: cpu@10200 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x10200>; + enable-method = "psci"; + power-domains = <&cpu_pd8>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + }; + + cpu9: cpu@10300 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x10300>; + enable-method = "psci"; + power-domains = <&cpu_pd9>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + }; + + cpu10: cpu@10400 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x10400>; + enable-method = "psci"; + power-domains = <&cpu_pd10>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + }; + + cpu11: cpu@10500 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x10500>; + enable-method = "psci"; + power-domains = <&cpu_pd11>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + }; + + cpu12: cpu@20000 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x20000>; + enable-method = "psci"; + power-domains = <&cpu_pd12>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + + l2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu13: cpu@20100 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x20100>; + enable-method = "psci"; + power-domains = <&cpu_pd13>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + }; + + cpu14: cpu@20200 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x20200>; + enable-method = "psci"; + power-domains = <&cpu_pd14>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + }; + + cpu15: cpu@20300 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x20300>; + enable-method = "psci"; + power-domains = <&cpu_pd15>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + }; + + cpu16: cpu@20400 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x20400>; + enable-method = "psci"; + power-domains = <&cpu_pd16>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + }; + + cpu17: cpu@20500 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x20500>; + enable-method = "psci"; + power-domains = <&cpu_pd17>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + + core5 { + cpu = <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu6>; + }; + + core1 { + cpu = <&cpu7>; + }; + + core2 { + cpu = <&cpu8>; + }; + + core3 { + cpu = <&cpu9>; + }; + + core4 { + cpu = <&cpu10>; + }; + + core5 { + cpu = <&cpu11>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu12>; + }; + + core1 { + cpu = <&cpu13>; + }; + + core2 { + cpu = <&cpu14>; + }; + + core3 { + cpu = <&cpu15>; + }; + + core4 { + cpu = <&cpu16>; + }; + + core5 { + cpu = <&cpu17>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + cpu_c4: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "ret"; + arm,psci-suspend-param = <0x00000004>; + entry-latency-us = <180>; + exit-latency-us = <320>; + min-residency-us = <1000>; + }; + }; + + domain-idle-states { + cluster_cl5: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x01000054>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <9000>; + }; + + domain_ss3: domain-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x0200c354>; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-glymur", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x4000>; + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + }; + + scmi { + compatible = "arm,scmi"; + mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>; + mbox-names = "tx", "rx"; + shmem = <&cpu_scp_lpri1>, <&cpu_scp_lpri0>; + + #address-cells = <1>; + #size-cells = <0>; + + scmi_perf: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + }; + }; + + clk_virt: interconnect-0 { + compatible = "qcom,glymur-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible = "qcom,glymur-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd8: power-domain-cpu8 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd9: power-domain-cpu9 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd10: power-domain-cpu10 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd11: power-domain-cpu11 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd12: power-domain-cpu12 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd13: power-domain-cpu13 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd14: power-domain-cpu14 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd15: power-domain-cpu15 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd16: power-domain-cpu16 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd17: power-domain-cpu17 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cluster0_pd: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + power-domains = <&system_pd>; + domain-idle-states = <&cluster_cl5>; + }; + + cluster1_pd: power-domain-cpu-cluster1 { + #power-domain-cells = <0>; + power-domains = <&system_pd>; + domain-idle-states = <&cluster_cl5>; + }; + + cluster2_pd: power-domain-cpu-cluster2 { + #power-domain-cells = <0>; + power-domains = <&system_pd>; + domain-idle-states = <&cluster_cl5>; + }; + + system_pd: power-domain-system { + #power-domain-cells = <0>; + domain-idle-states = <&domain_ss3>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pdp_mem: pdp@81400000 { + reg = <0x0 0x81400000 0x0 0x100000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@81c60000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + pdp_ns_shared_mem: pdp-ns-shared@81e00000 { + reg = <0x0 0x81e00000 0x0 0x200000>; + no-map; + }; + + oobdaretag_mem: oobdaretag@86e10000 { + reg = <0x0 0x86e10000 0x0 0x360000>; + no-map; + }; + + oob_secure_mem: oob-secure@87170000 { + reg = <0x0 0x87170000 0x0 0xbc0000>; + no-map; + }; + + oobdtbqc_mem: oobdtbqc@87d30000 { + reg = <0x0 0x87d30000 0x0 0x20000>; + no-map; + }; + + oobdtboem_mem: oobdtboem@87d50000 { + reg = <0x0 0x87d50000 0x0 0x20000>; + no-map; + }; + + oob_nonsecure_mem: oob-nonsecure@87e00000 { + reg = <0x0 0x87e00000 0x0 0xc00000>; + no-map; + }; + + spss_region_mem: spss@88a00000 { + reg = <0x0 0x88a00000 0x0 0x400000>; + no-map; + }; + + soccpdtb_mem: soccpdtb@892e0000 { + reg = <0x0 0x892e0000 0x0 0x20000>; + no-map; + }; + + soccp_mem: soccp@89300000 { + reg = <0x0 0x89300000 0x0 0x400000>; + no-map; + }; + + cvp_mem: cvp@89700000 { + reg = <0x0 0x89700000 0x0 0x700000>; + no-map; + }; + + adspslpi_mem: adspslpi@89e00000 { + reg = <0x0 0x89e00000 0x0 0x3a00000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb@8d800000 { + reg = <0x0 0x8d800000 0x0 0x80000>; + no-map; + }; + + cdsp_mem: cdsp@8d900000 { + reg = <0x0 0x8d900000 0x0 0x4000000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb@91900000 { + reg = <0x0 0x91900000 0x0 0x80000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@919fe000 { + reg = <0x0 0x919fe000 0x0 0x2000>; + no-map; + }; + + camera_mem: camera@91a00000 { + reg = <0x0 0x91a00000 0x0 0x800000>; + no-map; + }; + + av1_encoder_mem: av1-encoder@92200000 { + reg = <0x0 0x92200000 0x0 0x700000>; + no-map; + }; + + video_mem: video@92900000 { + reg = <0x0 0x92900000 0x0 0xc00000>; + no-map; + }; + + smem_mem: smem@ffe00000 { + compatible = "qcom,smem"; + reg = <0x0 0xffe00000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_LPASS IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <443>, <429>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_CDSP IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <94>, <432>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-soccp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <617>, <616>; + qcom,local-pid = <0>; + qcom,remote-pid = <19>; + + soccp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + soccp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + + gcc: clock-controller@100000 { + compatible = "qcom,glymur-gcc"; + reg = <0x0 0x00100000 0x0 0x1f9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, /* Board XO source */ + <&rpmhcc RPMH_CXO_CLK_A>, /* Board XO_A source */ + <&sleep_clk>, /* Sleep */ + <0>, /* USB 0 Phy DP0 GMUX */ + <0>, /* USB 0 Phy DP1 GMUX */ + <0>, /* USB 0 Phy PCIE PIPEGMUX */ + <0>, /* USB 0 Phy PIPEGMUX */ + <0>, /* USB 0 Phy SYS PCIE PIPEGMUX */ + <0>, /* USB 1 Phy DP0 GMUX 2 */ + <0>, /* USB 1 Phy DP1 GMUX 2 */ + <0>, /* USB 1 Phy PCIE PIPEGMUX */ + <0>, /* USB 1 Phy PIPEGMUX */ + <0>, /* USB 1 Phy SYS PCIE PIPEGMUX */ + <0>, /* USB 2 Phy DP0 GMUX 2 */ + <0>, /* USB 2 Phy DP1 GMUX 2 */ + <0>, /* USB 2 Phy PCIE PIPEGMUX */ + <0>, /* USB 2 Phy PIPEGMUX */ + <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ + <0>, /* PCIe 3a */ + <&pcie3b_phy>, /* PCIe 3b */ + <&pcie4_phy>, /* PCIe 4 */ + <&pcie5_phy>, /* PCIe 5 */ + <&pcie6_phy>, /* PCIe 6 */ + <0>, /* QUSB4 0 PHY RX 0 */ + <0>, /* QUSB4 0 PHY RX 1 */ + <0>, /* QUSB4 1 PHY RX 0 */ + <0>, /* QUSB4 1 PHY RX 1 */ + <0>, /* QUSB4 2 PHY RX 0 */ + <0>, /* QUSB4 2 PHY RX 1 */ + <0>, /* UFS PHY RX Symbol 0 */ + <0>, /* UFS PHY RX Symbol 1 */ + <0>, /* UFS PHY TX Symbol 0 */ + <0>, /* USB3 PHY 0 */ + <0>, /* USB3 PHY 1 */ + <0>, /* USB3 PHY 2 */ + <0>, /* USB3 UNI PHY pipe 0 */ + <0>, /* USB3 UNI PHY pipe 1 */ + <0>, /* USB4 PHY 0 pcie pipe */ + <0>, /* USB4 PHY 0 Max pipe */ + <0>, /* USB4 PHY 1 pcie pipe */ + <0>, /* USB4 PHY 1 Max pipe */ + <0>, /* USB4 PHY 2 pcie */ + <0>; /* USB4 PHY 2 Max */ + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + gpi_dma2: dma-controller@800000 { + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00800000 0x0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <16>; + dma-channel-mask = <0x3f>; + #dma-cells = <3>; + iommus = <&apps_smmu 0xd76 0x0>; + }; + + qupv3_2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x3000>; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + iommus = <&apps_smmu 0xd63 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c16: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00880000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c16_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi16: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00880000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c17: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00884000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c17_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi17: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00884000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c18: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c18_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi18: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c19: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c19_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi19: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart19: serial@88c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart19_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c20: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c20_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi20: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c21: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c21_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi21: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart21: serial@894000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart21_default>; + pinctrl-names = "default"; + }; + + i2c22: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, + <&gpi_dma2 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c22_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi22: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, + <&gpi_dma2 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart22: serial@898000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart22_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c23: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0089c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, + <&gpi_dma2 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c23_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi23: spi@89c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0089c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, + <&gpi_dma2 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00a00000 0x0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <16>; + dma-channel-mask = <0x3f>; + #dma-cells = <3>; + iommus = <&apps_smmu 0xcb6 0x0>; + }; + + qupv3_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x3000>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + iommus = <&apps_smmu 0xca3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c8_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c9_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c10_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c11_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c12_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c13_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a98000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c14_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi14: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a98000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart14: serial@a98000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a98000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart14_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a9c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c15_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi15: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a9c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gpi_dma0: dma-controller@b00000 { + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00b00000 0x0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <16>; + dma-channel-mask = <0x3f>; + #dma-cells = <3>; + iommus = <&apps_smmu 0xd36 0x0>; + }; + + qupv3_0: geniqup@bc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00bc0000 0x0 0x3000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + iommus = <&apps_smmu 0xd23 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c0: i2c@b80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c0_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi0: spi@b80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c1: i2c@b84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c1_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi1: spi@b84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c2: i2c@b88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c2_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi2: spi@b88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart2: serial@b88000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00b88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart2_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c3: i2c@b8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi3: spi@b8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c4: i2c@b90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c4_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi4: spi@b90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c5: i2c@b94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c5_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi5: spi@b94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c6: i2c@b98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b98000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c6_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi6: spi@b98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b98000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c7: i2c@b9c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b9c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c7_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi7: spi@b9c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b9c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,glymur-cnoc-main"; + reg = <0x0 0x01500000 0x0 0x17080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,glymur-cnoc-cfg"; + reg = <0x0 0x01600000 0x0 0x6600>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,glymur-system-noc"; + reg = <0x0 0x01680000 0x0 0x1c080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie_west_anoc: interconnect@16c0000 { + compatible = "qcom,glymur-pcie-west-anoc"; + reg = <0x0 0x016c0000 0x0 0xf580>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; + }; + + pcie_east_anoc: interconnect@16d0000 { + compatible = "qcom,glymur-pcie-east-anoc"; + reg = <0x0 0x016d0000 0x0 0xf300>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,glymur-aggre1-noc"; + reg = <0x0 0x016e0000 0x0 0x14400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + aggre2_noc: interconnect@1720000 { + compatible = "qcom,glymur-aggre2-noc"; + reg = <0x0 0x01720000 0x0 0x14400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_2_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; + }; + + aggre3_noc: interconnect@1700000 { + compatible = "qcom,glymur-aggre3-noc"; + reg = <0x0 0x01700000 0x0 0x1d400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + aggre4_noc: interconnect@1740000 { + compatible = "qcom,glymur-aggre4-noc"; + reg = <0x0 0x01740000 0x0 0x14400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_0_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_1_AXI_CLK>; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,glymur-mmss-noc"; + reg = <0x0 0x01780000 0x0 0x5b800>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie_east_slv_noc: interconnect@1900000 { + compatible = "qcom,glymur-pcie-east-slv-noc"; + reg = <0x0 0x01900000 0x0 0xe080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie_west_slv_noc: interconnect@1920000 { + compatible = "qcom,glymur-pcie-west-slv-noc"; + reg = <0x0 0x01920000 0x0 0xf180>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie4: pci@1bf0000 { + device_type = "pci"; + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg = <0x0 0x01bf0000 0x0 0x3000>, + <0x0 0x78000000 0x0 0xf20>, + <0x0 0x78000f40 0x0 0xa8>, + <0x0 0x78001000 0x0 0x4000>, + <0x0 0x78005000 0x0 0x100000>, + <0x0 0x01bf3000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x78105000 0x0 0x100000>, + <0x02000000 0x0 0x78205000 0x0 0x78205000 0x0 0x1dfb000>, + <0x03000000 0x7 0x80000000 0x7 0x80000000 0x0 0x20000000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <4>; + num-lanes = <2>; + + operating-points-v2 = <&pcie4_opp_table>; + + msi-map = <0x0 &gic_its 0xc0000 0x10000>; + iommu-map = <0x0 &pcie_smmu 0x40000 0x10000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 513 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 514 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 515 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 516 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_west_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_4_BCR>, + <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_4_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55>; + + status = "disabled"; + + pcie4_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <4>; + }; + + }; + + pcie4_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie4_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie4_phy: phy@1bf6000 { + compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; + reg = <0x0 0x01bf6000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_PHY_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_2_CLKREF_EN>, + <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_4_PIPE_CLK>, + <&gcc GCC_PCIE_4_PIPE_DIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_4_PHY_BCR>, + <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie4_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie5: pci@1b40000 { + device_type = "pci"; + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg = <0x0 0x01b40000 0x0 0x3000>, + <0x0 0x7a000000 0x0 0xf20>, + <0x0 0x7a000f40 0x0 0xa8>, + <0x0 0x7a001000 0x0 0x4000>, + <0x0 0x7a100000 0x0 0x100000>, + <0x0 0x01b43000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x7a200000 0x0 0x100000>, + <0x02000000 0x0 0x7a300000 0x0 0x7a300000 0x0 0x3d00000>, + <0x03000000 0x7 0xa0000000 0x7 0xa0000000 0x0 0x40000000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <5>; + num-lanes = <4>; + + operating-points-v2 = <&pcie5_opp_table>; + + msi-map = <0x0 &gic_its 0xd0000 0x10000>; + iommu-map = <0x0 &pcie_smmu 0x50000 0x10000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 526 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 428 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 429 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_5_AUX_CLK>, + <&gcc GCC_PCIE_5_CFG_AHB_CLK>, + <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_5_SLV_AXI_CLK>, + <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_east_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_east_slv_noc SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_5_BCR>, + <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_5_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + + status = "disabled"; + + pcie5_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* GEN 1 x4 */ + opp-10000000-1 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* GEN 2 x4 */ + opp-20000000-2 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <2000000 1>; + opp-level = <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + + /* GEN 3 x4 */ + opp-32000000-3 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <4>; + }; + + /* GEN 4 x4 */ + opp-64000000-4 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <7876000 1>; + opp-level = <4>; + }; + + /* GEN 5 x1 */ + opp-32000000-5 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + opp-level = <5>; + }; + + /* GEN 5 x2 */ + opp-64000000-5 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <7876000 1>; + opp-level = <5>; + }; + + /* GEN 5 x4 */ + opp-128000000-5 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <15753000 1>; + opp-level = <5>; + }; + }; + + pcie5_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie5_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie5_phy: phy@1b50000 { + compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; + reg = <0x0 0x01b50000 0x0 0x10000>; + + clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>, + <&gcc GCC_PCIE_5_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_5_PIPE_CLK>, + <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_5_PHY_BCR>, + <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie5_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie6: pci@1c00000 { + device_type = "pci"; + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x7e000000 0x0 0xf20>, + <0x0 0x7e000f40 0x0 0xa8>, + <0x0 0x7e001000 0x0 0x4000>, + <0x0 0x7e100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, + <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>, + <0x03000000 0x7 0xe0000000 0x7 0xe0000000 0x0 0x20000000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <6>; + num-lanes = <2>; + + operating-points-v2 = <&pcie6_opp_table>; + + msi-map = <0x0 &gic_its 0xe0000 0x10000>; + iommu-map = <0x0 &pcie_smmu 0x60000 0x10000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 472 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 473 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 474 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 475 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_6_AUX_CLK>, + <&gcc GCC_PCIE_6_CFG_AHB_CLK>, + <&gcc GCC_PCIE_6_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_6_SLV_AXI_CLK>, + <&gcc GCC_PCIE_6_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks = <&gcc GCC_PCIE_6_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_west_anoc MASTER_PCIE_6 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_6 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_6_BCR>, + <&gcc GCC_PCIE_6_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_6_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55>; + + status = "disabled"; + + pcie6_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <4>; + }; + + }; + + pcie6_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie6_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie6_phy: phy@1c06000 { + compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; + reg = <0x0 0x01c06000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_PHY_6_AUX_CLK>, + <&gcc GCC_PCIE_6_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_4_CLKREF_EN>, + <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_6_PIPE_CLK>, + <&gcc GCC_PCIE_6_PIPE_DIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_6_PHY_BCR>, + <&gcc GCC_PCIE_6_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie6_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie3b: pci@1b80000 { + device_type = "pci"; + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg = <0x0 0x01b80000 0x0 0x3000>, + <0x0 0x74000000 0x0 0xf20>, + <0x0 0x74000f40 0x0 0xa8>, + <0x0 0x74001000 0x0 0x4000>, + <0x0 0x74100000 0x0 0x100000>, + <0x0 0x01b83000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x74200000 0x0 0x100000>, + <0x02000000 0x0 0x74300000 0x0 0x74300000 0x0 0x3d00000>, + <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <7>; + num-lanes = <4>; + + operating-points-v2 = <&pcie3b_opp_table>; + + msi-map = <0x0 &gic_its 0xf0000 0x10000>; + iommu-map = <0x0 &pcie_smmu 0x70000 0x10000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 831 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 832 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 833 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 834 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_west_anoc MASTER_PCIE_3B QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_3B QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_3B_BCR>, + <&gcc GCC_PCIE_3B_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_3B_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + + status = "disabled"; + + pcie3b_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* GEN 1 x4 */ + opp-10000000-1 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* GEN 2 x4 */ + opp-20000000-2 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <2000000 1>; + opp-level = <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + + /* GEN 3 x4 */ + opp-32000000-3 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <4>; + }; + + /* GEN 4 x4 */ + opp-64000000-4 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <7876000 1>; + opp-level = <4>; + }; + + /* GEN 5 x1 */ + opp-32000000-5 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + opp-level = <5>; + }; + + /* GEN 5 x2 */ + opp-64000000-5 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <7876000 1>; + opp-level = <5>; + }; + + /* GEN 5 x4 */ + opp-128000000-5 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <15753000 1>; + opp-level = <5>; + }; + }; + + pcie3b_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie3b_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie3b_phy: phy@f10000 { + compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; + reg = <0x0 0x00f10000 0x0 0x10000>; + + clocks = <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_3_CLKREF_EN>, + <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3B_PIPE_CLK>, + <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_3B_PHY_BCR>, + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_3B_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie3b_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x20000>; + + #hwlock-cells = <1>; + }; + + tcsr: clock-controller@1fd5000 { + compatible = "qcom,glymur-tcsr", + "syscon"; + reg = <0x0 0x1fd5000 0x0 0x21000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + hsc_noc: interconnect@2000000 { + compatible = "qcom,glymur-hscnoc"; + reg = <0x0 0x02000000 0x0 0x93a080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + ipcc: mailbox@3e04000 { + compatible = "qcom,glymur-ipcc", "qcom,ipcc"; + reg = <0x0 0x03e04000 0x0 0x1000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + + #mbox-cells = <2>; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible = "qcom,glymur-lpass-lpiaon-noc"; + reg = <0x0 0x07400000 0x0 0x19080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + lpass_lpicx_noc: interconnect@7420000 { + compatible = "qcom,glymur-lpass-lpicx-noc"; + reg = <0x0 0x07420000 0x0 0x44080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + lpass_ag_noc: interconnect@7e40000 { + compatible = "qcom,glymur-lpass-ag-noc"; + reg = <0x0 0x07e40000 0x0 0xe080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,glymur-dispcc"; + reg = <0x0 0x0af00000 0x0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, /* dp0 */ + <0>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>, + <0>, /* dsi0 */ + <0>, + <0>, /* dsi1 */ + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,glymur-pdc", "qcom,pdc"; + reg = <0x0 0x0b220000 0x0 0x10000>; + qcom,pdc-ranges = <0 745 51>, + <51 527 47>, + <98 609 32>, + <130 717 12>, + <142 251 5>, + <147 796 16>, + <171 4104 36>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c22c000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22c000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <13>; + + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c22d000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22d000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <9>; + + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c22e000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22e000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <13>; + + #thermal-sensor-cells = <1>; + }; + + tsens3: thermal-sensor@c22f000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22f000 0x0 0x1000>, + <0x0 0x0c225000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <8>; + + #thermal-sensor-cells = <1>; + }; + + tsens4: thermal-sensor@c230000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c230000 0x0 0x1000>, + <0x0 0x0c226000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <13>; + + #thermal-sensor-cells = <1>; + }; + + tsens5: thermal-sensor@c231000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c231000 0x0 0x1000>, + <0x0 0x0c227000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <8>; + + #thermal-sensor-cells = <1>; + }; + + tsens6: thermal-sensor@c232000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c232000 0x0 0x1000>, + <0x0 0x0c228000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <13>; + + #thermal-sensor-cells = <1>; + }; + + tsens7: thermal-sensor@c233000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c233000 0x0 0x1000>, + <0x0 0x0c229000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <15>; + + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible = "qcom,glymur-aoss-qmp", "qcom,aoss-qmp"; + reg = <0x0 0x0c300000 0x0 0x400>; + interrupt-parent = <&ipcc>; + interrupts-extended = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + sram@c30f000 { + compatible = "qcom,rpmh-stats"; + reg = <0x0 0x0c30f000 0x0 0x400>; + }; + + arbiter@c400000 { + compatible = "qcom,glymur-spmi-pmic-arb"; + reg = <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c900000 0x0 0x400000>, + <0x0 0x0c4c0000 0x0 0x400000>, + <0x0 0x0c403000 0x0 0x8000>; + reg-names = "core", + "chnls", + "obsrvr", + "chnl_map"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + qcom,channel = <0>; + qcom,ee = <0>; + + spmi_bus0: spmi@c426000 { + reg = <0x0 0x0c426000 0x0 0x4000>, + <0x0 0x0c8c0000 0x0 0x10000>, + <0x0 0x0c42a000 0x0 0x8000>; + reg-names = "cnfg", + "intr", + "chnl_owner"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + + spmi_bus1: spmi@c437000 { + reg = <0x0 0x0c437000 0x0 0x4000>, + <0x0 0x0c8d0000 0x0 0x10000>, + <0x0 0x0c43b000 0x0 0x8000>; + reg-names = "cnfg", + "intr", + "chnl_owner"; + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + + spmi_bus2: spmi@c48000 { + reg = <0x0 0x0c448000 0x0 0x4000>, + <0x0 0x0c8e0000 0x0 0x10000>, + <0x0 0x0c44c000 0x0 0x8000>; + reg-names = "cnfg", + "intr", + "chnl_owner"; + interrupts-extended = <&pdc 72 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,glymur-tlmm"; + reg = <0x0 0x0f100000 0x0 0xf00000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 249>; + wakeup-parent = <&pdc>; + + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio0", "gpio1"; + function = "qup0_se0"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio4", "gpio5"; + function = "qup0_se1"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio8", "gpio9"; + function = "qup0_se2"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio12", "gpio13"; + function = "qup0_se3"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + /* SDA, SCL */ + pins = "gpio16", "gpio17"; + function = "qup0_se4"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins = "gpio20", "gpio21"; + function = "qup0_se5"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins = "gpio6", "gpio7"; + function = "qup0_se6"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins = "gpio14", "gpio15"; + function = "qup0_se7"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + /* SDA, SCL */ + pins = "gpio32", "gpio33"; + function = "qup1_se0"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + /* SDA, SCL */ + pins = "gpio36", "gpio37"; + function = "qup1_se1"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + /* SDA, SCL */ + pins = "gpio40", "gpio41"; + function = "qup1_se2"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + /* SDA, SCL */ + pins = "gpio44", "gpio45"; + function = "qup1_se3"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + /* SDA, SCL */ + pins = "gpio48", "gpio49"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + /* SDA, SCL */ + pins = "gpio52", "gpio53"; + function = "qup1_se5"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + /* SDA, SCL */ + pins = "gpio56", "gpio57"; + function = "qup1_se6"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + /* SDA, SCL */ + pins = "gpio54", "gpio55"; + function = "qup1_se7"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c16_data_clk: qup-i2c16-data-clk-state { + /* SDA, SCL */ + pins = "gpio64", "gpio65"; + function = "qup2_se0"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c17_data_clk: qup-i2c17-data-clk-state { + /* SDA, SCL */ + pins = "gpio68", "gpio69"; + function = "qup2_se1"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c18_data_clk: qup-i2c18-data-clk-state { + /* SDA, SCL */ + pins = "gpio72", "gpio73"; + function = "qup2_se2"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c19_data_clk: qup-i2c19-data-clk-state { + /* SDA, SCL */ + pins = "gpio76", "gpio77"; + function = "qup2_se3"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c20_data_clk: qup-i2c20-data-clk-state { + /* SDA, SCL */ + pins = "gpio80", "gpio81"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c21_data_clk: qup-i2c21-data-clk-state { + /* SDA, SCL */ + pins = "gpio84", "gpio85"; + function = "qup2_se5"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c22_data_clk: qup-i2c22-data-clk-state { + /* SDA, SCL */ + pins = "gpio88", "gpio89"; + function = "qup2_se6"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c23_data_clk: qup-i2c23-data-clk-state { + /* SDA, SCL */ + pins = "gpio80", "gpio81"; + function = "qup2_se7"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio3"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio0", "gpio1", "gpio2"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio7"; + function = "qup0_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio4", "gpio5", "gpio6"; + function = "qup0_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio11"; + function = "qup0_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio8", "gpio9", "gpio10"; + function = "qup0_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio15"; + function = "qup0_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio12", "gpio13", "gpio14"; + function = "qup0_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins = "gpio19"; + function = "qup0_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio16", "gpio17", "gpio18"; + function = "qup0_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins = "gpio23"; + function = "qup0_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio20", "gpio21", "gpio22"; + function = "qup0_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio5"; + function = "qup0_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio6", "gpio7", "gpio4"; + function = "qup0_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi7_cs: qup-spi7-cs-state { + pins = "gpio13"; + function = "qup0_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi7_data_clk: qup-spi7-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio14", "gpio15", "gpio12"; + function = "qup0_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins = "gpio35"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio32", "gpio33", "gpio34"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins = "gpio39"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio36", "gpio37", "gpio38"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio43"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio40", "gpio41", "gpio42"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins = "gpio47"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + pins = "gpio44", "gpio45", "gpio46"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi12_cs: qup-spi12-cs-state { + pins = "gpio51"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi12_data_clk: qup-spi12-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio48", "gpio49", "gpio50"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi13_cs: qup-spi13-cs-state { + pins = "gpio55"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi13_data_clk: qup-spi13-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio52", "gpio53", "gpio54"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi14_cs: qup-spi14-cs-state { + pins = "gpio59"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi14_data_clk: qup-spi14-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio56", "gpio57", "gpio58"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins = "gpio53"; + function = "qup1_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio54", "gpio55", "gpio52"; + function = "qup1_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi16_cs: qup-spi16-cs-state { + pins = "gpio67"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi16_data_clk: qup-spi16-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio64", "gpio65", "gpio66"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi17_cs: qup-spi17-cs-state { + pins = "gpio71"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi17_data_clk: qup-spi17-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio68", "gpio69", "gpio70"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi18_cs: qup-spi18-cs-state { + pins = "gpio75"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi18_data_clk: qup-spi18-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio72", "gpio73", "gpio74"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi19_cs: qup-spi19-cs-state { + pins = "gpio79"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi19_data_clk: qup-spi19-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio76", "gpio77", "gpio78"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi20_cs: qup-spi20-cs-state { + pins = "gpio83"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi20_data_clk: qup-spi20-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio80", "gpio81", "gpio82"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi21_cs: qup-spi21-cs-state { + pins = "gpio87"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi21_data_clk: qup-spi21-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio84", "gpio85", "gpio86"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi22_cs: qup-spi22-cs-state { + pins = "gpio91"; + function = "qup2_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi22_data_clk: qup-spi22-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio88", "gpio89", "gpio90"; + function = "qup2_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi23_cs: qup-spi23-cs-state { + pins = "gpio83"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi23_data_clk: qup-spi23-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio80", "gpio81", "gpio82"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_uart2_default: qup-uart2-default-state { + tx-pins { + pins = "gpio10"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio11"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_uart14_default: qup-uart14-default-state { + cts-pins { + pins = "gpio56"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + + rts-pins { + pins = "gpio57"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + + tx-pins { + pins = "gpio58"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio59"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_uart19_default: qup-uart19-default-state { + cts-pins { + pins = "gpio76"; + function = "qup2_se3"; + drive-strength = <2>; + bias-disable; + }; + + rts-pins { + pins = "gpio77"; + function = "qup2_se3"; + drive-strength = <2>; + bias-disable; + }; + + tx-pins { + pins = "gpio78"; + function = "qup2_se3"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio79"; + function = "qup2_se3"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_uart21_default: qup-uart21-default-state { + tx-pins { + pins = "gpio86"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio87"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_uart22_default: qup-uart22-default-state { + tx-pins { + pins = "gpio90"; + function = "qup2_se6"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio91"; + function = "qup2_se6"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,glymur-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + dma-coherent; + }; + + pcie_smmu: iommu@15480000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x15480000 0x0 0x20000>; + interrupts = , + , + ; + interrupt-names = "eventq", "cmdq-sync", "gerror"; + dma-coherent; + #iommu-cells = <1>; + }; + + intc: interrupt-controller@17000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17000000 0x0 0x10000>, + <0x0 0x17080000 0x0 0x480000>; + + interrupts = ; + + #interrupt-cells = <3>; + interrupt-controller; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic_its: msi-controller@17040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x17040000 0x0 0x40000>; + + msi-controller; + #msi-cells = <1>; + }; + }; + + watchdog@17600000 { + compatible = "qcom,apss-wdt-glymur", "qcom,kpss-wdt"; + reg = <0x0 0x17600000 0x0 0x1000>; + clocks = <&sleep_clk>; + interrupts = ; + }; + + pdp0_mbox: mailbox@17610000 { + compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg = <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; + interrupts = ; + #mbox-cells = <1>; + }; + + timer@17810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17810000 0x0 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x0 0x20000000>; + + frame@17811000 { + reg = <0x0 0x17811000 0x1000>, + <0x0 0x17812000 0x1000>; + + interrupts = , + ; + + frame-number = <0>; + }; + + frame@17813000 { + reg = <0x0 0x17813000 0x1000>; + + interrupts = ; + + frame-number = <1>; + + status = "disabled"; + }; + + frame@17815000 { + reg = <0x0 0x17815000 0x1000>; + + interrupts = ; + + frame-number = <2>; + + status = "disabled"; + }; + + frame@17817000 { + reg = <0x0 0x17817000 0x1000>; + + interrupts = ; + + frame-number = <3>; + + status = "disabled"; + }; + + frame@17819000 { + reg = <0x0 0x17819000 0x1000>; + + interrupts = ; + + frame-number = <4>; + + status = "disabled"; + }; + + frame@1781b000 { + reg = <0x0 0x1781b000 0x1000>; + + interrupts = ; + + frame-number = <5>; + + status = "disabled"; + }; + + frame@1781d000 { + reg = <0x0 0x1781d000 0x1000>; + + interrupts = ; + + frame-number = <6>; + + status = "disabled"; + }; + }; + + apps_rsc: rsc@18900000 { + compatible = "qcom,rpmh-rsc"; + label = "apps_rsc"; + reg = <0x0 0x18900000 0x0 0x10000>, + <0x0 0x18910000 0x0 0x10000>, + <0x0 0x18920000 0x0 0x10000>; + reg-names = "drv-0", + "drv-1", + "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + power-domains = <&system_pd>; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,glymur-rpmh-clk"; + + clocks = <&xo_board>; + clock-names = "xo"; + + #clock-cells = <1>; + }; + + rpmhpd: power-controller { + compatible = "qcom,glymur-rpmhpd"; + + operating-points-v2 = <&rpmhpd_opp_table>; + + #power-domain-cells = <1>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp-48 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d2: opp-52 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d0: opp-60 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_l1: opp-80 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level = ; + }; + + rpmhpd_opp_svs_l0: opp-144 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level = ; + }; + }; + }; + }; + + nsi_noc: interconnect@1d600000 { + compatible = "qcom,glymur-nsinoc"; + reg = <0x0 0x1d600000 0x0 0x14080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + oobm_ss_noc: interconnect@1f300000 { + compatible = "qcom,glymur-oobm-ss-noc"; + reg = <0x0 0x1f300000 0x0 0x49a00>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + system-cache-controller@20400000 { + compatible = "qcom,glymur-llcc"; + reg = <0x0 0x21800000 0x0 0x100000>, + <0x0 0x21a00000 0x0 0x100000>, + <0x0 0x21c00000 0x0 0x100000>, + <0x0 0x21e00000 0x0 0x100000>, + <0x0 0x22800000 0x0 0x100000>, + <0x0 0x22a00000 0x0 0x100000>, + <0x0 0x22c00000 0x0 0x100000>, + <0x0 0x22e00000 0x0 0x100000>, + <0x0 0x23800000 0x0 0x100000>, + <0x0 0x23a00000 0x0 0x100000>, + <0x0 0x23c00000 0x0 0x100000>, + <0x0 0x23e00000 0x0 0x100000>, + <0x0 0x20400000 0x0 0x100000>, + <0x0 0x20600000 0x0 0x100000>; + reg-names = "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc4_base", + "llcc5_base", + "llcc6_base", + "llcc7_base", + "llcc8_base", + "llcc9_base", + "llcc10_base", + "llcc11_base", + "llcc_broadcast_base", + "llcc_broadcast_and_base"; + + interrupts = ; + }; + + nsp_noc: interconnect@320c0000 { + compatible = "qcom,glymur-nsp-noc"; + reg = <0x0 0x320c0000 0x0 0x21280>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + imem: sram@81e08000 { + compatible = "mmio-sram"; + reg = <0x0 0x81e08600 0x0 0x300>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81e08600 0x300>; + + cpu_scp_lpri0: scp-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x180>; + }; + + cpu_scp_lpri1: scp-sram-section@180 { + compatible = "arm,scmi-shmem"; + reg = <0x180 0x180>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + }; + + thermal_zones: thermal-zones { + aoss-0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + aoss-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-0-0-thermal { + thermal-sensors = <&tsens0 1>; + + trips { + cpu-0-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-0-1-thermal { + thermal-sensors = <&tsens0 2>; + + trips { + cpu-0-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-1-0-thermal { + thermal-sensors = <&tsens0 3>; + + trips { + cpu-0-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-1-1-thermal { + thermal-sensors = <&tsens0 4>; + + trips { + cpu-0-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-2-0-thermal { + thermal-sensors = <&tsens0 5>; + + trips { + cpu-0-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-2-1-thermal { + thermal-sensors = <&tsens0 6>; + + trips { + cpu-0-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-3-0-thermal { + thermal-sensors = <&tsens0 7>; + + trips { + cpu-0-3-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-3-1-thermal { + thermal-sensors = <&tsens0 8>; + + trips { + cpu-0-3-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-4-0-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + cpu-0-4-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-4-1-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + cpu-0-4-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-5-0-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + cpu-0-5-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-5-1-thermal { + thermal-sensors = <&tsens0 12>; + + trips { + cpu-0-5-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-1-thermal { + thermal-sensors = <&tsens1 0>; + + trips { + aoss-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpullc-0-0-thermal { + thermal-sensors = <&tsens1 1>; + + trips { + cpullc-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpullc-0-1-thermal { + thermal-sensors = <&tsens1 2>; + + trips { + cpullc-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-0-0-thermal { + thermal-sensors = <&tsens1 3>; + + trips { + qmx-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-0-1-thermal { + thermal-sensors = <&tsens1 4>; + + trips { + qmx-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-0-2-thermal { + thermal-sensors = <&tsens1 5>; + + trips { + qmx-0-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ddr-0-thermal { + thermal-sensors = <&tsens1 6>; + + trips { + ddr-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + video-0-thermal { + thermal-sensors = <&tsens1 7>; + + trips { + video-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + video-1-thermal { + thermal-sensors = <&tsens1 8>; + + trips { + video-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-2-thermal { + thermal-sensors = <&tsens2 0>; + + trips { + aoss-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-0-0-thermal { + thermal-sensors = <&tsens2 1>; + + trips { + cpu-1-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-0-1-thermal { + thermal-sensors = <&tsens2 2>; + + trips { + cpu-1-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-1-0-thermal { + thermal-sensors = <&tsens2 3>; + + trips { + cpu-1-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-1-1-thermal { + thermal-sensors = <&tsens2 4>; + + trips { + cpu-1-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-2-0-thermal { + thermal-sensors = <&tsens2 5>; + + trips { + cpu-1-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-2-1-thermal { + thermal-sensors = <&tsens2 6>; + + trips { + cpu-1-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-3-0-thermal { + thermal-sensors = <&tsens2 7>; + + trips { + cpu-1-3-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-3-1-thermal { + thermal-sensors = <&tsens2 8>; + + trips { + cpu-1-3-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-4-0-thermal { + thermal-sensors = <&tsens2 9>; + + trips { + cpu-1-4-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-4-1-thermal { + thermal-sensors = <&tsens2 10>; + + trips { + cpu-1-4-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-5-0-thermal { + thermal-sensors = <&tsens2 11>; + + trips { + cpu-1-5-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-5-1-thermal { + thermal-sensors = <&tsens2 12>; + + trips { + cpu-1-5-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-3-thermal { + thermal-sensors = <&tsens3 0>; + + trips { + aoss-3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpullc-1-0-thermal { + thermal-sensors = <&tsens3 1>; + + trips { + cpullc-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpullc-1-1-thermal { + thermal-sensors = <&tsens3 2>; + + trips { + cpullc-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-1-0-thermal { + thermal-sensors = <&tsens3 3>; + + trips { + qmx-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-1-1-thermal { + thermal-sensors = <&tsens3 4>; + + trips { + qmx-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-1-2-thermal { + thermal-sensors = <&tsens3 5>; + + trips { + qmx-1-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-1-3-thermal { + thermal-sensors = <&tsens3 6>; + + trips { + qmx-1-3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-1-4-thermal { + thermal-sensors = <&tsens3 7>; + + trips { + qmx-1-4-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-4-thermal { + thermal-sensors = <&tsens4 0>; + + trips { + aoss-4-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-0-0-thermal { + thermal-sensors = <&tsens4 1>; + + trips { + cpu-2-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-0-1-thermal { + thermal-sensors = <&tsens4 2>; + + trips { + cpu-2-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-1-0-thermal { + thermal-sensors = <&tsens4 3>; + + trips { + cpu-2-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-1-1-thermal { + thermal-sensors = <&tsens4 4>; + + trips { + cpu-2-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-2-0-thermal { + thermal-sensors = <&tsens4 5>; + + trips { + cpu-2-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-2-1-thermal { + thermal-sensors = <&tsens4 6>; + + trips { + cpu-2-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-3-0-thermal { + thermal-sensors = <&tsens4 7>; + + trips { + cpu-2-3-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-3-1-thermal { + thermal-sensors = <&tsens4 8>; + + trips { + cpu-2-3-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-4-0-thermal { + thermal-sensors = <&tsens4 9>; + + trips { + cpu-2-4-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-4-1-thermal { + thermal-sensors = <&tsens4 10>; + + trips { + cpu-2-4-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-5-0-thermal { + thermal-sensors = <&tsens4 11>; + + trips { + cpu-2-5-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-2-5-1-thermal { + thermal-sensors = <&tsens4 12>; + + trips { + cpu-2-5-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-5-thermal { + thermal-sensors = <&tsens5 0>; + + trips { + aoss-5-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpullc-2-0-thermal { + thermal-sensors = <&tsens5 1>; + + trips { + cpullc-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuillc-2-1-thermal { + thermal-sensors = <&tsens5 2>; + + trips { + cpullc-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-2-0-thermal { + thermal-sensors = <&tsens5 3>; + + trips { + qmx-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-2-1-thermal { + thermal-sensors = <&tsens5 4>; + + trips { + qmx-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-2-2-thermal { + thermal-sensors = <&tsens5 5>; + + trips { + qmx-2-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-2-3-thermal { + thermal-sensors = <&tsens5 6>; + + trips { + qmx-2-3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-2-4-thermal { + thermal-sensors = <&tsens5 7>; + + trips { + qmx-2-4-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-6-thermal { + thermal-sensors = <&tsens6 0>; + + trips { + aoss-6-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsphvx-0-thermal { + thermal-sensors = <&tsens6 1>; + + trips { + nsphvx-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsphvx-1-thermal { + thermal-sensors = <&tsens6 2>; + + trips { + nsphvx-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsphvx-2-thermal { + thermal-sensors = <&tsens6 3>; + + trips { + nsphvx-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsphvx-3-thermal { + thermal-sensors = <&tsens6 4>; + + trips { + nsphvx-3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsphmx-0-thermal { + thermal-sensors = <&tsens6 5>; + + trips { + nsphmx-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsphmx-1-thermal { + thermal-sensors = <&tsens6 6>; + + trips { + nsphmx-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsphmx-2-thermal { + thermal-sensors = <&tsens6 7>; + + trips { + nsphmx-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsphmx-3-thermal { + thermal-sensors = <&tsens6 8>; + + trips { + nsphmx-3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camera-0-thermal { + thermal-sensors = <&tsens6 9>; + + trips { + camera-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camera-1-thermal { + thermal-sensors = <&tsens6 10>; + + trips { + camera-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ddr-1-thermal { + thermal-sensors = <&tsens6 11>; + + trips { + ddr-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ddr-2-thermal { + thermal-sensors = <&tsens6 12>; + + trips { + ddr-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-7-thermal { + thermal-sensors = <&tsens7 0>; + + trips { + aoss-7-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-0-0-thermal { + thermal-sensors = <&tsens7 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-0-1-thermal { + thermal-sensors = <&tsens7 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-0-2-thermal { + thermal-sensors = <&tsens7 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-0-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-1-0-thermal { + thermal-sensors = <&tsens7 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-1-1-thermal { + thermal-sensors = <&tsens7 5>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-1-2-thermal { + thermal-sensors = <&tsens7 6>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-1-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-2-0-thermal { + thermal-sensors = <&tsens7 7>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-2-1-thermal { + thermal-sensors = <&tsens7 8>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-2-2-thermal { + thermal-sensors = <&tsens7 9>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-2-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-3-0-thermal { + thermal-sensors = <&tsens7 10>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-3-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-3-1-thermal { + thermal-sensors = <&tsens7 11>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-3-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-3-2-thermal { + thermal-sensors = <&tsens7 12>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-3-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-0-thermal { + thermal-sensors = <&tsens7 13>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-1-thermal { + thermal-sensors = <&tsens7 14>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi new file mode 100644 index 000000000000..c3ccd2b75609 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmcx0102-c0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmcx0102_c_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmcx0102-c1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmcx0102_c_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmcx0102-d0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmcx0102_d_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmcx0102-d1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmcx0102_d_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pmcx0102_c_e0: pmic@2 { + compatible = "qcom,pmcx0102", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmcx0102_c_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmcx0102_c_e0_gpios: gpio@8800 { + compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmcx0102_c_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmcx0102_d_e0: pmic@3 { + compatible = "qcom,pmcx0102", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmcx0102_d_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmcx0102_d_e0_gpios: gpio@8800 { + compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmcx0102_d_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&spmi_bus1 { + pmcx0102_c_e1: pmic@2 { + compatible = "qcom,pmcx0102", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmcx0102_c_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmcx0102_c_e1_gpios: gpio@8800 { + compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmcx0102_c_e1_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmcx0102_d_e1: pmic@3 { + compatible = "qcom,pmcx0102", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmcx0102_d_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmcx0102_d_e1_gpios: gpio@8800 { + compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmcx0102_d_e1_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0101.dtsi b/arch/arm64/boot/dts/qcom/pmh0101.dtsi new file mode 100644 index 000000000000..b1ec41325958 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmh0101.dtsi @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmh0101-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0101_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pmic@1 { + compatible = "qcom,pmh0101", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0101_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0101_gpios: gpio@8800 { + compatible = "qcom,pmh0101-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0101_gpios 0 0 18>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmh0101_flash: led-controller@ee00 { + compatible = "qcom,pmh0101-flash-led", "qcom,spmi-flash-led"; + reg = <0xee00>; + status = "disabled"; + }; + + pmh0101_pwm: pwm { + compatible = "qcom,pmh0101-pwm", "qcom,pm8350c-pwm"; + #pwm-cells = <2>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi new file mode 100644 index 000000000000..d89cceda53a3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/{ + thermal_zones { + pmh0104-i0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0104_i_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0104-j0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0104_j_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0104-l1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0104_l_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pmh0104_i_e0: pmic@8 { + compatible = "qcom,pmh0104", "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0104_i_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0104_i_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0104_i_e0_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmh0104_j_e0: pmic@9 { + compatible = "qcom,pmh0104", "qcom,spmi-pmic"; + reg = <0x9 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0104_j_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0104_j_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0104_j_e0_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&spmi_bus1 { + pmh0104_l_e1: pmic@b { + compatible = "qcom,pmh0104", "qcom,spmi-pmic"; + reg = <0xb SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0104_l_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0xb 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0104_l_e1_gpios: gpio@8800 { + compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0104_l_e1_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi b/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi new file mode 100644 index 000000000000..7655bc030348 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmh0110-f0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0110_f_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0110-f1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0110_f_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0110-h0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0110_h_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pmh0110_f_e0: pmic@5 { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0110_f_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0110_f_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_f_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmh0110_h_e0: pmic@7 { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0110_h_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0110_h_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_h_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&spmi_bus1 { + pmh0110_f_e1: pmic@5 { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0110_f_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0110_f_e1_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_f_e1_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmk8850.dtsi b/arch/arm64/boot/dts/qcom/pmk8850.dtsi new file mode 100644 index 000000000000..c7ba72fd48bc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmk8850.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +&spmi_bus0 { + pmic@0 { + compatible = "qcom,pmk8850", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmk8850_pon: pon@1300 { + compatible = "qcom,pmk8350-pon"; + reg = <0x1300>, + <0x800>; + reg-names = "hlos", + "pbs"; + + pon_pwrkey: pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + + pon_resin: resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + status = "disabled"; + }; + }; + + pmk8850_gpios: gpio@b800 { + compatible = "qcom,pmk8850-gpio", "qcom,spmi-gpio"; + reg = <0xb800>; + gpio-controller; + gpio-ranges = <&pmk8850_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmk8850_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, + <0x6200>; + reg-names = "rtc", + "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pmk8850_sdam_2: nvram@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x7100 0x100>; + + reboot_reason: reboot-reason@48 { + reg = <0x48 0x1>; + bits = <1 7>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/smb2370.dtsi b/arch/arm64/boot/dts/qcom/smb2370.dtsi new file mode 100644 index 000000000000..80f3fdae5705 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/smb2370.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +&spmi_bus2 { + smb2370_j_e2: pmic@9 { + compatible = "qcom,smb2370", "qcom,spmi-pmic"; + reg = <0x9 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2370_j_e2_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2370-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; + + smb2370_k_e2: pmic@a { + compatible = "qcom,smb2370", "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2370_k_e2_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2370-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; + + smb2370_l_e2: pmic@b { + compatible = "qcom,smb2370", "qcom,spmi-pmic"; + reg = <0xb SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2370_l_e2_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2370-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; +}; From cb922b08ce1814547815a17bb7e98712b3b5ef44 Mon Sep 17 00:00:00 2001 From: Pankaj Patil Date: Thu, 11 Dec 2025 18:39:53 +0530 Subject: [PATCH 05/16] FROMLIST: arm64: dts: qcom: glymur: Enable Glymur CRD board support Add initial device tree support for the Glymur Compute Reference Device(CRD) board, with this board dts glymur crd can boot to shell with rootfs on nvme and uart21 as serial console Features enabled are: - Board and sleep clocks - Volume up/down keys - Regulators 0 - 4 - Power supplies and sideband signals (PERST, WAKE, CLKREQ) for PCIe3b/4/5/6 controllers and PHYs Link: https://lore.kernel.org/all/20260205-upstream_v3_glymur_introduction-v7-4-849e7a9e6888@oss.qualcomm.com/ Co-developed-by: Kamal Wadhwa Signed-off-by: Kamal Wadhwa Co-developed-by: Qiang Yu Signed-off-by: Qiang Yu Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Co-developed-by: Jyothi Kumar Seerapu Signed-off-by: Jyothi Kumar Seerapu Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Pankaj Patil Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/glymur-crd.dts | 598 ++++++++++++++++++++++++ 2 files changed, 599 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/glymur-crd.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6f34d5ed331c..6ff911cca06c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts new file mode 100644 index 000000000000..877945319012 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -0,0 +1,598 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "glymur.dtsi" +#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ +#include "pmh0101.dtsi" /* SPMI0: SID-1 */ +#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */ +#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */ +#include "pmk8850.dtsi" /* SPMI0: SID-0 */ +#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ + +/ { + model = "Qualcomm Technologies, Inc. Glymur CRD"; + compatible = "qcom,glymur-crd", "qcom,glymur"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + i2c0 = &i2c0; + i2c1 = &i2c4; + i2c2 = &i2c5; + spi0 = &spi18; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&key_vol_up_default>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pmh0101_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvmesec: regulator-nvmesec { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_SEC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0110_f_e1_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_sec_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wlan: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WLAN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wlan_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wwan: regulator-wwan { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WWAN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 246 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wwan_reg_en>; + pinctrl-names = "default"; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id = "B_E0"; + + vreg_bob1_e0: bob1 { + regulator-name = "vreg_bob1_e0"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <4224000>; + regulator-initial-mode = ; + }; + + vreg_bob2_e0: bob2 { + regulator-name = "vreg_bob2_e0"; + regulator-min-microvolt = <2540000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = ; + }; + + vreg_l1b_e0_1p8: ldo1 { + regulator-name = "vreg_l1b_e0_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_e0_2p9: ldo2 { + regulator-name = "vreg_l2b_e0_2p9"; + regulator-min-microvolt = <2904000>; + regulator-max-microvolt = <2904000>; + regulator-initial-mode = ; + }; + + vreg_l7b_e0_2p79: ldo7 { + regulator-name = "vreg_l7b_e0_2p79"; + regulator-min-microvolt = <2790000>; + regulator-max-microvolt = <2792000>; + regulator-initial-mode = ; + }; + + vreg_l8b_e0_1p50: ldo8 { + regulator-name = "vreg_l8b_e0_1p50"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + }; + + vreg_l9b_e0_2p7: ldo9 { + regulator-name = "vreg_l9b_e0_2p7"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = ; + }; + + vreg_l10b_e0_1p8: ldo10 { + regulator-name = "vreg_l10b_e0_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l11b_e0_1p2: ldo11 { + regulator-name = "vreg_l11b_e0_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l12b_e0_1p14: ldo12 { + regulator-name = "vreg_l12b_e0_1p14"; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1144000>; + regulator-initial-mode = ; + }; + + vreg_l15b_e0_1p8: ldo15 { + regulator-name = "vreg_l15b_e0_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l17b_e0_2p4: ldo17 { + regulator-name = "vreg_l17b_e0_2p4"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2700000>; + regulator-initial-mode = ; + }; + + vreg_l18b_e0_1p2: ldo18 { + regulator-name = "vreg_l18b_e0_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmcx0102-rpmh-regulators"; + qcom,pmic-id = "C_E1"; + + vreg_l1c_e1_0p82: ldo1 { + regulator-name = "vreg_l1c_e1_0p82"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l2c_e1_1p14: ldo2 { + regulator-name = "vreg_l2c_e1_1p14"; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1144000>; + regulator-initial-mode = ; + }; + + vreg_l3c_e1_0p89: ldo3 { + regulator-name = "vreg_l3c_e1_0p89"; + regulator-min-microvolt = <890000>; + regulator-max-microvolt = <980000>; + regulator-initial-mode = ; + }; + + vreg_l4c_e1_0p72: ldo4 { + regulator-name = "vreg_l4c_e1_0p72"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <720000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E0"; + + vreg_s7f_e0_1p32: smps7 { + regulator-name = "vreg_s7f_e0_1p32"; + regulator-min-microvolt = <1320000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vreg_s8f_e0_0p95: smps8 { + regulator-name = "vreg_s8f_e0_0p95"; + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_s9f_e0_1p9: smps9 { + regulator-name = "vreg_s9f_e0_1p9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l2f_e0_0p82: ldo2 { + regulator-name = "vreg_l2f_e0_0p82"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l3f_e0_0p72: ldo3 { + regulator-name = "vreg_l3f_e0_0p72"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <720000>; + regulator-initial-mode = ; + }; + + vreg_l4f_e0_0p3: ldo4 { + regulator-name = "vreg_l4f_e0_0p3"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E1"; + + vreg_s7f_e1_0p3: smps7 { + regulator-name = "vreg_s7f_e1_0p3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l1f_e1_0p82: ldo1 { + regulator-name = "vreg_l1f_e1_0p82"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l2f_e1_0p83: ldo2 { + regulator-name = "vreg_l2f_e1_0p83"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l4f_e1_1p08: ldo4 { + regulator-name = "vreg_l4f_e1_1p08"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "H_E0"; + + vreg_l1h_e0_0p89: ldo1 { + regulator-name = "vreg_l1h_e0_0p89"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l2h_e0_0p72: ldo2 { + regulator-name = "vreg_l2h_e0_0p72"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l3h_e0_0p32: ldo3 { + regulator-name = "vreg_l3h_e0_0p32"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l4h_e0_1p2: ldo4 { + regulator-name = "vreg_l4h_e0_1p2"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-initial-mode = ; + }; + }; +}; + +&pcie3b { + vddpe-3v3-supply = <&vreg_nvmesec>; + + pinctrl-0 = <&pcie3b_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie3b_phy { + vdda-phy-supply = <&vreg_l3c_e1_0p89>; + vdda-pll-supply = <&vreg_l2c_e1_1p14>; + + status = "okay"; +}; + +&pcie3b_port0 { + reset-gpios = <&tlmm 155 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 157 GPIO_ACTIVE_LOW>; +}; + +&pcie4 { + vddpe-3v3-supply = <&vreg_wlan>; + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l1c_e1_0p82>; + vdda-pll-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + +&pcie5 { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l2f_e0_0p82>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; + + status = "okay"; +}; + +&pcie5_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pcie6 { + vddpe-3v3-supply = <&vreg_wwan>; + + pinctrl-0 = <&pcie6_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6_phy { + vdda-phy-supply = <&vreg_l1c_e1_0p82>; + vdda-pll-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + +&pcie6_port0 { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +}; + +&pmh0101_gpios { + nvme_reg_en: nvme-reg-en-state { + pins = "gpio14"; + function = "normal"; + bias-disable; + }; +}; + +&pmh0110_f_e1_gpios { + nvme_sec_reg_en: nvme-reg-en-state { + pins = "gpio14"; + function = "normal"; + bias-disable; + }; +}; + +&pmh0101_gpios { + key_vol_up_default: key-vol-up-default-state { + pins = "gpio6"; + function = "normal"; + output-disable; + bias-pull-up; + }; +}; + +&pmk8850_rtc { + qcom,no-alarm; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ + <10 2>, /* OOB UART */ + <44 4>; /* Security SPI (TPM) */ + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie5_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6_default: pcie6-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie6_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio149"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie3b_default: pcie3b-default-state { + clkreq-n-pins { + pins = "gpio156"; + function = "pcie3b_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio155"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio157"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + wlan_reg_en: wlan-reg-en-state { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wwan_reg_en: wwan-reg-en-state { + pins = "gpio246"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; From b1c30b731612d8020059f78d1ad097447ac3f97a Mon Sep 17 00:00:00 2001 From: Wesley Cheng Date: Tue, 13 Jan 2026 14:33:05 +0200 Subject: [PATCH 06/16] FROMLIST: arm64: dts: qcom: glymur: Add USB related nodes The Glymur USB system contains 3 USB type C ports, 1 USB multiport controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS DWC3 based, so describe them as flattened DWC3 QCOM nodes. Link: https://lore.kernel.org/all/20260113-dts-qcom-glymur-add-usb-support-v1-2-98d6d387df01@oss.qualcomm.com/#r Signed-off-by: Wesley Cheng Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur.dtsi | 667 ++++++++++++++++++++++++++- 1 file changed, 662 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index e269cec7942c..b0df806d3367 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -750,11 +750,11 @@ <0>, /* UFS PHY RX Symbol 0 */ <0>, /* UFS PHY RX Symbol 1 */ <0>, /* UFS PHY TX Symbol 0 */ - <0>, /* USB3 PHY 0 */ - <0>, /* USB3 PHY 1 */ - <0>, /* USB3 PHY 2 */ - <0>, /* USB3 UNI PHY pipe 0 */ - <0>, /* USB3 UNI PHY pipe 1 */ + <&usb1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_mp_qmpphy0 QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_mp_qmpphy1 QMP_USB43DP_USB3_PIPE_CLK>, <0>, /* USB4 PHY 0 pcie pipe */ <0>, /* USB4 PHY 0 Max pipe */ <0>, /* USB4 PHY 1 pcie pipe */ @@ -2264,6 +2264,253 @@ }; }; + usb_mp_hsphy0: phy@fa1000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg = <0 0x00fa1000 0 0x29c>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; + + status = "disabled"; + }; + + usb_mp_hsphy1: phy@fa2000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg = <0 0x00fa2000 0 0x29c>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; + + status = "disabled"; + }; + + usb_mp_qmpphy0: phy@fa3000 { + compatible = "qcom,glymur-qmp-usb3-uni-phy"; + reg = <0 0x00fa3000 0 0x2000>; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&tcsr TCSR_USB3_0_CLKREF_EN>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; + clock-names = "aux", + "clkref", + "ref", + "com_aux", + "pipe"; + + power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; + + resets = <&gcc GCC_USB3_MP_SS0_PHY_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names = "phy", + "phy_phy"; + + clock-output-names = "usb3_uni_phy_0_pipe_clk_src"; + #clock-cells = <0>; + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_mp_qmpphy1: phy@fa5000 { + compatible = "qcom,glymur-qmp-usb3-uni-phy"; + reg = <0 0x00fa5000 0 0x2000>; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&tcsr TCSR_USB3_1_CLKREF_EN>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; + clock-names = "aux", + "clkref", + "ref", + "com_aux", + "pipe"; + + power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; + + resets = <&gcc GCC_USB3_MP_SS1_PHY_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names = "phy", + "phy_phy"; + + clock-output-names = "usb3_uni_phy_1_pipe_clk_src"; + + #clock-cells = <0>; + #phy-cells = <0>; + + status = "disabled"; + }; + + usb1_ss0_hsphy: phy@fd3000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg = <0 0x00fd3000 0 0x29c>; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status = "disabled"; + }; + + usb1_ss0_qmpphy: phy@fd5000 { + compatible = "qcom,glymur-qmp-usb3-dp-phy"; + reg = <0 0x00fd5000 0 0x8000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; + + reset-names = "phy", + "common"; + + power-domains = <&gcc GCC_USB_0_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <1>; + + mode-switch; + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb1_ss0_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb1_ss0_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb1_ss0_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb1_ss1_hsphy: phy@fdd000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg = <0 0x00fdd000 0 0x29c>; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + + status = "disabled"; + }; + + usb1_ss1_qmpphy: phy@fde000 { + compatible = "qcom,glymur-qmp-usb3-dp-phy"; + reg = <0 0x00fde000 0 0x8000>; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, + <&tcsr TCSR_USB4_1_CLKREF_EN>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe", + "clkref"; + + power-domains = <&gcc GCC_USB_1_PHY_GDSC>; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + mode-switch; + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb1_ss1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb1_ss1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb1_ss1_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb1_ss1_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb_2_hsphy: phy@fa0000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + reg = <0 0x00fa0000 0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; + + status = "disabled"; + }; + + cnoc_main: interconnect@1500000 { compatible = "qcom,glymur-cnoc-main"; reg = <0x0 0x01500000 0x0 0x17080>; @@ -3367,6 +3614,416 @@ #interconnect-cells = <2>; }; + usb1_ss2_hsphy: phy@88e0000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg = <0 0x088e0000 0 0x29c>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_4_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; + + status = "disabled"; + }; + + usb1_ss2_qmpphy: phy@88e1000 { + compatible = "qcom,glymur-qmp-usb3-dp-phy"; + reg = <0 0x088e1000 0 0x8000>; + + clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>, + <&tcsr TCSR_USB4_2_CLKREF_EN>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe", + "clkref"; + + power-domains = <&gcc GCC_USB_2_PHY_GDSC>; + + resets = <&gcc GCC_USB3_PHY_TERT_BCR>, + <&gcc GCC_USB3PHY_PHY_TERT_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + mode-switch; + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb1_ss2_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb1_ss2_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb1_ss2_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb1_ss2_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb1_ss0: usb@a600000 { + compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a600000 0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 90 IRQ_TYPE_EDGE_BOTH>, + <&pdc 60 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + resets = <&gcc GCC_USB30_PRIM_BCR>; + + iommus = <&apps_smmu 0x1420 0x0>; + phys = <&usb1_ss0_hsphy>, + <&usb1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis_u3_susphy_quirk; + snps,usb2-lpm-disable; + + usb-role-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb1_ss0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb1_ss0_dwc3_ss: endpoint { + remote-endpoint = <&usb1_ss0_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb1_ss1: usb@a800000 { + compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a800000 0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended = <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 88 IRQ_TYPE_EDGE_BOTH>, + <&pdc 87 IRQ_TYPE_EDGE_BOTH>, + <&pdc 76 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + resets = <&gcc GCC_USB30_SEC_BCR>; + power-domains = <&gcc GCC_USB30_SEC_GDSC>; + + iommus = <&apps_smmu 0x1460 0x0>; + + phys = <&usb1_ss1_hsphy>, + <&usb1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis_u3_susphy_quirk; + snps,usb2-lpm-disable; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb1_ss1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb1_ss1_dwc3_ss: endpoint { + remote-endpoint = <&usb1_ss1_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb1_ss2: usb@a000000 { + compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a000000 0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_SLEEP_CLK>, + <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended = <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 89 IRQ_TYPE_EDGE_BOTH>, + <&pdc 81 IRQ_TYPE_EDGE_BOTH>, + <&pdc 75 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + resets = <&gcc GCC_USB30_TERT_BCR>; + power-domains = <&gcc GCC_USB30_TERT_GDSC>; + + iommus = <&apps_smmu 0x420 0x0>; + + phys = <&usb1_ss2_hsphy>, + <&usb1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis_u3_susphy_quirk; + snps,usb2-lpm-disable; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb1_ss2_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb1_ss2_dwc3_ss: endpoint { + remote-endpoint = <&usb1_ss2_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb_2: usb@a2f8800 { + compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a200000 0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 92 IRQ_TYPE_EDGE_BOTH>, + <&pdc 57 IRQ_TYPE_EDGE_BOTH>, + <&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "hs_phy_irq"; + + resets = <&gcc GCC_USB20_PRIM_BCR>; + + power-domains = <&gcc GCC_USB20_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x0ce0 0x0>; + + interconnects = <&aggre3_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", + "apps-usb"; + + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; + + dr_mode = "host"; + + maximum-speed = "high-speed"; + + status = "disabled"; + }; + + usb_mp: usb@a400000 { + compatible = "qcom,glymur-dwc3-mp", "qcom,snps-dwc3"; + reg = <0 0x0a400000 0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended = <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 12 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 11 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 13 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 78 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 77 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event_1", + "pwr_event_2", + "hs_phy_1", + "hs_phy_2", + "dp_hs_phy_1", + "dm_hs_phy_1", + "dp_hs_phy_2", + "dm_hs_phy_2", + "ss_phy_1", + "ss_phy_2"; + + resets = <&gcc GCC_USB30_MP_BCR>; + power-domains = <&gcc GCC_USB30_MP_GDSC>; + + iommus = <&apps_smmu 0xda0 0x0>; + + phys = <&usb_mp_hsphy0>, + <&usb_mp_qmpphy0>, + <&usb_mp_hsphy1>, + <&usb_mp_qmpphy1>; + phy-names = "usb2-0", + "usb3-0", + "usb2-1", + "usb3-1"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + snps,dis_u3_susphy_quirk; + snps,usb2-lpm-disable; + + dr_mode = "host"; + + status = "disabled"; + }; + + dispcc: clock-controller@af00000 { compatible = "qcom,glymur-dispcc"; reg = <0x0 0x0af00000 0x0 0x20000>; From 7cf80ccd3e3f99d611e79cbf3e6dd984c1a4c6bf Mon Sep 17 00:00:00 2001 From: Wesley Cheng Date: Tue, 20 Jan 2026 11:45:10 +0530 Subject: [PATCH 07/16] FROMLIST: arm64: dts: qcom: glymur-crd: Enable USB support The Qualcomm Glymur Compute Reference Device comes with 3 Type-C ports, one USB Type-A, and a fingerprint reader connected over USB. Each of these 3 Type-C ports are connected to one of the USB combo PHYs and one of the M31 eUSB2 PHYs. The Type-A is connected to the USB Multi-port controller via one of the M31 eUSB2 PHYs and one combo PHY. The fingerprint reader is connected to the USB_2 controller. All M31 eUSB2 PHYs have associated eUSB2 to USB 2.0 repeaters, which are either part of SMB2360 PMICs or dedicated NXP PTN3222. So enable all needed controllers, PHYs and repeaters, while describing their supplies. Also describe the PMIC glink graph for Type-C connectors. Link: https://lore.kernel.org/all/20260113-dts-qcom-glymur-add-usb-support-v1-3-98d6d387df01@oss.qualcomm.com/ Signed-off-by: Wesley Cheng Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 283 ++++++++++++++++++++++++ 1 file changed, 283 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 877945319012..43f86f841cc2 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -60,6 +60,97 @@ }; }; + pmic-glink { + compatible = "qcom,glymur-pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb1_ss0_qmpphy_out>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in1: endpoint { + remote-endpoint = <&usb1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in1: endpoint { + remote-endpoint = <&usb1_ss1_qmpphy_out>; + }; + }; + }; + }; + + connector@2 { + compatible = "usb-c-connector"; + reg = <2>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in2: endpoint { + remote-endpoint = <&usb1_ss2_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in2: endpoint { + remote-endpoint = <&usb1_ss2_qmpphy_out>; + }; + }; + }; + }; + }; + vreg_nvme: regulator-nvme { compatible = "regulator-fixed"; @@ -367,6 +458,48 @@ }; }; +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + ptn3222_0: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b_e0_1p50>; + vdd1v8-supply = <&vreg_l15b_e0_1p8>; + + #phy-cells = <0>; + }; + + ptn3222_1: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b_e0_1p50>; + vdd1v8-supply = <&vreg_l15b_e0_1p8>; + + #phy-cells = <0>; + }; + + ptn3222_2: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + + reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b_e0_1p50>; + vdd1v8-supply = <&vreg_l15b_e0_1p8>; + + #phy-cells = <0>; + }; +}; + &pcie3b { vddpe-3v3-supply = <&vreg_nvmesec>; @@ -485,6 +618,21 @@ status = "okay"; }; +&smb2370_j_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0_1p8>; + vdd3-supply = <&vreg_l7b_e0_2p79>; +}; + +&smb2370_k_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0_1p8>; + vdd3-supply = <&vreg_l7b_e0_2p79>; +}; + +&smb2370_l_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0_1p8>; + vdd3-supply = <&vreg_l7b_e0_2p79>; +}; + &tlmm { gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ <10 2>, /* OOB UART */ @@ -596,3 +744,138 @@ bias-disable; }; }; + +&usb1_ss0_hsphy { + vdd-supply = <&vreg_l3f_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&smb2370_j_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l3f_e0_0p72>; + refgen-supply = <&vreg_l2f_e0_0p82>; + + status = "okay"; +}; + +&usb1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb1_ss0 { + status = "okay"; +}; + +&usb1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in1>; +}; + +&usb1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in1>; +}; + +&usb1_ss1_hsphy { + vdd-supply = <&vreg_l3f_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&smb2370_k_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l1h_e0_0p89>; + refgen-supply = <&vreg_l2f_e0_0p82>; + + status = "okay"; +}; + +&usb1_ss1 { + status = "okay"; +}; + +&usb1_ss2_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in2>; +}; + +&usb1_ss2_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in2>; +}; + +&usb1_ss2_hsphy { + vdd-supply = <&vreg_l4c_e1_0p72>; + vdda12-supply = <&vreg_l4f_e1_1p08>; + + phys = <&smb2370_l_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l4f_e1_1p08>; + vdda-pll-supply = <&vreg_l4c_e1_0p72>; + refgen-supply = <&vreg_l1c_e1_0p82>; + + status = "okay"; +}; + +&usb1_ss2 { + status = "okay"; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_hsphy { + phys = <&ptn3222_2>; + + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2h_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&ptn3222_0>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2h_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&ptn3222_1>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l2h_e0_0p72>; + refgen-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l2h_e0_0p72>; + refgen-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; From 776d8a7f6032cd5c63d6e20b916ecf10bc8269f4 Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Tue, 10 Feb 2026 23:37:59 +0530 Subject: [PATCH 08/16] FROMLIST: arm64: dts: qcom: glymur: Add ADSP and CDSP for Glymur SoC Add remoteproc PAS loader for ADSP and CDSP with its fastrpc nodes. Link: https://lore.kernel.org/lkml/20260129001358.770053-5-sibi.sankar@oss.qualcomm.com/ Signed-off-by: Sibi Sankar Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur.dtsi | 286 +++++++++++++++++++++++++++ 1 file changed, 286 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index b0df806d3367..ea6e95dd0f30 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3593,6 +3593,122 @@ #mbox-cells = <2>; }; + remoteproc_adsp: remoteproc@6800000 { + compatible = "qcom,glymur-adsp-pas", "qcom,sm8550-adsp-pas"; + reg = <0x0 0x06800000 0x0 0x10000>; + + iommus = <&apps_smmu 0x1000 0x0>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + qcom,remote-pid = <2>; + + label = "lpass"; + + fastrpc { + compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + + iommus = <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1043 0x20>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1044 0x20>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + + iommus = <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1045 0x20>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + + iommus = <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1046 0x20>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + + iommus = <&apps_smmu 0x1007 0x40>, + <&apps_smmu 0x1067 0x0>, + <&apps_smmu 0x1087 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + + iommus = <&apps_smmu 0x1008 0x80>, + <&apps_smmu 0x1048 0x20>; + dma-coherent; + }; + }; + }; + }; + lpass_lpiaon_noc: interconnect@7400000 { compatible = "qcom,glymur-lpass-lpiaon-noc"; reg = <0x0 0x07400000 0x0 0x19080>; @@ -5349,6 +5465,176 @@ #interconnect-cells = <2>; }; + remoteproc_cdsp: remoteproc@32300000 { + compatible = "qcom,glymur-cdsp-pas", "qcom,sm8550-cdsp-pas"; + reg = <0x0 0x32300000 0x0 0x10000>; + + iommus = <&apps_smmu 0x2000 0x400>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP>; + power-domain-names = "cx", + "mxc", + "nsp"; + + memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid = <5>; + label = "cdsp"; + + fastrpc { + compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + + iommus = <&apps_smmu 0x2001 0x440>, + <&apps_smmu 0x1961 0x0>, + <&apps_smmu 0x19c1 0x0>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + + iommus = <&apps_smmu 0x2002 0x440>, + <&apps_smmu 0x1962 0x0>, + <&apps_smmu 0x19c2 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + + iommus = <&apps_smmu 0x2003 0x440>, + <&apps_smmu 0x1963 0x0>, + <&apps_smmu 0x19c3 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + + iommus = <&apps_smmu 0x2004 0x440>, + <&apps_smmu 0x1964 0x0>, + <&apps_smmu 0x19c4 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + + iommus = <&apps_smmu 0x2005 0x440>, + <&apps_smmu 0x1965 0x0>, + <&apps_smmu 0x19c5 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + + iommus = <&apps_smmu 0x2006 0x440>, + <&apps_smmu 0x1966 0x0>, + <&apps_smmu 0x19c6 0x0>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + + iommus = <&apps_smmu 0x2007 0x440>, + <&apps_smmu 0x1967 0x0>, + <&apps_smmu 0x19c7 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + + iommus = <&apps_smmu 0x2008 0x440>, + <&apps_smmu 0x1968 0x0>, + <&apps_smmu 0x19c8 0x0>; + dma-coherent; + }; + + /* note: compute-cb@9 is secure */ + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <10>; + + iommus = <&apps_smmu 0x200c 0x440>, + <&apps_smmu 0x196c 0x0>, + <&apps_smmu 0x19cc 0x0>; + dma-coherent; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + + iommus = <&apps_smmu 0x200d 0x440>, + <&apps_smmu 0x196d 0x0>, + <&apps_smmu 0x19cd 0x0>; + dma-coherent; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + + iommus = <&apps_smmu 0x200e 0x440>, + <&apps_smmu 0x196e 0x0>, + <&apps_smmu 0x19ce 0x0>; + dma-coherent; + }; + }; + }; + }; + imem: sram@81e08000 { compatible = "mmio-sram"; reg = <0x0 0x81e08600 0x0 0x300>; From 7b91e645e0f4260850d5df1bae287ccf35751b71 Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Tue, 10 Feb 2026 23:40:07 +0530 Subject: [PATCH 09/16] FROMLIST: arm64: dts: qcom: glymur-crd: Enable ADSP and CDSP Enable ADSP and CDSP on Glymur CRD board. Link: https://lore.kernel.org/lkml/20260129001358.770053-6-sibi.sankar@oss.qualcomm.com/ Signed-off-by: Sibi Sankar Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 43f86f841cc2..130bb9f801b5 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -633,6 +633,20 @@ vdd3-supply = <&vreg_l7b_e0_2p79>; }; +&remoteproc_adsp { + firmware-name = "qcom/glymur/adsp.mbn", + "qcom/glymur/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/glymur/cdsp.mbn", + "qcom/glymur/cdsp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ <10 2>, /* OOB UART */ From bba510f7c3b5acdb2d97ce64ca31f6d96427ddc0 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 13 Jan 2026 17:00:05 +0200 Subject: [PATCH 10/16] arm64: dts: qcom: glymur: Describe display related nodes The MDSS (Mobile Display SubSystem) on Glymur comes with 4 DisplayPort controllers. Describe them along with display controller and the eDP PHY. Then, attach the combo PHYs link and vco_div clocks to the Display clock controller and link up the PHYs and DP endpoints in the graph. Signed-off-by: Abel Vesa Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/glymur.dtsi | 431 ++++++++++++++++++++++++++- 1 file changed, 423 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index ea6e95dd0f30..c02cd2367f71 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2419,6 +2419,7 @@ reg = <2>; usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -2491,6 +2492,7 @@ reg = <2>; usb1_ss1_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp1_out>; }; }; }; @@ -2510,6 +2512,27 @@ status = "disabled"; }; + mdss_dp3_phy: phy@faac00 { + compatible = "qcom,glymur-dp-phy"; + reg = <0 0x00faac00 0 0x1d0>, + <0 0x00faa400 0 0x128>, + <0 0x00faa800 0 0x128>, + <0 0x00faa000 0 0x358>; + + clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb", + "ref"; + + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; cnoc_main: interconnect@1500000 { compatible = "qcom,glymur-cnoc-main"; @@ -3798,6 +3821,7 @@ reg = <2>; usb1_ss2_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp2_out>; }; }; }; @@ -4139,20 +4163,411 @@ status = "disabled"; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,glymur-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus = <&apps_smmu 0x1de0 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,glymur-dpu"; + reg = <0 0x0ae01000 0 0x93000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + + mdss_intf4_out: endpoint { + remote-endpoint = <&mdss_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + + mdss_intf5_out: endpoint { + remote-endpoint = <&mdss_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + + mdss_intf6_out: endpoint { + remote-endpoint = <&mdss_dp2_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-205000000 { + opp-hz = /bits/ 64 <205000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz = /bits/ 64 <337000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz = /bits/ 64 <417000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz = /bits/ 64 <532000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + }; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0xaf54000 0x0 0x104>, + <0x0 0xaf54200 0x0 0xc0>, + <0x0 0xaf55000 0x0 0x770>, + <0x0 0xaf56000 0x0 0x9c>, + <0x0 0xaf57000 0x0 0x9c>; + + interrupts-extended = <&mdss 12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb1_ss0_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; + }; + }; + }; + + mdss_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp1: displayport-controller@af5c000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0xaf5c000 0x0 0x104>, + <0x0 0xaf5c200 0x0 0xc0>, + <0x0 0xaf5d000 0x0 0x770>, + <0x0 0xaf5e000 0x0 0x9c>, + <0x0 0xaf5f000 0x0 0x9c>; + + interrupts-extended = <&mdss 13>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb1_ss1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp1_in: endpoint { + remote-endpoint = <&mdss_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp1_out: endpoint { + remote-endpoint = <&usb1_ss1_qmpphy_dp_in>; + }; + }; + }; + }; + + mdss_dp2: displayport-controller@af64000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0x0af64000 0x0 0x104>, + <0x0 0x0af64200 0x0 0xc0>, + <0x0 0x0af65000 0x0 0x770>, + <0x0 0x0af66000 0x0 0x9c>, + <0x0 0x0af67000 0x0 0x9c>; + + interrupts-extended = <&mdss 14>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb1_ss2_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp2_in: endpoint { + remote-endpoint = <&mdss_intf6_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp2_out: endpoint { + remote-endpoint = <&usb1_ss2_qmpphy_dp_in>; + }; + }; + }; + }; + + mdss_dp3: displayport-controller@af6c000 { + compatible = "qcom,glymur-dp"; + reg = <0 0x0af6c000 0 0x200>, + <0 0x0af6c200 0 0x200>, + <0 0x0af6d000 0 0xc00>, + <0 0x0af6e000 0 0x400>, + <0 0x0af6f000 0 0x400>; + + interrupts-extended = <&mdss 15>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss_dp3_phy 0>, + <&mdss_dp3_phy 1>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dp3_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp3_in: endpoint { + remote-endpoint = <&mdss_intf5_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + }; + }; + }; + }; + }; dispcc: clock-controller@af00000 { compatible = "qcom,glymur-dispcc"; reg = <0x0 0x0af00000 0x0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, - <0>, /* dp0 */ - <0>, - <0>, /* dp1 */ - <0>, - <0>, /* dp2 */ - <0>, - <0>, /* dp3 */ - <0>, + <&usb1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ + <&usb1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ + <&usb1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ + <&usb1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&mdss_dp3_phy 0>, /* dp3 */ + <&mdss_dp3_phy 1>, <0>, /* dsi0 */ <0>, <0>, /* dsi1 */ From 2f5bb8ba84745a5f453b53750e6ea725626db3e7 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 27 Jan 2026 18:04:09 +0530 Subject: [PATCH 11/16] arm64: dts: qcom: glymur-crd: Enable eDP display support Enable the MDSS (Mobile Display SubSystem) along with the 3rd DisplayPort controller and its PHY in order to bring support for the panel on Glymur CRD platform. Also describe the voltage regulator needed by the eDP panel. Signed-off-by: Pankaj Patil --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 71 +++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 130bb9f801b5..fd1e48fcfd25 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -151,6 +151,22 @@ }; }; + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + vreg_nvme: regulator-nvme { compatible = "regulator-fixed"; @@ -500,6 +516,47 @@ }; }; +&mdss { + status = "okay"; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel { + compatible = "samsung,atna60cl08", "samsung,atna33xc20"; + enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_3p3>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l2f_e1_0p83>; + vdda-pll-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + &pcie3b { vddpe-3v3-supply = <&vreg_nvmesec>; @@ -652,6 +709,20 @@ <10 2>, /* OOB UART */ <44 4>; /* Security SPI (TPM) */ + edp_bl_en: edp-bl-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins = "gpio147"; From f16178d3115a791418be108075cbb93e48084a0e Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 1 Oct 2025 12:00:56 +0300 Subject: [PATCH 12/16] arm64: dts: qcom: glymur-crd: Enable keyboard, trackpad and touchscreen Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 117 ++++++++++++++++++++++++ 1 file changed, 117 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index fd1e48fcfd25..9777287a5b8a 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include + #include "glymur.dtsi" #include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ #include "pmh0101.dtsi" /* SPMI0: SID-1 */ @@ -167,6 +169,23 @@ regulator-boot-on; }; + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&misc_3p3_reg_en>; + + regulator-boot-on; + regulator-always-on; + }; + vreg_nvme: regulator-nvme { compatible = "regulator-fixed"; @@ -474,6 +493,44 @@ }; }; +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + &i2c5 { clock-frequency = <400000>; @@ -516,6 +573,26 @@ }; }; +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@38 { + compatible = "hid-over-i2c"; + reg = <0x38>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + &mdss { status = "okay"; }; @@ -666,6 +743,19 @@ }; }; +&pmh0110_f_e0_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-disable; + output-enable; + drive-push-pull; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + &pmk8850_rtc { qcom,no-alarm; }; @@ -746,6 +836,33 @@ }; }; + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; + pcie5_default: pcie5-default-state { clkreq-n-pins { pins = "gpio153"; From a0ca980002718e4b268c83be165930c4f6d5c977 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Mon, 25 Aug 2025 15:25:08 +0530 Subject: [PATCH 13/16] arm64: dts: qcom: glymur: Add GPU clock and smmu nodes Add the nodes to describe GPU clock controller and the GPU SMMU node Signed-off-by: Rajendra Nayak --- arch/arm64/boot/dts/qcom/glymur.dtsi | 65 ++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index c02cd2367f71..437a67fce128 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -5,7 +5,9 @@ #include #include +#include #include +#include #include #include #include @@ -3605,6 +3607,69 @@ #interconnect-cells = <2>; }; + gxclkctl: clock-controller@3d64000 { + compatible = "qcom,glymur-gxclkctl"; + reg = <0x0 0x03d64000 0x0 0x6000>; + + power-domains = <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,glymur-gpucc"; + reg = <0x0 0x03d90000 0x0 0x9800>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,glymur-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>; + clock-names = "hlos"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + interconnects = <&hsc_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; + dma-coherent; + }; + ipcc: mailbox@3e04000 { compatible = "qcom,glymur-ipcc", "qcom,ipcc"; reg = <0x0 0x03e04000 0x0 0x1000>; From ffe218842ae96380b8d3b4e883b30c48b0412f18 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Tue, 23 Sep 2025 01:44:26 +0530 Subject: [PATCH 14/16] arm64: dts: qcom: Add Glymur GPU support The Adreno X2 series GPU present in Glymur SoC belongs to the A8x family. It is a new HW IP with architectural improvements as well as different set of hw configs like GMEM, num SPs, Caches sizes etc. Add the GPU and GMU nodes to describe this hardware. Signed-off-by: Akhil P Oommen --- arch/arm64/boot/dts/qcom/glymur.dtsi | 168 +++++++++++++++++++++++++++ 1 file changed, 168 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 437a67fce128..e3579f99e7ef 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3618,6 +3618,174 @@ #power-domain-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-44070001", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x2000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + #cooling-cells = <2>; + + interconnects = <&hsc_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2-adreno", + "operating-points-v2"; + + opp-310000000 { + opp-hz = /bits/ 64 <310000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + }; + + opp-410000000 { + opp-hz = /bits/ 64 <410000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + }; + + opp-572000000 { + opp-hz = /bits/ 64 <572000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xe02d5ffd>; + }; + + opp-760000000 { + opp-hz = /bits/ 64 <760000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xc0285ffd>; + }; + + opp-820000000 { + opp-hz = /bits/ 64 <820000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xa82e5ffd>; + }; + + opp-915000000 { + opp-hz = /bits/ 64 <915000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x882d5ffd>; + }; + + opp-1070000000 { + opp-hz = /bits/ 64 <1070000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x882b5ffd>; + }; + + opp-1185000000 { + opp-hz = /bits/ 64 <1185000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x882a5ffd>; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x882a5ffd>; + }; + + opp-1550000000 { + opp-hz = /bits/ 64 <1550000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xa8295ffd>; + }; + + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x88295ffd>; + }; + + opp-1850000000 { + opp-hz = /bits/ 64 <1850000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x88285ffd>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-x285.1", "qcom,adreno-gmu"; + + reg = <0x0 0x03d37000 0x0 0x68000>; + reg-names = "gmu"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_GPU_GEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "memnoc", + "hub"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>, <&gpucc GPU_CC_CX_GDSC>; + //<&gxclkctl GX_CLKCTL_GX_GDSC>; TODO: + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + opp-level = ; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-level = ; + }; + + opp-725000000 { + opp-hz = /bits/ 64 <725000000>; + opp-level = ; + }; + + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,glymur-gpucc"; reg = <0x0 0x03d90000 0x0 0x9800>; From a5a9e0f4b58fe86e252b7f974cee2f9d4632bc45 Mon Sep 17 00:00:00 2001 From: Pankaj Patil Date: Mon, 16 Feb 2026 19:12:49 +0530 Subject: [PATCH 15/16] arm64: dts: qcom: glymur: Upgrade dispcc opp entry to turbo Switch opp entry for dispcc to turbo Signed-off-by: Pankaj Patil --- arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index e3579f99e7ef..6b7d63ffa979 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4810,7 +4810,7 @@ <0>, <0>; power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + required-opps = <&rpmhpd_opp_turbo>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From d7d0453b379f8911e04d68df199114acf6f814ed Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Mon, 16 Feb 2026 23:08:54 +0530 Subject: [PATCH 16/16] arm64: defconfig: Enable Config for Glymur Enable defconfig for Glymur Signed-off-by: Pradyot Kumar Nayak --- arch/arm64/configs/defconfig | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 35e9eb180c9a..e2ba03d7cf57 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -624,12 +624,14 @@ CONFIG_PINCTRL_IMX91=y CONFIG_PINCTRL_IMX93=y CONFIG_PINCTRL_IMX_SCMI=y CONFIG_PINCTRL_MSM=y +CONFIG_PINCTRL_GLYMUR=y CONFIG_PINCTRL_IPQ5018=y CONFIG_PINCTRL_IPQ5332=y CONFIG_PINCTRL_IPQ5424=y CONFIG_PINCTRL_IPQ8074=y CONFIG_PINCTRL_IPQ6018=y CONFIG_PINCTRL_IPQ9574=y +CONFIG_PINCTRL_KAANAPALI=y CONFIG_PINCTRL_MSM8916=y CONFIG_PINCTRL_MSM8953=y CONFIG_PINCTRL_MSM8976=y @@ -965,7 +967,9 @@ CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m CONFIG_DRM_DISPLAY_CONNECTOR=m CONFIG_DRM_FSL_LDB=m CONFIG_DRM_ITE_IT6263=m +CONFIG_DRM_LONTIUM_LT8713SX=m CONFIG_DRM_LONTIUM_LT8912B=m +CONFIG_DRM_LONTIUM_LT9211=m CONFIG_DRM_LONTIUM_LT9611=m CONFIG_DRM_LONTIUM_LT9611UXC=m CONFIG_DRM_ITE_IT66121=m @@ -1095,6 +1099,7 @@ CONFIG_SND_SOC_J721E_EVM=m CONFIG_SND_SOC_AK4613=m CONFIG_SND_SOC_AK4619=m CONFIG_SND_SOC_DA7213=m +CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_ES7134=m CONFIG_SND_SOC_ES7241=m CONFIG_SND_SOC_ES8316=m @@ -1396,6 +1401,16 @@ CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y CONFIG_COMMON_CLK_MT8192_VDECSYS=y CONFIG_COMMON_CLK_MT8192_VENCSYS=y CONFIG_COMMON_CLK_QCOM=y +CONFIG_CLK_GLYMUR_DISPCC=y +CONFIG_CLK_GLYMUR_GCC=y +CONFIG_CLK_GLYMUR_TCSRCC=y +CONFIG_CLK_GLYMUR_GPUCC=m +CONFIG_CLK_KAANAPALI_CAMCC=m +CONFIG_CLK_KAANAPALI_GCC=y +CONFIG_CLK_KAANAPALI_DISPCC=m +CONFIG_CLK_KAANAPALI_GPUCC=m +CONFIG_CLK_KAANAPALI_TCSRCC=m +CONFIG_CLK_KAANAPALI_VIDEOCC=m CONFIG_CLK_X1E80100_CAMCC=m CONFIG_CLK_X1E80100_DISPCC=m CONFIG_CLK_X1E80100_GCC=y @@ -1464,6 +1479,7 @@ CONFIG_SM_CAMCC_6350=m CONFIG_SM_CAMCC_8250=m CONFIG_SM_CAMCC_8550=m CONFIG_SM_CAMCC_8650=m +CONFIG_SM_CAMCC_8750=m CONFIG_SM_DISPCC_6115=m CONFIG_SM_DISPCC_8250=y CONFIG_SM_DISPCC_6350=m @@ -1493,6 +1509,7 @@ CONFIG_SA_VIDEOCC_8775P=m CONFIG_SM_VIDEOCC_6350=m CONFIG_SM_VIDEOCC_8250=y CONFIG_SM_VIDEOCC_8550=m +CONFIG_SM_VIDEOCC_8750=m CONFIG_QCOM_HFPLL=y CONFIG_CLK_GFM_LPASS_SM8250=m CONFIG_SM_VIDEOCC_8450=m @@ -1749,6 +1766,7 @@ CONFIG_OF_FPGA_REGION=m CONFIG_OF_OVERLAY=y CONFIG_TEE=y CONFIG_OPTEE=y +CONFIG_QCOMTEE=y CONFIG_MUX_GPIO=m CONFIG_MUX_MMIO=y CONFIG_SLIMBUS=m @@ -1761,6 +1779,8 @@ CONFIG_INTERCONNECT_IMX8MN=m CONFIG_INTERCONNECT_IMX8MQ=m CONFIG_INTERCONNECT_IMX8MP=y CONFIG_INTERCONNECT_QCOM=y +CONFIG_INTERCONNECT_QCOM_GLYMUR=y +CONFIG_INTERCONNECT_QCOM_KAANAPALI=y CONFIG_INTERCONNECT_QCOM_MSM8916=m CONFIG_INTERCONNECT_QCOM_MSM8953=y CONFIG_INTERCONNECT_QCOM_MSM8996=y