diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 130bb9f801b5..9777287a5b8a 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include + #include "glymur.dtsi" #include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ #include "pmh0101.dtsi" /* SPMI0: SID-1 */ @@ -151,6 +153,39 @@ }; }; + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&misc_3p3_reg_en>; + + regulator-boot-on; + regulator-always-on; + }; + vreg_nvme: regulator-nvme { compatible = "regulator-fixed"; @@ -458,6 +493,44 @@ }; }; +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + &i2c5 { clock-frequency = <400000>; @@ -500,6 +573,67 @@ }; }; +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@38 { + compatible = "hid-over-i2c"; + reg = <0x38>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel { + compatible = "samsung,atna60cl08", "samsung,atna33xc20"; + enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_3p3>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l2f_e1_0p83>; + vdda-pll-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + &pcie3b { vddpe-3v3-supply = <&vreg_nvmesec>; @@ -609,6 +743,19 @@ }; }; +&pmh0110_f_e0_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-disable; + output-enable; + drive-push-pull; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + &pmk8850_rtc { qcom,no-alarm; }; @@ -652,6 +799,20 @@ <10 2>, /* OOB UART */ <44 4>; /* Security SPI (TPM) */ + edp_bl_en: edp-bl-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins = "gpio147"; @@ -675,6 +836,33 @@ }; }; + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; + pcie5_default: pcie5-default-state { clkreq-n-pins { pins = "gpio153"; diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index d775352f2393..6b7d63ffa979 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -5,7 +5,9 @@ #include #include +#include #include +#include #include #include #include @@ -341,18 +343,6 @@ }; }; - dummy-sink { - compatible = "arm,coresight-dummy-sink"; - - in-ports { - port { - eud_in: endpoint { - remote-endpoint = <&swao_rep_out1>; - }; - }; - }; - }; - firmware { scm: scm { compatible = "qcom,scm-glymur", "qcom,scm"; @@ -2431,6 +2421,7 @@ reg = <2>; usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -2503,6 +2494,7 @@ reg = <2>; usb1_ss1_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp1_out>; }; }; }; @@ -2522,6 +2514,27 @@ status = "disabled"; }; + mdss_dp3_phy: phy@faac00 { + compatible = "qcom,glymur-dp-phy"; + reg = <0 0x00faac00 0 0x1d0>, + <0 0x00faa400 0 0x128>, + <0 0x00faa800 0 0x128>, + <0 0x00faa000 0 0x358>; + + clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb", + "ref"; + + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; cnoc_main: interconnect@1500000 { compatible = "qcom,glymur-cnoc-main"; @@ -3594,6 +3607,237 @@ #interconnect-cells = <2>; }; + gxclkctl: clock-controller@3d64000 { + compatible = "qcom,glymur-gxclkctl"; + reg = <0x0 0x03d64000 0x0 0x6000>; + + power-domains = <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells = <1>; + }; + + gpu: gpu@3d00000 { + compatible = "qcom,adreno-44070001", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x2000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + #cooling-cells = <2>; + + interconnects = <&hsc_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2-adreno", + "operating-points-v2"; + + opp-310000000 { + opp-hz = /bits/ 64 <310000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + }; + + opp-410000000 { + opp-hz = /bits/ 64 <410000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + }; + + opp-572000000 { + opp-hz = /bits/ 64 <572000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xe02d5ffd>; + }; + + opp-760000000 { + opp-hz = /bits/ 64 <760000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xc0285ffd>; + }; + + opp-820000000 { + opp-hz = /bits/ 64 <820000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xa82e5ffd>; + }; + + opp-915000000 { + opp-hz = /bits/ 64 <915000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x882d5ffd>; + }; + + opp-1070000000 { + opp-hz = /bits/ 64 <1070000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x882b5ffd>; + }; + + opp-1185000000 { + opp-hz = /bits/ 64 <1185000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x882a5ffd>; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x882a5ffd>; + }; + + opp-1550000000 { + opp-hz = /bits/ 64 <1550000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xa8295ffd>; + }; + + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x88295ffd>; + }; + + opp-1850000000 { + opp-hz = /bits/ 64 <1850000000>; + opp-level = ; + opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0x88285ffd>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-x285.1", "qcom,adreno-gmu"; + + reg = <0x0 0x03d37000 0x0 0x68000>; + reg-names = "gmu"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_GPU_GEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "memnoc", + "hub"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>, <&gpucc GPU_CC_CX_GDSC>; + //<&gxclkctl GX_CLKCTL_GX_GDSC>; TODO: + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + opp-level = ; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-level = ; + }; + + opp-725000000 { + opp-hz = /bits/ 64 <725000000>; + opp-level = ; + }; + + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,glymur-gpucc"; + reg = <0x0 0x03d90000 0x0 0x9800>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,glymur-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>; + clock-names = "hlos"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + interconnects = <&hsc_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; + dma-coherent; + }; + ipcc: mailbox@3e04000 { compatible = "qcom,glymur-ipcc", "qcom,ipcc"; reg = <0x0 0x03e04000 0x0 0x1000>; @@ -3810,6 +4054,7 @@ reg = <2>; usb1_ss2_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp2_out>; }; }; }; @@ -4151,20 +4396,411 @@ status = "disabled"; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,glymur-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus = <&apps_smmu 0x1de0 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,glymur-dpu"; + reg = <0 0x0ae01000 0 0x93000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + + mdss_intf4_out: endpoint { + remote-endpoint = <&mdss_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + + mdss_intf5_out: endpoint { + remote-endpoint = <&mdss_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + + mdss_intf6_out: endpoint { + remote-endpoint = <&mdss_dp2_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-205000000 { + opp-hz = /bits/ 64 <205000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz = /bits/ 64 <337000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz = /bits/ 64 <417000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz = /bits/ 64 <532000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + }; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0xaf54000 0x0 0x104>, + <0x0 0xaf54200 0x0 0xc0>, + <0x0 0xaf55000 0x0 0x770>, + <0x0 0xaf56000 0x0 0x9c>, + <0x0 0xaf57000 0x0 0x9c>; + + interrupts-extended = <&mdss 12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb1_ss0_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; + }; + }; + }; + + mdss_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp1: displayport-controller@af5c000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0xaf5c000 0x0 0x104>, + <0x0 0xaf5c200 0x0 0xc0>, + <0x0 0xaf5d000 0x0 0x770>, + <0x0 0xaf5e000 0x0 0x9c>, + <0x0 0xaf5f000 0x0 0x9c>; + + interrupts-extended = <&mdss 13>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb1_ss1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp1_in: endpoint { + remote-endpoint = <&mdss_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp1_out: endpoint { + remote-endpoint = <&usb1_ss1_qmpphy_dp_in>; + }; + }; + }; + }; + + mdss_dp2: displayport-controller@af64000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0x0af64000 0x0 0x104>, + <0x0 0x0af64200 0x0 0xc0>, + <0x0 0x0af65000 0x0 0x770>, + <0x0 0x0af66000 0x0 0x9c>, + <0x0 0x0af67000 0x0 0x9c>; + + interrupts-extended = <&mdss 14>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb1_ss2_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp2_in: endpoint { + remote-endpoint = <&mdss_intf6_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp2_out: endpoint { + remote-endpoint = <&usb1_ss2_qmpphy_dp_in>; + }; + }; + }; + }; + + mdss_dp3: displayport-controller@af6c000 { + compatible = "qcom,glymur-dp"; + reg = <0 0x0af6c000 0 0x200>, + <0 0x0af6c200 0 0x200>, + <0 0x0af6d000 0 0xc00>, + <0 0x0af6e000 0 0x400>, + <0 0x0af6f000 0 0x400>; + + interrupts-extended = <&mdss 15>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss_dp3_phy 0>, + <&mdss_dp3_phy 1>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dp3_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp3_in: endpoint { + remote-endpoint = <&mdss_intf5_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + }; + }; + }; + }; + }; dispcc: clock-controller@af00000 { compatible = "qcom,glymur-dispcc"; reg = <0x0 0x0af00000 0x0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, - <0>, /* dp0 */ - <0>, - <0>, /* dp1 */ - <0>, - <0>, /* dp2 */ - <0>, - <0>, /* dp3 */ - <0>, + <&usb1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ + <&usb1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ + <&usb1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ + <&usb1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&mdss_dp3_phy 0>, /* dp3 */ + <&mdss_dp3_phy 1>, <0>, /* dsi0 */ <0>, <0>, /* dsi1 */ @@ -4174,7 +4810,7 @@ <0>, <0>; power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + required-opps = <&rpmhpd_opp_turbo>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -5064,1117 +5700,14 @@ }; }; - stm: stm@10002000 { - compatible = "arm,coresight-stm", "arm,primecell"; - reg = <0x0 0x10002000 0x0 0x1000>, - <0x0 0x16280000 0x0 0x180000>; - reg-names = "stm-base", - "stm-stimulus-base"; + apps_smmu: iommu@15000000 { + compatible = "qcom,glymur-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - out-ports { - port { - stm_out: endpoint { - remote-endpoint = <&funnel0_in7>; - }; - }; - }; - }; - - tpda@10004000 { - compatible = "qcom,coresight-tpda", "arm,primecell"; - reg = <0x0 0x10004000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - qdss_tpda_in1: endpoint { - remote-endpoint = <&spdm_tpdm_out>; - }; - }; - }; - - out-ports { - port { - qdss_tpda_out: endpoint { - remote-endpoint = <&funnel0_in6>; - }; - }; - }; - }; - - tpdm@1000f000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1000f000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <32>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - spdm_tpdm_out: endpoint { - remote-endpoint = <&qdss_tpda_in1>; - }; - }; - }; - }; - - funnel@10041000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x0 0x10041000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - funnel0_in0: endpoint { - remote-endpoint = <&tn_ag_out>; - }; - }; - - port@6 { - reg = <6>; - - funnel0_in6: endpoint { - remote-endpoint = <&qdss_tpda_out>; - }; - }; - - port@7 { - reg = <7>; - - funnel0_in7: endpoint { - remote-endpoint = <&stm_out>; - }; - }; - }; - - out-ports { - port { - funnel0_out: endpoint { - remote-endpoint = <&aoss_funnel_in6>; - }; - }; - }; - }; - - tpdm@1102c000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1102c000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - gcc_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in36>; - }; - }; - }; - }; - - cti@11161000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0 0x11161000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - }; - - cti@11162000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0 0x11162000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - }; - - tpdm@11180000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11180000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-element-bits = <32>; - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - cdsp_tpdm_out: endpoint { - remote-endpoint = <&cdsp_tpda_in0>; - }; - }; - }; - }; - - tpdm@11183000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11183000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <32>; - qcom,cmb-msrs-num = <32>; - qcom,dsb-element-bits = <32>; - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - cdsp_cmsr_tpdm_out: endpoint { - remote-endpoint = <&cdsp_tpda_in3>; - }; - }; - }; - }; - - tpdm@11184000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11184000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <32>; - qcom,cmb-msrs-num = <32>; - qcom,dsb-element-bits = <32>; - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - cdsp_cmsr2_tpdm_out: endpoint { - remote-endpoint = <&cdsp_tpda_in4>; - }; - }; - }; - }; - - tpdm@11185000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11185000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <64>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - cdsp_dpm1_tpdm_out: endpoint { - remote-endpoint = <&cdsp_tpda_in5>; - }; - }; - }; - }; - - tpdm@11186000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11186000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <64>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - cdsp_dpm2_tpdm_out: endpoint { - remote-endpoint = <&cdsp_tpda_in6>; - }; - }; - }; - }; - - tpda@11188000 { - compatible = "qcom,coresight-tpda", "arm,primecell"; - reg = <0x0 0x11188000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - cdsp_tpda_in0: endpoint { - remote-endpoint = <&cdsp_tpdm_out>; - }; - }; - - port@1 { - reg = <1>; - - cdsp_tpda_in1: endpoint { - remote-endpoint = <&cdsp_llm_tpdm_out>; - }; - }; - - port@2 { - reg = <2>; - - cdsp_tpda_in2: endpoint { - remote-endpoint = <&cdsp_llm2_tpdm_out>; - }; - }; - - port@3 { - reg = <3>; - - cdsp_tpda_in3: endpoint { - remote-endpoint = <&cdsp_cmsr_tpdm_out>; - }; - }; - - port@4 { - reg = <4>; - - cdsp_tpda_in4: endpoint { - remote-endpoint = <&cdsp_cmsr2_tpdm_out>; - }; - }; - - port@5 { - reg = <5>; - - cdsp_tpda_in5: endpoint { - remote-endpoint = <&cdsp_dpm1_tpdm_out>; - }; - }; - - port@6 { - reg = <6>; - - cdsp_tpda_in6: endpoint { - remote-endpoint = <&cdsp_dpm2_tpdm_out>; - }; - }; - }; - - out-ports { - port { - cdsp_tpda_out: endpoint { - remote-endpoint = <&cdsp_funnel_in0>; - }; - }; - }; - }; - - funnel@11189000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x0 0x11189000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - port { - cdsp_funnel_in0: endpoint { - remote-endpoint = <&cdsp_tpda_out>; - }; - }; - }; - - out-ports { - port { - cdsp_funnel_out: endpoint { - remote-endpoint = <&tn_ag_in53>; - }; - }; - }; - }; - - cti@11193000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0 0x11193000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - }; - - cti@111ab000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0 0x111ab000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - }; - - tpdm@111d0000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x111d0000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - qm_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in35>; - }; - }; - }; - }; - - tn@11200000 { - compatible = "qcom,coresight-tnoc", "arm,primecell"; - reg = <0x0 0x11200000 0x0 0x4200>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@6 { - reg = <6>; - - tn_ag_in6: endpoint { - remote-endpoint = <&mm_dsb_tpdm_out>; - }; - }; - - port@10 { - reg = <0x10>; - - tn_ag_in16: endpoint { - remote-endpoint = <&east_dsb_tpdm_out>; - }; - }; - - port@21 { - reg = <0x21>; - - tn_ag_in33: endpoint { - remote-endpoint = <&west_dsb_tpdm_out>; - }; - }; - - port@23 { - reg = <0x23>; - - tn_ag_in35: endpoint { - remote-endpoint = <&qm_tpdm_out>; - }; - }; - - port@24 { - reg = <0x24>; - - tn_ag_in36: endpoint { - remote-endpoint = <&gcc_tpdm_out>; - }; - }; - - port@32 { - reg = <0x32>; - - tn_ag_in50: endpoint { - remote-endpoint = <&pcie_rscc_tpda_out>; - }; - }; - - port@35 { - reg = <0x35>; - - tn_ag_in53: endpoint { - remote-endpoint = <&cdsp_funnel_out>; - }; - }; - - port@3f { - reg = <0x3f>; - - tn_ag_in63: endpoint { - remote-endpoint = <¢er_dsb_tpdm_out>; - }; - }; - - port@40 { - reg = <0x40>; - - tn_ag_in64: endpoint { - remote-endpoint = <&ipcc_cmb_tpdm_out>; - }; - }; - - port@41 { - reg = <0x41>; - - tn_ag_in65: endpoint { - remote-endpoint = <&qrng_tpdm_out>; - }; - }; - - port@42 { - reg = <0x42>; - - tn_ag_in66: endpoint { - remote-endpoint = <&pmu_tpdm_out>; - }; - }; - - port@43 { - reg = <0x43>; - - tn_ag_in67: endpoint { - remote-endpoint = <&rdpm_west_cmb0_tpdm_out>; - }; - }; - - port@44 { - reg = <0x44>; - - tn_ag_in68: endpoint { - remote-endpoint = <&rdpm_west_cmb1_tpdm_out>; - }; - }; - - port@45 { - reg = <0x45>; - - tn_ag_in69: endpoint { - remote-endpoint = <&rdpm_west_cmb2_tpdm_out>; - }; - }; - - port@4b { - reg = <0x4b>; - - tn_ag_in75: endpoint { - remote-endpoint = <&south_dsb2_tpdm_out>; - }; - }; - - port@52 { - reg = <0x52>; - - tn_ag_in82: endpoint { - remote-endpoint = <&south_dsb_tpdm_out>; - }; - }; - - port@53 { - reg = <0x53>; - - tn_ag_in83: endpoint { - remote-endpoint = <¢er_dsb1_tpdm_out>; - }; - }; - }; - - out-ports { - port { - tn_ag_out: endpoint { - remote-endpoint = <&funnel0_in0>; - }; - }; - }; - }; - - tpdm@11207000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11207000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - mm_dsb_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in6>; - }; - }; - }; - }; - - tpdm@1120b000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1120b000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - east_dsb_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in16>; - }; - }; - }; - }; - - tpdm@11213000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11213000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - west_dsb_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in33>; - }; - }; - }; - }; - - tpdm@11219000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11219000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - center_dsb_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in63>; - }; - }; - }; - }; - - tpdm@1121a000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1121a000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - ipcc_cmb_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in64>; - }; - }; - }; - }; - - tpdm@1121b000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1121b000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - qrng_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in65>; - }; - }; - }; - }; - - tpdm@1121c000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1121c000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - pmu_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in66>; - }; - }; - }; - }; - - tpdm@1121d000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1121d000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - rdpm_west_cmb0_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in67>; - }; - }; - }; - }; - - tpdm@1121e000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1121e000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - rdpm_west_cmb1_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in68>; - }; - }; - }; - }; - - tpdm@1121f000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x1121f000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - rdpm_west_cmb2_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in69>; - }; - }; - }; - }; - - tpdm@11220000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11220000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - center_dsb1_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in83>; - }; - }; - }; - }; - - tpdm@11224000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11224000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - south_dsb2_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in75>; - }; - }; - }; - }; - - tpdm@11228000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11228000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - south_dsb_tpdm_out: endpoint { - remote-endpoint = <&tn_ag_in82>; - }; - }; - }; - }; - - tpdm@11470000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11470000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <32>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - pcie_rscc_tpdm_out: endpoint { - remote-endpoint = <&pcie_rscc_tpda_in0>; - }; - }; - }; - }; - - tpda@11471000 { - compatible = "qcom,coresight-tpda", "arm,primecell"; - reg = <0x0 0x11471000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - port { - pcie_rscc_tpda_in0: endpoint { - remote-endpoint = <&pcie_rscc_tpdm_out>; - }; - }; - }; - - out-ports { - port { - pcie_rscc_tpda_out: endpoint { - remote-endpoint = <&tn_ag_in50>; - }; - }; - }; - }; - - tpdm@11c03000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11c03000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <64>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - swao_prio4_tpdm_out: endpoint { - remote-endpoint = <&aoss_tpda_in4>; - }; - }; - }; - }; - - funnel@11c04000 { - compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; - reg = <0x0 0x11c04000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@5 { - reg = <5>; - - aoss_funnel_in5: endpoint { - remote-endpoint = <&aoss_tpda_out>; - }; - }; - - port@6 { - reg = <6>; - - aoss_funnel_in6: endpoint { - remote-endpoint = <&funnel0_out>; - }; - }; - }; - - out-ports { - port { - aoss_funnel_out: endpoint { - remote-endpoint = <&etf0_in>; - }; - }; - }; - }; - - tmc_etf: tmc@11c05000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x0 0x11c05000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - port { - etf0_in: endpoint { - remote-endpoint = <&aoss_funnel_out>; - }; - }; - }; - - out-ports { - port { - etf0_out: endpoint { - remote-endpoint = <&swao_rep_in>; - }; - }; - }; - }; - - replicator@11c06000 { - compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; - reg = <0x0 0x11c06000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - port { - swao_rep_in: endpoint { - remote-endpoint = <&etf0_out>; - }; - }; - }; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - swao_rep_out1: endpoint { - remote-endpoint = <&eud_in>; - }; - }; - }; - }; - - tpda@11c08000 { - compatible = "qcom,coresight-tpda", "arm,primecell"; - reg = <0x0 0x11c08000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - aoss_tpda_in0: endpoint { - remote-endpoint = <&swao_prio0_tpdm_out>; - }; - }; - - port@1 { - reg = <1>; - - aoss_tpda_in1: endpoint { - remote-endpoint = <&swao_prio1_tpdm_out>; - }; - }; - - port@2 { - reg = <2>; - - aoss_tpda_in2: endpoint { - remote-endpoint = <&swao_prio2_tpdm_out>; - }; - }; - - port@3 { - reg = <3>; - - aoss_tpda_in3: endpoint { - remote-endpoint = <&swao_prio3_tpdm_out>; - }; - }; - - port@4 { - reg = <4>; - - aoss_tpda_in4: endpoint { - remote-endpoint = <&swao_prio4_tpdm_out>; - }; - }; - - port@5 { - reg = <5>; - - aoss_tpda_in5: endpoint { - remote-endpoint = <&swao_tpdm_out>; - }; - }; - }; - - out-ports { - port { - aoss_tpda_out: endpoint { - remote-endpoint = <&aoss_funnel_in5>; - }; - }; - }; - }; - - tpdm@11c09000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11c09000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <64>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - swao_prio0_tpdm_out: endpoint { - remote-endpoint = <&aoss_tpda_in0>; - }; - }; - }; - }; - - tpdm@11c0a000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11c0a000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <64>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - swao_prio1_tpdm_out: endpoint { - remote-endpoint = <&aoss_tpda_in1>; - }; - }; - }; - }; - - tpdm@11c0b000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11c0b000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <64>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - swao_prio2_tpdm_out: endpoint { - remote-endpoint = <&aoss_tpda_in2>; - }; - }; - }; - }; - - tpdm@11c0c000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11c0c000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,cmb-element-bits = <64>; - qcom,cmb-msrs-num = <32>; - - out-ports { - port { - swao_prio3_tpdm_out: endpoint { - remote-endpoint = <&aoss_tpda_in3>; - }; - }; - }; - }; - - cti@11c42000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0 0x11c42000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - }; - - cti@11c4b000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x0 0x11c4b000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - }; - - tpdm@11c0d000 { - compatible = "qcom,coresight-tpdm", "arm,primecell"; - reg = <0x0 0x11c0d000 0x0 0x1000>; - - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - - qcom,dsb-element-bits = <32>; - qcom,dsb-msrs-num = <32>; - - out-ports { - port { - swao_tpdm_out: endpoint { - remote-endpoint = <&aoss_tpda_in5>; - }; - }; - }; - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,glymur-smmu-500", - "qcom,smmu-500", - "arm,mmu-500"; - reg = <0x0 0x15000000 0x0 0x100000>; - - #iommu-cells = <2>; - #global-interrupts = <1>; + #iommu-cells = <2>; + #global-interrupts = <1>; interrupts = , , @@ -7968,30 +7501,4 @@ }; }; }; - - tpdm-cdsp-llm { - compatible = "qcom,coresight-static-tpdm"; - qcom,cmb-element-bits = <32>; - - out-ports { - port { - cdsp_llm_tpdm_out: endpoint { - remote-endpoint = <&cdsp_tpda_in1>; - }; - }; - }; - }; - - tpdm-cdsp-llm2 { - compatible = "qcom,coresight-static-tpdm"; - qcom,cmb-element-bits = <32>; - - out-ports { - port { - cdsp_llm2_tpdm_out: endpoint { - remote-endpoint = <&cdsp_tpda_in2>; - }; - }; - }; - }; }; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 35e9eb180c9a..e2ba03d7cf57 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -624,12 +624,14 @@ CONFIG_PINCTRL_IMX91=y CONFIG_PINCTRL_IMX93=y CONFIG_PINCTRL_IMX_SCMI=y CONFIG_PINCTRL_MSM=y +CONFIG_PINCTRL_GLYMUR=y CONFIG_PINCTRL_IPQ5018=y CONFIG_PINCTRL_IPQ5332=y CONFIG_PINCTRL_IPQ5424=y CONFIG_PINCTRL_IPQ8074=y CONFIG_PINCTRL_IPQ6018=y CONFIG_PINCTRL_IPQ9574=y +CONFIG_PINCTRL_KAANAPALI=y CONFIG_PINCTRL_MSM8916=y CONFIG_PINCTRL_MSM8953=y CONFIG_PINCTRL_MSM8976=y @@ -965,7 +967,9 @@ CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m CONFIG_DRM_DISPLAY_CONNECTOR=m CONFIG_DRM_FSL_LDB=m CONFIG_DRM_ITE_IT6263=m +CONFIG_DRM_LONTIUM_LT8713SX=m CONFIG_DRM_LONTIUM_LT8912B=m +CONFIG_DRM_LONTIUM_LT9211=m CONFIG_DRM_LONTIUM_LT9611=m CONFIG_DRM_LONTIUM_LT9611UXC=m CONFIG_DRM_ITE_IT66121=m @@ -1095,6 +1099,7 @@ CONFIG_SND_SOC_J721E_EVM=m CONFIG_SND_SOC_AK4613=m CONFIG_SND_SOC_AK4619=m CONFIG_SND_SOC_DA7213=m +CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_ES7134=m CONFIG_SND_SOC_ES7241=m CONFIG_SND_SOC_ES8316=m @@ -1396,6 +1401,16 @@ CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y CONFIG_COMMON_CLK_MT8192_VDECSYS=y CONFIG_COMMON_CLK_MT8192_VENCSYS=y CONFIG_COMMON_CLK_QCOM=y +CONFIG_CLK_GLYMUR_DISPCC=y +CONFIG_CLK_GLYMUR_GCC=y +CONFIG_CLK_GLYMUR_TCSRCC=y +CONFIG_CLK_GLYMUR_GPUCC=m +CONFIG_CLK_KAANAPALI_CAMCC=m +CONFIG_CLK_KAANAPALI_GCC=y +CONFIG_CLK_KAANAPALI_DISPCC=m +CONFIG_CLK_KAANAPALI_GPUCC=m +CONFIG_CLK_KAANAPALI_TCSRCC=m +CONFIG_CLK_KAANAPALI_VIDEOCC=m CONFIG_CLK_X1E80100_CAMCC=m CONFIG_CLK_X1E80100_DISPCC=m CONFIG_CLK_X1E80100_GCC=y @@ -1464,6 +1479,7 @@ CONFIG_SM_CAMCC_6350=m CONFIG_SM_CAMCC_8250=m CONFIG_SM_CAMCC_8550=m CONFIG_SM_CAMCC_8650=m +CONFIG_SM_CAMCC_8750=m CONFIG_SM_DISPCC_6115=m CONFIG_SM_DISPCC_8250=y CONFIG_SM_DISPCC_6350=m @@ -1493,6 +1509,7 @@ CONFIG_SA_VIDEOCC_8775P=m CONFIG_SM_VIDEOCC_6350=m CONFIG_SM_VIDEOCC_8250=y CONFIG_SM_VIDEOCC_8550=m +CONFIG_SM_VIDEOCC_8750=m CONFIG_QCOM_HFPLL=y CONFIG_CLK_GFM_LPASS_SM8250=m CONFIG_SM_VIDEOCC_8450=m @@ -1749,6 +1766,7 @@ CONFIG_OF_FPGA_REGION=m CONFIG_OF_OVERLAY=y CONFIG_TEE=y CONFIG_OPTEE=y +CONFIG_QCOMTEE=y CONFIG_MUX_GPIO=m CONFIG_MUX_MMIO=y CONFIG_SLIMBUS=m @@ -1761,6 +1779,8 @@ CONFIG_INTERCONNECT_IMX8MN=m CONFIG_INTERCONNECT_IMX8MQ=m CONFIG_INTERCONNECT_IMX8MP=y CONFIG_INTERCONNECT_QCOM=y +CONFIG_INTERCONNECT_QCOM_GLYMUR=y +CONFIG_INTERCONNECT_QCOM_KAANAPALI=y CONFIG_INTERCONNECT_QCOM_MSM8916=m CONFIG_INTERCONNECT_QCOM_MSM8953=y CONFIG_INTERCONNECT_QCOM_MSM8996=y