From 98f010fa5e7b5e28c10d2d44a659dc34032adb20 Mon Sep 17 00:00:00 2001 From: Jonathan Bell Date: Fri, 29 May 2026 14:20:27 +0100 Subject: [PATCH 1/2] nvme: pci: use LE accessors for HMB segment table entries on arm64 Align with the non-arm64 code, as it's technically possible to run the cpu in BE mode. Fixes: d30fd123fee1 ("nvme-pci: manually allocate Host Memory Buffer segments on arm64") Signed-off-by: Jonathan Bell --- drivers/nvme/host/pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index 8fe9e696ab4d4..5eb3c4d4d0ab2 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -2431,9 +2431,9 @@ static int nvme_alloc_host_mem_multi(struct nvme_dev *dev, u64 preferred, i = dev->nr_host_mem_descs = mapped_nents; while (--i >= 0) { - descs[i].addr = sg_dma_address(&slist[i]); + descs[i].addr = cpu_to_le64(sg_dma_address(&slist[i])); WARN_ON_ONCE(sg_dma_len(&slist[i]) & (NVME_CTRL_PAGE_SIZE - 1)); - descs[i].size = sg_dma_len(&slist[i]) / NVME_CTRL_PAGE_SIZE; + descs[i].size = cpu_to_le32(sg_dma_len(&slist[i]) / NVME_CTRL_PAGE_SIZE); } dev->host_mem_size = size; From 11aa2004c8187e3f30d6df899ff54704e6444603 Mon Sep 17 00:00:00 2001 From: Jonathan Bell Date: Fri, 29 May 2026 14:31:14 +0100 Subject: [PATCH 2/2] pcie-brcmstb: preserve HARD_DEBUG register bits in brcm_config_clkreq() In commit df289f8bf714 ("pcie-brcmstb: move the unilateral disable of CLKREQ# before link-up") the clkreq_cntl ending up being initialised to zero instead of the read/reset value of the hardware register. Preserve non-clkreq related bits by restoring the read. Signed-off-by: Jonathan Bell --- drivers/pci/controller/pcie-brcmstb.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index b182ab75a8fc5..94d15c85ddba1 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1575,7 +1575,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie) { static const char err_msg[] = "invalid 'brcm,clkreq-mode' DT string\n"; const char *mode = "default"; - u32 clkreq_cntl = 0; + u32 clkreq_cntl; int ret, tmp; ret = of_property_read_string(pcie->np, "brcm,clkreq-mode", &mode); @@ -1584,6 +1584,10 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie) mode = "safe"; } + /* Start out assuming safe mode (both mode bits cleared) */ + clkreq_cntl = readl(pcie->base + HARD_DEBUG(pcie)); + clkreq_cntl &= ~PCIE_CLKREQ_MASK; + if (strcmp(mode, "no-l1ss") == 0) { /* * "no-l1ss" -- Provides Clock Power Management, L0s, and