From 4e13a7805433e526266ee54e32cc6f2be69ad9cf Mon Sep 17 00:00:00 2001 From: Adam Gemmell Date: Fri, 8 May 2026 17:58:49 +0100 Subject: [PATCH] Remove the aes feature from many arm intrinsics The exceptions to this are the vaes* intrinsics, and ones using the P64 variants of PMULL[2] instructions --- .../core_arch/src/aarch64/neon/generated.rs | 60 ++++++------- .../src/arm_shared/neon/generated.rs | 90 +++++++++---------- .../spec/neon/aarch64.spec.yml | 40 ++------- .../spec/neon/arm_shared.spec.yml | 31 +------ 4 files changed, 85 insertions(+), 136 deletions(-) diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs index 8d701d9b88..29ea86a412 100644 --- a/crates/core_arch/src/aarch64/neon/generated.rs +++ b/crates/core_arch/src/aarch64/neon/generated.rs @@ -10212,7 +10212,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { @@ -10223,7 +10223,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ldr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { @@ -10405,7 +10405,7 @@ pub unsafe fn vld2_lane_s64(a: *const i64, b: int64x1x2_t) -> i #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -10431,7 +10431,7 @@ pub unsafe fn vld2_lane_u64(a: *const u64, b: uint64x1x2_t) -> #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2r))] pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t { @@ -10550,7 +10550,7 @@ pub unsafe fn vld2q_lane_s64(a: *const i64, b: int64x2x2_t) -> #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld2, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -10602,7 +10602,7 @@ pub unsafe fn vld2q_lane_p8(a: *const p8, b: poly8x16x2_t) -> p #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2))] pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t { @@ -10715,7 +10715,7 @@ pub unsafe fn vld3_lane_f64(a: *const f64, b: float64x1x3_t) -> #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -10767,7 +10767,7 @@ pub unsafe fn vld3_lane_u64(a: *const u64, b: uint64x1x3_t) -> #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3r))] pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t { @@ -10837,7 +10837,7 @@ pub unsafe fn vld3q_lane_f64(a: *const f64, b: float64x2x3_t) - #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld3, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -10941,7 +10941,7 @@ pub unsafe fn vld3q_lane_p8(a: *const p8, b: poly8x16x3_t) -> p #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t { @@ -11082,7 +11082,7 @@ pub unsafe fn vld4_lane_s64(a: *const i64, b: int64x1x4_t) -> i #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11108,7 +11108,7 @@ pub unsafe fn vld4_lane_u64(a: *const u64, b: uint64x1x4_t) -> #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t { @@ -11233,7 +11233,7 @@ pub unsafe fn vld4q_lane_s64(a: *const i64, b: int64x2x4_t) -> #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -11285,8 +11285,8 @@ pub unsafe fn vld4q_lane_p8(a: *const p8, b: poly8x16x4_t) -> p #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t { transmute(vld4q_s64(transmute(a))) @@ -13627,7 +13627,7 @@ pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 { #[doc = "Polynomial multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p8)"] #[inline] -#[target_feature(enable = "neon")] +#[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(all(test, target_endian = "little"), assert_instr(pmull2))] pub fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t { @@ -23689,7 +23689,7 @@ pub fn vsliq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p64)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -23700,7 +23700,7 @@ pub fn vsli_n_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { #[doc = "Shift Left and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p64)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sli, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24571,7 +24571,7 @@ pub fn vsriq_n_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p64)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24582,7 +24582,7 @@ pub fn vsri_n_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p64)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(sri, N = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24931,7 +24931,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -24943,7 +24943,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(str))] #[allow(clippy::cast_ptr_alignment)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25152,7 +25152,7 @@ pub unsafe fn vst2_lane_s64(a: *mut i64, b: int64x1x2_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25260,7 +25260,7 @@ pub unsafe fn vst2q_lane_s64(a: *mut i64, b: int64x2x2_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -25312,7 +25312,7 @@ pub unsafe fn vst2q_lane_p8(a: *mut p8, b: poly8x16x2_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(st2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vst2q_p64(a: *mut p64, b: poly64x2x2_t) { @@ -25385,8 +25385,8 @@ pub unsafe fn vst3_lane_s64(a: *mut i64, b: int64x1x3_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] #[rustc_legacy_const_generics(2)] pub unsafe fn vst3_lane_p64(a: *mut p64, b: poly64x1x3_t) { @@ -25493,8 +25493,8 @@ pub unsafe fn vst3q_lane_s64(a: *mut i64, b: int64x2x3_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st3, LANE = 0))] #[rustc_legacy_const_generics(2)] pub unsafe fn vst3q_lane_p64(a: *mut p64, b: poly64x2x3_t) { @@ -25545,8 +25545,8 @@ pub unsafe fn vst3q_lane_p8(a: *mut p8, b: poly8x16x3_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st3))] pub unsafe fn vst3q_p64(a: *mut p64, b: poly64x2x3_t) { vst3q_s64(transmute(a), transmute(b)) @@ -25632,8 +25632,8 @@ pub unsafe fn vst4_lane_s64(a: *mut i64, b: int64x1x4_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] #[rustc_legacy_const_generics(2)] pub unsafe fn vst4_lane_p64(a: *mut p64, b: poly64x1x4_t) { @@ -25761,8 +25761,8 @@ pub unsafe fn vst4q_lane_s64(a: *mut i64, b: int64x2x4_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st4, LANE = 0))] #[rustc_legacy_const_generics(2)] pub unsafe fn vst4q_lane_p64(a: *mut p64, b: poly64x2x4_t) { @@ -25813,8 +25813,8 @@ pub unsafe fn vst4q_lane_p8(a: *mut p8, b: poly8x16x4_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[target_feature(enable = "neon,aes")] #[cfg_attr(test, assert_instr(st4))] pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) { vst4q_s64(transmute(a), transmute(b)) diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs index 5284a3c44a..ca9fd31aac 100644 --- a/crates/core_arch/src/arm_shared/neon/generated.rs +++ b/crates/core_arch/src/arm_shared/neon/generated.rs @@ -8560,7 +8560,7 @@ pub fn vcreate_p16(a: u64) -> poly16x4_t { #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p64)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -18551,7 +18551,7 @@ pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] #[cfg_attr( @@ -18972,7 +18972,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t { #[doc = " * Neon intrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon,v7")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.64"))] pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { @@ -19712,7 +19712,7 @@ pub unsafe fn vld1q_lane_u8(ptr: *const u8, src: uint8x16_t) -> #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[rustc_legacy_const_generics(2)] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 0))] @@ -19737,7 +19737,7 @@ pub unsafe fn vld1_lane_p64(ptr: *const p64, src: poly64x1_t) - #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[rustc_legacy_const_generics(2)] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr, LANE = 1))] @@ -19762,8 +19762,8 @@ pub unsafe fn vld1q_lane_p64(ptr: *const p64, src: poly64x2_t) #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] +#[target_feature(enable = "neon")] #[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,aes")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { @@ -19780,7 +19780,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( @@ -19803,7 +19803,7 @@ pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -19826,7 +19826,7 @@ pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -19849,7 +19849,7 @@ pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -19872,7 +19872,7 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -19895,7 +19895,7 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -21560,7 +21560,7 @@ unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))] #[cfg_attr( @@ -21950,7 +21950,7 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -23248,7 +23248,7 @@ pub unsafe fn vld2q_lane_p16(a: *const p16, b: poly16x8x2_t) -> #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -23944,7 +23944,7 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -25189,7 +25189,7 @@ pub unsafe fn vld3q_lane_p16(a: *const p16, b: poly16x8x3_t) -> #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -25899,7 +25899,7 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -27181,8 +27181,8 @@ pub unsafe fn vld4q_lane_p16(a: *const p16, b: poly16x8x4_t) -> #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,aes")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -48738,7 +48738,7 @@ pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -48759,7 +48759,7 @@ pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -48780,7 +48780,7 @@ pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -48801,7 +48801,7 @@ pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -48822,7 +48822,7 @@ pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -48843,7 +48843,7 @@ pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -48864,7 +48864,7 @@ pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -48885,7 +48885,7 @@ pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -48906,7 +48906,7 @@ pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -48927,7 +48927,7 @@ pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -48948,7 +48948,7 @@ pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -48969,7 +48969,7 @@ pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { #[doc = "Vector reinterpret cast operation"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -54287,7 +54287,7 @@ pub fn vsetq_lane_p16(a: p16, b: poly16x8_t) -> poly16x8_t { #[doc = "Insert vector element from another vector element"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p64)"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( @@ -54357,7 +54357,7 @@ pub fn vset_lane_u64(a: u64, b: uint64x1_t) -> uint64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"] #[inline] #[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( @@ -54381,7 +54381,7 @@ pub fn vsetq_lane_p64(a: p64, b: poly64x2_t) -> poly64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"] #[inline] #[cfg(target_endian = "big")] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( @@ -58934,8 +58934,8 @@ pub unsafe fn vst1q_lane_p16(a: *mut p16, b: poly16x8_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,aes")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -59009,7 +59009,7 @@ pub unsafe fn vst1_lane_u64(a: *mut u64, b: uint64x1_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] #[cfg_attr( @@ -59032,7 +59032,7 @@ pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -59055,7 +59055,7 @@ pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -59078,7 +59078,7 @@ pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -59101,7 +59101,7 @@ pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -59124,7 +59124,7 @@ pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( @@ -60991,8 +60991,8 @@ unsafe fn vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,aes")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -61881,8 +61881,8 @@ pub unsafe fn vst2q_lane_p16(a: *mut p16, b: poly16x8x2_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,aes")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -63070,8 +63070,8 @@ pub unsafe fn vst3q_lane_p16(a: *mut p16, b: poly16x8x3_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,aes")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), @@ -64426,8 +64426,8 @@ pub unsafe fn vst4q_lane_p16(a: *mut p16, b: poly16x8x4_t) { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline] +#[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[target_feature(enable = "neon,aes")] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml index 03fea5e0a4..c85d0a8eae 100644 --- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml +++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml @@ -3391,7 +3391,6 @@ intrinsics: arguments: ["a: {type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld2, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-stable @@ -3445,7 +3444,6 @@ intrinsics: arguments: ["a: {type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld2, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-stable @@ -3527,7 +3525,6 @@ intrinsics: arguments: ["a: {type[0]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - *neon-stable assert_instr: [ld2] safety: @@ -3591,7 +3588,6 @@ intrinsics: arguments: ["a: {type[0]}"] return_type: "{type[1]}" attr: - - *neon-aes - *neon-stable assert_instr: [ld2r] safety: @@ -3777,7 +3773,6 @@ intrinsics: arguments: ["a: {type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld3, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-stable @@ -3801,7 +3796,6 @@ intrinsics: arguments: ["a: {type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld3, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-stable @@ -3876,7 +3870,6 @@ intrinsics: arguments: ["a: {type[0]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - *neon-stable safety: unsafe: [neon] @@ -3938,7 +3931,6 @@ intrinsics: arguments: ["a: {type[0]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - *neon-stable assert_instr: [ld3r] safety: @@ -4014,7 +4006,6 @@ intrinsics: return_type: "{neon_type[1]}" attr: - *neon-stable - - *neon-aes assert_instr: [ld4] safety: unsafe: [neon] @@ -4122,7 +4113,6 @@ intrinsics: arguments: ["a: {type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-stable @@ -4169,9 +4159,6 @@ intrinsics: arguments: ["a: {type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[1]}" attr: - - FnCall: - - target_feature - - - 'enable = "neon,aes"' - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-stable @@ -4487,7 +4474,6 @@ intrinsics: doc: "Store multiple 2-element structures from two registers" arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] attr: - - *neon-aes - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st2, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-stable @@ -4507,7 +4493,6 @@ intrinsics: doc: "Store multiple 2-element structures from two registers" arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] attr: - - *neon-aes - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st2, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-stable @@ -4527,7 +4512,6 @@ intrinsics: doc: "Store multiple 2-element structures from two registers" arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] attr: - - *neon-aes - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st2]]}]] - *neon-stable safety: @@ -4557,7 +4541,6 @@ intrinsics: arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] attr: - *neon-stable - - *neon-aes - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st3, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] static_defs: ['const LANE: i32'] @@ -4577,7 +4560,6 @@ intrinsics: arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] attr: - *neon-stable - - *neon-aes - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st3, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] static_defs: ['const LANE: i32'] @@ -4597,7 +4579,6 @@ intrinsics: arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] attr: - *neon-stable - - *neon-aes assert_instr: [st3] safety: unsafe: [neon] @@ -4751,7 +4732,6 @@ intrinsics: arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] attr: - *neon-stable - - *neon-aes - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st4, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] static_defs: ['const LANE: i32'] @@ -4771,7 +4751,6 @@ intrinsics: arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] attr: - *neon-stable - - *neon-aes - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st4, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['2']] static_defs: ['const LANE: i32'] @@ -4791,7 +4770,6 @@ intrinsics: arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] attr: - *neon-stable - - *neon-aes assert_instr: [st4] safety: unsafe: [neon] @@ -5002,6 +4980,7 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] return_type: "{neon_type[1]}" attr: + - *neon-aes - *neon-stable - FnCall: [cfg_attr, [*all-test-little-endian, {FnCall: [assert_instr, [pmull2]]}]] safety: safe @@ -11916,7 +11895,6 @@ intrinsics: arguments: ["a: {type[0]}"] return_type: "{neon_type[1]}" attr: - - FnCall: [target_feature, ['enable = "neon,aes"']] - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4r]]}]] - *neon-stable safety: @@ -12788,8 +12766,8 @@ intrinsics: - ['*const p8', poly8x16_t, "neon"] - ['*const p16', poly16x4_t, "neon"] - ['*const p16', poly16x8_t, "neon"] - - ['*const p64', poly64x1_t, "neon,aes"] - - ['*const p64', poly64x2_t, "neon,aes"] + - ['*const p64', poly64x1_t, "neon"] + - ['*const p64', poly64x2_t, "neon"] - ['*const f32', float32x2_t, "neon"] - ['*const f32', float32x4_t, "neon"] - ['*const f64', float64x1_t, "neon"] @@ -12855,8 +12833,8 @@ intrinsics: - ['*mut p8', poly8x16_t, "neon"] - ['*mut p16', poly16x4_t, "neon"] - ['*mut p16', poly16x8_t, "neon"] - - ['*mut p64', poly64x1_t, "neon,aes"] - - ['*mut p64', poly64x2_t, "neon,aes"] + - ['*mut p64', poly64x1_t, "neon"] + - ['*mut p64', poly64x2_t, "neon"] - ['*mut f32', float32x2_t, "neon"] - ['*mut f32', float32x4_t, "neon"] - ['*mut f64', float64x1_t, "neon"] @@ -13488,8 +13466,8 @@ intrinsics: - [poly8x16_t, int8x16_t, 'static_assert_uimm_bits!', 'N, 3', "neon"] - [poly16x4_t, int16x4_t, 'static_assert_uimm_bits!', 'N, 4', "neon"] - [poly16x8_t, int16x8_t, 'static_assert_uimm_bits!', 'N, 4', "neon"] - - [poly64x1_t, int64x1_t, 'static_assert!', 'N >= 0 && N <= 63', "neon,aes"] - - [poly64x2_t, int64x2_t, 'static_assert!', 'N >= 0 && N <= 63', "neon,aes"] + - [poly64x1_t, int64x1_t, 'static_assert!', 'N >= 0 && N <= 63', "neon"] + - [poly64x2_t, int64x2_t, 'static_assert!', 'N >= 0 && N <= 63', "neon"] compose: - FnCall: ['{type[2]}', ['{type[3]}']] - FnCall: @@ -13550,8 +13528,8 @@ intrinsics: - [poly8x16_t, int8x16_t, 'N >= 1 && N <= 8', "neon"] - [poly16x4_t, int16x4_t, 'N >= 1 && N <= 16', "neon"] - [poly16x8_t, int16x8_t, 'N >= 1 && N <= 16', "neon"] - - [poly64x1_t, int64x1_t, 'N >= 1 && N <= 64', "neon,aes"] - - [poly64x2_t, int64x2_t, 'N >= 1 && N <= 64', "neon,aes"] + - [poly64x1_t, int64x1_t, 'N >= 1 && N <= 64', "neon"] + - [poly64x2_t, int64x2_t, 'N >= 1 && N <= 64', "neon"] compose: - FnCall: ['static_assert!', ['{type[2]}']] - FnCall: diff --git a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml index e8682cf45f..5044be6590 100644 --- a/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml +++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml @@ -2754,7 +2754,6 @@ intrinsics: arguments: ["a: {type[0]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] @@ -2781,7 +2780,6 @@ intrinsics: arguments: ["a: {type[0]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] @@ -3043,7 +3041,6 @@ intrinsics: arguments: ["a: {type[0]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] @@ -3389,7 +3386,6 @@ intrinsics: arguments: ["a: {type[0]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld2r]]}]] @@ -4187,7 +4183,6 @@ intrinsics: arguments: ["a: {type[0]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] @@ -4343,7 +4338,6 @@ intrinsics: arguments: ["a: {type[0]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld3r]]}]] @@ -4555,9 +4549,6 @@ intrinsics: return_type: "{neon_type[1]}" attr: - *neon-v8 - - FnCall: - - target_feature - - - 'enable = "neon,aes"' - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - *neon-not-arm-stable @@ -4676,9 +4667,6 @@ intrinsics: unsafe: [neon] attr: - *neon-v8 - - FnCall: - - target_feature - - - 'enable = "neon,aes"' - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] @@ -4701,9 +4689,6 @@ intrinsics: unsafe: [neon] attr: - *neon-v8 - - FnCall: - - target_feature - - - 'enable = "neon,aes"' - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] @@ -5035,7 +5020,6 @@ intrinsics: arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] attr: - *neon-v8 - - *neon-aes - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - *neon-not-arm-stable @@ -5418,7 +5402,6 @@ intrinsics: arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] attr: - *neon-v8 - - *neon-aes - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - *neon-not-arm-stable @@ -5767,7 +5750,6 @@ intrinsics: arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] attr: - *neon-v8 - - *neon-aes - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - *neon-not-arm-stable @@ -8482,7 +8464,6 @@ intrinsics: arguments: ["a: {type[0]}"] return_type: "{type[1]}" attr: - - *neon-aes - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] @@ -9245,7 +9226,6 @@ intrinsics: arguments: ["a: {type[0]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] @@ -9346,7 +9326,6 @@ intrinsics: arguments: ["a: {type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] @@ -9367,7 +9346,6 @@ intrinsics: arguments: ["a: {type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] @@ -10156,7 +10134,6 @@ intrinsics: doc: "Store multiple single-element structures to one, two, three, or four registers" arguments: ["a: {type[0]}", "b: {neon_type[1]}"] attr: - - *neon-aes - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vst1]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [st1]]}]] @@ -10176,7 +10153,6 @@ intrinsics: doc: "Store multiple single-element structures to one, two, three, or four registers" arguments: ["a: {type[0]}", "b: {neon_type[1]}"] attr: - - *neon-aes - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [st1]]}]] @@ -11898,7 +11874,6 @@ intrinsics: arguments: ["a: {type[0]}"] return_type: "{neon_type[1]}" attr: - - *neon-aes - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld4r]]}]] @@ -12025,7 +12000,7 @@ intrinsics: - ['*const p8', poly8x16_t, '"vld1.8"', 'neon,v7', 'crate::mem::align_of::()', 'q_v16i8'] - ['*const p16', poly16x4_t, '"vld1.16"', 'neon,v7', 'crate::mem::align_of::()', '_v4i16' ] - ['*const p16', poly16x8_t, '"vld1.16"', 'neon,v7', 'crate::mem::align_of::()', 'q_v8i16'] - - ['*const p64', poly64x2_t, '"vld1.64"', 'neon,aes', 'crate::mem::align_of::()', 'q_v2i64'] + - ['*const p64', poly64x2_t, '"vld1.64"', 'neon,v7', 'crate::mem::align_of::()', 'q_v2i64'] - ['*const f32', float32x2_t, 'vldr', 'neon,v7', 'crate::mem::align_of::()', '_v2f32' ] - ['*const f32', float32x4_t, '"vld1.32"', 'neon,v7', 'crate::mem::align_of::()', 'q_v4f32'] compose: @@ -12072,7 +12047,6 @@ intrinsics: unsafe: [neon] attr: - *target-is-arm - - *neon-aes - *neon-arm-unstable - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['vldr']]}]] types: @@ -14305,7 +14279,6 @@ intrinsics: arguments: ["ptr: {type[1]}", "src: {neon_type[2]}"] return_type: "{neon_type[2]}" attr: - - *neon-aes - *neon-v7 - FnCall: [rustc_legacy_const_generics, ['2']] - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ["{type[3]}", 'LANE = {type[4]}']] } ]] @@ -14346,7 +14319,6 @@ intrinsics: arguments: ["ptr: {type[1]}"] return_type: "{neon_type[2]}" attr: - - *neon-aes - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ["{type[3]}"]] } ]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, { FnCall: [assert_instr, ['{type[4]}']]}] ] @@ -14365,7 +14337,6 @@ intrinsics: arguments: ["ptr: {type[1]}"] return_type: "{neon_type[2]}" attr: - - *neon-aes - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ["{type[3]}"]] } ]] - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, { FnCall: [assert_instr, ['{type[4]}']]}] ]