From 771695bda521fa965d6509ce25e7c747ea9c6910 Mon Sep 17 00:00:00 2001 From: Alex Lanzano Date: Tue, 5 May 2026 14:32:09 -0400 Subject: [PATCH 1/7] [error] simplify the error values to reduce code size --- wolfHAL/error.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/wolfHAL/error.h b/wolfHAL/error.h index ed3bc46..071e410 100644 --- a/wolfHAL/error.h +++ b/wolfHAL/error.h @@ -7,26 +7,26 @@ * @brief Shared error codes for wolfHAL APIs. */ -/* Signed 16-bit status code type used by wolfHAL. */ +/* Status code type used by wolfHAL. Zero is success, non-zero is error. */ typedef int whal_Error; enum { /* Operation completed successfully. */ WHAL_SUCCESS = 0, /* Invalid argument (null pointer, bad configuration). */ - WHAL_EINVAL = -4000, + WHAL_EINVAL = 1, /* Resource not ready or busy. */ - WHAL_ENOTREADY = -4001, + WHAL_ENOTREADY = 2, /* Hardware device error. */ - WHAL_EHARDWARE = -4002, + WHAL_EHARDWARE = 3, /* Operation timed out. */ - WHAL_ETIMEOUT = -4003, + WHAL_ETIMEOUT = 4, /* Operation or argument not supported by the selected driver/hardware * (use for requests that are valid in general but this implementation * cannot fulfill — e.g., hardware lacks the feature or the specific * parameter combination isn't supported). For universally invalid * arguments (null pointer, out-of-range enum) return WHAL_EINVAL. */ - WHAL_ENOTSUP = -4004, + WHAL_ENOTSUP = 5, }; #endif /* WHAL_ERROR_H */ From 72ccb12bac860d4c94dcfd6396edfbac4ebb3d0b Mon Sep 17 00:00:00 2001 From: Alex Lanzano Date: Tue, 5 May 2026 14:56:07 -0400 Subject: [PATCH 2/7] [dev, regmap] Drop .regmap field from device structs. use .base instead --- .claude/skills/port-stm32-platform/SKILL.md | 6 +- boards/pic32cz_curiosity_ultra/board.c | 12 +-- boards/stm32c031_nucleo/board.c | 12 +-- boards/stm32f091rc_nucleo/board.c | 16 +-- boards/stm32f302r8_nucleo/board.c | 18 ++-- boards/stm32f411_blackpill/board.c | 12 +-- boards/stm32h563zi_nucleo/board.c | 16 +-- boards/stm32l152re_nucleo/board.c | 20 ++-- boards/stm32n657a0_nucleo/board.c | 28 ++--- boards/stm32wb55xx_nucleo/board.c | 28 ++--- boards/stm32wba55cg_nucleo/board.c | 30 +++--- docs/adding_a_board.md | 2 +- docs/adding_a_test.md | 2 +- docs/getting_started.md | 18 ++-- docs/writing_a_driver.md | 22 ++-- src/clock/pic32cz_clock.c | 27 ++--- src/clock/stm32c0_rcc.c | 14 +-- src/clock/stm32f0_rcc.c | 28 ++--- src/clock/stm32f3_rcc.c | 30 +++--- src/clock/stm32f4_rcc.c | 26 ++--- src/clock/stm32h5_rcc.c | 30 +++--- src/clock/stm32l1_rcc.c | 30 +++--- src/clock/stm32n6_rcc.c | 34 +++--- src/clock/stm32wb_rcc.c | 28 ++--- src/clock/stm32wba_rcc.c | 38 +++---- src/crypto/stm32n6_cryp.c | 28 ++--- src/crypto/stm32wb_aes.c | 28 ++--- src/crypto/stm32wba_hash.c | 10 +- src/dma/stm32wb_dma.c | 12 +-- src/dma/stm32wba_gpdma.c | 12 +-- src/eth/stm32h5_eth.c | 18 ++-- src/eth/stm32n6_eth.c | 18 ++-- src/flash/pic32cz_flash.c | 112 ++++++++++---------- src/flash/stm32c0_flash.c | 43 ++++---- src/flash/stm32f0_flash.c | 33 +++--- src/flash/stm32f4_flash.c | 57 +++++----- src/flash/stm32h5_flash.c | 49 ++++----- src/flash/stm32l1_flash.c | 8 +- src/flash/stm32wb_flash.c | 45 ++++---- src/flash/stm32wba_flash.c | 47 ++++---- src/gpio/pic32cz_gpio.c | 15 +-- src/gpio/stm32wb_gpio.c | 4 +- src/i2c/stm32l1_i2c.c | 8 +- src/i2c/stm32wb_i2c.c | 40 +++---- src/irq/cortex_m4_nvic.c | 4 +- src/power/pic32cz_supc.c | 4 +- src/power/stm32l1_pwr.c | 2 +- src/rng/stm32h5_rng.c | 26 ++--- src/rng/stm32wb_rng.c | 12 +-- src/rng/stm32wba_rng.c | 20 ++-- src/spi/stm32f4_spi.c | 44 ++++---- src/spi/stm32h5_spi.c | 54 +++++----- src/spi/stm32wb_spi.c | 46 ++++---- src/timer/systick.c | 21 ++-- src/uart/pic32cz_uart.c | 52 ++++----- src/uart/stm32f0_uart.c | 32 +++--- src/uart/stm32f4_uart.c | 32 +++--- src/uart/stm32wb_uart.c | 32 +++--- src/uart/stm32wb_uart_dma.c | 26 ++--- src/uart/stm32wba_uart_dma.c | 26 ++--- src/watchdog/stm32f0_wwdg.c | 4 +- src/watchdog/stm32wb_iwdg.c | 18 ++-- src/watchdog/stm32wb_wwdg.c | 4 +- tests/clock/test_pic32cz_clock.c | 10 +- tests/clock/test_stm32wb_clock.c | 6 +- tests/eth/test_stm32n6_eth.c | 3 +- tests/flash/test_stm32wb_flash.c | 2 +- tests/gpio/test_pic32cz_gpio.c | 6 +- tests/gpio/test_stm32wb_gpio.c | 2 +- wolfHAL/block/block.h | 3 +- wolfHAL/clock/clock.h | 4 +- wolfHAL/crypto/crypto.h | 3 +- wolfHAL/dma/dma.h | 3 +- wolfHAL/eth/eth.h | 3 +- wolfHAL/flash/flash.h | 3 +- wolfHAL/gpio/gpio.h | 3 +- wolfHAL/i2c/i2c.h | 3 +- wolfHAL/ipc/ipc.h | 3 +- wolfHAL/irq/irq.h | 3 +- wolfHAL/platform/arm/cortex_m0.h | 4 +- wolfHAL/platform/arm/cortex_m0plus.h | 4 +- wolfHAL/platform/arm/cortex_m3.h | 8 +- wolfHAL/platform/arm/cortex_m33.h | 8 +- wolfHAL/platform/arm/cortex_m4.h | 8 +- wolfHAL/platform/arm/cortex_m55.h | 8 +- wolfHAL/platform/arm/cortex_m7.h | 4 +- wolfHAL/platform/microchip/pic32cz.h | 20 +--- wolfHAL/platform/st/stm32c031xx.h | 24 ++--- wolfHAL/platform/st/stm32f091xx.h | 48 +++------ wolfHAL/platform/st/stm32f302r8.h | 52 +++------ wolfHAL/platform/st/stm32f411xx.h | 32 ++---- wolfHAL/platform/st/stm32h563xx.h | 36 ++----- wolfHAL/platform/st/stm32l152re.h | 56 +++------- wolfHAL/platform/st/stm32n657a0.h | 60 +++-------- wolfHAL/platform/st/stm32wb55xx.h | 56 +++------- wolfHAL/platform/st/stm32wba55cg.h | 60 +++-------- wolfHAL/power/pic32cz_supc.h | 1 + wolfHAL/power/power.h | 4 +- wolfHAL/regmap.h | 8 -- wolfHAL/rng/rng.h | 3 +- wolfHAL/spi/spi.h | 3 +- wolfHAL/timer/timer.h | 3 +- wolfHAL/uart/uart.h | 3 +- wolfHAL/watchdog/stm32wb_iwdg.h | 1 + wolfHAL/watchdog/watchdog.h | 3 +- 105 files changed, 946 insertions(+), 1204 deletions(-) diff --git a/.claude/skills/port-stm32-platform/SKILL.md b/.claude/skills/port-stm32-platform/SKILL.md index 93b40d0..a6d7055 100644 --- a/.claude/skills/port-stm32-platform/SKILL.md +++ b/.claude/skills/port-stm32-platform/SKILL.md @@ -51,7 +51,7 @@ For each device type, decide **reuse existing driver (with alias)** OR **write a The clock driver is almost always new per family. GPIO, I2C, and IWDG/WWDG are almost always reusable. UART, flash, RNG, DMA require careful diffing. -**Clock is the architectural exception.** Unlike every other driver type, the clock subsystem has no `whal_ClockDriver` vtable and no generic `whal_Clock_Init`/`Enable`/`Disable` API. Chip clock drivers expose imperative `Enable*`/`Disable*`/`Set*` helpers (e.g. `whal__Rcc_EnableOsc`, `EnablePll`, `SetSysClock`, `EnablePeriphClk`) and boards call them directly. See `docs/writing_a_driver.md` "Clock" section. The platform header does NOT define a `WHAL__RCC_DRIVER` macro, and the chip's `g_whalClock` global has only `.regmap = { ... }` — no `.driver`, no `.cfg`. Reference: `wolfHAL/clock/stm32wb_rcc.h` and `boards/stm32wb55xx_nucleo/board.c`. +**Clock is the architectural exception.** Unlike every other driver type, the clock subsystem has no `whal_ClockDriver` vtable and no generic `whal_Clock_Init`/`Enable`/`Disable` API. Chip clock drivers expose imperative `Enable*`/`Disable*`/`Set*` helpers (e.g. `whal__Rcc_EnableOsc`, `EnablePll`, `SetSysClock`, `EnablePeriphClk`) and boards call them directly. See `docs/writing_a_driver.md` "Clock" section. The platform header does NOT define a `WHAL__RCC_DRIVER` macro, and the chip's `g_whalClock` global has only `.base = ...` — no `.driver`, no `.cfg`. Reference: `wolfHAL/clock/stm32wb_rcc.h` and `boards/stm32wb55xx_nucleo/board.c`. ## Phase 2 — Platform header @@ -74,7 +74,7 @@ Skeleton: /* ...one include per device type... */ #define WHAL__USART1_DEVICE \ - .regmap = { .base = 0x, .size = 0x400 }, \ + .base = 0x, \ .driver = &whal_Uart_Driver #define WHAL__USART1_CLOCK \ @@ -188,7 +188,7 @@ Create `boards//` with: Exports `extern whal_` instances and declares `Board_Init`/`Board_Deinit`/`Board_WaitMs`. Follow `docs/adding_a_board.md`. ### `board.c` -Define each `whal_` global with its platform macro + board-specific config (pins, baud rates, timeout, DMA channel assignments). The `whal_Clock` global is just `.regmap = { ... }` (no `.driver`, no `.cfg`) since the clock subsystem has no vtable. Implement `Board_Init` in dependency order: PWR → bring up clock tree imperatively (oscillator on, PLL configure+enable, sysclk switch) → enable peripheral clocks → GPIO → UART → Timer → the rest. Keep the watchdog out of `Board_Init` (the app starts it when ready to refresh) per `docs/adding_a_board.md`. Guard DMA-specific setup under `#ifdef BOARD_DMA`, matching `boards/stm32wba55cg_nucleo/board.c`. +Define each `whal_` global with its platform macro + board-specific config (pins, baud rates, timeout, DMA channel assignments). The `whal_Clock` global is just `.base = ...` (no `.driver`, no `.cfg`) since the clock subsystem has no vtable. Implement `Board_Init` in dependency order: PWR → bring up clock tree imperatively (oscillator on, PLL configure+enable, sysclk switch) → enable peripheral clocks → GPIO → UART → Timer → the rest. Keep the watchdog out of `Board_Init` (the app starts it when ready to refresh) per `docs/adding_a_board.md`. Guard DMA-specific setup under `#ifdef BOARD_DMA`, matching `boards/stm32wba55cg_nucleo/board.c`. ### GPIO pin conflict check After writing the `pinCfg` array in `board.c`, scan every entry pair and verify no two entries share the same physical port+pin. This is a common mistake when a pin serves double duty (e.g., PA5 used as both an LED and SPI1_SCK). If a conflict is found, consult the chip's alternate-function table in the datasheet and remap the conflicting peripheral to an alternate pin on a different port. diff --git a/boards/pic32cz_curiosity_ultra/board.c b/boards/pic32cz_curiosity_ultra/board.c index 10ab949..645c95e 100644 --- a/boards/pic32cz_curiosity_ultra/board.c +++ b/boards/pic32cz_curiosity_ultra/board.c @@ -8,12 +8,12 @@ /* Power */ static whal_Power g_whalPower = { - .regmap = { WHAL_PIC32CZ_SUPC_REGMAP }, + .base = WHAL_PIC32CZ_SUPC_BASE, }; /* Clock */ whal_Clock g_whalClock = { - .regmap = { WHAL_PIC32CZ_CLOCK_REGMAP }, + .base = WHAL_PIC32CZ_CLOCK_BASE, }; /* Peripheral clocks */ @@ -30,7 +30,7 @@ static const whal_Pic32cz_Clock_PeriphClk g_periphClks[] = { /* GPIO */ whal_Gpio g_whalGpio = { - .regmap = { WHAL_PIC32CZ_GPIO_REGMAP }, + .base = WHAL_PIC32CZ_GPIO_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Pic32cz_Gpio_Cfg) { @@ -60,7 +60,7 @@ whal_Gpio g_whalGpio = { /* UART */ whal_Uart g_whalUart = { - .regmap = { WHAL_PIC32CZ_SERCOM4_UART_REGMAP }, + .base = WHAL_PIC32CZ_SERCOM4_UART_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Pic32cz_Uart_Cfg) { @@ -72,7 +72,7 @@ whal_Uart g_whalUart = { /* Timer */ whal_Timer g_whalTimer = { - .regmap = { WHAL_CORTEX_M7_SYSTICK_REGMAP }, + .base = WHAL_CORTEX_M7_SYSTICK_BASE, .driver = WHAL_CORTEX_M7_SYSTICK_DRIVER, .cfg = &(whal_SysTick_Cfg) { @@ -84,7 +84,7 @@ whal_Timer g_whalTimer = { /* Flash */ whal_Flash g_whalFlash = { - .regmap = { WHAL_PIC32CZ_FLASH_REGMAP }, + .base = WHAL_PIC32CZ_FLASH_BASE, .driver = WHAL_PIC32CZ_FLASH_DRIVER, }; diff --git a/boards/stm32c031_nucleo/board.c b/boards/stm32c031_nucleo/board.c index 76e4e7a..02fc763 100644 --- a/boards/stm32c031_nucleo/board.c +++ b/boards/stm32c031_nucleo/board.c @@ -32,7 +32,7 @@ whal_Timeout g_whalTimeout = { /* Clock */ whal_Clock g_whalClock = { - .regmap = { WHAL_STM32C031_RCC_REGMAP }, + .base = WHAL_STM32C031_RCC_BASE, }; static const whal_Stm32c0_Rcc_PeriphClk g_periphClks[] = { @@ -46,7 +46,7 @@ static const whal_Stm32c0_Rcc_PeriphClk g_periphClks[] = { /* GPIO */ whal_Gpio g_whalGpio = { - .regmap = { WHAL_STM32C031_GPIO_REGMAP }, + .base = WHAL_STM32C031_GPIO_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32c0_Gpio_Cfg) { @@ -88,7 +88,7 @@ whal_Gpio g_whalGpio = { /* Timer */ whal_Timer g_whalTimer = { - .regmap = { WHAL_CORTEX_M0PLUS_SYSTICK_REGMAP }, + .base = WHAL_CORTEX_M0PLUS_SYSTICK_BASE, .driver = WHAL_CORTEX_M0PLUS_SYSTICK_DRIVER, .cfg = &(whal_SysTick_Cfg) { @@ -100,7 +100,7 @@ whal_Timer g_whalTimer = { /* UART */ whal_Uart g_whalUart = { - .regmap = { WHAL_STM32C031_USART2_REGMAP }, + .base = WHAL_STM32C031_USART2_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32c0_Uart_Cfg) { @@ -111,7 +111,7 @@ whal_Uart g_whalUart = { /* SPI */ whal_Spi g_whalSpi = { - .regmap = { WHAL_STM32C031_SPI1_REGMAP }, + .base = WHAL_STM32C031_SPI1_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32c0_Spi_Cfg) { @@ -122,7 +122,7 @@ whal_Spi g_whalSpi = { /* Flash */ whal_Flash g_whalFlash = { - .regmap = { WHAL_STM32C031_FLASH_REGMAP }, + .base = WHAL_STM32C031_FLASH_BASE, .driver = WHAL_STM32C031_FLASH_DRIVER, .cfg = &(whal_Stm32c0_Flash_Cfg) { diff --git a/boards/stm32f091rc_nucleo/board.c b/boards/stm32f091rc_nucleo/board.c index 804509a..06d9dfd 100644 --- a/boards/stm32f091rc_nucleo/board.c +++ b/boards/stm32f091rc_nucleo/board.c @@ -29,7 +29,7 @@ whal_Timeout g_whalTimeout = { /* Clock — PLL at 48 MHz (HSI/2 * 12) */ whal_Clock g_whalClock = { - .regmap = { WHAL_STM32F091_RCC_REGMAP }, + .base = WHAL_STM32F091_RCC_BASE, }; static const whal_Stm32f0_Rcc_PeriphClk g_periphClks[] = { @@ -44,7 +44,7 @@ static const whal_Stm32f0_Rcc_PeriphClk g_periphClks[] = { /* GPIO */ whal_Gpio g_whalGpio = { - .regmap = { WHAL_STM32F091_GPIO_REGMAP }, + .base = WHAL_STM32F091_GPIO_BASE, .cfg = &(whal_Stm32f0_Gpio_Cfg) { .pinCfg = (whal_Stm32f0_Gpio_PinCfg[PIN_COUNT]) { @@ -100,7 +100,7 @@ whal_Gpio g_whalGpio = { /* Timer — SysTick at 1 ms */ whal_Timer g_whalTimer = { - .regmap = { WHAL_CORTEX_M0_SYSTICK_REGMAP }, + .base = WHAL_CORTEX_M0_SYSTICK_BASE, .driver = WHAL_CORTEX_M0_SYSTICK_DRIVER, .cfg = &(whal_SysTick_Cfg) { @@ -112,7 +112,7 @@ whal_Timer g_whalTimer = { /* UART — USART2 at 115200 baud */ whal_Uart g_whalUart = { - .regmap = { WHAL_STM32F091_USART2_REGMAP }, + .base = WHAL_STM32F091_USART2_BASE, .cfg = &(whal_Stm32f0_Uart_Cfg) { .timeout = &g_whalTimeout, @@ -122,7 +122,7 @@ whal_Uart g_whalUart = { /* SPI */ whal_Spi g_whalSpi = { - .regmap = { WHAL_STM32F091_SPI1_REGMAP }, + .base = WHAL_STM32F091_SPI1_BASE, .cfg = &(whal_Stm32f0_Spi_Cfg) { .pclk = 48000000, @@ -132,7 +132,7 @@ whal_Spi g_whalSpi = { /* I2C — I2C1 */ whal_I2c g_whalI2c = { - .regmap = { WHAL_STM32F091_I2C1_REGMAP }, + .base = WHAL_STM32F091_I2C1_BASE, .cfg = &(whal_Stm32f0_I2c_Cfg) { .pclk = 48000000, @@ -142,7 +142,7 @@ whal_I2c g_whalI2c = { /* Flash — 256 KB */ whal_Flash g_whalFlash = { - .regmap = { WHAL_STM32F091_FLASH_REGMAP }, + .base = WHAL_STM32F091_FLASH_BASE, .driver = WHAL_STM32F091_FLASH_DRIVER, .cfg = &(whal_Stm32f0_Flash_Cfg) { @@ -154,7 +154,7 @@ whal_Flash g_whalFlash = { #ifdef BOARD_WATCHDOG_IWDG whal_Watchdog g_whalWatchdog = { - .regmap = { WHAL_STM32F091_IWDG_REGMAP }, + .base = WHAL_STM32F091_IWDG_BASE, .driver = WHAL_STM32F091_IWDG_DRIVER, .cfg = &(whal_Stm32f0_Iwdg_Cfg) { diff --git a/boards/stm32f302r8_nucleo/board.c b/boards/stm32f302r8_nucleo/board.c index e8d0eb8..804aad6 100644 --- a/boards/stm32f302r8_nucleo/board.c +++ b/boards/stm32f302r8_nucleo/board.c @@ -29,7 +29,7 @@ whal_Timeout g_whalTimeout = { /* Clock — PLL at 48 MHz (HSI/2 * 12) */ whal_Clock g_whalClock = { - .regmap = { WHAL_STM32F302_RCC_REGMAP }, + .base = WHAL_STM32F302_RCC_BASE, }; static const whal_Stm32f3_Rcc_PeriphClk g_periphClks[] = { @@ -47,7 +47,7 @@ static const whal_Stm32f3_Rcc_PeriphClk g_periphClks[] = { /* GPIO */ whal_Gpio g_whalGpio = { - .regmap = { WHAL_STM32F302_GPIO_REGMAP }, + .base = WHAL_STM32F302_GPIO_BASE, .cfg = &(whal_Stm32f3_Gpio_Cfg) { .pinCfg = (whal_Stm32f3_Gpio_PinCfg[PIN_COUNT]) { @@ -103,7 +103,7 @@ whal_Gpio g_whalGpio = { /* Timer — SysTick at 1 ms */ whal_Timer g_whalTimer = { - .regmap = { WHAL_CORTEX_M4_SYSTICK_REGMAP }, + .base = WHAL_CORTEX_M4_SYSTICK_BASE, .driver = WHAL_CORTEX_M4_SYSTICK_DRIVER, .cfg = &(whal_SysTick_Cfg) { @@ -115,7 +115,7 @@ whal_Timer g_whalTimer = { /* UART — USART2 at 115200 baud */ whal_Uart g_whalUart = { - .regmap = { WHAL_STM32F302_USART2_REGMAP }, + .base = WHAL_STM32F302_USART2_BASE, .cfg = &(whal_Stm32f3_Uart_Cfg) { .timeout = &g_whalTimeout, @@ -125,7 +125,7 @@ whal_Uart g_whalUart = { /* SPI — SPI3 */ whal_Spi g_whalSpi = { - .regmap = { WHAL_STM32F302_SPI3_REGMAP }, + .base = WHAL_STM32F302_SPI3_BASE, .cfg = &(whal_Stm32f3_Spi_Cfg) { .pclk = 48000000, @@ -135,7 +135,7 @@ whal_Spi g_whalSpi = { /* I2C — I2C1 (HSI at 8 MHz per RCC_CFGR3.I2C1SW reset default) */ whal_I2c g_whalI2c = { - .regmap = { WHAL_STM32F302_I2C1_REGMAP }, + .base = WHAL_STM32F302_I2C1_BASE, .cfg = &(whal_Stm32f3_I2c_Cfg) { .pclk = 8000000, @@ -145,7 +145,7 @@ whal_I2c g_whalI2c = { /* Flash — 64 KB */ whal_Flash g_whalFlash = { - .regmap = { WHAL_STM32F302_FLASH_REGMAP }, + .base = WHAL_STM32F302_FLASH_BASE, .driver = WHAL_STM32F302_FLASH_DRIVER, .cfg = &(whal_Stm32f3_Flash_Cfg) { @@ -157,7 +157,7 @@ whal_Flash g_whalFlash = { #ifdef BOARD_WATCHDOG_IWDG whal_Watchdog g_whalWatchdog = { - .regmap = { WHAL_STM32F302_IWDG_REGMAP }, + .base = WHAL_STM32F302_IWDG_BASE, .driver = WHAL_STM32F302_IWDG_DRIVER, .cfg = &(whal_Stm32f3_Iwdg_Cfg) { @@ -168,7 +168,7 @@ whal_Watchdog g_whalWatchdog = { }; #elif defined(BOARD_WATCHDOG_WWDG) whal_Watchdog g_whalWatchdog = { - .regmap = { WHAL_STM32F302_WWDG_REGMAP }, + .base = WHAL_STM32F302_WWDG_BASE, .driver = WHAL_STM32F302_WWDG_DRIVER, .cfg = &(whal_Stm32f3_Wwdg_Cfg) { diff --git a/boards/stm32f411_blackpill/board.c b/boards/stm32f411_blackpill/board.c index 6cebb64..c7a4c81 100644 --- a/boards/stm32f411_blackpill/board.c +++ b/boards/stm32f411_blackpill/board.c @@ -39,7 +39,7 @@ static const whal_Stm32f4_Flash_Sector g_flashSectors[] = { /* Clock */ whal_Clock g_whalClock = { - .regmap = { WHAL_STM32F411_RCC_REGMAP }, + .base = WHAL_STM32F411_RCC_BASE, }; static const whal_Stm32f4_Rcc_PeriphClk g_periphClks[] = { @@ -52,7 +52,7 @@ static const whal_Stm32f4_Rcc_PeriphClk g_periphClks[] = { /* GPIO */ whal_Gpio g_whalGpio = { - .regmap = { WHAL_STM32F411_GPIO_REGMAP }, + .base = WHAL_STM32F411_GPIO_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32f4_Gpio_Cfg) { @@ -94,7 +94,7 @@ whal_Gpio g_whalGpio = { /* Timer */ whal_Timer g_whalTimer = { - .regmap = { WHAL_CORTEX_M4_SYSTICK_REGMAP }, + .base = WHAL_CORTEX_M4_SYSTICK_BASE, .driver = WHAL_CORTEX_M4_SYSTICK_DRIVER, .cfg = &(whal_SysTick_Cfg) { @@ -106,7 +106,7 @@ whal_Timer g_whalTimer = { /* UART */ whal_Uart g_whalUart = { - .regmap = { WHAL_STM32F411_USART2_REGMAP }, + .base = WHAL_STM32F411_USART2_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32f4_Uart_Cfg) { @@ -117,7 +117,7 @@ whal_Uart g_whalUart = { /* SPI */ whal_Spi g_whalSpi = { - .regmap = { WHAL_STM32F411_SPI1_REGMAP }, + .base = WHAL_STM32F411_SPI1_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32f4_Spi_Cfg) { @@ -128,7 +128,7 @@ whal_Spi g_whalSpi = { /* Flash */ whal_Flash g_whalFlash = { - .regmap = { WHAL_STM32F411_FLASH_REGMAP }, + .base = WHAL_STM32F411_FLASH_BASE, .driver = WHAL_STM32F411_FLASH_DRIVER, .cfg = &(whal_Stm32f4_Flash_Cfg) { diff --git a/boards/stm32h563zi_nucleo/board.c b/boards/stm32h563zi_nucleo/board.c index 3076af8..a451e2d 100644 --- a/boards/stm32h563zi_nucleo/board.c +++ b/boards/stm32h563zi_nucleo/board.c @@ -27,7 +27,7 @@ whal_Timeout g_whalTimeout = { /* Clock */ whal_Clock g_whalClock = { - .regmap = { WHAL_STM32H563_RCC_REGMAP }, + .base = WHAL_STM32H563_RCC_BASE, }; static const whal_Stm32h5_Rcc_PeriphClk g_periphClks[] = { @@ -52,7 +52,7 @@ static const whal_Stm32h5_Rcc_PeriphClk g_ethClocks[] = { /* GPIO */ whal_Gpio g_whalGpio = { - .regmap = { WHAL_STM32H563_GPIO_REGMAP }, + .base = WHAL_STM32H563_GPIO_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32h5_Gpio_Cfg) { @@ -144,7 +144,7 @@ whal_Gpio g_whalGpio = { /* Timer */ whal_Timer g_whalTimer = { - .regmap = { WHAL_CORTEX_M33_SYSTICK_REGMAP }, + .base = WHAL_CORTEX_M33_SYSTICK_BASE, .driver = WHAL_CORTEX_M33_SYSTICK_DRIVER, .cfg = &(whal_SysTick_Cfg) { @@ -156,7 +156,7 @@ whal_Timer g_whalTimer = { /* UART */ whal_Uart g_whalUart = { - .regmap = { WHAL_STM32H563_USART3_REGMAP }, + .base = WHAL_STM32H563_USART3_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32h5_Uart_Cfg) { @@ -167,7 +167,7 @@ whal_Uart g_whalUart = { /* SPI */ whal_Spi g_whalSpi = { - .regmap = { WHAL_STM32H563_SPI1_REGMAP }, + .base = WHAL_STM32H563_SPI1_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32h5_Spi_Cfg) { @@ -178,7 +178,7 @@ whal_Spi g_whalSpi = { /* RNG */ whal_Rng g_whalRng = { - .regmap = { WHAL_STM32H563_RNG_REGMAP }, + .base = WHAL_STM32H563_RNG_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32h5_Rng_Cfg) { @@ -189,7 +189,7 @@ whal_Rng g_whalRng = { /* Flash */ whal_Flash g_whalFlash = { - .regmap = { WHAL_STM32H563_FLASH_REGMAP }, + .base = WHAL_STM32H563_FLASH_BASE, .driver = WHAL_STM32H563_FLASH_DRIVER, .cfg = &(whal_Stm32h5_Flash_Cfg) { @@ -215,7 +215,7 @@ static uint8_t ethRxBufs[ETH_RX_DESC_COUNT * ETH_RX_BUF_SIZE] __attribute__((aligned(4))); whal_Eth g_whalEth = { - .regmap = { WHAL_STM32H563_ETH_REGMAP }, + .base = WHAL_STM32H563_ETH_BASE, /* .driver: direct API mapping */ .macAddr = {0x00, 0x80, 0xE1, 0x00, 0x00, 0x01}, diff --git a/boards/stm32l152re_nucleo/board.c b/boards/stm32l152re_nucleo/board.c index 5ec167d..ac1d063 100644 --- a/boards/stm32l152re_nucleo/board.c +++ b/boards/stm32l152re_nucleo/board.c @@ -34,7 +34,7 @@ whal_Timeout g_whalTimeout = { * SYSCLK = PLLVCO / PLLDIV = 64 MHz / 2 = 32 MHz */ whal_Clock g_whalClock = { - .regmap = { WHAL_STM32L152_RCC_REGMAP }, + .base = WHAL_STM32L152_RCC_BASE, }; static const whal_Stm32l1_Rcc_PeriphClk g_pwrClock = {WHAL_STM32L152_PWR_CLOCK}; @@ -54,12 +54,12 @@ static const whal_Stm32l1_Rcc_PeriphClk g_periphClks[] = { /* PWR -- Range 1 (1.8 V) to allow SYSCLK up to 32 MHz. */ whal_Power g_whalPower = { - .regmap = { WHAL_STM32L152_PWR_REGMAP }, + .base = WHAL_STM32L152_PWR_BASE, }; /* GPIO */ whal_Gpio g_whalGpio = { - .regmap = { WHAL_STM32L152_GPIO_REGMAP }, + .base = WHAL_STM32L152_GPIO_BASE, .cfg = &(whal_Stm32l1_Gpio_Cfg) { .pinCfg = (whal_Stm32l1_Gpio_PinCfg[PIN_COUNT]) { @@ -115,7 +115,7 @@ whal_Gpio g_whalGpio = { /* Timer -- SysTick at 1 ms (32 MHz / 1000) */ whal_Timer g_whalTimer = { - .regmap = { WHAL_CORTEX_M3_SYSTICK_REGMAP }, + .base = WHAL_CORTEX_M3_SYSTICK_BASE, .driver = WHAL_CORTEX_M3_SYSTICK_DRIVER, .cfg = &(whal_SysTick_Cfg) { @@ -127,7 +127,7 @@ whal_Timer g_whalTimer = { /* UART -- USART2 at 115200 baud */ whal_Uart g_whalUart = { - .regmap = { WHAL_STM32L152_USART2_REGMAP }, + .base = WHAL_STM32L152_USART2_BASE, .cfg = &(whal_Stm32l1_Uart_Cfg) { .timeout = &g_whalTimeout, @@ -137,7 +137,7 @@ whal_Uart g_whalUart = { /* SPI -- SPI3 */ whal_Spi g_whalSpi = { - .regmap = { WHAL_STM32L152_SPI3_REGMAP }, + .base = WHAL_STM32L152_SPI3_BASE, .cfg = &(whal_Stm32l1_Spi_Cfg) { .pclk = 32000000, @@ -147,7 +147,7 @@ whal_Spi g_whalSpi = { /* I2C -- I2C1 */ whal_I2c g_whalI2c = { - .regmap = { WHAL_STM32L152_I2C1_REGMAP }, + .base = WHAL_STM32L152_I2C1_BASE, .cfg = &(whal_Stm32l1_I2c_Cfg) { .pclk = 32000000, @@ -157,7 +157,7 @@ whal_I2c g_whalI2c = { /* Flash -- 512 KB */ whal_Flash g_whalFlash = { - .regmap = { WHAL_STM32L152_FLASH_REGMAP }, + .base = WHAL_STM32L152_FLASH_BASE, .driver = WHAL_STM32L152_FLASH_DRIVER, .cfg = &(whal_Stm32l1_Flash_Cfg) { @@ -169,7 +169,7 @@ whal_Flash g_whalFlash = { #ifdef BOARD_WATCHDOG_IWDG whal_Watchdog g_whalWatchdog = { - .regmap = { WHAL_STM32L152_IWDG_REGMAP }, + .base = WHAL_STM32L152_IWDG_BASE, .driver = WHAL_STM32L152_IWDG_DRIVER, .cfg = &(whal_Stm32l1_Iwdg_Cfg) { @@ -180,7 +180,7 @@ whal_Watchdog g_whalWatchdog = { }; #elif defined(BOARD_WATCHDOG_WWDG) whal_Watchdog g_whalWatchdog = { - .regmap = { WHAL_STM32L152_WWDG_REGMAP }, + .base = WHAL_STM32L152_WWDG_BASE, .driver = WHAL_STM32L152_WWDG_DRIVER, .cfg = &(whal_Stm32l1_Wwdg_Cfg) { diff --git a/boards/stm32n657a0_nucleo/board.c b/boards/stm32n657a0_nucleo/board.c index b5deafa..d73d5dd 100644 --- a/boards/stm32n657a0_nucleo/board.c +++ b/boards/stm32n657a0_nucleo/board.c @@ -27,7 +27,7 @@ whal_Timeout g_whalTimeout = { /* IRQ */ whal_Irq g_whalIrq = { - .regmap = { WHAL_CORTEX_M55_NVIC_REGMAP }, + .base = WHAL_CORTEX_M55_NVIC_BASE, .driver = WHAL_CORTEX_M55_NVIC_DRIVER, }; @@ -36,7 +36,7 @@ whal_Irq g_whalIrq = { * For initial bring-up, run at HSI 64 MHz. */ /* API is directly mapped */ whal_Clock g_whalClock = { - .regmap = { WHAL_STM32N657_RCC_REGMAP }, + .base = WHAL_STM32N657_RCC_BASE, }; static const whal_Stm32n6_Rcc_PeriphClk g_periphClks[] = { @@ -68,7 +68,7 @@ static const whal_Stm32n6_Rcc_PeriphClk g_ethClocks[] = { /* GPIO */ /* API is directly mapped */ whal_Gpio g_whalGpio = { - .regmap = { WHAL_STM32N657_GPIO_REGMAP }, + .base = WHAL_STM32N657_GPIO_BASE, .cfg = &(whal_Stm32n6_Gpio_Cfg) { .pinCfg = (whal_Stm32n6_Gpio_PinCfg[PIN_COUNT]) { @@ -170,7 +170,7 @@ whal_Gpio g_whalGpio = { /* I2C */ /* API is directly mapped */ whal_I2c g_whalI2c = { - .regmap = { WHAL_STM32N657_I2C1_REGMAP }, + .base = WHAL_STM32N657_I2C1_BASE, .cfg = &(whal_Stm32n6_I2c_Cfg) { .pclk = 64000000, @@ -181,7 +181,7 @@ whal_I2c g_whalI2c = { /* SPI */ /* API is directly mapped */ whal_Spi g_whalSpi = { - .regmap = { WHAL_STM32N657_SPI1_REGMAP }, + .base = WHAL_STM32N657_SPI1_BASE, .cfg = &(whal_Stm32n6_Spi_Cfg) { .pclk = 64000000, @@ -191,7 +191,7 @@ whal_Spi g_whalSpi = { /* Timer (SysTick at 64 MHz HSI) */ whal_Timer g_whalTimer = { - .regmap = { WHAL_CORTEX_M55_SYSTICK_REGMAP }, + .base = WHAL_CORTEX_M55_SYSTICK_BASE, .driver = WHAL_CORTEX_M55_SYSTICK_DRIVER, .cfg = &(whal_SysTick_Cfg) { @@ -205,7 +205,7 @@ whal_Timer g_whalTimer = { #ifdef BOARD_DMA /* API is directly mapped */ whal_Dma g_whalDma1 = { - .regmap = { WHAL_STM32N657_GPDMA1_REGMAP }, + .base = WHAL_STM32N657_GPDMA1_BASE, .cfg = &(whal_Stm32n6_Gpdma_Cfg){ .numChannels = 16, .timeout = &g_whalTimeout, @@ -218,7 +218,7 @@ static const whal_Stm32n6_Rcc_PeriphClk g_dmaClock = {WHAL_STM32N657_GPDMA1_CLOC /* UART (USART1 via VCP at 115200 baud, 64 MHz HSI) */ /* API is directly mapped */ whal_Uart g_whalUart = { - .regmap = { WHAL_STM32N657_USART1_REGMAP }, + .base = WHAL_STM32N657_USART1_BASE, .cfg = &(whal_Stm32n6_Uart_Cfg) { .timeout = &g_whalTimeout, @@ -229,7 +229,7 @@ whal_Uart g_whalUart = { /* RNG */ /* API is directly mapped */ whal_Rng g_whalRng = { - .regmap = { WHAL_STM32N657_RNG_REGMAP }, + .base = WHAL_STM32N657_RNG_BASE, .cfg = &(whal_Stm32n6_Rng_Cfg) { .timeout = &g_whalTimeout, @@ -238,7 +238,7 @@ whal_Rng g_whalRng = { /* Crypto (CRYP hardware accelerator) */ whal_Crypto g_whalCrypto = { - .regmap = { WHAL_STM32N657_CRYP_REGMAP }, + .base = WHAL_STM32N657_CRYP_BASE, .driver = WHAL_STM32N657_CRYP_DRIVER, .cfg = &(whal_Stm32n6_Cryp_Cfg) { @@ -248,7 +248,7 @@ whal_Crypto g_whalCrypto = { /* Hash (HASH hardware accelerator) */ whal_Crypto g_whalHash = { - .regmap = { WHAL_STM32N657_HASH_REGMAP }, + .base = WHAL_STM32N657_HASH_BASE, .driver = WHAL_STM32N657_HASH_DRIVER, .cfg = &(whal_Stm32n6_Hash_Cfg) { @@ -258,7 +258,7 @@ whal_Crypto g_whalHash = { #ifdef BOARD_WATCHDOG_IWDG whal_Watchdog g_whalWatchdog = { - .regmap = { WHAL_STM32N657_IWDG_REGMAP }, + .base = WHAL_STM32N657_IWDG_BASE, .driver = WHAL_STM32N657_IWDG_DRIVER, .cfg = &(whal_Stm32n6_Iwdg_Cfg) { @@ -269,7 +269,7 @@ whal_Watchdog g_whalWatchdog = { }; #elif defined(BOARD_WATCHDOG_WWDG) whal_Watchdog g_whalWatchdog = { - .regmap = { WHAL_STM32N657_WWDG_REGMAP }, + .base = WHAL_STM32N657_WWDG_BASE, .driver = WHAL_STM32N657_WWDG_DRIVER, .cfg = &(whal_Stm32n6_Wwdg_Cfg) { @@ -301,7 +301,7 @@ static uint8_t ethRxBufs[ETH_RX_DESC_COUNT * ETH_RX_BUF_SIZE] /* API is directly mapped */ whal_Eth g_whalEth = { - .regmap = { WHAL_STM32N657_ETH_REGMAP }, + .base = WHAL_STM32N657_ETH_BASE, .macAddr = {0x00, 0x80, 0xE1, 0x00, 0x00, 0x01}, .cfg = &(whal_Stm32n6_Eth_Cfg) { diff --git a/boards/stm32wb55xx_nucleo/board.c b/boards/stm32wb55xx_nucleo/board.c index 132689e..5f25420 100644 --- a/boards/stm32wb55xx_nucleo/board.c +++ b/boards/stm32wb55xx_nucleo/board.c @@ -27,13 +27,13 @@ whal_Timeout g_whalTimeout = { /* IRQ */ whal_Irq g_whalIrq = { - .regmap = { WHAL_CORTEX_M4_NVIC_REGMAP }, + .base = WHAL_CORTEX_M4_NVIC_BASE, .driver = WHAL_CORTEX_M4_NVIC_DRIVER, }; /* Clock */ whal_Clock g_whalClock = { - .regmap = { WHAL_STM32WB55_RCC_REGMAP }, + .base = WHAL_STM32WB55_RCC_BASE, /* .driver: direct API mapping */ }; @@ -53,7 +53,7 @@ static const whal_Stm32wb_Rcc_PeriphClk g_periphClks[] = { /* GPIO */ whal_Gpio g_whalGpio = { - .regmap = { WHAL_STM32WB55_GPIO_REGMAP }, + .base = WHAL_STM32WB55_GPIO_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32wb_Gpio_Cfg) { @@ -110,7 +110,7 @@ whal_Gpio g_whalGpio = { /* I2C */ whal_I2c g_whalI2c = { - .regmap = { WHAL_STM32WB55_I2C1_REGMAP }, + .base = WHAL_STM32WB55_I2C1_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32wb_I2c_Cfg) { @@ -121,7 +121,7 @@ whal_I2c g_whalI2c = { /* SPI */ whal_Spi g_whalSpi = { - .regmap = { WHAL_STM32WB55_SPI1_REGMAP }, + .base = WHAL_STM32WB55_SPI1_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32wb_Spi_Cfg) { @@ -132,7 +132,7 @@ whal_Spi g_whalSpi = { /* Timer */ whal_Timer g_whalTimer = { - .regmap = { WHAL_CORTEX_M4_SYSTICK_REGMAP }, + .base = WHAL_CORTEX_M4_SYSTICK_BASE, .driver = WHAL_CORTEX_M4_SYSTICK_DRIVER, .cfg = &(whal_SysTick_Cfg) { @@ -146,7 +146,7 @@ whal_Timer g_whalTimer = { #ifdef BOARD_DMA whal_Dma g_whalDma1 = { - .regmap = { WHAL_STM32WB55_DMA1_REGMAP }, + .base = WHAL_STM32WB55_DMA1_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32wb_Dma_Cfg){WHAL_STM32WB55_DMA1_CFG}, }; @@ -167,7 +167,7 @@ void DMA1_Channel5_IRQHandler(void) /* UART */ #ifdef BOARD_DMA whal_Uart g_whalUart = { - .regmap = { WHAL_STM32WB55_UART1_REGMAP }, + .base = WHAL_STM32WB55_UART1_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32wb_UartDma_Cfg) { .base = { @@ -183,7 +183,7 @@ whal_Uart g_whalUart = { }; #else whal_Uart g_whalUart = { - .regmap = { WHAL_STM32WB55_UART1_REGMAP }, + .base = WHAL_STM32WB55_UART1_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32wb_Uart_Cfg) { @@ -196,7 +196,7 @@ whal_Uart g_whalUart = { /* Flash */ whal_Flash g_whalFlash = { - .regmap = { WHAL_STM32WB55_FLASH_REGMAP }, + .base = WHAL_STM32WB55_FLASH_BASE, .driver = WHAL_STM32WB55_FLASH_DRIVER, .cfg = &(whal_Stm32wb_Flash_Cfg) { @@ -209,7 +209,7 @@ whal_Flash g_whalFlash = { /* RNG */ whal_Rng g_whalRng = { - .regmap = { WHAL_STM32WB55_RNG_REGMAP }, + .base = WHAL_STM32WB55_RNG_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32wb_Rng_Cfg) { @@ -219,7 +219,7 @@ whal_Rng g_whalRng = { /* Crypto */ whal_Crypto g_whalCrypto = { - .regmap = { WHAL_STM32WB55_AES1_REGMAP }, + .base = WHAL_STM32WB55_AES1_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32wb_Aes_Cfg) { @@ -229,7 +229,7 @@ whal_Crypto g_whalCrypto = { #ifdef BOARD_WATCHDOG_IWDG whal_Watchdog g_whalWatchdog = { - .regmap = { WHAL_STM32WB55_IWDG_REGMAP }, + .base = WHAL_STM32WB55_IWDG_BASE, .driver = WHAL_STM32WB55_IWDG_DRIVER, .cfg = &(whal_Stm32wb_Iwdg_Cfg) { @@ -240,7 +240,7 @@ whal_Watchdog g_whalWatchdog = { }; #elif defined(BOARD_WATCHDOG_WWDG) whal_Watchdog g_whalWatchdog = { - .regmap = { WHAL_STM32WB55_WWDG_REGMAP }, + .base = WHAL_STM32WB55_WWDG_BASE, .driver = WHAL_STM32WB55_WWDG_DRIVER, .cfg = &(whal_Stm32wb_Wwdg_Cfg) { diff --git a/boards/stm32wba55cg_nucleo/board.c b/boards/stm32wba55cg_nucleo/board.c index 41c1678..815db56 100644 --- a/boards/stm32wba55cg_nucleo/board.c +++ b/boards/stm32wba55cg_nucleo/board.c @@ -26,7 +26,7 @@ whal_Timeout g_whalTimeout = { /* IRQ */ whal_Irq g_whalIrq = { - .regmap = { WHAL_CORTEX_M33_NVIC_REGMAP }, + .base = WHAL_CORTEX_M33_NVIC_BASE, .driver = WHAL_CORTEX_M33_NVIC_DRIVER, }; @@ -38,7 +38,7 @@ whal_Irq g_whalIrq = { * PLL1RGE = 3 (8-16 MHz range) */ whal_Clock g_whalClock = { - .regmap = { WHAL_STM32WBA55_RCC_REGMAP }, + .base = WHAL_STM32WBA55_RCC_BASE, }; static const whal_Stm32wba_Rcc_PeriphClk g_flashClock = {WHAL_STM32WBA55_FLASH_CLOCK}; @@ -61,7 +61,7 @@ static const whal_Stm32wba_Rcc_PeriphClk g_periphClks[] = { /* GPIO */ whal_Gpio g_whalGpio = { - .regmap = { WHAL_STM32WBA55_GPIO_REGMAP }, + .base = WHAL_STM32WBA55_GPIO_BASE, .driver = WHAL_STM32WBA55_GPIO_DRIVER, .cfg = &(whal_Stm32wba_Gpio_Cfg) { @@ -118,7 +118,7 @@ whal_Gpio g_whalGpio = { /* I2C */ whal_I2c g_whalI2c = { - .regmap = { WHAL_STM32WBA55_I2C1_REGMAP }, + .base = WHAL_STM32WBA55_I2C1_BASE, .driver = WHAL_STM32WBA55_I2C1_DRIVER, .cfg = &(whal_Stm32wba_I2c_Cfg) { @@ -129,7 +129,7 @@ whal_I2c g_whalI2c = { /* SPI */ whal_Spi g_whalSpi = { - .regmap = { WHAL_STM32WBA55_SPI1_REGMAP }, + .base = WHAL_STM32WBA55_SPI1_BASE, .driver = WHAL_STM32WBA55_SPI1_DRIVER, .cfg = &(whal_Stm32wba_Spi_Cfg) { @@ -140,7 +140,7 @@ whal_Spi g_whalSpi = { /* Timer (SysTick at 100 MHz) */ whal_Timer g_whalTimer = { - .regmap = { WHAL_CORTEX_M33_SYSTICK_REGMAP }, + .base = WHAL_CORTEX_M33_SYSTICK_BASE, .driver = WHAL_CORTEX_M33_SYSTICK_DRIVER, .cfg = &(whal_SysTick_Cfg) { @@ -154,7 +154,7 @@ whal_Timer g_whalTimer = { #ifdef BOARD_DMA whal_Dma g_whalDma1 = { - .regmap = { WHAL_STM32WBA55_GPDMA1_REGMAP }, + .base = WHAL_STM32WBA55_GPDMA1_BASE, .driver = WHAL_STM32WBA55_GPDMA1_DRIVER, .cfg = &(whal_Stm32wba_Gpdma_Cfg){ .numChannels = 8, @@ -182,7 +182,7 @@ void GPDMA1_Channel1_IRQHandler(void) /* UART (USART1 via VCP at 115200 baud) */ #ifdef BOARD_DMA whal_Uart g_whalUart = { - .regmap = { WHAL_STM32WBA55_USART1_REGMAP }, + .base = WHAL_STM32WBA55_USART1_BASE, .driver = &whal_Stm32wba_UartDma_Driver, .cfg = &(whal_Stm32wba_UartDma_Cfg) { .base = { @@ -198,7 +198,7 @@ whal_Uart g_whalUart = { }; #else whal_Uart g_whalUart = { - .regmap = { WHAL_STM32WBA55_USART1_REGMAP }, + .base = WHAL_STM32WBA55_USART1_BASE, .driver = WHAL_STM32WBA55_USART1_DRIVER, .cfg = &(whal_Stm32wba_Uart_Cfg) { @@ -210,7 +210,7 @@ whal_Uart g_whalUart = { /* Flash */ whal_Flash g_whalFlash = { - .regmap = { WHAL_STM32WBA55_FLASH_REGMAP }, + .base = WHAL_STM32WBA55_FLASH_BASE, .driver = WHAL_STM32WBA55_FLASH_DRIVER, .cfg = &(whal_Stm32wba_Flash_Cfg) { @@ -222,7 +222,7 @@ whal_Flash g_whalFlash = { /* RNG */ whal_Rng g_whalRng = { - .regmap = { WHAL_STM32WBA55_RNG_REGMAP }, + .base = WHAL_STM32WBA55_RNG_BASE, .driver = WHAL_STM32WBA55_RNG_DRIVER, .cfg = &(whal_Stm32wba_Rng_Cfg) { @@ -232,7 +232,7 @@ whal_Rng g_whalRng = { /* Crypto (AES hardware accelerator) */ whal_Crypto g_whalCrypto = { - .regmap = { WHAL_STM32WBA55_AES_REGMAP }, + .base = WHAL_STM32WBA55_AES_BASE, .driver = WHAL_STM32WBA55_AES_DRIVER, .cfg = &(whal_Stm32wba_Aes_Cfg) { @@ -242,7 +242,7 @@ whal_Crypto g_whalCrypto = { /* Hash (HASH hardware accelerator) */ whal_Crypto g_whalHash = { - .regmap = { WHAL_STM32WBA55_HASH_REGMAP }, + .base = WHAL_STM32WBA55_HASH_BASE, .driver = WHAL_STM32WBA55_HASH_DRIVER, .cfg = &(whal_Stm32wba_Hash_Cfg) { @@ -252,7 +252,7 @@ whal_Crypto g_whalHash = { #ifdef BOARD_WATCHDOG_IWDG whal_Watchdog g_whalWatchdog = { - .regmap = { WHAL_STM32WBA55_IWDG_REGMAP }, + .base = WHAL_STM32WBA55_IWDG_BASE, .driver = WHAL_STM32WBA55_IWDG_DRIVER, .cfg = &(whal_Stm32wba_Iwdg_Cfg) { @@ -263,7 +263,7 @@ whal_Watchdog g_whalWatchdog = { }; #elif defined(BOARD_WATCHDOG_WWDG) whal_Watchdog g_whalWatchdog = { - .regmap = { WHAL_STM32WBA55_WWDG_REGMAP }, + .base = WHAL_STM32WBA55_WWDG_BASE, .driver = WHAL_STM32WBA55_WWDG_DRIVER, .cfg = &(whal_Stm32wba_Wwdg_Cfg) { diff --git a/docs/adding_a_board.md b/docs/adding_a_board.md index ef65cdf..215f148 100644 --- a/docs/adding_a_board.md +++ b/docs/adding_a_board.md @@ -59,7 +59,7 @@ static whal_Myplatform_Gpio_Cfg gpioConfig = { }; whal_Gpio g_whalGpio = { - .regmap = { WHAL_MYPLATFORM_GPIO_REGMAP }, + .base = WHAL_MYPLATFORM_GPIO_BASE, .cfg = &gpioConfig, }; diff --git a/docs/adding_a_test.md b/docs/adding_a_test.md index 0bc8b2d..fb40e60 100644 --- a/docs/adding_a_test.md +++ b/docs/adding_a_test.md @@ -79,7 +79,7 @@ Create `tests//test__.c`: static void Test_Foo_SomeRegister(void) { size_t val = 0; - whal_Reg_Get(g_whalFoo.regmap.base, REG_OFFSET, MASK, POS, &val); + whal_Reg_Get(g_whalFoo.base, REG_OFFSET, MASK, POS, &val); WHAL_ASSERT_EQ(val, EXPECTED); } diff --git a/docs/getting_started.md b/docs/getting_started.md index 17f1f08..436fa6b 100644 --- a/docs/getting_started.md +++ b/docs/getting_started.md @@ -67,25 +67,25 @@ three fields: ```c struct whal_Gpio { - const whal_Regmap regmap; /* base address and size */ + const size_t base; /* peripheral base address */ const whal_GpioDriver *driver; /* vtable of function pointers */ const void *cfg; /* platform-specific configuration */ }; ``` -- **regmap** — identifies the peripheral's memory-mapped register block +- **base** — the peripheral's memory-mapped register base address - **driver** — points to the driver implementation (the vtable) - **cfg** — points to a driver-specific configuration struct that the driver reads during Init -Platform headers provide `_REGMAP` and `_DRIVER` macros for each peripheral, +Platform headers provide `_BASE` and `_DRIVER` macros for each peripheral, so you only need to fill in the `cfg`: ```c #include whal_Gpio g_whalGpio = { - .regmap = { WHAL_STM32WB55_GPIO_REGMAP }, + .base = WHAL_STM32WB55_GPIO_BASE, .driver = WHAL_STM32WB55_GPIO_DRIVER, .cfg = &gpioConfig, }; @@ -119,11 +119,11 @@ driver) — the device pointer determines which implementation runs. ### Board-level drivers Board-level drivers (clock, power) only expose chip-specific helpers — no -vtable, no generic `whal__*` API. The device struct is just a regmap: +vtable, no generic `whal__*` API. The device struct is just a base address: ```c whal_Clock g_whalClock = { - .regmap = { WHAL_STM32WB55_RCC_REGMAP }, + .base = WHAL_STM32WB55_RCC_BASE, }; ``` @@ -143,7 +143,7 @@ each entry compactly: ```c whal_Gpio g_whalGpio = { - .regmap = { WHAL_STM32WB55_GPIO_REGMAP }, + .base = WHAL_STM32WB55_GPIO_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32wb_Gpio_Cfg) { @@ -163,7 +163,7 @@ timeout: ```c whal_Uart g_whalUart = { - .regmap = { WHAL_STM32WB55_UART1_REGMAP }, + .base = WHAL_STM32WB55_UART1_BASE, /* .driver: direct API mapping */ .cfg = &(whal_Stm32wb_Uart_Cfg) { @@ -343,7 +343,7 @@ static const whal_GpioDriver myGpioDriver = { }; whal_Gpio g_whalGpio = { - .regmap = { .base = 0x48000000, .size = 0x2000 }, + .base = 0x48000000, .driver = &myGpioDriver, .cfg = &gpioConfig, }; diff --git a/docs/writing_a_driver.md b/docs/writing_a_driver.md index 38b48dd..c3a3f25 100644 --- a/docs/writing_a_driver.md +++ b/docs/writing_a_driver.md @@ -152,7 +152,7 @@ There are two exceptions: ### Register Access -wolfHAL provides register access helpers in `wolfHAL/regmap.h`: +wolfHAL provides register access helpers in `wolfHAL/reg.h`: - `whal_Reg_Write()` — write a full register value - `whal_Reg_Read()` — read a full register value @@ -190,7 +190,7 @@ do not need to know the tick rate. #### whal_Reg_ReadPoll For the common case of polling a register bit, use `whal_Reg_ReadPoll` from -`wolfHAL/regmap.h`: +`wolfHAL/reg.h`: ```c whal_Error whal_Reg_ReadPoll(size_t base, size_t offset, @@ -347,14 +347,12 @@ than a clean separate implementation. ### Platform Device Macros -Add regmap and driver macros to your platform header +Add base address and driver macros to your platform header (`wolfHAL/platform//.h`) so that board configs can instantiate devices without knowing the register addresses or driver symbols: ```c -#define WHAL_MYPLATFORM_FOO_REGMAP \ - .base = 0x40000000, \ - .size = 0x400 +#define WHAL_MYPLATFORM_FOO_BASE 0x40000000 #define WHAL_MYPLATFORM_FOO_DRIVER &whal_Myplatform_Foo_Driver ``` @@ -362,7 +360,7 @@ The board uses these in device struct initializers: ```c whal_Foo g_whalFoo = { - .regmap = { WHAL_MYPLATFORM_FOO_REGMAP }, + .base = WHAL_MYPLATFORM_FOO_BASE, .driver = WHAL_MYPLATFORM_FOO_DRIVER, .cfg = &fooCfg, }; @@ -374,7 +372,7 @@ you are doing so with the following comment. ```c whal_Foo g_whalFoo = { - .regmap = { WHAL_MYPLATFORM_FOO_REGMAP }, + .base = WHAL_MYPLATFORM_FOO_BASE, /* .driver: direct API mapping */ .cfg = &fooCfg, }; @@ -387,7 +385,7 @@ whal_Foo g_whalFoo = { Header: `wolfHAL/clock/clock.h` Clock is a **board-level driver** (see Driver Categories). The generic -`clock.h` declares only the typed handle `whal_Clock { regmap }` — no +`clock.h` declares only the typed handle `whal_Clock { base }` — no `whal_Clock_Init`/`Deinit`/`Enable`/`Disable` API, no `whal_ClockDriver` vtable. Each chip clock driver exposes imperative chip-specific helpers that boards call directly from `Board_Init` in the right order. @@ -964,7 +962,7 @@ streaming use cases. ```c struct whal_Crypto { - const whal_Regmap regmap; + const size_t base; const whal_CryptoDriver *driver; const void *cfg; }; @@ -1045,7 +1043,7 @@ instantiates the crypto device: ```c whal_Crypto g_whalCrypto = { - .regmap = { WHAL_STM32WB55_AES1_REGMAP }, + .base = WHAL_STM32WB55_AES1_BASE, .cfg = &(whal_Stm32wb_Aes_Cfg) { .timeout = &g_whalTimeout }, }; ``` @@ -1061,7 +1059,7 @@ vtable indirection. Header: `wolfHAL/power/power.h` Power is a **board-level driver** (see Driver Categories). The generic -`power.h` declares only the typed handle `whal_Power { regmap }` — no +`power.h` declares only the typed handle `whal_Power { base }` — no `whal_Power_Init`/`Deinit`/`Enable`/`Disable` API, no `whal_PowerDriver` vtable. Each chip power driver exposes imperative chip-specific helpers that boards call directly from `Board_Init` (typically before clock setup, diff --git a/src/clock/pic32cz_clock.c b/src/clock/pic32cz_clock.c index 00137bf..f243931 100644 --- a/src/clock/pic32cz_clock.c +++ b/src/clock/pic32cz_clock.c @@ -1,4 +1,5 @@ #include +#include #include #include #include @@ -76,21 +77,21 @@ whal_Error whal_Pic32cz_Clock_EnablePll(whal_Clock *clkDev, pllRefdivReg = OSCCTRL_PLLxREFDIV_REG(cfg->pllInst); pllPostdivaReg = OSCCTRL_PLLxPOSTDIVA_REG(cfg->pllInst); - whal_Reg_Update(clkDev->regmap.base, pllFbdivReg, OSCCTRL_PLLxFBDIV_Msk, + whal_Reg_Update(clkDev->base, pllFbdivReg, OSCCTRL_PLLxFBDIV_Msk, whal_SetBits(OSCCTRL_PLLxFBDIV_Msk, OSCCTRL_PLLxFBDIV_Pos, cfg->fbDiv)); - whal_Reg_Update(clkDev->regmap.base, pllRefdivReg, OSCCTRL_PLLxREFDIV_Msk, + whal_Reg_Update(clkDev->base, pllRefdivReg, OSCCTRL_PLLxREFDIV_Msk, whal_SetBits(OSCCTRL_PLLxREFDIV_Msk, OSCCTRL_PLLxREFDIV_Pos, cfg->refDiv)); for (i = 0; i < cfg->outCfgCount; i++) { const whal_Pic32cz_Clock_PllOutCfg *out = &cfg->outCfg[i]; - whal_Reg_Update(clkDev->regmap.base, pllPostdivaReg, + whal_Reg_Update(clkDev->base, pllPostdivaReg, out->outEnMask | out->postDivMask, whal_SetBits(out->postDivMask, out->postDivPos, out->postDiv) | whal_SetBits(out->outEnMask, out->outEnPos, 1)); } - whal_Reg_Update(clkDev->regmap.base, pllCtrlReg, + whal_Reg_Update(clkDev->base, pllCtrlReg, OSCCTRL_PLLxCTRL_ENABLE_Msk | OSCCTRL_PLLxCTRL_REFSEL_Msk | OSCCTRL_PLLxCTRL_BWSEL_Msk, @@ -99,7 +100,7 @@ whal_Error whal_Pic32cz_Clock_EnablePll(whal_Clock *clkDev, whal_SetBits(OSCCTRL_PLLxCTRL_BWSEL_Msk, OSCCTRL_PLLxCTRL_BWSEL_Pos, cfg->bwSel)); do { - whal_Reg_Get(clkDev->regmap.base, OSCCTRL_STATUS_REG, + whal_Reg_Get(clkDev->base, OSCCTRL_STATUS_REG, OSCCTRL_STATUS_PLLxLOCK_Msk(cfg->pllInst), OSCCTRL_STATUS_PLLxLOCK_Pos(cfg->pllInst), &status); } while (!status); @@ -114,14 +115,14 @@ whal_Error whal_Pic32cz_Clock_EnableGclkGen(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, GCLK_GENCTRLx_REG(cfg->gen), + whal_Reg_Update(clkDev->base, GCLK_GENCTRLx_REG(cfg->gen), GCLK_GENCTRLx_SRC_Msk | GCLK_GENCTRLx_GENEN_Msk | GCLK_GENCTRLx_DIV_Msk, whal_SetBits(GCLK_GENCTRLx_SRC_Msk, GCLK_GENCTRLx_SRC_Pos, cfg->genSrc) | GCLK_GENCTRLx_GENEN_Msk | whal_SetBits(GCLK_GENCTRLx_DIV_Msk, GCLK_GENCTRLx_DIV_Pos, cfg->genDiv)); do { - whal_Reg_Get(clkDev->regmap.base, GCLK_SYNCBUSY_REG, + whal_Reg_Get(clkDev->base, GCLK_SYNCBUSY_REG, GCLK_SYNCBUSY_GENCTRLx_Msk(cfg->gen), GCLK_SYNCBUSY_GENCTRLx_Pos(cfg->gen), &status); } while (status); @@ -135,10 +136,10 @@ whal_Error whal_Pic32cz_Clock_SetMclkDiv(whal_Clock *clkDev, uint8_t div) if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, MCLK_DIV1_REG, MCLK_DIV1_Msk, + whal_Reg_Update(clkDev->base, MCLK_DIV1_REG, MCLK_DIV1_Msk, whal_SetBits(MCLK_DIV1_Msk, MCLK_DIV1_Pos, div)); do { - whal_Reg_Get(clkDev->regmap.base, MCLK_INTFLAG_REG, + whal_Reg_Get(clkDev->base, MCLK_INTFLAG_REG, MCLK_INTFLAG_CKRDY_Msk, MCLK_INTFLAG_CKRDY_Pos, &status); } while (!status); return WHAL_SUCCESS; @@ -150,11 +151,11 @@ whal_Error whal_Pic32cz_Clock_EnablePeriphClk(whal_Clock *clkDev, if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, GCLK_PCHCTRLx_REG(clk->gclkPeriphChannel), + whal_Reg_Update(clkDev->base, GCLK_PCHCTRLx_REG(clk->gclkPeriphChannel), GCLK_PCHCTRLx_GEN_Msk | GCLK_PCHCTRLx_CHEN_Msk, whal_SetBits(GCLK_PCHCTRLx_GEN_Msk, GCLK_PCHCTRLx_GEN_Pos, clk->gclkPeriphSrc) | GCLK_PCHCTRLx_CHEN_Msk); - whal_Reg_Update(clkDev->regmap.base, MCLK_CLKxMSK_REG(clk->mclkEnableInst), + whal_Reg_Update(clkDev->base, MCLK_CLKxMSK_REG(clk->mclkEnableInst), clk->mclkEnableMask, whal_SetBits(clk->mclkEnableMask, clk->mclkEnablePos, 1)); return WHAL_SUCCESS; @@ -166,10 +167,10 @@ whal_Error whal_Pic32cz_Clock_DisablePeriphClk(whal_Clock *clkDev, if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, MCLK_CLKxMSK_REG(clk->mclkEnableInst), + whal_Reg_Update(clkDev->base, MCLK_CLKxMSK_REG(clk->mclkEnableInst), clk->mclkEnableMask, whal_SetBits(clk->mclkEnableMask, clk->mclkEnablePos, 0)); - whal_Reg_Update(clkDev->regmap.base, GCLK_PCHCTRLx_REG(clk->gclkPeriphChannel), + whal_Reg_Update(clkDev->base, GCLK_PCHCTRLx_REG(clk->gclkPeriphChannel), GCLK_PCHCTRLx_CHEN_Msk, 0); return WHAL_SUCCESS; } diff --git a/src/clock/stm32c0_rcc.c b/src/clock/stm32c0_rcc.c index b7f3c19..89e4c47 100644 --- a/src/clock/stm32c0_rcc.c +++ b/src/clock/stm32c0_rcc.c @@ -32,13 +32,13 @@ whal_Error whal_Stm32c0_Rcc_EnableHsi(whal_Clock *clkDev, if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_HSION_Msk, + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_HSION_Msk, RCC_CR_HSION_Msk); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CR_REG, RCC_CR_HSIRDY_Msk, + whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_HSIRDY_Msk, RCC_CR_HSIRDY_Pos, &rdy); } while (!rdy); - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_HSIDIV_Msk, + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_HSIDIV_Msk, whal_SetBits(RCC_CR_HSIDIV_Msk, RCC_CR_HSIDIV_Pos, hsidiv)); return WHAL_SUCCESS; } @@ -51,10 +51,10 @@ whal_Error whal_Stm32c0_Rcc_SetSysClock(whal_Clock *clkDev, if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, src)); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, + whal_Reg_Get(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, RCC_CFGR_SWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; @@ -66,7 +66,7 @@ whal_Error whal_Stm32c0_Rcc_EnablePeriphClk(whal_Clock *clkDev, if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -77,7 +77,7 @@ whal_Error whal_Stm32c0_Rcc_DisablePeriphClk(whal_Clock *clkDev, if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/src/clock/stm32f0_rcc.c b/src/clock/stm32f0_rcc.c index 9990395..cbf2371 100644 --- a/src/clock/stm32f0_rcc.c +++ b/src/clock/stm32f0_rcc.c @@ -31,9 +31,9 @@ whal_Error whal_Stm32f0_Rcc_EnableOsc(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, cfg->onReg, cfg->onMsk, cfg->onMsk); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); do { - whal_Reg_Get(clkDev->regmap.base, cfg->rdyReg, cfg->rdyMsk, + whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, cfg->rdyPos, &rdy); } while (!rdy); return WHAL_SUCCESS; @@ -45,7 +45,7 @@ whal_Error whal_Stm32f0_Rcc_DisableOsc(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, cfg->onReg, cfg->onMsk, 0); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); return WHAL_SUCCESS; } @@ -61,25 +61,25 @@ whal_Error whal_Stm32f0_Rcc_EnablePll(whal_Clock *clkDev, return WHAL_EINVAL; /* Disable PLL before reconfiguring. */ - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR2_REG, RCC_CFGR2_PREDIV_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR2_REG, RCC_CFGR2_PREDIV_Msk, whal_SetBits(RCC_CFGR2_PREDIV_Msk, RCC_CFGR2_PREDIV_Pos, cfg->prediv - 1)); - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_PLLMUL_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_PLLMUL_Msk, whal_SetBits(RCC_CFGR_PLLMUL_Msk, RCC_CFGR_PLLMUL_Pos, cfg->pllmul - 2)); pllsrc = (cfg->clkSrc == WHAL_STM32F0_RCC_PLLSRC_HSE_PREDIV || cfg->clkSrc == WHAL_STM32F0_RCC_PLLSRC_HSI48_PREDIV) ? 1 : 0; - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_PLLSRC_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_PLLSRC_Msk, whal_SetBits(RCC_CFGR_PLLSRC_Msk, RCC_CFGR_PLLSRC_Pos, pllsrc)); - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLON_Msk, + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, RCC_CR_PLLON_Msk); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, + whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, RCC_CR_PLLRDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; @@ -89,7 +89,7 @@ whal_Error whal_Stm32f0_Rcc_DisablePll(whal_Clock *clkDev) { if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); return WHAL_SUCCESS; } @@ -101,10 +101,10 @@ whal_Error whal_Stm32f0_Rcc_SetSysClock(whal_Clock *clkDev, if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, src)); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, + whal_Reg_Get(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, RCC_CFGR_SWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; @@ -115,7 +115,7 @@ whal_Error whal_Stm32f0_Rcc_EnablePeriphClk(whal_Clock *clkDev, { if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -125,7 +125,7 @@ whal_Error whal_Stm32f0_Rcc_DisablePeriphClk(whal_Clock *clkDev, { if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/src/clock/stm32f3_rcc.c b/src/clock/stm32f3_rcc.c index c282d33..d4247af 100644 --- a/src/clock/stm32f3_rcc.c +++ b/src/clock/stm32f3_rcc.c @@ -35,9 +35,9 @@ whal_Error whal_Stm32f3_Rcc_EnableOsc(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, cfg->onReg, cfg->onMsk, cfg->onMsk); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); do { - whal_Reg_Get(clkDev->regmap.base, cfg->rdyReg, cfg->rdyMsk, + whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, cfg->rdyPos, &rdy); } while (!rdy); return WHAL_SUCCESS; @@ -49,7 +49,7 @@ whal_Error whal_Stm32f3_Rcc_DisableOsc(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, cfg->onReg, cfg->onMsk, 0); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); return WHAL_SUCCESS; } @@ -65,24 +65,24 @@ whal_Error whal_Stm32f3_Rcc_EnablePll(whal_Clock *clkDev, return WHAL_EINVAL; /* Disable PLL before reconfiguring. */ - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR2_REG, RCC_CFGR2_PREDIV_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR2_REG, RCC_CFGR2_PREDIV_Msk, whal_SetBits(RCC_CFGR2_PREDIV_Msk, RCC_CFGR2_PREDIV_Pos, cfg->prediv - 1)); - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_PLLMUL_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_PLLMUL_Msk, whal_SetBits(RCC_CFGR_PLLMUL_Msk, RCC_CFGR_PLLMUL_Pos, cfg->pllmul - 2)); pllsrc = (cfg->clkSrc == WHAL_STM32F3_RCC_PLLSRC_HSE_PREDIV) ? 1 : 0; - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_PLLSRC_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_PLLSRC_Msk, whal_SetBits(RCC_CFGR_PLLSRC_Msk, RCC_CFGR_PLLSRC_Pos, pllsrc)); - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLON_Msk, + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, RCC_CR_PLLON_Msk); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, + whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, RCC_CR_PLLRDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; @@ -92,7 +92,7 @@ whal_Error whal_Stm32f3_Rcc_DisablePll(whal_Clock *clkDev) { if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); return WHAL_SUCCESS; } @@ -104,10 +104,10 @@ whal_Error whal_Stm32f3_Rcc_SetSysClock(whal_Clock *clkDev, if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, src)); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, + whal_Reg_Get(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, RCC_CFGR_SWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; @@ -119,7 +119,7 @@ whal_Error whal_Stm32f3_Rcc_SetI2c1ClkSrc(whal_Clock *clkDev, if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR3_REG, RCC_CFGR3_I2C1SW_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR3_REG, RCC_CFGR3_I2C1SW_Msk, whal_SetBits(RCC_CFGR3_I2C1SW_Msk, RCC_CFGR3_I2C1SW_Pos, src)); return WHAL_SUCCESS; @@ -130,7 +130,7 @@ whal_Error whal_Stm32f3_Rcc_EnablePeriphClk(whal_Clock *clkDev, { if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -140,7 +140,7 @@ whal_Error whal_Stm32f3_Rcc_DisablePeriphClk(whal_Clock *clkDev, { if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/src/clock/stm32f4_rcc.c b/src/clock/stm32f4_rcc.c index a761a47..84fc352 100644 --- a/src/clock/stm32f4_rcc.c +++ b/src/clock/stm32f4_rcc.c @@ -43,9 +43,9 @@ whal_Error whal_Stm32f4_Rcc_EnableOsc(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, cfg->onReg, cfg->onMsk, cfg->onMsk); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); do { - whal_Reg_Get(clkDev->regmap.base, cfg->rdyReg, cfg->rdyMsk, + whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, cfg->rdyPos, &rdy); } while (!rdy); return WHAL_SUCCESS; @@ -57,7 +57,7 @@ whal_Error whal_Stm32f4_Rcc_DisableOsc(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, cfg->onReg, cfg->onMsk, 0); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); return WHAL_SUCCESS; } @@ -70,19 +70,19 @@ whal_Error whal_Stm32f4_Rcc_EnablePll(whal_Clock *clkDev, return WHAL_EINVAL; /* Disable PLL before reconfiguring. */ - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); - whal_Reg_Update(clkDev->regmap.base, RCC_PLLCFGR_REG, RCC_PLLCFGR_Msk, + whal_Reg_Update(clkDev->base, RCC_PLLCFGR_REG, RCC_PLLCFGR_Msk, whal_SetBits(RCC_PLLCFGR_PLLM_Msk, RCC_PLLCFGR_PLLM_Pos, cfg->m) | whal_SetBits(RCC_PLLCFGR_PLLN_Msk, RCC_PLLCFGR_PLLN_Pos, cfg->n) | whal_SetBits(RCC_PLLCFGR_PLLP_Msk, RCC_PLLCFGR_PLLP_Pos, cfg->p) | whal_SetBits(RCC_PLLCFGR_PLLSRC_Msk, RCC_PLLCFGR_PLLSRC_Pos, cfg->clkSrc) | whal_SetBits(RCC_PLLCFGR_PLLQ_Msk, RCC_PLLCFGR_PLLQ_Pos, cfg->q)); - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLON_Msk, + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, RCC_CR_PLLON_Msk); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, + whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, RCC_CR_PLLRDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; @@ -92,7 +92,7 @@ whal_Error whal_Stm32f4_Rcc_DisablePll(whal_Clock *clkDev) { if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); return WHAL_SUCCESS; } @@ -102,7 +102,7 @@ whal_Error whal_Stm32f4_Rcc_SetBusPrescalers(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, + whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_PPRE1_Msk | RCC_CFGR_PPRE2_Msk, whal_SetBits(RCC_CFGR_PPRE1_Msk, RCC_CFGR_PPRE1_Pos, cfg->ppre1) | whal_SetBits(RCC_CFGR_PPRE2_Msk, RCC_CFGR_PPRE2_Pos, cfg->ppre2)); @@ -117,10 +117,10 @@ whal_Error whal_Stm32f4_Rcc_SetSysClock(whal_Clock *clkDev, if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, src)); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, + whal_Reg_Get(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, RCC_CFGR_SWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; @@ -131,7 +131,7 @@ whal_Error whal_Stm32f4_Rcc_EnablePeriphClk(whal_Clock *clkDev, { if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -141,7 +141,7 @@ whal_Error whal_Stm32f4_Rcc_DisablePeriphClk(whal_Clock *clkDev, { if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/src/clock/stm32h5_rcc.c b/src/clock/stm32h5_rcc.c index ec4adba..9e9e9c5 100644 --- a/src/clock/stm32h5_rcc.c +++ b/src/clock/stm32h5_rcc.c @@ -49,9 +49,9 @@ whal_Error whal_Stm32h5_Rcc_EnableOsc(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, cfg->onReg, cfg->onMsk, cfg->onMsk); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); do { - whal_Reg_Get(clkDev->regmap.base, cfg->rdyReg, cfg->rdyMsk, + whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, cfg->rdyPos, &rdy); } while (!rdy); return WHAL_SUCCESS; @@ -63,7 +63,7 @@ whal_Error whal_Stm32h5_Rcc_DisableOsc(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, cfg->onReg, cfg->onMsk, 0); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); return WHAL_SUCCESS; } @@ -76,13 +76,13 @@ whal_Error whal_Stm32h5_Rcc_EnablePll1(whal_Clock *clkDev, return WHAL_EINVAL; /* Disable PLL1 before reconfiguring; wait until off. */ - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLL1RDY_Msk, + whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLL1RDY_Msk, RCC_CR_PLL1RDY_Pos, &rdy); } while (rdy); - whal_Reg_Update(clkDev->regmap.base, RCC_PLL1CFGR_REG, + whal_Reg_Update(clkDev->base, RCC_PLL1CFGR_REG, RCC_PLL1CFGR_PLL1SRC_Msk | RCC_PLL1CFGR_PLL1M_Msk | RCC_PLL1CFGR_PLL1PEN_Msk | RCC_PLL1CFGR_PLL1QEN_Msk | RCC_PLL1CFGR_PLL1REN_Msk, @@ -91,7 +91,7 @@ whal_Error whal_Stm32h5_Rcc_EnablePll1(whal_Clock *clkDev, whal_SetBits(RCC_PLL1CFGR_PLL1PEN_Msk, RCC_PLL1CFGR_PLL1PEN_Pos, 1) | whal_SetBits(RCC_PLL1CFGR_PLL1QEN_Msk, RCC_PLL1CFGR_PLL1QEN_Pos, 1) | whal_SetBits(RCC_PLL1CFGR_PLL1REN_Msk, RCC_PLL1CFGR_PLL1REN_Pos, 1)); - whal_Reg_Update(clkDev->regmap.base, RCC_PLL1DIVR_REG, + whal_Reg_Update(clkDev->base, RCC_PLL1DIVR_REG, RCC_PLL1DIVR_PLL1N_Msk | RCC_PLL1DIVR_PLL1P_Msk | RCC_PLL1DIVR_PLL1Q_Msk | RCC_PLL1DIVR_PLL1R_Msk, whal_SetBits(RCC_PLL1DIVR_PLL1N_Msk, RCC_PLL1DIVR_PLL1N_Pos, cfg->n) | @@ -99,10 +99,10 @@ whal_Error whal_Stm32h5_Rcc_EnablePll1(whal_Clock *clkDev, whal_SetBits(RCC_PLL1DIVR_PLL1Q_Msk, RCC_PLL1DIVR_PLL1Q_Pos, cfg->q) | whal_SetBits(RCC_PLL1DIVR_PLL1R_Msk, RCC_PLL1DIVR_PLL1R_Pos, cfg->r)); - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, RCC_CR_PLL1ON_Msk); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLL1RDY_Msk, + whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLL1RDY_Msk, RCC_CR_PLL1RDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; @@ -112,7 +112,7 @@ whal_Error whal_Stm32h5_Rcc_DisablePll1(whal_Clock *clkDev) { if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); return WHAL_SUCCESS; } @@ -124,10 +124,10 @@ whal_Error whal_Stm32h5_Rcc_SetSysClock(whal_Clock *clkDev, if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR1_REG, RCC_CFGR1_SW_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR1_REG, RCC_CFGR1_SW_Msk, whal_SetBits(RCC_CFGR1_SW_Msk, RCC_CFGR1_SW_Pos, src)); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CFGR1_REG, RCC_CFGR1_SWS_Msk, + whal_Reg_Get(clkDev->base, RCC_CFGR1_REG, RCC_CFGR1_SWS_Msk, RCC_CFGR1_SWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; @@ -137,7 +137,7 @@ whal_Error whal_Stm32h5_Rcc_SetHsiDiv(whal_Clock *clkDev, uint8_t div) { if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_HSIDIV_Msk, + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_HSIDIV_Msk, whal_SetBits(RCC_CR_HSIDIV_Msk, RCC_CR_HSIDIV_Pos, div)); return WHAL_SUCCESS; } @@ -147,7 +147,7 @@ whal_Error whal_Stm32h5_Rcc_EnablePeriphClk(whal_Clock *clkDev, { if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -157,7 +157,7 @@ whal_Error whal_Stm32h5_Rcc_DisablePeriphClk(whal_Clock *clkDev, { if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/src/clock/stm32l1_rcc.c b/src/clock/stm32l1_rcc.c index 35f650c..904fc93 100644 --- a/src/clock/stm32l1_rcc.c +++ b/src/clock/stm32l1_rcc.c @@ -29,9 +29,9 @@ whal_Error whal_Stm32l1_Rcc_EnableOsc(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, cfg->onReg, cfg->onMsk, cfg->onMsk); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); do { - whal_Reg_Get(clkDev->regmap.base, cfg->rdyReg, cfg->rdyMsk, + whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, cfg->rdyPos, &rdy); } while (!rdy); return WHAL_SUCCESS; @@ -43,7 +43,7 @@ whal_Error whal_Stm32l1_Rcc_DisableOsc(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, cfg->onReg, cfg->onMsk, 0); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); return WHAL_SUCCESS; } @@ -57,27 +57,27 @@ whal_Error whal_Stm32l1_Rcc_EnablePll(whal_Clock *clkDev, return WHAL_EINVAL; /* Disable PLL before reconfiguring; wait until it's actually off. */ - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, + whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, RCC_CR_PLLRDY_Pos, &rdy); } while (rdy); pllsrc = (cfg->clkSrc == WHAL_STM32L1_RCC_PLLSRC_HSE) ? 1 : 0; - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_PLLSRC_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_PLLSRC_Msk, whal_SetBits(RCC_CFGR_PLLSRC_Msk, RCC_CFGR_PLLSRC_Pos, pllsrc)); - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_PLLMUL_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_PLLMUL_Msk, whal_SetBits(RCC_CFGR_PLLMUL_Msk, RCC_CFGR_PLLMUL_Pos, cfg->pllmul)); - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_PLLDIV_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_PLLDIV_Msk, whal_SetBits(RCC_CFGR_PLLDIV_Msk, RCC_CFGR_PLLDIV_Pos, cfg->plldiv)); - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLON_Msk, + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, RCC_CR_PLLON_Msk); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, + whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, RCC_CR_PLLRDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; @@ -87,7 +87,7 @@ whal_Error whal_Stm32l1_Rcc_DisablePll(whal_Clock *clkDev) { if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); return WHAL_SUCCESS; } @@ -99,10 +99,10 @@ whal_Error whal_Stm32l1_Rcc_SetSysClock(whal_Clock *clkDev, if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, src)); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, + whal_Reg_Get(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, RCC_CFGR_SWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; @@ -113,7 +113,7 @@ whal_Error whal_Stm32l1_Rcc_EnablePeriphClk(whal_Clock *clkDev, { if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -123,7 +123,7 @@ whal_Error whal_Stm32l1_Rcc_DisablePeriphClk(whal_Clock *clkDev, { if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/src/clock/stm32n6_rcc.c b/src/clock/stm32n6_rcc.c index abbc1b7..15a44e8 100644 --- a/src/clock/stm32n6_rcc.c +++ b/src/clock/stm32n6_rcc.c @@ -48,9 +48,9 @@ whal_Error whal_Stm32n6_Rcc_EnableOsc(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, cfg->onReg, cfg->onMsk, cfg->onMsk); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); do { - whal_Reg_Get(clkDev->regmap.base, cfg->rdyReg, cfg->rdyMsk, + whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, cfg->rdyPos, &rdy); } while (!rdy); return WHAL_SUCCESS; @@ -62,7 +62,7 @@ whal_Error whal_Stm32n6_Rcc_DisableOsc(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, cfg->onReg, cfg->onMsk, 0); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); return WHAL_SUCCESS; } @@ -75,17 +75,17 @@ whal_Error whal_Stm32n6_Rcc_EnablePll1(whal_Clock *clkDev, return WHAL_EINVAL; /* Disable PLL1 before reconfiguring; wait until off. */ - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); do { - whal_Reg_Get(clkDev->regmap.base, RCC_SR_REG, RCC_SR_PLL1RDY_Msk, + whal_Reg_Get(clkDev->base, RCC_SR_REG, RCC_SR_PLL1RDY_Msk, RCC_SR_PLL1RDY_Pos, &rdy); } while (rdy); - whal_Reg_Write(clkDev->regmap.base, RCC_PLL1CFGR1_REG, + whal_Reg_Write(clkDev->base, RCC_PLL1CFGR1_REG, whal_SetBits(RCC_PLL1CFGR1_PLL1SEL_Msk, RCC_PLL1CFGR1_PLL1SEL_Pos, cfg->clkSrc) | whal_SetBits(RCC_PLL1CFGR1_PLL1DIVM_Msk, RCC_PLL1CFGR1_PLL1DIVM_Pos, cfg->m) | whal_SetBits(RCC_PLL1CFGR1_PLL1DIVN_Msk, RCC_PLL1CFGR1_PLL1DIVN_Pos, cfg->n)); - whal_Reg_Update(clkDev->regmap.base, RCC_PLL1CFGR3_REG, + whal_Reg_Update(clkDev->base, RCC_PLL1CFGR3_REG, RCC_PLL1CFGR3_PLL1PDIVEN_Msk | RCC_PLL1CFGR3_PLL1PDIV1_Msk | RCC_PLL1CFGR3_PLL1PDIV2_Msk, @@ -93,10 +93,10 @@ whal_Error whal_Stm32n6_Rcc_EnablePll1(whal_Clock *clkDev, whal_SetBits(RCC_PLL1CFGR3_PLL1PDIV1_Msk, RCC_PLL1CFGR3_PLL1PDIV1_Pos, cfg->pdiv1) | whal_SetBits(RCC_PLL1CFGR3_PLL1PDIV2_Msk, RCC_PLL1CFGR3_PLL1PDIV2_Pos, cfg->pdiv2)); - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, RCC_CR_PLL1ON_Msk); do { - whal_Reg_Get(clkDev->regmap.base, RCC_SR_REG, RCC_SR_PLL1RDY_Msk, + whal_Reg_Get(clkDev->base, RCC_SR_REG, RCC_SR_PLL1RDY_Msk, RCC_SR_PLL1RDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; @@ -106,7 +106,7 @@ whal_Error whal_Stm32n6_Rcc_DisablePll1(whal_Clock *clkDev) { if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); return WHAL_SUCCESS; } @@ -118,10 +118,10 @@ whal_Error whal_Stm32n6_Rcc_SetSysClock(whal_Clock *clkDev, if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR1_REG, RCC_CFGR1_SYSSW_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR1_REG, RCC_CFGR1_SYSSW_Msk, whal_SetBits(RCC_CFGR1_SYSSW_Msk, RCC_CFGR1_SYSSW_Pos, src)); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CFGR1_REG, RCC_CFGR1_SYSSWS_Msk, + whal_Reg_Get(clkDev->base, RCC_CFGR1_REG, RCC_CFGR1_SYSSWS_Msk, RCC_CFGR1_SYSSWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; @@ -135,10 +135,10 @@ whal_Error whal_Stm32n6_Rcc_SetCpuClock(whal_Clock *clkDev, if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR1_REG, RCC_CFGR1_CPUSW_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR1_REG, RCC_CFGR1_CPUSW_Msk, whal_SetBits(RCC_CFGR1_CPUSW_Msk, RCC_CFGR1_CPUSW_Pos, src)); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CFGR1_REG, RCC_CFGR1_CPUSWS_Msk, + whal_Reg_Get(clkDev->base, RCC_CFGR1_REG, RCC_CFGR1_CPUSWS_Msk, RCC_CFGR1_CPUSWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; @@ -149,7 +149,7 @@ whal_Error whal_Stm32n6_Rcc_SetEth1If(whal_Clock *clkDev, { if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CCIPR2_REG, RCC_CCIPR2_ETH1SEL_Msk, + whal_Reg_Update(clkDev->base, RCC_CCIPR2_REG, RCC_CCIPR2_ETH1SEL_Msk, whal_SetBits(RCC_CCIPR2_ETH1SEL_Msk, RCC_CCIPR2_ETH1SEL_Pos, mode)); return WHAL_SUCCESS; @@ -160,7 +160,7 @@ whal_Error whal_Stm32n6_Rcc_EnablePeriphClk(whal_Clock *clkDev, { if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -170,7 +170,7 @@ whal_Error whal_Stm32n6_Rcc_DisablePeriphClk(whal_Clock *clkDev, { if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/src/clock/stm32wb_rcc.c b/src/clock/stm32wb_rcc.c index 11e6cbd..c40ac93 100644 --- a/src/clock/stm32wb_rcc.c +++ b/src/clock/stm32wb_rcc.c @@ -55,9 +55,9 @@ whal_Error whal_Stm32wb_Rcc_EnableOsc(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, cfg->onReg, cfg->onMsk, cfg->onMsk); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); do { - whal_Reg_Get(clkDev->regmap.base, cfg->rdyReg, cfg->rdyMsk, + whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, cfg->rdyPos, &rdy); } while (!rdy); return WHAL_SUCCESS; @@ -69,7 +69,7 @@ whal_Error whal_Stm32wb_Rcc_DisableOsc(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, cfg->onReg, cfg->onMsk, 0); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); return WHAL_SUCCESS; } @@ -81,13 +81,13 @@ whal_Error whal_Stm32wb_Rcc_EnableMsi(whal_Clock *clkDev, if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_MSION_Msk, + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_MSION_Msk, RCC_CR_MSION_Msk); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CR_REG, RCC_CR_MSIRDY_Msk, + whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_MSIRDY_Msk, RCC_CR_MSIRDY_Pos, &rdy); } while (!rdy); - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_MSIRANGE_Msk, + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_MSIRANGE_Msk, whal_SetBits(RCC_CR_MSIRANGE_Msk, RCC_CR_MSIRANGE_Pos, range)); return WHAL_SUCCESS; @@ -101,7 +101,7 @@ whal_Error whal_Stm32wb_Rcc_EnablePll(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_PLLCFGR_REG, RCC_PLLCFGR_Msk, + whal_Reg_Update(clkDev->base, RCC_PLLCFGR_REG, RCC_PLLCFGR_Msk, whal_SetBits(RCC_PLLCFGR_PLLSRC_Msk, RCC_PLLCFGR_PLLSRC_Pos, cfg->clkSrc) | whal_SetBits(RCC_PLLCFGR_PLLM_Msk, RCC_PLLCFGR_PLLM_Pos, cfg->m) | whal_SetBits(RCC_PLLCFGR_PLLN_Msk, RCC_PLLCFGR_PLLN_Pos, cfg->n) | @@ -109,10 +109,10 @@ whal_Error whal_Stm32wb_Rcc_EnablePll(whal_Clock *clkDev, whal_SetBits(RCC_PLLCFGR_PLLQ_Msk, RCC_PLLCFGR_PLLQ_Pos, cfg->q) | whal_SetBits(RCC_PLLCFGR_PLLREN_Msk, RCC_PLLCFGR_PLLREN_Pos, 1) | whal_SetBits(RCC_PLLCFGR_PLLR_Msk, RCC_PLLCFGR_PLLR_Pos, cfg->r)); - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLON_Msk, + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, RCC_CR_PLLON_Msk); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, + whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, RCC_CR_PLLRDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; @@ -123,7 +123,7 @@ whal_Error whal_Stm32wb_Rcc_DisablePll(whal_Clock *clkDev) if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); return WHAL_SUCCESS; } @@ -135,10 +135,10 @@ whal_Error whal_Stm32wb_Rcc_SetSysClock(whal_Clock *clkDev, if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, src)); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, + whal_Reg_Get(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, RCC_CFGR_SWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; @@ -150,7 +150,7 @@ whal_Error whal_Stm32wb_Rcc_EnablePeriphClk(whal_Clock *clkDev, if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -161,7 +161,7 @@ whal_Error whal_Stm32wb_Rcc_DisablePeriphClk(whal_Clock *clkDev, if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/src/clock/stm32wba_rcc.c b/src/clock/stm32wba_rcc.c index be85b75..c5ddac2 100644 --- a/src/clock/stm32wba_rcc.c +++ b/src/clock/stm32wba_rcc.c @@ -56,9 +56,9 @@ whal_Error whal_Stm32wba_Rcc_EnableOsc(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, cfg->onReg, cfg->onMsk, cfg->onMsk); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); do { - whal_Reg_Get(clkDev->regmap.base, cfg->rdyReg, cfg->rdyMsk, + whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, cfg->rdyPos, &rdy); } while (!rdy); return WHAL_SUCCESS; @@ -70,7 +70,7 @@ whal_Error whal_Stm32wba_Rcc_DisableOsc(whal_Clock *clkDev, if (!clkDev || !cfg) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, cfg->onReg, cfg->onMsk, 0); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); return WHAL_SUCCESS; } @@ -83,27 +83,27 @@ whal_Error whal_Stm32wba_Rcc_EnablePll1(whal_Clock *clkDev, return WHAL_EINVAL; /* Disable PLL1 before reconfiguring; wait until off. */ - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLL1RDY_Msk, + whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLL1RDY_Msk, RCC_CR_PLL1RDY_Pos, &rdy); } while (rdy); - whal_Reg_Write(clkDev->regmap.base, RCC_PLL1CFGR_REG, + whal_Reg_Write(clkDev->base, RCC_PLL1CFGR_REG, whal_SetBits(RCC_PLL1CFGR_SRC_Msk, RCC_PLL1CFGR_SRC_Pos, cfg->clkSrc) | whal_SetBits(RCC_PLL1CFGR_RGE_Msk, RCC_PLL1CFGR_RGE_Pos, cfg->rge) | whal_SetBits(RCC_PLL1CFGR_M_Msk, RCC_PLL1CFGR_M_Pos, cfg->m) | whal_SetBits(RCC_PLL1CFGR_REN_Msk, RCC_PLL1CFGR_REN_Pos, 1)); - whal_Reg_Write(clkDev->regmap.base, RCC_PLL1DIVR_REG, + whal_Reg_Write(clkDev->base, RCC_PLL1DIVR_REG, whal_SetBits(RCC_PLL1DIVR_N_Msk, RCC_PLL1DIVR_N_Pos, cfg->n) | whal_SetBits(RCC_PLL1DIVR_P_Msk, RCC_PLL1DIVR_P_Pos, cfg->p) | whal_SetBits(RCC_PLL1DIVR_Q_Msk, RCC_PLL1DIVR_Q_Pos, cfg->q) | whal_SetBits(RCC_PLL1DIVR_R_Msk, RCC_PLL1DIVR_R_Pos, cfg->r)); - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, RCC_CR_PLL1ON_Msk); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLL1RDY_Msk, + whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLL1RDY_Msk, RCC_CR_PLL1RDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; @@ -113,7 +113,7 @@ whal_Error whal_Stm32wba_Rcc_DisablePll1(whal_Clock *clkDev) { if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); + whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); return WHAL_SUCCESS; } @@ -124,10 +124,10 @@ whal_Error whal_Stm32wba_Rcc_EnableLsi(whal_Clock *clkDev) if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_BDCR1_REG, RCC_BDCR1_LSI1ON_Msk, + whal_Reg_Update(clkDev->base, RCC_BDCR1_REG, RCC_BDCR1_LSI1ON_Msk, RCC_BDCR1_LSI1ON_Msk); do { - whal_Reg_Get(clkDev->regmap.base, RCC_BDCR1_REG, RCC_BDCR1_LSI1RDY_Msk, + whal_Reg_Get(clkDev->base, RCC_BDCR1_REG, RCC_BDCR1_LSI1RDY_Msk, RCC_BDCR1_LSI1RDY_Pos, &rdy); } while (!rdy); return WHAL_SUCCESS; @@ -137,7 +137,7 @@ whal_Error whal_Stm32wba_Rcc_DisableLsi(whal_Clock *clkDev) { if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_BDCR1_REG, RCC_BDCR1_LSI1ON_Msk, 0); + whal_Reg_Update(clkDev->base, RCC_BDCR1_REG, RCC_BDCR1_LSI1ON_Msk, 0); return WHAL_SUCCESS; } @@ -149,10 +149,10 @@ whal_Error whal_Stm32wba_Rcc_SetSysClock(whal_Clock *clkDev, if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR1_REG, RCC_CFGR1_SW_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR1_REG, RCC_CFGR1_SW_Msk, whal_SetBits(RCC_CFGR1_SW_Msk, RCC_CFGR1_SW_Pos, src)); do { - whal_Reg_Get(clkDev->regmap.base, RCC_CFGR1_REG, RCC_CFGR1_SWS_Msk, + whal_Reg_Get(clkDev->base, RCC_CFGR1_REG, RCC_CFGR1_SWS_Msk, RCC_CFGR1_SWS_Pos, &sws); } while (sws != (size_t)src); return WHAL_SUCCESS; @@ -163,7 +163,7 @@ whal_Error whal_Stm32wba_Rcc_SetRngClockSrc(whal_Clock *clkDev, { if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CCIPR2_REG, RCC_CCIPR2_RNGSEL_Msk, + whal_Reg_Update(clkDev->base, RCC_CCIPR2_REG, RCC_CCIPR2_RNGSEL_Msk, whal_SetBits(RCC_CCIPR2_RNGSEL_Msk, RCC_CCIPR2_RNGSEL_Pos, src)); return WHAL_SUCCESS; @@ -173,7 +173,7 @@ whal_Error whal_Stm32wba_Rcc_SetHpre5(whal_Clock *clkDev, uint8_t hpre5) { if (!clkDev) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, RCC_CFGR4_REG, RCC_CFGR4_HPRE5_Msk, + whal_Reg_Update(clkDev->base, RCC_CFGR4_REG, RCC_CFGR4_HPRE5_Msk, whal_SetBits(RCC_CFGR4_HPRE5_Msk, RCC_CFGR4_HPRE5_Pos, hpre5)); return WHAL_SUCCESS; } @@ -183,7 +183,7 @@ whal_Error whal_Stm32wba_Rcc_EnablePeriphClk(whal_Clock *clkDev, { if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 1)); return WHAL_SUCCESS; } @@ -193,7 +193,7 @@ whal_Error whal_Stm32wba_Rcc_DisablePeriphClk(whal_Clock *clkDev, { if (!clkDev || !clk) return WHAL_EINVAL; - whal_Reg_Update(clkDev->regmap.base, clk->regOffset, clk->enableMask, + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, whal_SetBits(clk->enableMask, clk->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/src/crypto/stm32n6_cryp.c b/src/crypto/stm32n6_cryp.c index d872583..57bccf2 100644 --- a/src/crypto/stm32n6_cryp.c +++ b/src/crypto/stm32n6_cryp.c @@ -239,7 +239,7 @@ whal_Error whal_Stm32n6_Cryp_Deinit(whal_Crypto *cryptoDev) return WHAL_EINVAL; } - Disable(cryptoDev->regmap.base); + Disable(cryptoDev->base); return WHAL_SUCCESS; } @@ -277,7 +277,7 @@ static whal_Error Process_BlockCipher(whal_Crypto *cryptoDev, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; whal_Error err; size_t i; @@ -302,7 +302,7 @@ static whal_Error Process_BlockCipher(whal_Crypto *cryptoDev, static whal_Error EndOp_BlockCipher(whal_Crypto *cryptoDev) { - Disable(cryptoDev->regmap.base); + Disable(cryptoDev->base); return WHAL_SUCCESS; } #endif /* AES_ECB || AES_CBC || AES_CTR */ @@ -313,7 +313,7 @@ static whal_Error StartOp_AesEcb(whal_Crypto *cryptoDev, void *opArgs) whal_Crypto_AesEcbArgs *args = (whal_Crypto_AesEcbArgs *)opArgs; const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; uint32_t keySizeBits; whal_Error err; @@ -353,7 +353,7 @@ static whal_Error StartOp_AesCbc(whal_Crypto *cryptoDev, void *opArgs) whal_Crypto_AesCbcArgs *args = (whal_Crypto_AesCbcArgs *)opArgs; const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; uint32_t keySizeBits; whal_Error err; @@ -395,7 +395,7 @@ static whal_Error StartOp_AesCtr(whal_Crypto *cryptoDev, void *opArgs) whal_Crypto_AesCtrArgs *args = (whal_Crypto_AesCtrArgs *)opArgs; const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; uint32_t keySizeBits; uint32_t algoDir; whal_Error err; @@ -434,7 +434,7 @@ static whal_Error GcmInit(whal_Crypto *cryptoDev, const uint8_t *key, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; whal_Error err; DisableAndFlush(base); @@ -461,7 +461,7 @@ static whal_Error GcmHeaderPhase(whal_Crypto *cryptoDev, const uint8_t *aad, { const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; whal_Error err; size_t i; @@ -531,7 +531,7 @@ static whal_Error Process_AesGcm(whal_Crypto *cryptoDev, void *opArgs) whal_Crypto_AesGcmArgs *args = (whal_Crypto_AesGcmArgs *)opArgs; const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; whal_Error err; size_t i; @@ -593,7 +593,7 @@ static whal_Error EndOp_AesGcm(whal_Crypto *cryptoDev, void *opArgs) whal_Crypto_AesGcmArgs *args = (whal_Crypto_AesGcmArgs *)opArgs; const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; uint8_t tagBuf[16]; uint64_t aadBits; uint64_t payloadBits; @@ -665,7 +665,7 @@ static whal_Error EndOp_AesGmac(whal_Crypto *cryptoDev, void *opArgs) whal_Crypto_AesGmacArgs *args = (whal_Crypto_AesGmacArgs *)opArgs; const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; uint8_t tagBuf[16]; uint64_t aadBits; whal_Error err; @@ -730,7 +730,7 @@ static whal_Error StartOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) { whal_Crypto_AesCcmArgs *args = (whal_Crypto_AesCcmArgs *)opArgs; whal_Stm32n6_Cryp_Cfg *cfg = (whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; uint32_t keySizeBits; uint32_t algoDir; uint8_t b0[16]; @@ -832,7 +832,7 @@ static whal_Error Process_AesCcm(whal_Crypto *cryptoDev, void *opArgs) whal_Crypto_AesCcmArgs *args = (whal_Crypto_AesCcmArgs *)opArgs; const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; whal_Error err; size_t i; @@ -894,7 +894,7 @@ static whal_Error EndOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) whal_Crypto_AesCcmArgs *args = (whal_Crypto_AesCcmArgs *)opArgs; const whal_Stm32n6_Cryp_Cfg *cfg = (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; uint8_t tagBuf[16]; whal_Error err; size_t i; diff --git a/src/crypto/stm32wb_aes.c b/src/crypto/stm32wb_aes.c index c463114..7a7ff27 100644 --- a/src/crypto/stm32wb_aes.c +++ b/src/crypto/stm32wb_aes.c @@ -166,7 +166,7 @@ whal_Error whal_Stm32wb_Aes_Deinit(whal_Crypto *cryptoDev) return WHAL_EINVAL; } - whal_Reg_Update(cryptoDev->regmap.base, AES_CR_REG, AES_CR_EN_Msk, + whal_Reg_Update(cryptoDev->base, AES_CR_REG, AES_CR_EN_Msk, whal_SetBits(AES_CR_EN_Msk, AES_CR_EN_Pos, 0)); return WHAL_SUCCESS; @@ -176,7 +176,7 @@ whal_Error whal_Stm32wb_Aes_Deinit(whal_Crypto *cryptoDev) static whal_Error StartOp_AesEcb(whal_Crypto *cryptoDev, void *opArgs) { whal_Crypto_AesEcbArgs *args = (whal_Crypto_AesEcbArgs *)opArgs; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; size_t mode; size_t keySizeBit; @@ -215,7 +215,7 @@ static whal_Error StartOp_AesEcb(whal_Crypto *cryptoDev, void *opArgs) static whal_Error StartOp_AesCbc(whal_Crypto *cryptoDev, void *opArgs) { whal_Crypto_AesCbcArgs *args = (whal_Crypto_AesCbcArgs *)opArgs; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; size_t mode; size_t keySizeBit; @@ -255,7 +255,7 @@ static whal_Error StartOp_AesCbc(whal_Crypto *cryptoDev, void *opArgs) static whal_Error StartOp_AesCtr(whal_Crypto *cryptoDev, void *opArgs) { whal_Crypto_AesCtrArgs *args = (whal_Crypto_AesCtrArgs *)opArgs; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; size_t keySizeBit; if (!args->key || !args->iv) @@ -297,7 +297,7 @@ static whal_Error Process_BlockCipher(whal_Crypto *cryptoDev, { const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; whal_Error err; size_t i; @@ -325,7 +325,7 @@ static whal_Error Process_BlockCipher(whal_Crypto *cryptoDev, static whal_Error EndOp_BlockCipher(whal_Crypto *cryptoDev) { - whal_Reg_Update(cryptoDev->regmap.base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg_Update(cryptoDev->base, AES_CR_REG, AES_CR_EN_Msk, 0); return WHAL_SUCCESS; } @@ -338,7 +338,7 @@ static whal_Error StartOp_AesGcm(whal_Crypto *cryptoDev, void *opArgs) whal_Crypto_AesGcmArgs *args = (whal_Crypto_AesGcmArgs *)opArgs; const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; const uint8_t *iv; const uint8_t *aad; size_t keySizeBit; @@ -436,7 +436,7 @@ static whal_Error Process_AesGcm(whal_Crypto *cryptoDev, void *opArgs) whal_Crypto_AesGcmArgs *args = (whal_Crypto_AesGcmArgs *)opArgs; const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; size_t mode; whal_Error err; size_t i; @@ -501,7 +501,7 @@ static whal_Error EndOp_AesGcm(whal_Crypto *cryptoDev, void *opArgs) whal_Crypto_AesGcmArgs *args = (whal_Crypto_AesGcmArgs *)opArgs; const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; uint8_t *tag; whal_Error err; uint8_t tagBuf[16]; @@ -550,7 +550,7 @@ static whal_Error StartOp_AesGmac(whal_Crypto *cryptoDev, void *opArgs) whal_Crypto_AesGmacArgs *args = (whal_Crypto_AesGmacArgs *)opArgs; const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; const uint8_t *iv; const uint8_t *aad; size_t keySizeBit; @@ -645,7 +645,7 @@ static whal_Error EndOp_AesGmac(whal_Crypto *cryptoDev, void *opArgs) whal_Crypto_AesGmacArgs *args = (whal_Crypto_AesGmacArgs *)opArgs; const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; uint8_t *tag; whal_Error err; uint8_t tagBuf[16]; @@ -694,7 +694,7 @@ static whal_Error StartOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) whal_Crypto_AesCcmArgs *args = (whal_Crypto_AesCcmArgs *)opArgs; const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; const uint8_t *nonce = (const uint8_t *)args->nonce; const uint8_t *aad = (const uint8_t *)args->aad; size_t keySizeBit; @@ -822,7 +822,7 @@ static whal_Error Process_AesCcm(whal_Crypto *cryptoDev, void *opArgs) whal_Crypto_AesCcmArgs *args = (whal_Crypto_AesCcmArgs *)opArgs; const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; size_t mode; whal_Error err; size_t i; @@ -887,7 +887,7 @@ static whal_Error EndOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) whal_Crypto_AesCcmArgs *args = (whal_Crypto_AesCcmArgs *)opArgs; const whal_Stm32wb_Aes_Cfg *cfg = (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; uint8_t *tag; whal_Error err; uint8_t tagBuf[16]; diff --git a/src/crypto/stm32wba_hash.c b/src/crypto/stm32wba_hash.c index 24ea5f1..f43ee11 100644 --- a/src/crypto/stm32wba_hash.c +++ b/src/crypto/stm32wba_hash.c @@ -98,7 +98,7 @@ static whal_Error Process_Hash(whal_Crypto *cryptoDev, const void *in, if (!in) return WHAL_EINVAL; - WriteData(cryptoDev->regmap.base, (const uint8_t *)in, inSz); + WriteData(cryptoDev->base, (const uint8_t *)in, inSz); return WHAL_SUCCESS; } @@ -135,7 +135,7 @@ whal_Error whal_Stm32wba_Hash_Deinit(whal_Crypto *cryptoDev) defined(WHAL_CFG_CRYPTO_SHA256) static whal_Error StartOp_Hash(whal_Crypto *cryptoDev, size_t algo) { - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); @@ -153,7 +153,7 @@ static whal_Error EndOp_Hash(whal_Crypto *cryptoDev, size_t expectedDigestSz, whal_Crypto_HashArgs *args = (whal_Crypto_HashArgs *)opArgs; const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; whal_Error err; if (!args->digest || args->digestSz != expectedDigestSz) @@ -182,7 +182,7 @@ static whal_Error StartOp_Hmac(whal_Crypto *cryptoDev, size_t algo, whal_Crypto_HmacArgs *args = (whal_Crypto_HmacArgs *)opArgs; const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; size_t lkey; whal_Error err; @@ -220,7 +220,7 @@ static whal_Error EndOp_Hmac(whal_Crypto *cryptoDev, size_t expectedDigestSz, whal_Crypto_HmacArgs *args = (whal_Crypto_HmacArgs *)opArgs; const whal_Stm32wba_Hash_Cfg *cfg = (const whal_Stm32wba_Hash_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->regmap.base; + size_t base = cryptoDev->base; whal_Error err; if (!args->key || !args->digest || args->digestSz != expectedDigestSz) diff --git a/src/dma/stm32wb_dma.c b/src/dma/stm32wb_dma.c index 6098660..d683f62 100644 --- a/src/dma/stm32wb_dma.c +++ b/src/dma/stm32wb_dma.c @@ -106,7 +106,7 @@ whal_Error whal_Stm32wb_Dma_Init(whal_Dma *dmaDev) } cfg = (whal_Stm32wb_Dma_Cfg *)dmaDev->cfg; - base = dmaDev->regmap.base; + base = dmaDev->base; /* Clear all interrupt flags for all channels */ { @@ -130,7 +130,7 @@ whal_Error whal_Stm32wb_Dma_Deinit(whal_Dma *dmaDev) } cfg = (whal_Stm32wb_Dma_Cfg *)dmaDev->cfg; - base = dmaDev->regmap.base; + base = dmaDev->base; /* Disable all channels and clear all interrupt flags */ for (size_t i = 1; i <= cfg->numChannels; ++i) { @@ -171,7 +171,7 @@ whal_Error whal_Stm32wb_Dma_Configure(whal_Dma *dmaDev, size_t ch, cfg = (whal_Stm32wb_Dma_Cfg *)dmaDev->cfg; dmaChCfg = (const whal_Stm32wb_Dma_ChCfg *)chCfg; - base = dmaDev->regmap.base; + base = dmaDev->base; if (ch >= cfg->numChannels) { return WHAL_EINVAL; @@ -281,7 +281,7 @@ whal_Error whal_Stm32wb_Dma_Start(whal_Dma *dmaDev, size_t ch) } cfg = (whal_Stm32wb_Dma_Cfg *)dmaDev->cfg; - base = dmaDev->regmap.base; + base = dmaDev->base; if (ch >= cfg->numChannels) { return WHAL_EINVAL; @@ -311,7 +311,7 @@ whal_Error whal_Stm32wb_Dma_Stop(whal_Dma *dmaDev, size_t ch) } cfg = (whal_Stm32wb_Dma_Cfg *)dmaDev->cfg; - base = dmaDev->regmap.base; + base = dmaDev->base; if (ch >= cfg->numChannels) { return WHAL_EINVAL; @@ -340,7 +340,7 @@ void whal_Stm32wb_Dma_IRQHandler(whal_Dma *dmaDev, size_t ch, if (!dmaDev) return; - base = dmaDev->regmap.base; + base = dmaDev->base; hw_ch = ch + 1; isr = whal_Reg_Read(base, DMA_ISR_REG); diff --git a/src/dma/stm32wba_gpdma.c b/src/dma/stm32wba_gpdma.c index b3c9449..3fe04f7 100644 --- a/src/dma/stm32wba_gpdma.c +++ b/src/dma/stm32wba_gpdma.c @@ -132,7 +132,7 @@ whal_Error whal_Stm32wba_Gpdma_Deinit(whal_Dma *dmaDev) /* Reset all channels */ for (uint8_t ch = 0; ch < cfg->numChannels; ch++) { - whal_Reg_Write(dmaDev->regmap.base, GPDMA_CxCR(ch), + whal_Reg_Write(dmaDev->base, GPDMA_CxCR(ch), GPDMA_CxCR_RESET_Msk); } @@ -153,7 +153,7 @@ whal_Error whal_Stm32wba_Gpdma_Configure(whal_Dma *dmaDev, size_t ch, cfg = (const whal_Stm32wba_Gpdma_Cfg *)dmaDev->cfg; ccfg = (const whal_Stm32wba_Gpdma_ChCfg *)chCfg; - base = dmaDev->regmap.base; + base = dmaDev->base; if (ch >= cfg->numChannels) return WHAL_EINVAL; @@ -230,10 +230,10 @@ whal_Error whal_Stm32wba_Gpdma_Start(whal_Dma *dmaDev, size_t ch) return WHAL_EINVAL; /* Clear any stale flags from the previous transfer before enabling */ - whal_Reg_Write(dmaDev->regmap.base, GPDMA_CxFCR(ch), GPDMA_CxFCR_ALL); + whal_Reg_Write(dmaDev->base, GPDMA_CxFCR(ch), GPDMA_CxFCR_ALL); /* Set EN bit without disturbing the already-configured interrupt enables */ - whal_Reg_Update(dmaDev->regmap.base, GPDMA_CxCR(ch), GPDMA_CxCR_EN_Msk, + whal_Reg_Update(dmaDev->base, GPDMA_CxCR(ch), GPDMA_CxCR_EN_Msk, GPDMA_CxCR_EN_Msk); return WHAL_SUCCESS; @@ -248,7 +248,7 @@ whal_Error whal_Stm32wba_Gpdma_Stop(whal_Dma *dmaDev, size_t ch) return WHAL_EINVAL; cfg = (const whal_Stm32wba_Gpdma_Cfg *)dmaDev->cfg; - base = dmaDev->regmap.base; + base = dmaDev->base; if (ch >= cfg->numChannels) return WHAL_EINVAL; @@ -269,7 +269,7 @@ void whal_Stm32wba_Gpdma_IRQHandler(whal_Dma *dmaDev, size_t ch, if (!dmaDev) return; - base = dmaDev->regmap.base; + base = dmaDev->base; sr = whal_Reg_Read(base, GPDMA_CxSR(ch)); if (sr & GPDMA_CxSR_ALL_ERR) { diff --git a/src/eth/stm32h5_eth.c b/src/eth/stm32h5_eth.c index 03d7b1c..3ed8542 100644 --- a/src/eth/stm32h5_eth.c +++ b/src/eth/stm32h5_eth.c @@ -150,7 +150,7 @@ whal_Error whal_Stm32h5_Eth_Init(whal_Eth *ethDev) return WHAL_EINVAL; cfg = (whal_Stm32h5_Eth_Cfg *)ethDev->cfg; - base = ethDev->regmap.base; + base = ethDev->base; if (!cfg->txDescs || !cfg->txBufs || cfg->txDescCount == 0 || !cfg->rxDescs || !cfg->rxBufs || cfg->rxDescCount == 0 || @@ -237,7 +237,7 @@ whal_Error whal_Stm32h5_Eth_Deinit(whal_Eth *ethDev) if (!ethDev) return WHAL_EINVAL; - whal_Reg_Update(ethDev->regmap.base, ETH_DMAMR_REG, + whal_Reg_Update(ethDev->base, ETH_DMAMR_REG, ETH_DMAMR_SWR_Msk, ETH_DMAMR_SWR_Msk); return WHAL_SUCCESS; @@ -253,7 +253,7 @@ whal_Error whal_Stm32h5_Eth_Start(whal_Eth *ethDev, uint8_t speed, return WHAL_EINVAL; cfg = (whal_Stm32h5_Eth_Cfg *)ethDev->cfg; - base = ethDev->regmap.base; + base = ethDev->base; /* Configure MAC speed and duplex to match PHY */ whal_Reg_Update(base, ETH_MACCR_REG, @@ -288,7 +288,7 @@ whal_Error whal_Stm32h5_Eth_Stop(whal_Eth *ethDev) if (!ethDev) return WHAL_EINVAL; - base = ethDev->regmap.base; + base = ethDev->base; /* Stop DMA TX */ whal_Reg_Update(base, ETH_DMACTXCR_REG, ETH_DMACTXCR_ST_Msk, 0); @@ -319,7 +319,7 @@ whal_Error whal_Stm32h5_Eth_Send(whal_Eth *ethDev, const void *frame, if (len > cfg->txBufSize) return WHAL_EINVAL; - base = ethDev->regmap.base; + base = ethDev->base; idx = cfg->txHead; desc = &cfg->txDescs[idx]; @@ -363,7 +363,7 @@ whal_Error whal_Stm32h5_Eth_Recv(whal_Eth *ethDev, void *frame, return WHAL_EINVAL; cfg = (whal_Stm32h5_Eth_Cfg *)ethDev->cfg; - base = ethDev->regmap.base; + base = ethDev->base; idx = cfg->rxHead; desc = &cfg->rxDescs[idx]; @@ -421,7 +421,7 @@ whal_Error whal_Stm32h5_Eth_MdioRead(whal_Eth *ethDev, uint8_t phyAddr, return WHAL_EINVAL; cfg = (whal_Stm32h5_Eth_Cfg *)ethDev->cfg; - base = ethDev->regmap.base; + base = ethDev->base; err = MdioPoll(base, cfg->timeout); if (err) @@ -459,7 +459,7 @@ whal_Error whal_Stm32h5_Eth_MdioWrite(whal_Eth *ethDev, uint8_t phyAddr, return WHAL_EINVAL; cfg = (whal_Stm32h5_Eth_Cfg *)ethDev->cfg; - base = ethDev->regmap.base; + base = ethDev->base; err = MdioPoll(base, cfg->timeout); if (err) @@ -494,7 +494,7 @@ whal_Error whal_Stm32h5_Eth_Ext_EnableLoopback(whal_Eth *ethDev, if (!ethDev) return WHAL_EINVAL; - whal_Reg_Update(ethDev->regmap.base, ETH_MACCR_REG, ETH_MACCR_LM_Msk, + whal_Reg_Update(ethDev->base, ETH_MACCR_REG, ETH_MACCR_LM_Msk, whal_SetBits(ETH_MACCR_LM_Msk, ETH_MACCR_LM_Pos, enable ? 1 : 0)); diff --git a/src/eth/stm32n6_eth.c b/src/eth/stm32n6_eth.c index a7c0afd..cab19b0 100644 --- a/src/eth/stm32n6_eth.c +++ b/src/eth/stm32n6_eth.c @@ -161,7 +161,7 @@ whal_Error whal_Stm32n6_Eth_Init(whal_Eth *ethDev) return WHAL_EINVAL; cfg = (whal_Stm32n6_Eth_Cfg *)ethDev->cfg; - base = ethDev->regmap.base; + base = ethDev->base; if (!cfg->txDescs || !cfg->txBufs || cfg->txDescCount == 0 || !cfg->rxDescs || !cfg->rxBufs || cfg->rxDescCount == 0 || @@ -265,7 +265,7 @@ whal_Error whal_Stm32n6_Eth_Deinit(whal_Eth *ethDev) if (!ethDev) return WHAL_EINVAL; - whal_Reg_Update(ethDev->regmap.base, ETH_DMAMR_REG, + whal_Reg_Update(ethDev->base, ETH_DMAMR_REG, ETH_DMAMR_SWR_Msk, ETH_DMAMR_SWR_Msk); return WHAL_SUCCESS; @@ -281,7 +281,7 @@ whal_Error whal_Stm32n6_Eth_Start(whal_Eth *ethDev, uint8_t speed, return WHAL_EINVAL; cfg = (whal_Stm32n6_Eth_Cfg *)ethDev->cfg; - base = ethDev->regmap.base; + base = ethDev->base; /* Configure MAC speed and duplex to match PHY. PS=1 selects the * MII/RMII data path; required because the EQOS MAC defaults to GMII @@ -319,7 +319,7 @@ whal_Error whal_Stm32n6_Eth_Stop(whal_Eth *ethDev) if (!ethDev) return WHAL_EINVAL; - base = ethDev->regmap.base; + base = ethDev->base; /* Stop DMA TX */ whal_Reg_Update(base, ETH_DMAC0TXCR_REG, ETH_DMAC0TXCR_ST_Msk, 0); @@ -350,7 +350,7 @@ whal_Error whal_Stm32n6_Eth_Send(whal_Eth *ethDev, const void *frame, if (len > cfg->txBufSize) return WHAL_EINVAL; - base = ethDev->regmap.base; + base = ethDev->base; idx = cfg->txHead; desc = &cfg->txDescs[idx]; @@ -399,7 +399,7 @@ whal_Error whal_Stm32n6_Eth_Recv(whal_Eth *ethDev, void *frame, return WHAL_EINVAL; cfg = (whal_Stm32n6_Eth_Cfg *)ethDev->cfg; - base = ethDev->regmap.base; + base = ethDev->base; idx = cfg->rxHead; desc = &cfg->rxDescs[idx]; @@ -460,7 +460,7 @@ whal_Error whal_Stm32n6_Eth_MdioRead(whal_Eth *ethDev, uint8_t phyAddr, return WHAL_EINVAL; cfg = (whal_Stm32n6_Eth_Cfg *)ethDev->cfg; - base = ethDev->regmap.base; + base = ethDev->base; err = MdioPoll(base, cfg->timeout); if (err) @@ -498,7 +498,7 @@ whal_Error whal_Stm32n6_Eth_MdioWrite(whal_Eth *ethDev, uint8_t phyAddr, return WHAL_EINVAL; cfg = (whal_Stm32n6_Eth_Cfg *)ethDev->cfg; - base = ethDev->regmap.base; + base = ethDev->base; err = MdioPoll(base, cfg->timeout); if (err) @@ -533,7 +533,7 @@ whal_Error whal_Stm32n6_Eth_Ext_EnableLoopback(whal_Eth *ethDev, if (!ethDev) return WHAL_EINVAL; - whal_Reg_Update(ethDev->regmap.base, ETH_MACCR_REG, ETH_MACCR_LM_Msk, + whal_Reg_Update(ethDev->base, ETH_MACCR_REG, ETH_MACCR_LM_Msk, whal_SetBits(ETH_MACCR_LM_Msk, ETH_MACCR_LM_Pos, enable ? 1 : 0)); diff --git a/src/flash/pic32cz_flash.c b/src/flash/pic32cz_flash.c index 6448fa0..79f9e2f 100644 --- a/src/flash/pic32cz_flash.c +++ b/src/flash/pic32cz_flash.c @@ -104,34 +104,34 @@ #define whal_Pic32cz_Flash_Erase whal_Flash_Erase #endif /* WHAL_CFG_PIC32CZ_FLASH_DIRECT_API_MAPPING */ -static whal_Error whal_Pic32cz_Flash_MutexLock(const whal_Regmap *reg, +static whal_Error whal_Pic32cz_Flash_MutexLock(size_t base, whal_Timeout *timeout) { WHAL_TIMEOUT_START(timeout); - while (whal_Reg_Read(reg->base, FCW_MUTEX_REG) & FCW_MUTEX_LOCK_Msk) { + while (whal_Reg_Read(base, FCW_MUTEX_REG) & FCW_MUTEX_LOCK_Msk) { if (WHAL_TIMEOUT_EXPIRED(timeout)) return WHAL_ETIMEOUT; } - whal_Reg_Update(reg->base, FCW_MUTEX_REG, FCW_MUTEX_LOCK_Msk | FCW_MUTEX_OWNER_Msk, + whal_Reg_Update(base, FCW_MUTEX_REG, FCW_MUTEX_LOCK_Msk | FCW_MUTEX_OWNER_Msk, whal_SetBits(FCW_MUTEX_LOCK_Msk, FCW_MUTEX_LOCK_Pos, 1) | whal_SetBits(FCW_MUTEX_OWNER_Msk, FCW_MUTEX_OWNER_Pos, 1)); return WHAL_SUCCESS; } -static void whal_Pic32cz_Flash_MutexUnlock(const whal_Regmap *reg) +static void whal_Pic32cz_Flash_MutexUnlock(size_t base) { - whal_Reg_Update(reg->base, FCW_MUTEX_REG, FCW_MUTEX_LOCK_Msk | FCW_MUTEX_OWNER_Msk, + whal_Reg_Update(base, FCW_MUTEX_REG, FCW_MUTEX_LOCK_Msk | FCW_MUTEX_OWNER_Msk, whal_SetBits(FCW_MUTEX_LOCK_Msk, FCW_MUTEX_LOCK_Pos, 0) | whal_SetBits(FCW_MUTEX_OWNER_Msk, FCW_MUTEX_OWNER_Pos, 1)); } -static whal_Error whal_Pic32cz_Flash_WaitBusy(const whal_Regmap *reg, +static whal_Error whal_Pic32cz_Flash_WaitBusy(size_t base, whal_Timeout *timeout) { WHAL_TIMEOUT_START(timeout); - while (whal_Reg_Read(reg->base, FCW_STATUS_REG) & FCW_STATUS_BUSY_Msk) { + while (whal_Reg_Read(base, FCW_STATUS_REG) & FCW_STATUS_BUSY_Msk) { if (WHAL_TIMEOUT_EXPIRED(timeout)) return WHAL_ETIMEOUT; } @@ -143,35 +143,35 @@ static whal_Error whal_Pic32cz_Flash_WaitBusy(const whal_Regmap *reg, * Execute an FCW command: unlock, trigger, wait, and check for errors. * Caller must set up FCW_ADDR and FCW_DATA registers before calling. */ -static whal_Error whal_Pic32cz_Flash_ExecCmd(const whal_Regmap *reg, size_t cmd, +static whal_Error whal_Pic32cz_Flash_ExecCmd(size_t base, size_t cmd, whal_Timeout *timeout) { whal_Error err; size_t errFlags; /* Write unlock key */ - whal_Reg_Update(reg->base, FCW_KEY_REG, 0xFFFFFFFF, FCW_UNLOCK_WRKEY); + whal_Reg_Update(base, FCW_KEY_REG, 0xFFFFFFFF, FCW_UNLOCK_WRKEY); /* Trigger operation with pre-program enabled */ - whal_Reg_Update(reg->base, FCW_CTRLA_REG, + whal_Reg_Update(base, FCW_CTRLA_REG, FCW_CTRLA_NVMOP_Msk | FCW_CTRLA_PREPG_Msk, whal_SetBits(FCW_CTRLA_NVMOP_Msk, FCW_CTRLA_NVMOP_Pos, cmd) | FCW_CTRLA_PREPG_Msk); /* Wait for completion */ - err = whal_Pic32cz_Flash_WaitBusy(reg, timeout); + err = whal_Pic32cz_Flash_WaitBusy(base, timeout); if (err) return err; /* Check for errors */ - whal_Reg_Get(reg->base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL_ERR, 0, &errFlags); + whal_Reg_Get(base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL_ERR, 0, &errFlags); /* Clear DONE flag */ - whal_Reg_Update(reg->base, FCW_INTFLAG_REG, FCW_INTFLAG_DONE_Msk, + whal_Reg_Update(base, FCW_INTFLAG_REG, FCW_INTFLAG_DONE_Msk, FCW_INTFLAG_DONE_Msk); if (errFlags) { /* Clear error flags */ - whal_Reg_Update(reg->base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL_ERR, + whal_Reg_Update(base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL_ERR, FCW_INTFLAG_ALL_ERR); return WHAL_EINVAL; } @@ -181,21 +181,21 @@ static whal_Error whal_Pic32cz_Flash_ExecCmd(const whal_Regmap *reg, size_t cmd, whal_Error whal_Pic32cz_Flash_Init(whal_Flash *flashDev) { - const whal_Regmap *reg; + size_t base; if (!flashDev) { return WHAL_EINVAL; } - reg = &flashDev->regmap; + base = flashDev->base; - whal_Pic32cz_Flash_MutexUnlock(reg); - whal_Reg_Update(reg->base, FCW_KEY_REG, 0xFFFFFFFF, 0); - whal_Reg_Update(reg->base, FCW_ADDR_REG, 0xFFFFFFFF, 0); - whal_Reg_Update(reg->base, FCW_SRCADDR_REG, 0xFFFFFFFF, 0); + whal_Pic32cz_Flash_MutexUnlock(base); + whal_Reg_Update(base, FCW_KEY_REG, 0xFFFFFFFF, 0); + whal_Reg_Update(base, FCW_ADDR_REG, 0xFFFFFFFF, 0); + whal_Reg_Update(base, FCW_SRCADDR_REG, 0xFFFFFFFF, 0); /* Clear all pending interrupt flags */ - whal_Reg_Update(reg->base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL, + whal_Reg_Update(base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL, FCW_INTFLAG_ALL); return WHAL_SUCCESS; @@ -203,21 +203,21 @@ whal_Error whal_Pic32cz_Flash_Init(whal_Flash *flashDev) whal_Error whal_Pic32cz_Flash_Deinit(whal_Flash *flashDev) { - const whal_Regmap *reg; + size_t base; if (!flashDev) { return WHAL_EINVAL; } - reg = &flashDev->regmap; + base = flashDev->base; - whal_Pic32cz_Flash_MutexUnlock(reg); - whal_Reg_Update(reg->base, FCW_KEY_REG, 0xFFFFFFFF, 0); - whal_Reg_Update(reg->base, FCW_ADDR_REG, 0xFFFFFFFF, 0); - whal_Reg_Update(reg->base, FCW_SRCADDR_REG, 0xFFFFFFFF, 0); + whal_Pic32cz_Flash_MutexUnlock(base); + whal_Reg_Update(base, FCW_KEY_REG, 0xFFFFFFFF, 0); + whal_Reg_Update(base, FCW_ADDR_REG, 0xFFFFFFFF, 0); + whal_Reg_Update(base, FCW_SRCADDR_REG, 0xFFFFFFFF, 0); /* Clear all pending interrupt flags */ - whal_Reg_Update(reg->base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL, + whal_Reg_Update(base, FCW_INTFLAG_REG, FCW_INTFLAG_ALL, FCW_INTFLAG_ALL); return WHAL_SUCCESS; @@ -256,7 +256,7 @@ whal_Error whal_Pic32cz_Flash_Read(whal_Flash *flashDev, size_t addr, void *data size_t dataSz) { uint8_t *dataBuf = (uint8_t *)data; - const whal_Regmap *reg; + size_t base; whal_Pic32cz_Flash_Cfg *cfg; uint8_t *flashAddr = (uint8_t *)addr; whal_Error err; @@ -266,11 +266,11 @@ whal_Error whal_Pic32cz_Flash_Read(whal_Flash *flashDev, size_t addr, void *data return WHAL_EINVAL; } - reg = &flashDev->regmap; + base = flashDev->base; cfg = flashDev->cfg; - err = whal_Pic32cz_Flash_MutexLock(reg, cfg->timeout); + err = whal_Pic32cz_Flash_MutexLock(base, cfg->timeout); if (err) return err; @@ -279,7 +279,7 @@ whal_Error whal_Pic32cz_Flash_Read(whal_Flash *flashDev, size_t addr, void *data dataBuf[i] = flashAddr[i]; } - whal_Pic32cz_Flash_MutexUnlock(reg); + whal_Pic32cz_Flash_MutexUnlock(base); return WHAL_SUCCESS; } @@ -288,7 +288,7 @@ whal_Error whal_Pic32cz_Flash_Write(whal_Flash *flashDev, size_t addr, const voi size_t dataSz) { const uint8_t *dataBuf = (const uint8_t *)data; - const whal_Regmap *reg; + size_t base; whal_Pic32cz_Flash_Cfg *cfg; const uint32_t *src; whal_Error err; @@ -305,11 +305,11 @@ whal_Error whal_Pic32cz_Flash_Write(whal_Flash *flashDev, size_t addr, const voi return WHAL_EINVAL; } - reg = &flashDev->regmap; + base = flashDev->base; src = (const uint32_t *)dataBuf; - err = whal_Pic32cz_Flash_MutexLock(reg, cfg->timeout); + err = whal_Pic32cz_Flash_MutexLock(base, cfg->timeout); if (err) return err; @@ -317,9 +317,9 @@ whal_Error whal_Pic32cz_Flash_Write(whal_Flash *flashDev, size_t addr, const voi size_t curAddr = addr + offset; size_t remaining = dataSz - offset; - err = whal_Pic32cz_Flash_WaitBusy(reg, cfg->timeout); + err = whal_Pic32cz_Flash_WaitBusy(base, cfg->timeout); if (err) { - whal_Pic32cz_Flash_MutexUnlock(reg); + whal_Pic32cz_Flash_MutexUnlock(base); return err; } @@ -327,32 +327,32 @@ whal_Error whal_Pic32cz_Flash_Write(whal_Flash *flashDev, size_t addr, const voi /* Quad double word write (32 bytes) */ size_t j; for (j = 0; j < 8; j++) { - whal_Reg_Update(reg->base, FCW_DATA_REG(j), + whal_Reg_Update(base, FCW_DATA_REG(j), 0xFFFFFFFF, src[offset / 4 + j]); } - whal_Reg_Update(reg->base, FCW_ADDR_REG, 0xFFFFFFFF, curAddr); + whal_Reg_Update(base, FCW_ADDR_REG, 0xFFFFFFFF, curAddr); - err = whal_Pic32cz_Flash_ExecCmd(reg, + err = whal_Pic32cz_Flash_ExecCmd(base, FCW_CTRLA_NVMOP_QUAD_DWORD, cfg->timeout); if (err) { - whal_Pic32cz_Flash_MutexUnlock(reg); + whal_Pic32cz_Flash_MutexUnlock(base); return err; } offset += FCW_QDWORD_SIZE; } else { /* Single double word write (8 bytes) */ - whal_Reg_Update(reg->base, FCW_DATA_REG(0), + whal_Reg_Update(base, FCW_DATA_REG(0), 0xFFFFFFFF, src[offset / 4]); - whal_Reg_Update(reg->base, FCW_DATA_REG(1), + whal_Reg_Update(base, FCW_DATA_REG(1), 0xFFFFFFFF, src[offset / 4 + 1]); - whal_Reg_Update(reg->base, FCW_ADDR_REG, 0xFFFFFFFF, curAddr); + whal_Reg_Update(base, FCW_ADDR_REG, 0xFFFFFFFF, curAddr); - err = whal_Pic32cz_Flash_ExecCmd(reg, + err = whal_Pic32cz_Flash_ExecCmd(base, FCW_CTRLA_NVMOP_SINGLE_DWORD, cfg->timeout); if (err) { - whal_Pic32cz_Flash_MutexUnlock(reg); + whal_Pic32cz_Flash_MutexUnlock(base); return err; } offset += FCW_DWORD_SIZE; @@ -360,14 +360,14 @@ whal_Error whal_Pic32cz_Flash_Write(whal_Flash *flashDev, size_t addr, const voi } - whal_Pic32cz_Flash_MutexUnlock(reg); + whal_Pic32cz_Flash_MutexUnlock(base); return WHAL_SUCCESS; } whal_Error whal_Pic32cz_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t dataSz) { - const whal_Regmap *reg; + size_t base; whal_Pic32cz_Flash_Cfg *cfg; whal_Error err; size_t pageAddr; @@ -378,37 +378,37 @@ whal_Error whal_Pic32cz_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t da } cfg = flashDev->cfg; - reg = &flashDev->regmap; + base = flashDev->base; /* Align down to page boundary */ pageAddr = addr & ~(FCW_PAGE_SIZE - 1); endAddr = addr + dataSz; - err = whal_Pic32cz_Flash_MutexLock(reg, cfg->timeout); + err = whal_Pic32cz_Flash_MutexLock(base, cfg->timeout); if (err) return err; while (pageAddr < endAddr) { - err = whal_Pic32cz_Flash_WaitBusy(reg, cfg->timeout); + err = whal_Pic32cz_Flash_WaitBusy(base, cfg->timeout); if (err) { - whal_Pic32cz_Flash_MutexUnlock(reg); + whal_Pic32cz_Flash_MutexUnlock(base); return err; } - whal_Reg_Update(reg->base, FCW_ADDR_REG, 0xFFFFFFFF, pageAddr); + whal_Reg_Update(base, FCW_ADDR_REG, 0xFFFFFFFF, pageAddr); - err = whal_Pic32cz_Flash_ExecCmd(reg, FCW_CTRLA_NVMOP_PAGE_ERASE, + err = whal_Pic32cz_Flash_ExecCmd(base, FCW_CTRLA_NVMOP_PAGE_ERASE, cfg->timeout); if (err) { - whal_Pic32cz_Flash_MutexUnlock(reg); + whal_Pic32cz_Flash_MutexUnlock(base); return err; } pageAddr += FCW_PAGE_SIZE; } - whal_Pic32cz_Flash_MutexUnlock(reg); + whal_Pic32cz_Flash_MutexUnlock(base); return WHAL_SUCCESS; } diff --git a/src/flash/stm32c0_flash.c b/src/flash/stm32c0_flash.c index ab48e17..c027761 100644 --- a/src/flash/stm32c0_flash.c +++ b/src/flash/stm32c0_flash.c @@ -1,4 +1,5 @@ #include +#include #include #include #include @@ -111,7 +112,7 @@ whal_Error whal_Stm32c0_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32c0_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { - const whal_Regmap *regmap; + size_t base; (void)addr; (void)len; @@ -120,10 +121,10 @@ whal_Error whal_Stm32c0_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len return WHAL_EINVAL; } - regmap = &flashDev->regmap; + base = flashDev->base; /* Setting LOCK bit prevents further flash modifications until next unlock */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, whal_SetBits(FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, 1)); return WHAL_SUCCESS; @@ -131,7 +132,7 @@ whal_Error whal_Stm32c0_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len whal_Error whal_Stm32c0_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { - const whal_Regmap *regmap; + size_t base; (void)addr; (void)len; @@ -140,14 +141,14 @@ whal_Error whal_Stm32c0_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t l return WHAL_EINVAL; } - regmap = &flashDev->regmap; + base = flashDev->base; /* * Unlock sequence: write KEY1 then KEY2 to KEYR register. * Incorrect sequence or order will trigger a bus error. */ - whal_Reg_Update(regmap->base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0x45670123); - whal_Reg_Update(regmap->base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0xCDEF89AB); + whal_Reg_Update(base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0x45670123); + whal_Reg_Update(base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0xCDEF89AB); return WHAL_SUCCESS; } @@ -187,7 +188,7 @@ static whal_Error whal_Stm32c0_Flash_WriteOrErase(whal_Flash *flashDev, size_t a size_t dataSz, uint8_t write) { whal_Stm32c0_Flash_Cfg *cfg; - const whal_Regmap *regmap; + size_t base; size_t bsy; if (!flashDev || !flashDev->cfg) { @@ -195,7 +196,7 @@ static whal_Error whal_Stm32c0_Flash_WriteOrErase(whal_Flash *flashDev, size_t a } cfg = flashDev->cfg; - regmap = &flashDev->regmap; + base = flashDev->base; if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) return WHAL_EINVAL; @@ -208,20 +209,20 @@ static whal_Error whal_Stm32c0_Flash_WriteOrErase(whal_Flash *flashDev, size_t a return WHAL_SUCCESS; /* Check if flash is busy */ - whal_Reg_Get(regmap->base, FLASH_SR_REG, FLASH_SR_BSY_Msk, FLASH_SR_BSY_Pos, &bsy); + whal_Reg_Get(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, FLASH_SR_BSY_Pos, &bsy); if (bsy) { return WHAL_ENOTREADY; } /* Clear all error flags by writing 1 to each */ - whal_Reg_Update(regmap->base, FLASH_SR_REG, FLASH_SR_ALL_ERR, 0xffffffff); + whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, 0xffffffff); whal_Error err = WHAL_SUCCESS; if (write) { /* Enable flash programming mode */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PG_Msk, 1); + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk, 1); /* Program data in 64-bit (8 byte) double-word chunks */ for (size_t i = 0; i < dataSz; i += 8) { @@ -233,7 +234,7 @@ static whal_Error whal_Stm32c0_Flash_WriteOrErase(whal_Flash *flashDev, size_t a flashAddr[1] = dataAddr[1]; /* Wait for programming to complete */ - err = whal_Reg_ReadPoll(regmap->base, FLASH_SR_REG, + err = whal_Reg_ReadPoll(base, FLASH_SR_REG, FLASH_SR_CFGBSY_Msk, 0, cfg->timeout); if (err) goto cleanup; @@ -246,34 +247,34 @@ static whal_Error whal_Stm32c0_Flash_WriteOrErase(whal_Flash *flashDev, size_t a endPage = ((addr - cfg->startAddr) + dataSz - 1) >> 11; /* Enable page erase mode */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PER_Msk, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PER_Msk, whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 1)); /* Erase each page in the range */ for (size_t page = startPage; page <= endPage; ++page) { /* Select page number */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PNB_Msk, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PNB_Msk, whal_SetBits(FLASH_CR_PNB_Msk, FLASH_CR_PNB_Pos, page)); /* Start erase operation */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_STRT_Msk, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_STRT_Msk, whal_SetBits(FLASH_CR_STRT_Msk, FLASH_CR_STRT_Pos, 1)); /* Wait for erase to complete */ - err = whal_Reg_ReadPoll(regmap->base, FLASH_SR_REG, + err = whal_Reg_ReadPoll(base, FLASH_SR_REG, FLASH_SR_CFGBSY_Msk, 0, cfg->timeout); if (err) goto cleanup; } /* Disable page erase mode */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PER_Msk, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PER_Msk, whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 0)); } cleanup: /* Clear programming and erase mode bits */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk | FLASH_CR_PER_Msk, 0); return err; @@ -297,8 +298,8 @@ whal_Error whal_Stm32c0_Flash_Ext_SetLatency(whal_Flash *flashDev, enum whal_Stm return WHAL_EINVAL; } - const whal_Regmap *reg = &flashDev->regmap; - whal_Reg_Update(reg->base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); + size_t base = flashDev->base; + whal_Reg_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); return WHAL_SUCCESS; } diff --git a/src/flash/stm32f0_flash.c b/src/flash/stm32f0_flash.c index 6495ad6..becfc99 100644 --- a/src/flash/stm32f0_flash.c +++ b/src/flash/stm32f0_flash.c @@ -1,4 +1,5 @@ #include +#include #include #include #include @@ -67,7 +68,7 @@ whal_Error whal_Stm32f0_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len if (!flashDev) return WHAL_EINVAL; - whal_Reg_Update(flashDev->regmap.base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, + whal_Reg_Update(flashDev->base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, whal_SetBits(FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, 1)); return WHAL_SUCCESS; @@ -81,9 +82,9 @@ whal_Error whal_Stm32f0_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t l if (!flashDev) return WHAL_EINVAL; - whal_Reg_Update(flashDev->regmap.base, FLASH_KEYR_REG, + whal_Reg_Update(flashDev->base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0x45670123); - whal_Reg_Update(flashDev->regmap.base, FLASH_KEYR_REG, + whal_Reg_Update(flashDev->base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0xCDEF89AB); return WHAL_SUCCESS; @@ -119,14 +120,14 @@ static whal_Error whal_Stm32f0_Flash_WriteOrErase(whal_Flash *flashDev, size_t dataSz, uint8_t write) { whal_Stm32f0_Flash_Cfg *cfg; - const whal_Regmap *regmap; + size_t base; size_t bsy; if (!flashDev || !flashDev->cfg) return WHAL_EINVAL; cfg = flashDev->cfg; - regmap = &flashDev->regmap; + base = flashDev->base; if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) return WHAL_EINVAL; @@ -138,19 +139,19 @@ static whal_Error whal_Stm32f0_Flash_WriteOrErase(whal_Flash *flashDev, if (!write && dataSz == 0) return WHAL_SUCCESS; - whal_Reg_Get(regmap->base, FLASH_SR_REG, + whal_Reg_Get(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, FLASH_SR_BSY_Pos, &bsy); if (bsy) return WHAL_ENOTREADY; /* Clear error flags */ - whal_Reg_Update(regmap->base, FLASH_SR_REG, FLASH_SR_ALL_ERR, 0xffffffff); + whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, 0xffffffff); whal_Error err = WHAL_SUCCESS; if (write) { /* Enable programming */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PG_Msk, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk, whal_SetBits(FLASH_CR_PG_Msk, FLASH_CR_PG_Pos, 1)); /* Program in 16-bit half-words */ @@ -160,7 +161,7 @@ static whal_Error whal_Stm32f0_Flash_WriteOrErase(whal_Flash *flashDev, *flashAddr = hw; - err = whal_Reg_ReadPoll(regmap->base, FLASH_SR_REG, + err = whal_Reg_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, 0, cfg->timeout); if (err) goto cleanup; @@ -172,30 +173,30 @@ static whal_Error whal_Stm32f0_Flash_WriteOrErase(whal_Flash *flashDev, for (size_t page = startPage; page <= endPage; ++page) { /* Enable page erase */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PER_Msk, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PER_Msk, whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 1)); /* Write page start address to AR */ - whal_Reg_Write(regmap->base, FLASH_AR_REG, + whal_Reg_Write(base, FLASH_AR_REG, cfg->startAddr + (page << 11)); /* Start erase */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_STRT_Msk, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_STRT_Msk, whal_SetBits(FLASH_CR_STRT_Msk, FLASH_CR_STRT_Pos, 1)); - err = whal_Reg_ReadPoll(regmap->base, FLASH_SR_REG, + err = whal_Reg_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, 0, cfg->timeout); if (err) goto cleanup; } /* Disable page erase */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PER_Msk, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PER_Msk, whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 0)); } cleanup: - whal_Reg_Update(regmap->base, FLASH_CR_REG, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk | FLASH_CR_PER_Msk, 0); return err; @@ -220,7 +221,7 @@ whal_Error whal_Stm32f0_Flash_Ext_SetLatency(whal_Flash *flashDev, if (!flashDev) return WHAL_EINVAL; - whal_Reg_Update(flashDev->regmap.base, FLASH_ACR_REG, + whal_Reg_Update(flashDev->base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); return WHAL_SUCCESS; } diff --git a/src/flash/stm32f4_flash.c b/src/flash/stm32f4_flash.c index 41311f0..fd0b3ca 100644 --- a/src/flash/stm32f4_flash.c +++ b/src/flash/stm32f4_flash.c @@ -1,4 +1,5 @@ #include +#include #include #include #include @@ -103,7 +104,7 @@ whal_Error whal_Stm32f4_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32f4_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { - const whal_Regmap *regmap; + size_t base; (void)addr; (void)len; @@ -111,9 +112,9 @@ whal_Error whal_Stm32f4_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len if (!flashDev) return WHAL_EINVAL; - regmap = &flashDev->regmap; + base = flashDev->base; - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, whal_SetBits(FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, 1)); return WHAL_SUCCESS; @@ -121,7 +122,7 @@ whal_Error whal_Stm32f4_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len whal_Error whal_Stm32f4_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { - const whal_Regmap *regmap; + size_t base; (void)addr; (void)len; @@ -129,10 +130,10 @@ whal_Error whal_Stm32f4_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t l if (!flashDev) return WHAL_EINVAL; - regmap = &flashDev->regmap; + base = flashDev->base; - whal_Reg_Write(regmap->base, FLASH_KEYR_REG, FLASH_KEY1); - whal_Reg_Write(regmap->base, FLASH_KEYR_REG, FLASH_KEY2); + whal_Reg_Write(base, FLASH_KEYR_REG, FLASH_KEY1); + whal_Reg_Write(base, FLASH_KEYR_REG, FLASH_KEY2); return WHAL_SUCCESS; } @@ -163,14 +164,14 @@ whal_Error whal_Stm32f4_Flash_Write(whal_Flash *flashDev, size_t addr, { const uint8_t *dataBuf = (const uint8_t *)data; whal_Stm32f4_Flash_Cfg *cfg; - const whal_Regmap *regmap; + size_t base; whal_Error err = WHAL_SUCCESS; if (!flashDev || !flashDev->cfg || !data) return WHAL_EINVAL; cfg = flashDev->cfg; - regmap = &flashDev->regmap; + base = flashDev->base; /* Address and size must be 4-byte aligned for word programming */ if ((addr & 0x3) || (dataSz & 0x3)) @@ -180,16 +181,16 @@ whal_Error whal_Stm32f4_Flash_Write(whal_Flash *flashDev, size_t addr, return WHAL_EINVAL; /* Wait for any ongoing operation */ - err = whal_Reg_ReadPoll(regmap->base, FLASH_SR_REG, FLASH_SR_BSY_Msk, + err = whal_Reg_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, 0, cfg->timeout); if (err) return err; /* Clear all error flags */ - whal_Reg_Update(regmap->base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); + whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); /* Set programming mode with word-size parallelism */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk | FLASH_CR_PSIZE_Msk, whal_SetBits(FLASH_CR_PG_Msk, FLASH_CR_PG_Pos, 1) | whal_SetBits(FLASH_CR_PSIZE_Msk, FLASH_CR_PSIZE_Pos, FLASH_PSIZE_WORD)); @@ -202,14 +203,14 @@ whal_Error whal_Stm32f4_Flash_Write(whal_Flash *flashDev, size_t addr, *flashAddr = *dataAddr; /* Wait for programming to complete */ - err = whal_Reg_ReadPoll(regmap->base, FLASH_SR_REG, FLASH_SR_BSY_Msk, + err = whal_Reg_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, 0, cfg->timeout); if (err) goto cleanup; /* Check for errors */ - if (whal_Reg_Read(regmap->base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { - whal_Reg_Update(regmap->base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); + if (whal_Reg_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { + whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); err = WHAL_EHARDWARE; goto cleanup; } @@ -217,7 +218,7 @@ whal_Error whal_Stm32f4_Flash_Write(whal_Flash *flashDev, size_t addr, cleanup: /* Disable programming mode */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PG_Msk, 0); + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk, 0); return err; } @@ -226,14 +227,14 @@ whal_Error whal_Stm32f4_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t dataSz) { whal_Stm32f4_Flash_Cfg *cfg; - const whal_Regmap *regmap; + size_t base; whal_Error err = WHAL_SUCCESS; if (!flashDev || !flashDev->cfg) return WHAL_EINVAL; cfg = flashDev->cfg; - regmap = &flashDev->regmap; + base = flashDev->base; if (dataSz == 0) return WHAL_SUCCESS; @@ -242,13 +243,13 @@ whal_Error whal_Stm32f4_Flash_Erase(whal_Flash *flashDev, size_t addr, return WHAL_EINVAL; /* Wait for any ongoing operation */ - err = whal_Reg_ReadPoll(regmap->base, FLASH_SR_REG, FLASH_SR_BSY_Msk, + err = whal_Reg_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, 0, cfg->timeout); if (err) return err; /* Clear all error flags */ - whal_Reg_Update(regmap->base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); + whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); /* Find and erase sectors that overlap with the address range */ for (size_t s = 0; s < cfg->sectorCount; s++) { @@ -260,25 +261,25 @@ whal_Error whal_Stm32f4_Flash_Erase(whal_Flash *flashDev, size_t addr, continue; /* Set sector erase with word parallelism */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_SER_Msk | FLASH_CR_SNB_Msk | FLASH_CR_PSIZE_Msk, whal_SetBits(FLASH_CR_SER_Msk, FLASH_CR_SER_Pos, 1) | whal_SetBits(FLASH_CR_SNB_Msk, FLASH_CR_SNB_Pos, s) | whal_SetBits(FLASH_CR_PSIZE_Msk, FLASH_CR_PSIZE_Pos, FLASH_PSIZE_WORD)); /* Start erase */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_STRT_Msk, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_STRT_Msk, whal_SetBits(FLASH_CR_STRT_Msk, FLASH_CR_STRT_Pos, 1)); /* Wait for erase to complete */ - err = whal_Reg_ReadPoll(regmap->base, FLASH_SR_REG, FLASH_SR_BSY_Msk, + err = whal_Reg_ReadPoll(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, 0, cfg->timeout); if (err) goto cleanup; /* Check for errors */ - if (whal_Reg_Read(regmap->base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { - whal_Reg_Update(regmap->base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); + if (whal_Reg_Read(base, FLASH_SR_REG) & FLASH_SR_ALL_ERR) { + whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, FLASH_SR_ALL_ERR); err = WHAL_EHARDWARE; goto cleanup; } @@ -286,7 +287,7 @@ whal_Error whal_Stm32f4_Flash_Erase(whal_Flash *flashDev, size_t addr, cleanup: /* Clear sector erase mode */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_SER_Msk, 0); + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_SER_Msk, 0); return err; } @@ -297,8 +298,8 @@ whal_Error whal_Stm32f4_Flash_Ext_SetLatency(whal_Flash *flashDev, if (!flashDev) return WHAL_EINVAL; - const whal_Regmap *reg = &flashDev->regmap; - whal_Reg_Update(reg->base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, + size_t base = flashDev->base; + whal_Reg_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, whal_SetBits(FLASH_ACR_LATENCY_Msk, FLASH_ACR_LATENCY_Pos, latency)); return WHAL_SUCCESS; } diff --git a/src/flash/stm32h5_flash.c b/src/flash/stm32h5_flash.c index fe4f84f..6f1da8e 100644 --- a/src/flash/stm32h5_flash.c +++ b/src/flash/stm32h5_flash.c @@ -1,4 +1,5 @@ #include +#include #include #include #include @@ -133,7 +134,7 @@ whal_Error whal_Stm32h5_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32h5_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { - const whal_Regmap *regmap; + size_t base; (void)addr; (void)len; @@ -141,9 +142,9 @@ whal_Error whal_Stm32h5_Flash_Lock(whal_Flash *flashDev, size_t addr, if (!flashDev) return WHAL_EINVAL; - regmap = &flashDev->regmap; + base = flashDev->base; - whal_Reg_Update(regmap->base, FLASH_NSCR_REG, FLASH_NSCR_LOCK_Msk, + whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_LOCK_Msk, whal_SetBits(FLASH_NSCR_LOCK_Msk, FLASH_NSCR_LOCK_Pos, 1)); return WHAL_SUCCESS; @@ -152,7 +153,7 @@ whal_Error whal_Stm32h5_Flash_Lock(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32h5_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { - const whal_Regmap *regmap; + size_t base; (void)addr; (void)len; @@ -160,10 +161,10 @@ whal_Error whal_Stm32h5_Flash_Unlock(whal_Flash *flashDev, size_t addr, if (!flashDev) return WHAL_EINVAL; - regmap = &flashDev->regmap; + base = flashDev->base; - whal_Reg_Write(regmap->base, FLASH_NSKEYR_REG, FLASH_KEY1); - whal_Reg_Write(regmap->base, FLASH_NSKEYR_REG, FLASH_KEY2); + whal_Reg_Write(base, FLASH_NSKEYR_REG, FLASH_KEY1); + whal_Reg_Write(base, FLASH_NSKEYR_REG, FLASH_KEY2); return WHAL_SUCCESS; } @@ -211,14 +212,14 @@ whal_Error whal_Stm32h5_Flash_Write(whal_Flash *flashDev, size_t addr, { const uint8_t *dataBuf = (const uint8_t *)data; whal_Stm32h5_Flash_Cfg *cfg; - const whal_Regmap *regmap; + size_t base; whal_Error err; if (!flashDev || !flashDev->cfg || !data) return WHAL_EINVAL; cfg = flashDev->cfg; - regmap = &flashDev->regmap; + base = flashDev->base; /* Address and size must be 16-byte aligned (128-bit flash-word) */ if ((addr & 0xF) || (dataSz & 0xF)) @@ -228,15 +229,15 @@ whal_Error whal_Stm32h5_Flash_Write(whal_Flash *flashDev, size_t addr, return WHAL_EINVAL; /* Wait for any ongoing operation */ - err = WaitNotBusy(regmap->base, cfg->timeout); + err = WaitNotBusy(base, cfg->timeout); if (err) return err; /* Clear all error and status flags */ - whal_Reg_Write(regmap->base, FLASH_NSCCR_REG, FLASH_NSCCR_CLR_ALL); + whal_Reg_Write(base, FLASH_NSCCR_REG, FLASH_NSCCR_CLR_ALL); /* Enable programming */ - whal_Reg_Update(regmap->base, FLASH_NSCR_REG, FLASH_NSCR_PG_Msk, + whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_PG_Msk, whal_SetBits(FLASH_NSCR_PG_Msk, FLASH_NSCR_PG_Pos, 1)); /* Program data in 128-bit (16 byte) flash-word chunks */ @@ -249,18 +250,18 @@ whal_Error whal_Stm32h5_Flash_Write(whal_Flash *flashDev, size_t addr, flashAddr[2] = dataAddr[2]; flashAddr[3] = dataAddr[3]; - err = WaitNotBusy(regmap->base, cfg->timeout); + err = WaitNotBusy(base, cfg->timeout); if (err) goto cleanup; - err = CheckErrors(regmap->base); + err = CheckErrors(base); if (err) goto cleanup; } cleanup: /* Disable programming */ - whal_Reg_Update(regmap->base, FLASH_NSCR_REG, FLASH_NSCR_PG_Msk, 0); + whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_PG_Msk, 0); return err; } @@ -269,7 +270,7 @@ whal_Error whal_Stm32h5_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t dataSz) { whal_Stm32h5_Flash_Cfg *cfg; - const whal_Regmap *regmap; + size_t base; whal_Error err; size_t offset; size_t startSector, endSector; @@ -278,7 +279,7 @@ whal_Error whal_Stm32h5_Flash_Erase(whal_Flash *flashDev, size_t addr, return WHAL_EINVAL; cfg = flashDev->cfg; - regmap = &flashDev->regmap; + base = flashDev->base; if (dataSz == 0) return WHAL_SUCCESS; @@ -287,12 +288,12 @@ whal_Error whal_Stm32h5_Flash_Erase(whal_Flash *flashDev, size_t addr, return WHAL_EINVAL; /* Wait for any ongoing operation */ - err = WaitNotBusy(regmap->base, cfg->timeout); + err = WaitNotBusy(base, cfg->timeout); if (err) return err; /* Clear all error and status flags */ - whal_Reg_Write(regmap->base, FLASH_NSCCR_REG, FLASH_NSCCR_CLR_ALL); + whal_Reg_Write(base, FLASH_NSCCR_REG, FLASH_NSCCR_CLR_ALL); offset = addr - cfg->startAddr; startSector = offset >> FLASH_SECTOR_SHIFT; @@ -303,7 +304,7 @@ whal_Error whal_Stm32h5_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t sectorInBank = sector - (bank * FLASH_SECTORS_PER_BANK); /* Configure and start sector erase in one write */ - whal_Reg_Update(regmap->base, FLASH_NSCR_REG, + whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_SER_Msk | FLASH_NSCR_SNB_Msk | FLASH_NSCR_BKSEL_Msk | FLASH_NSCR_STRT_Msk, whal_SetBits(FLASH_NSCR_SER_Msk, FLASH_NSCR_SER_Pos, 1) | @@ -313,18 +314,18 @@ whal_Error whal_Stm32h5_Flash_Erase(whal_Flash *flashDev, size_t addr, bank) | whal_SetBits(FLASH_NSCR_STRT_Msk, FLASH_NSCR_STRT_Pos, 1)); - err = WaitNotBusy(regmap->base, cfg->timeout); + err = WaitNotBusy(base, cfg->timeout); if (err) goto cleanup; - err = CheckErrors(regmap->base); + err = CheckErrors(base); if (err) goto cleanup; } cleanup: /* Clear sector erase mode */ - whal_Reg_Update(regmap->base, FLASH_NSCR_REG, FLASH_NSCR_SER_Msk, 0); + whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_SER_Msk, 0); return err; } @@ -337,7 +338,7 @@ whal_Error whal_Stm32h5_Flash_Ext_SetLatency(whal_Flash *flashDev, if (!flashDev) return WHAL_EINVAL; - whal_Reg_Update(flashDev->regmap.base, FLASH_ACR_REG, + whal_Reg_Update(flashDev->base, FLASH_ACR_REG, FLASH_ACR_LATENCY_WRHIGHFREQ_Msk, latency); return WHAL_SUCCESS; diff --git a/src/flash/stm32l1_flash.c b/src/flash/stm32l1_flash.c index 49d7d60..2c14873 100644 --- a/src/flash/stm32l1_flash.c +++ b/src/flash/stm32l1_flash.c @@ -126,7 +126,7 @@ whal_Error whal_Stm32l1_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len return WHAL_EINVAL; /* Set PELOCK to lock everything */ - whal_Reg_Update(flashDev->regmap.base, FLASH_PECR_REG, + whal_Reg_Update(flashDev->base, FLASH_PECR_REG, FLASH_PECR_PELOCK_Msk, whal_SetBits(FLASH_PECR_PELOCK_Msk, FLASH_PECR_PELOCK_Pos, 1)); @@ -142,7 +142,7 @@ whal_Error whal_Stm32l1_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t l if (!flashDev) return WHAL_EINVAL; - size_t base = flashDev->regmap.base; + size_t base = flashDev->base; /* Unlock PECR then program memory */ UnlockPecr(base); @@ -195,7 +195,7 @@ whal_Error whal_Stm32l1_Flash_Write(whal_Flash *flashDev, size_t addr, return WHAL_EINVAL; cfg = flashDev->cfg; - base = flashDev->regmap.base; + base = flashDev->base; if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) return WHAL_EINVAL; @@ -243,7 +243,7 @@ whal_Error whal_Stm32l1_Flash_Erase(whal_Flash *flashDev, size_t addr, return WHAL_SUCCESS; cfg = flashDev->cfg; - base = flashDev->regmap.base; + base = flashDev->base; if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) return WHAL_EINVAL; diff --git a/src/flash/stm32wb_flash.c b/src/flash/stm32wb_flash.c index dec4626..39b0dd5 100644 --- a/src/flash/stm32wb_flash.c +++ b/src/flash/stm32wb_flash.c @@ -1,4 +1,5 @@ #include +#include #include #include #include @@ -118,7 +119,7 @@ whal_Error whal_Stm32wb_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32wb_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { - const whal_Regmap *regmap; + size_t base; (void)addr; (void)len; @@ -127,10 +128,10 @@ whal_Error whal_Stm32wb_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len return WHAL_EINVAL; } - regmap = &flashDev->regmap; + base = flashDev->base; /* Setting LOCK bit prevents further flash modifications until next unlock */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, whal_SetBits(FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, 1)); return WHAL_SUCCESS; @@ -138,7 +139,7 @@ whal_Error whal_Stm32wb_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len whal_Error whal_Stm32wb_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { - const whal_Regmap *regmap; + size_t base; (void)addr; (void)len; @@ -147,14 +148,14 @@ whal_Error whal_Stm32wb_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t l return WHAL_EINVAL; } - regmap = &flashDev->regmap; + base = flashDev->base; /* * Unlock sequence: write KEY1 then KEY2 to KEYR register. * Incorrect sequence or order will trigger a bus error. */ - whal_Reg_Update(regmap->base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0x45670123); - whal_Reg_Update(regmap->base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0xCDEF89AB); + whal_Reg_Update(base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0x45670123); + whal_Reg_Update(base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0xCDEF89AB); return WHAL_SUCCESS; } @@ -194,7 +195,7 @@ static whal_Error whal_Stm32wb_Flash_WriteOrErase(whal_Flash *flashDev, size_t a size_t dataSz, uint8_t write) { whal_Stm32wb_Flash_Cfg *cfg; - const whal_Regmap *regmap; + size_t base; size_t bsy; size_t pesd; @@ -203,7 +204,7 @@ static whal_Error whal_Stm32wb_Flash_WriteOrErase(whal_Flash *flashDev, size_t a } cfg = flashDev->cfg; - regmap = &flashDev->regmap; + base = flashDev->base; if (dataSz == 0) return WHAL_SUCCESS; @@ -214,21 +215,21 @@ static whal_Error whal_Stm32wb_Flash_WriteOrErase(whal_Flash *flashDev, size_t a } /* Check if flash is busy or suspended */ - whal_Reg_Get(regmap->base, FLASH_SR_REG, FLASH_SR_BSY_Msk, FLASH_SR_BSY_Pos, &bsy); - whal_Reg_Get(regmap->base, FLASH_SR_REG, FLASH_SR_PESD_Msk, FLASH_SR_PESD_Pos, &pesd); + whal_Reg_Get(base, FLASH_SR_REG, FLASH_SR_BSY_Msk, FLASH_SR_BSY_Pos, &bsy); + whal_Reg_Get(base, FLASH_SR_REG, FLASH_SR_PESD_Msk, FLASH_SR_PESD_Pos, &pesd); if (bsy || pesd) { return WHAL_ENOTREADY; } /* Clear all error flags by writing 1 to each */ - whal_Reg_Update(regmap->base, FLASH_SR_REG, FLASH_SR_ALL_ERR, 0xffffffff); + whal_Reg_Update(base, FLASH_SR_REG, FLASH_SR_ALL_ERR, 0xffffffff); whal_Error err = WHAL_SUCCESS; if (write) { /* Enable flash programming mode */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PG_Msk, 1); + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk, 1); /* Program data in 64-bit (8 byte) double-word chunks */ for (size_t i = 0; i < dataSz; i += 8) { @@ -240,7 +241,7 @@ static whal_Error whal_Stm32wb_Flash_WriteOrErase(whal_Flash *flashDev, size_t a flashAddr[1] = dataAddr[1]; /* Wait for programming to complete */ - err = whal_Reg_ReadPoll(regmap->base, FLASH_SR_REG, + err = whal_Reg_ReadPoll(base, FLASH_SR_REG, FLASH_SR_CFGBSY_Msk, 0, cfg->timeout); if (err) goto cleanup; @@ -253,34 +254,34 @@ static whal_Error whal_Stm32wb_Flash_WriteOrErase(whal_Flash *flashDev, size_t a endPage = ((addr - cfg->startAddr) + dataSz - 1) >> 12; /* Enable page erase mode */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PER_Msk, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PER_Msk, whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 1)); /* Erase each page in the range */ for (size_t page = startPage; page <= endPage; ++page) { /* Select page number */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PNB_Msk, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PNB_Msk, whal_SetBits(FLASH_CR_PNB_Msk, FLASH_CR_PNB_Pos, page)); /* Start erase operation */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_STRT_Msk, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_STRT_Msk, whal_SetBits(FLASH_CR_STRT_Msk, FLASH_CR_STRT_Pos, 1)); /* Wait for erase to complete */ - err = whal_Reg_ReadPoll(regmap->base, FLASH_SR_REG, + err = whal_Reg_ReadPoll(base, FLASH_SR_REG, FLASH_SR_CFGBSY_Msk, 0, cfg->timeout); if (err) goto cleanup; } /* Disable page erase mode */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PER_Msk, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PER_Msk, whal_SetBits(FLASH_CR_PER_Msk, FLASH_CR_PER_Pos, 0)); } cleanup: /* Disable flash programming mode */ - whal_Reg_Update(regmap->base, FLASH_CR_REG, FLASH_CR_PG_Msk, 0); + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_PG_Msk, 0); return err; } @@ -303,8 +304,8 @@ whal_Error whal_Stm32wb_Flash_Ext_SetLatency(whal_Flash *flashDev, enum whal_Stm return WHAL_EINVAL; } - const whal_Regmap *reg = &flashDev->regmap; - whal_Reg_Update(reg->base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); + size_t base = flashDev->base; + whal_Reg_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); return WHAL_SUCCESS; } diff --git a/src/flash/stm32wba_flash.c b/src/flash/stm32wba_flash.c index 03ad144..c87f410 100644 --- a/src/flash/stm32wba_flash.c +++ b/src/flash/stm32wba_flash.c @@ -1,4 +1,5 @@ #include +#include #include #include #include @@ -91,7 +92,7 @@ whal_Error whal_Stm32wba_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t le if (!flashDev) return WHAL_EINVAL; - whal_Reg_Update(flashDev->regmap.base, FLASH_NSCR1_REG, FLASH_NSCR1_LOCK_Msk, + whal_Reg_Update(flashDev->base, FLASH_NSCR1_REG, FLASH_NSCR1_LOCK_Msk, whal_SetBits(FLASH_NSCR1_LOCK_Msk, FLASH_NSCR1_LOCK_Pos, 1)); return WHAL_SUCCESS; @@ -106,9 +107,9 @@ whal_Error whal_Stm32wba_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t return WHAL_EINVAL; /* Only write the unlock sequence if LOCK bit is set */ - if (whal_Reg_Read(flashDev->regmap.base, FLASH_NSCR1_REG) & FLASH_NSCR1_LOCK_Msk) { - whal_Reg_Write(flashDev->regmap.base, FLASH_NSKEYR_REG, FLASH_KEY1); - whal_Reg_Write(flashDev->regmap.base, FLASH_NSKEYR_REG, FLASH_KEY2); + if (whal_Reg_Read(flashDev->base, FLASH_NSCR1_REG) & FLASH_NSCR1_LOCK_Msk) { + whal_Reg_Write(flashDev->base, FLASH_NSKEYR_REG, FLASH_KEY1); + whal_Reg_Write(flashDev->base, FLASH_NSKEYR_REG, FLASH_KEY2); } return WHAL_SUCCESS; @@ -155,14 +156,14 @@ whal_Error whal_Stm32wba_Flash_Write(whal_Flash *flashDev, size_t addr, { const uint8_t *dataBuf = (const uint8_t *)data; whal_Stm32wba_Flash_Cfg *cfg; - const whal_Regmap *regmap; + size_t base; whal_Error err; if (!flashDev || !flashDev->cfg || !data) return WHAL_EINVAL; cfg = flashDev->cfg; - regmap = &flashDev->regmap; + base = flashDev->base; /* Address and size must be 16-byte aligned (128-bit flash-word) */ if ((addr & 0xF) || (dataSz & 0xF)) @@ -171,16 +172,16 @@ whal_Error whal_Stm32wba_Flash_Write(whal_Flash *flashDev, size_t addr, if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) return WHAL_EINVAL; - err = WaitNotBusy(regmap->base, cfg->timeout); + err = WaitNotBusy(base, cfg->timeout); if (err) return err; /* Clear error flags */ - whal_Reg_Write(regmap->base, FLASH_NSSR_REG, - whal_Reg_Read(regmap->base, FLASH_NSSR_REG) & FLASH_NSSR_ALL_ERR); + whal_Reg_Write(base, FLASH_NSSR_REG, + whal_Reg_Read(base, FLASH_NSSR_REG) & FLASH_NSSR_ALL_ERR); /* Enable programming */ - whal_Reg_Update(regmap->base, FLASH_NSCR1_REG, FLASH_NSCR1_PG_Msk, + whal_Reg_Update(base, FLASH_NSCR1_REG, FLASH_NSCR1_PG_Msk, whal_SetBits(FLASH_NSCR1_PG_Msk, FLASH_NSCR1_PG_Pos, 1)); /* Program in 128-bit (16 byte) flash-word chunks */ @@ -193,24 +194,24 @@ whal_Error whal_Stm32wba_Flash_Write(whal_Flash *flashDev, size_t addr, flashAddr[2] = dataAddr[2]; flashAddr[3] = dataAddr[3]; - err = WaitNotBusy(regmap->base, cfg->timeout); + err = WaitNotBusy(base, cfg->timeout); if (err) goto cleanup; - err = CheckAndClearErrors(regmap->base); + err = CheckAndClearErrors(base); if (err) goto cleanup; } cleanup: - whal_Reg_Update(regmap->base, FLASH_NSCR1_REG, FLASH_NSCR1_PG_Msk, 0); + whal_Reg_Update(base, FLASH_NSCR1_REG, FLASH_NSCR1_PG_Msk, 0); return err; } whal_Error whal_Stm32wba_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t dataSz) { whal_Stm32wba_Flash_Cfg *cfg; - const whal_Regmap *regmap; + size_t base; whal_Error err; size_t offset, startPage, endPage; @@ -218,7 +219,7 @@ whal_Error whal_Stm32wba_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t d return WHAL_EINVAL; cfg = flashDev->cfg; - regmap = &flashDev->regmap; + base = flashDev->base; if (dataSz == 0) return WHAL_SUCCESS; @@ -226,13 +227,13 @@ whal_Error whal_Stm32wba_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t d if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) return WHAL_EINVAL; - err = WaitNotBusy(regmap->base, cfg->timeout); + err = WaitNotBusy(base, cfg->timeout); if (err) return err; /* Clear error flags */ - whal_Reg_Write(regmap->base, FLASH_NSSR_REG, - whal_Reg_Read(regmap->base, FLASH_NSSR_REG) & FLASH_NSSR_ALL_ERR); + whal_Reg_Write(base, FLASH_NSSR_REG, + whal_Reg_Read(base, FLASH_NSSR_REG) & FLASH_NSSR_ALL_ERR); offset = addr - cfg->startAddr; startPage = offset >> FLASH_SECTOR_SHIFT; @@ -240,23 +241,23 @@ whal_Error whal_Stm32wba_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t d for (size_t page = startPage; page <= endPage; page++) { /* Configure page erase: PER=1, PNB=page, STRT=1 */ - whal_Reg_Update(regmap->base, FLASH_NSCR1_REG, + whal_Reg_Update(base, FLASH_NSCR1_REG, FLASH_NSCR1_PER_Msk | FLASH_NSCR1_PNB_Msk | FLASH_NSCR1_STRT_Msk, whal_SetBits(FLASH_NSCR1_PER_Msk, FLASH_NSCR1_PER_Pos, 1) | whal_SetBits(FLASH_NSCR1_PNB_Msk, FLASH_NSCR1_PNB_Pos, page) | whal_SetBits(FLASH_NSCR1_STRT_Msk, FLASH_NSCR1_STRT_Pos, 1)); - err = WaitNotBusy(regmap->base, cfg->timeout); + err = WaitNotBusy(base, cfg->timeout); if (err) goto cleanup; - err = CheckAndClearErrors(regmap->base); + err = CheckAndClearErrors(base); if (err) goto cleanup; } cleanup: - whal_Reg_Update(regmap->base, FLASH_NSCR1_REG, FLASH_NSCR1_PER_Msk, 0); + whal_Reg_Update(base, FLASH_NSCR1_REG, FLASH_NSCR1_PER_Msk, 0); return err; } @@ -265,7 +266,7 @@ whal_Error whal_Stm32wba_Flash_Ext_SetLatency(whal_Flash *flashDev, uint8_t late if (!flashDev) return WHAL_EINVAL; - whal_Reg_Update(flashDev->regmap.base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); + whal_Reg_Update(flashDev->base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); return WHAL_SUCCESS; } diff --git a/src/gpio/pic32cz_gpio.c b/src/gpio/pic32cz_gpio.c index 969c81a..c52d07c 100644 --- a/src/gpio/pic32cz_gpio.c +++ b/src/gpio/pic32cz_gpio.c @@ -1,4 +1,5 @@ #include +#include #include #include @@ -81,12 +82,12 @@ whal_Error whal_Pic32cz_Gpio_Init(whal_Gpio *gpioDev) size_t pmuxenMask = PINCFGx_PMUXEN_Msk(pinCfg->pin); size_t pmuxenPos = PINCFGx_PMUXEN_Pos(pinCfg->pin); - whal_Reg_Update(gpioDev->regmap.base, + whal_Reg_Update(gpioDev->base, PMUXx_REG(pinCfg->port, pinCfg->pin), pmuxMask, whal_SetBits(pmuxMask, pmuxPos, pinCfg->pmux)); - whal_Reg_Update(gpioDev->regmap.base, + whal_Reg_Update(gpioDev->base, PINCFGx_REG(pinCfg->port, pinCfg->pin), pmuxenMask, whal_SetBits(pmuxenMask, pmuxenPos, 1)); @@ -102,12 +103,12 @@ whal_Error whal_Pic32cz_Gpio_Init(whal_Gpio *gpioDev) */ /* Set pin direction */ - whal_Reg_Update(gpioDev->regmap.base, DIR_REG(pinCfg->port), + whal_Reg_Update(gpioDev->base, DIR_REG(pinCfg->port), pinMask, whal_SetBits(pinMask, pinCfg->pin, pinCfg->dir)); /* Set initial output value */ - whal_Reg_Update(gpioDev->regmap.base, OUT_REG(pinCfg->port), + whal_Reg_Update(gpioDev->base, OUT_REG(pinCfg->port), pinMask, whal_SetBits(pinMask, pinCfg->pin, pinCfg->out)); @@ -118,7 +119,7 @@ whal_Error whal_Pic32cz_Gpio_Init(whal_Gpio *gpioDev) size_t pullenMask = PINCFGx_PULLEN_Msk(pinCfg->pin); size_t pullenPos = PINCFGx_PULLEN_Pos(pinCfg->pin); - whal_Reg_Update(gpioDev->regmap.base, + whal_Reg_Update(gpioDev->base, PINCFGx_REG(pinCfg->port, pinCfg->pin), inenMask | pullenMask, whal_SetBits(inenMask, inenPos, pinCfg->inEn) | @@ -166,7 +167,7 @@ whal_Error whal_Pic32cz_Gpio_Get(whal_Gpio *gpioDev, size_t pin, size_t *value) reg = IN_REG(pinCfg->port); } - whal_Reg_Get(gpioDev->regmap.base, reg, pinMask, pinCfg->pin, value); + whal_Reg_Get(gpioDev->base, reg, pinMask, pinCfg->pin, value); return WHAL_SUCCESS; } @@ -187,7 +188,7 @@ whal_Error whal_Pic32cz_Gpio_Set(whal_Gpio *gpioDev, size_t pin, size_t value) size_t pinMask = (1UL << (pinCfg->pin)); /* Update the output register to drive the new value */ - whal_Reg_Update(gpioDev->regmap.base, OUT_REG(pinCfg->port), + whal_Reg_Update(gpioDev->base, OUT_REG(pinCfg->port), pinMask, whal_SetBits(pinMask, pinCfg->pin, value)); diff --git a/src/gpio/stm32wb_gpio.c b/src/gpio/stm32wb_gpio.c index 2916f97..5080f61 100644 --- a/src/gpio/stm32wb_gpio.c +++ b/src/gpio/stm32wb_gpio.c @@ -67,7 +67,7 @@ static inline whal_Error whal_Stm32wb_Gpio_InitPin(whal_Gpio *gpioDev, if (pin > 15) return WHAL_EINVAL; - portBase = gpioDev->regmap.base + + portBase = gpioDev->base + (WHAL_STM32WB_GPIO_GET_PORT(cfg) * GPIO_PORT_SIZE); pos2 = pin << 1; mask2 = WHAL_BITMASK(2) << pos2; @@ -157,7 +157,7 @@ static whal_Error whal_Stm32wb_Gpio_SetOrGet(whal_Gpio *gpioDev, size_t idx, return WHAL_EINVAL; } - portBase = gpioDev->regmap.base + (port * GPIO_PORT_SIZE); + portBase = gpioDev->base + (port * GPIO_PORT_SIZE); mask = 1UL << pin; if (set) { diff --git a/src/i2c/stm32l1_i2c.c b/src/i2c/stm32l1_i2c.c index 1f9913d..53d1fe3 100644 --- a/src/i2c/stm32l1_i2c.c +++ b/src/i2c/stm32l1_i2c.c @@ -293,7 +293,7 @@ whal_Error whal_Stm32l1_I2c_Init(whal_I2c *i2cDev) if (!i2cDev || !i2cDev->cfg) return WHAL_EINVAL; - base = i2cDev->regmap.base; + base = i2cDev->base; whal_Reg_Update(base, I2C_CR1, CR1_PE_Msk, 0); whal_Reg_Update(base, I2C_CR1, CR1_SWRST_Msk, CR1_SWRST_Msk); @@ -308,7 +308,7 @@ whal_Error whal_Stm32l1_I2c_Deinit(whal_I2c *i2cDev) if (!i2cDev || !i2cDev->cfg) return WHAL_EINVAL; - whal_Reg_Update(i2cDev->regmap.base, I2C_CR1, CR1_PE_Msk, 0); + whal_Reg_Update(i2cDev->base, I2C_CR1, CR1_PE_Msk, 0); return WHAL_SUCCESS; } @@ -326,7 +326,7 @@ whal_Error whal_Stm32l1_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) return WHAL_EINVAL; cfg = (whal_Stm32l1_I2c_Cfg *)i2cDev->cfg; - base = i2cDev->regmap.base; + base = i2cDev->base; whal_Reg_Update(base, I2C_CR1, CR1_PE_Msk, 0); @@ -371,7 +371,7 @@ whal_Error whal_Stm32l1_I2c_Transfer(whal_I2c *i2cDev, whal_I2c_Msg *msgs, return WHAL_EINVAL; cfg = (whal_Stm32l1_I2c_Cfg *)i2cDev->cfg; - base = i2cDev->regmap.base; + base = i2cDev->base; for (size_t i = 0; i < numMsgs; i++) { uint8_t isRead = (msgs[i].flags & WHAL_I2C_MSG_READ) ? 1 : 0; diff --git a/src/i2c/stm32wb_i2c.c b/src/i2c/stm32wb_i2c.c index f6692b6..23fbae1 100644 --- a/src/i2c/stm32wb_i2c.c +++ b/src/i2c/stm32wb_i2c.c @@ -371,26 +371,26 @@ static whal_Error Stm32wb_I2c_TransferMsg(size_t base, whal_I2c_Msg *msg, whal_Error whal_Stm32wb_I2c_Init(whal_I2c *i2cDev) { - const whal_Regmap *reg; + size_t base; if (!i2cDev || !i2cDev->cfg) { return WHAL_EINVAL; } - reg = &i2cDev->regmap; + base = i2cDev->base; /* Disable PE before configuring */ - whal_Reg_Update(reg->base, I2C_CR1_REG, I2C_CR1_PE_Msk, + whal_Reg_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, whal_SetBits(I2C_CR1_PE_Msk, I2C_CR1_PE_Pos, 0)); /* Enable analog noise filter (ANFOFF=0), disable digital filter (DNF=0) */ - whal_Reg_Update(reg->base, I2C_CR1_REG, + whal_Reg_Update(base, I2C_CR1_REG, I2C_CR1_ANFOFF_Msk | I2C_CR1_DNF_Msk, whal_SetBits(I2C_CR1_ANFOFF_Msk, I2C_CR1_ANFOFF_Pos, 0) | whal_SetBits(I2C_CR1_DNF_Msk, I2C_CR1_DNF_Pos, 0)); /* Enable peripheral */ - whal_Reg_Update(reg->base, I2C_CR1_REG, I2C_CR1_PE_Msk, + whal_Reg_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, whal_SetBits(I2C_CR1_PE_Msk, I2C_CR1_PE_Pos, 1)); return WHAL_SUCCESS; @@ -398,16 +398,16 @@ whal_Error whal_Stm32wb_I2c_Init(whal_I2c *i2cDev) whal_Error whal_Stm32wb_I2c_Deinit(whal_I2c *i2cDev) { - const whal_Regmap *reg; + size_t base; if (!i2cDev || !i2cDev->cfg) { return WHAL_EINVAL; } - reg = &i2cDev->regmap; + base = i2cDev->base; /* Disable peripheral */ - whal_Reg_Update(reg->base, I2C_CR1_REG, I2C_CR1_PE_Msk, + whal_Reg_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, whal_SetBits(I2C_CR1_PE_Msk, I2C_CR1_PE_Pos, 0)); return WHAL_SUCCESS; @@ -415,7 +415,7 @@ whal_Error whal_Stm32wb_I2c_Deinit(whal_I2c *i2cDev) whal_Error whal_Stm32wb_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) { - const whal_Regmap *reg; + size_t base; whal_Stm32wb_I2c_Cfg *cfg; uint32_t cr2 = 0; @@ -427,19 +427,19 @@ whal_Error whal_Stm32wb_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) return WHAL_EINVAL; } - reg = &i2cDev->regmap; + base = i2cDev->base; cfg = (whal_Stm32wb_I2c_Cfg *)i2cDev->cfg; /* Disable PE to configure timing */ - whal_Reg_Update(reg->base, I2C_CR1_REG, I2C_CR1_PE_Msk, + whal_Reg_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, whal_SetBits(I2C_CR1_PE_Msk, I2C_CR1_PE_Pos, 0)); /* Compute and write timing register */ - whal_Reg_Write(reg->base, I2C_TIMINGR_REG, + whal_Reg_Write(base, I2C_TIMINGR_REG, Stm32wb_I2c_CalcTimingr(cfg->pclk, comCfg->freq)); /* Re-enable PE */ - whal_Reg_Update(reg->base, I2C_CR1_REG, I2C_CR1_PE_Msk, + whal_Reg_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, whal_SetBits(I2C_CR1_PE_Msk, I2C_CR1_PE_Pos, 1)); /* Configure target address and addressing mode in CR2 */ @@ -452,7 +452,7 @@ whal_Error whal_Stm32wb_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) (uint32_t)comCfg->addr << 1); } - whal_Reg_Update(reg->base, I2C_CR2_REG, + whal_Reg_Update(base, I2C_CR2_REG, I2C_CR2_SADD_Msk | I2C_CR2_ADD10_Msk, cr2); return WHAL_SUCCESS; @@ -460,16 +460,16 @@ whal_Error whal_Stm32wb_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) whal_Error whal_Stm32wb_I2c_EndCom(whal_I2c *i2cDev) { - const whal_Regmap *reg; + size_t base; if (!i2cDev || !i2cDev->cfg) { return WHAL_EINVAL; } - reg = &i2cDev->regmap; + base = i2cDev->base; /* Clear target address and addressing mode */ - whal_Reg_Update(reg->base, I2C_CR2_REG, + whal_Reg_Update(base, I2C_CR2_REG, I2C_CR2_SADD_Msk | I2C_CR2_ADD10_Msk, 0); return WHAL_SUCCESS; @@ -478,7 +478,7 @@ whal_Error whal_Stm32wb_I2c_EndCom(whal_I2c *i2cDev) whal_Error whal_Stm32wb_I2c_Transfer(whal_I2c *i2cDev, whal_I2c_Msg *msgs, size_t numMsgs) { - const whal_Regmap *reg; + size_t base; whal_Stm32wb_I2c_Cfg *cfg; whal_Error err; @@ -486,7 +486,7 @@ whal_Error whal_Stm32wb_I2c_Transfer(whal_I2c *i2cDev, whal_I2c_Msg *msgs, return WHAL_EINVAL; } - reg = &i2cDev->regmap; + base = i2cDev->base; cfg = (whal_Stm32wb_I2c_Cfg *)i2cDev->cfg; for (size_t i = 0; i < numMsgs; i++) { @@ -502,7 +502,7 @@ whal_Error whal_Stm32wb_I2c_Transfer(whal_I2c *i2cDev, whal_I2c_Msg *msgs, reloadLast = 1; } - err = Stm32wb_I2c_TransferMsg(reg->base, &msgs[i], reloadLast, + err = Stm32wb_I2c_TransferMsg(base, &msgs[i], reloadLast, cfg->timeout); if (err) return err; diff --git a/src/irq/cortex_m4_nvic.c b/src/irq/cortex_m4_nvic.c index 3fbdfe8..5d7b437 100644 --- a/src/irq/cortex_m4_nvic.c +++ b/src/irq/cortex_m4_nvic.c @@ -46,7 +46,7 @@ whal_Error whal_Nvic_Enable(whal_Irq *irqDev, size_t irq, return WHAL_EINVAL; } - size_t base = irqDev->regmap.base; + size_t base = irqDev->base; /* Set priority if config provided */ if (irqCfg) { @@ -69,7 +69,7 @@ whal_Error whal_Nvic_Disable(whal_Irq *irqDev, size_t irq) return WHAL_EINVAL; } - size_t base = irqDev->regmap.base; + size_t base = irqDev->base; whal_Reg_Write(base, NVIC_ICER_REG(irq), (1UL << (irq & 0x1F))); diff --git a/src/power/pic32cz_supc.c b/src/power/pic32cz_supc.c index 3d5a176..aa2880a 100644 --- a/src/power/pic32cz_supc.c +++ b/src/power/pic32cz_supc.c @@ -13,7 +13,7 @@ whal_Error whal_Pic32cz_Supc_EnableSupply(whal_Power *powerDev, if (!powerDev || !supply) return WHAL_EINVAL; - whal_Reg_Update(powerDev->regmap.base, VREGCTRL_REG, supply->enableMask, + whal_Reg_Update(powerDev->base, VREGCTRL_REG, supply->enableMask, whal_SetBits(supply->enableMask, supply->enablePos, 1)); return WHAL_SUCCESS; } @@ -24,7 +24,7 @@ whal_Error whal_Pic32cz_Supc_DisableSupply(whal_Power *powerDev, if (!powerDev || !supply) return WHAL_EINVAL; - whal_Reg_Update(powerDev->regmap.base, VREGCTRL_REG, supply->enableMask, + whal_Reg_Update(powerDev->base, VREGCTRL_REG, supply->enableMask, whal_SetBits(supply->enableMask, supply->enablePos, 0)); return WHAL_SUCCESS; } diff --git a/src/power/stm32l1_pwr.c b/src/power/stm32l1_pwr.c index 56befb1..607d08f 100644 --- a/src/power/stm32l1_pwr.c +++ b/src/power/stm32l1_pwr.c @@ -20,7 +20,7 @@ whal_Error whal_Stm32l1_Pwr_SetVosRange(whal_Power *powerDev, if (!powerDev) return WHAL_EINVAL; - base = powerDev->regmap.base; + base = powerDev->base; err = whal_Reg_ReadPoll(base, PWR_CSR_REG, PWR_CSR_VOSF_Msk, 0, timeout); if (err) diff --git a/src/rng/stm32h5_rng.c b/src/rng/stm32h5_rng.c index 7426ab4..8b487c6 100644 --- a/src/rng/stm32h5_rng.c +++ b/src/rng/stm32h5_rng.c @@ -64,14 +64,14 @@ whal_Error whal_Stm32h5_Rng_Init(whal_Rng *rngDev) { whal_Stm32h5_Rng_Cfg *cfg; - const whal_Regmap *reg; + size_t base; whal_Error err; if (!rngDev || !rngDev->cfg) return WHAL_EINVAL; cfg = (whal_Stm32h5_Rng_Cfg *)rngDev->cfg; - reg = &rngDev->regmap; + base = rngDev->base; /* * Apply NIST-certified configuration via CONDRST sequence: @@ -80,18 +80,18 @@ whal_Error whal_Stm32h5_Rng_Init(whal_Rng *rngDev) * 3. Write NSCR value (while CONDRST=1) * 4. Write CONDRST=0 with RNGEN=1 to start */ - whal_Reg_Write(reg->base, RNG_CR_REG, + whal_Reg_Write(base, RNG_CR_REG, RNG_CR_NIST_CFG | RNG_CR_CONDRST_Msk); - whal_Reg_Write(reg->base, RNG_HTCR_REG, RNG_HTCR_MAGIC); - whal_Reg_Write(reg->base, RNG_HTCR_REG, RNG_HTCR_NIST_VAL); - whal_Reg_Write(reg->base, RNG_NSCR_REG, RNG_NSCR_NIST_VAL); + whal_Reg_Write(base, RNG_HTCR_REG, RNG_HTCR_MAGIC); + whal_Reg_Write(base, RNG_HTCR_REG, RNG_HTCR_NIST_VAL); + whal_Reg_Write(base, RNG_NSCR_REG, RNG_NSCR_NIST_VAL); - whal_Reg_Write(reg->base, RNG_CR_REG, + whal_Reg_Write(base, RNG_CR_REG, RNG_CR_NIST_CFG | RNG_CR_RNGEN_Msk); /* Wait for CONDRST to clear (reset complete) */ - err = whal_Reg_ReadPoll(reg->base, RNG_CR_REG, + err = whal_Reg_ReadPoll(base, RNG_CR_REG, RNG_CR_CONDRST_Msk, 0, cfg->timeout); return err; @@ -103,7 +103,7 @@ whal_Error whal_Stm32h5_Rng_Deinit(whal_Rng *rngDev) return WHAL_EINVAL; /* Disable the RNG peripheral */ - whal_Reg_Update(rngDev->regmap.base, RNG_CR_REG, RNG_CR_RNGEN_Msk, + whal_Reg_Update(rngDev->base, RNG_CR_REG, RNG_CR_RNGEN_Msk, whal_SetBits(RNG_CR_RNGEN_Msk, RNG_CR_RNGEN_Pos, 0)); return WHAL_SUCCESS; @@ -115,7 +115,7 @@ whal_Error whal_Stm32h5_Rng_Generate(whal_Rng *rngDev, void *rngData, uint8_t *rngBuf = (uint8_t *)rngData; whal_Error err = WHAL_SUCCESS; whal_Stm32h5_Rng_Cfg *cfg; - const whal_Regmap *reg; + size_t base; size_t sr; size_t offset = 0; @@ -123,7 +123,7 @@ whal_Error whal_Stm32h5_Rng_Generate(whal_Rng *rngDev, void *rngData, return WHAL_EINVAL; cfg = (whal_Stm32h5_Rng_Cfg *)rngDev->cfg; - reg = &rngDev->regmap; + base = rngDev->base; #ifdef WHAL_CFG_NO_TIMEOUT (void)(cfg); #endif @@ -137,7 +137,7 @@ whal_Error whal_Stm32h5_Rng_Generate(whal_Rng *rngDev, void *rngData, goto exit; } - sr = whal_Reg_Read(reg->base, RNG_SR_REG); + sr = whal_Reg_Read(base, RNG_SR_REG); if (sr & RNG_SR_SECS_Msk) { err = WHAL_EHARDWARE; @@ -153,7 +153,7 @@ whal_Error whal_Stm32h5_Rng_Generate(whal_Rng *rngDev, void *rngData, } /* Read 32-bit random value */ - uint32_t rnd = (uint32_t)whal_Reg_Read(reg->base, RNG_DR_REG); + uint32_t rnd = (uint32_t)whal_Reg_Read(base, RNG_DR_REG); /* Copy bytes into output buffer */ for (size_t i = 0; i < 4 && offset < rngDataSz; i++, offset++) diff --git a/src/rng/stm32wb_rng.c b/src/rng/stm32wb_rng.c index 55fecee..c9fa014 100644 --- a/src/rng/stm32wb_rng.c +++ b/src/rng/stm32wb_rng.c @@ -70,7 +70,7 @@ whal_Error whal_Stm32wb_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rng uint8_t *rngBuf = (uint8_t *)rngData; whal_Error err = WHAL_SUCCESS; whal_Stm32wb_Rng_Cfg *cfg; - const whal_Regmap *reg; + size_t base; size_t sr; size_t offset = 0; @@ -79,13 +79,13 @@ whal_Error whal_Stm32wb_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rng } cfg = (whal_Stm32wb_Rng_Cfg *)rngDev->cfg; - reg = &rngDev->regmap; + base = rngDev->base; #ifdef WHAL_CFG_NO_TIMEOUT (void)(cfg); #endif /* Enable the RNG peripheral */ - whal_Reg_Update(reg->base, RNG_CR_REG, RNG_CR_RNGEN_Msk, + whal_Reg_Update(base, RNG_CR_REG, RNG_CR_RNGEN_Msk, whal_SetBits(RNG_CR_RNGEN_Msk, RNG_CR_RNGEN_Pos, 1)); while (offset < rngDataSz) { @@ -97,7 +97,7 @@ whal_Error whal_Stm32wb_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rng goto exit; } - sr = whal_Reg_Read(reg->base, RNG_SR_REG); + sr = whal_Reg_Read(base, RNG_SR_REG); /* Check for seed or clock error */ if (sr & RNG_SR_SECS_Msk) { @@ -114,7 +114,7 @@ whal_Error whal_Stm32wb_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rng } /* Read 32-bit random value */ - uint32_t rnd = *(volatile uint32_t *)(reg->base + RNG_DR_REG); + uint32_t rnd = *(volatile uint32_t *)(base + RNG_DR_REG); /* Copy bytes into output buffer */ for (size_t i = 0; i < 4 && offset < rngDataSz; i++, offset++) { @@ -124,7 +124,7 @@ whal_Error whal_Stm32wb_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rng exit: /* Disable the RNG peripheral */ - whal_Reg_Update(reg->base, RNG_CR_REG, RNG_CR_RNGEN_Msk, + whal_Reg_Update(base, RNG_CR_REG, RNG_CR_RNGEN_Msk, whal_SetBits(RNG_CR_RNGEN_Msk, RNG_CR_RNGEN_Pos, 0)); return err; diff --git a/src/rng/stm32wba_rng.c b/src/rng/stm32wba_rng.c index aaefcc2..e410080 100644 --- a/src/rng/stm32wba_rng.c +++ b/src/rng/stm32wba_rng.c @@ -68,24 +68,24 @@ whal_Error whal_Stm32wba_Rng_Init(whal_Rng *rngDev) { const whal_Stm32wba_Rng_Cfg *cfg; - const whal_Regmap *reg; + size_t base; if (!rngDev || !rngDev->cfg) return WHAL_EINVAL; cfg = (const whal_Stm32wba_Rng_Cfg *)rngDev->cfg; - reg = &rngDev->regmap; + base = rngDev->base; /* Apply Configuration C with CONDRST=1 and RNGEN=1 */ - whal_Reg_Write(reg->base, RNG_CR_REG, + whal_Reg_Write(base, RNG_CR_REG, RNG_CR_CONDRST_Msk | RNG_CR_CONFIG_C | RNG_CR_RNGEN_Msk); /* Clear CONDRST to start conditioning */ - whal_Reg_Write(reg->base, RNG_CR_REG, + whal_Reg_Write(base, RNG_CR_REG, RNG_CR_CONFIG_C | RNG_CR_RNGEN_Msk); /* Wait for CONDRST to self-clear */ - return whal_Reg_ReadPoll(reg->base, RNG_CR_REG, RNG_CR_CONDRST_Msk, 0, + return whal_Reg_ReadPoll(base, RNG_CR_REG, RNG_CR_CONDRST_Msk, 0, cfg->timeout); } @@ -95,7 +95,7 @@ whal_Error whal_Stm32wba_Rng_Deinit(whal_Rng *rngDev) return WHAL_EINVAL; /* Disable RNG */ - whal_Reg_Update(rngDev->regmap.base, RNG_CR_REG, RNG_CR_RNGEN_Msk, 0); + whal_Reg_Update(rngDev->base, RNG_CR_REG, RNG_CR_RNGEN_Msk, 0); return WHAL_SUCCESS; } @@ -105,7 +105,7 @@ whal_Error whal_Stm32wba_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rn uint8_t *rngBuf = (uint8_t *)rngData; whal_Error err = WHAL_SUCCESS; whal_Stm32wba_Rng_Cfg *cfg; - const whal_Regmap *reg; + size_t base; size_t sr; size_t offset = 0; @@ -113,7 +113,7 @@ whal_Error whal_Stm32wba_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rn return WHAL_EINVAL; cfg = (whal_Stm32wba_Rng_Cfg *)rngDev->cfg; - reg = &rngDev->regmap; + base = rngDev->base; #ifdef WHAL_CFG_NO_TIMEOUT (void)(cfg); #endif @@ -126,7 +126,7 @@ whal_Error whal_Stm32wba_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rn goto exit; } - sr = whal_Reg_Read(reg->base, RNG_SR_REG); + sr = whal_Reg_Read(base, RNG_SR_REG); if (sr & RNG_SR_SECS_Msk) { err = WHAL_EHARDWARE; @@ -141,7 +141,7 @@ whal_Error whal_Stm32wba_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rn break; } - uint32_t rnd = *(volatile uint32_t *)(reg->base + RNG_DR_REG); + uint32_t rnd = *(volatile uint32_t *)(base + RNG_DR_REG); for (size_t i = 0; i < 4 && offset < rngDataSz; i++, offset++) rngBuf[offset] = (uint8_t)(rnd >> (i * 8)); diff --git a/src/spi/stm32f4_spi.c b/src/spi/stm32f4_spi.c index dd56ddf..d651ee1 100644 --- a/src/spi/stm32f4_spi.c +++ b/src/spi/stm32f4_spi.c @@ -87,15 +87,15 @@ static uint32_t whal_Stm32f4_Spi_CalcBr(size_t pclk, uint32_t targetBaud) whal_Error whal_Stm32f4_Spi_Init(whal_Spi *spiDev) { - const whal_Regmap *reg; + size_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; - reg = &spiDev->regmap; + base = spiDev->base; /* Master mode with software slave management */ - whal_Reg_Update(reg->base, SPI_CR1_REG, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_MSTR_Msk | SPI_CR1_SSM_Msk | SPI_CR1_SSI_Msk, whal_SetBits(SPI_CR1_MSTR_Msk, SPI_CR1_MSTR_Pos, 1) | whal_SetBits(SPI_CR1_SSM_Msk, SPI_CR1_SSM_Pos, 1) | @@ -106,15 +106,15 @@ whal_Error whal_Stm32f4_Spi_Init(whal_Spi *spiDev) whal_Error whal_Stm32f4_Spi_Deinit(whal_Spi *spiDev) { - const whal_Regmap *reg; + size_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; - reg = &spiDev->regmap; + base = spiDev->base; /* Disable SPI */ - whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); return WHAL_SUCCESS; @@ -122,7 +122,7 @@ whal_Error whal_Stm32f4_Spi_Deinit(whal_Spi *spiDev) whal_Error whal_Stm32f4_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) { - const whal_Regmap *reg; + size_t base; whal_Stm32f4_Spi_Cfg *cfg; uint32_t cpol, cpha, br; @@ -136,7 +136,7 @@ whal_Error whal_Stm32f4_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) if (comCfg->mode > 3 || comCfg->dataLines != 1 || comCfg->freq == 0) return WHAL_EINVAL; - reg = &spiDev->regmap; + base = spiDev->base; cfg = (whal_Stm32f4_Spi_Cfg *)spiDev->cfg; br = whal_Stm32f4_Spi_CalcBr(cfg->pclk, comCfg->freq); @@ -145,18 +145,18 @@ whal_Error whal_Stm32f4_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) cpha = comCfg->mode & 1; /* Disable SPE before reconfiguring */ - whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); /* Set mode and baud rate (DFF=0 for 8-bit) */ - whal_Reg_Update(reg->base, SPI_CR1_REG, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_CPOL_Msk | SPI_CR1_CPHA_Msk | SPI_CR1_BR_Msk | SPI_CR1_DFF_Msk, whal_SetBits(SPI_CR1_CPOL_Msk, SPI_CR1_CPOL_Pos, cpol) | whal_SetBits(SPI_CR1_CPHA_Msk, SPI_CR1_CPHA_Pos, cpha) | whal_SetBits(SPI_CR1_BR_Msk, SPI_CR1_BR_Pos, br)); /* Enable SPE */ - whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 1)); return WHAL_SUCCESS; @@ -164,15 +164,15 @@ whal_Error whal_Stm32f4_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) whal_Error whal_Stm32f4_Spi_EndCom(whal_Spi *spiDev) { - const whal_Regmap *reg; + size_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; - reg = &spiDev->regmap; + base = spiDev->base; /* Disable SPE */ - whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); return WHAL_SUCCESS; @@ -184,7 +184,7 @@ whal_Error whal_Stm32f4_Spi_SendRecv(whal_Spi *spiDev, { const uint8_t *txBuf = (const uint8_t *)tx; uint8_t *rxBuf = (uint8_t *)rx; - const whal_Regmap *reg; + size_t base; whal_Stm32f4_Spi_Cfg *cfg; size_t totalLen; whal_Error err; @@ -193,13 +193,13 @@ whal_Error whal_Stm32f4_Spi_SendRecv(whal_Spi *spiDev, if (!spiDev || !spiDev->cfg || (!tx && txLen) || (!rx && rxLen)) return WHAL_EINVAL; - reg = &spiDev->regmap; + base = spiDev->base; cfg = (whal_Stm32f4_Spi_Cfg *)spiDev->cfg; totalLen = txLen > rxLen ? txLen : rxLen; for (size_t i = 0; i < totalLen; i++) { /* Wait for TX buffer empty */ - err = whal_Reg_ReadPoll(reg->base, SPI_SR_REG, + err = whal_Reg_ReadPoll(base, SPI_SR_REG, SPI_SR_TXE_Msk, SPI_SR_TXE_Msk, cfg->timeout); if (err) @@ -207,10 +207,10 @@ whal_Error whal_Stm32f4_Spi_SendRecv(whal_Spi *spiDev, /* Write TX data, pad with 0xFF when tx is exhausted or NULL */ txByte = (txBuf && i < txLen) ? txBuf[i] : 0xFF; - *(volatile uint8_t *)(reg->base + SPI_DR_REG) = txByte; + *(volatile uint8_t *)(base + SPI_DR_REG) = txByte; /* Wait for RX byte */ - err = whal_Reg_ReadPoll(reg->base, SPI_SR_REG, + err = whal_Reg_ReadPoll(base, SPI_SR_REG, SPI_SR_RXNE_Msk, SPI_SR_RXNE_Msk, cfg->timeout); if (err) @@ -218,13 +218,13 @@ whal_Error whal_Stm32f4_Spi_SendRecv(whal_Spi *spiDev, /* Store or discard received byte */ if (rxBuf && i < rxLen) - rxBuf[i] = *(volatile uint8_t *)(reg->base + SPI_DR_REG); + rxBuf[i] = *(volatile uint8_t *)(base + SPI_DR_REG); else - (void)*(volatile uint8_t *)(reg->base + SPI_DR_REG); + (void)*(volatile uint8_t *)(base + SPI_DR_REG); } /* Wait for not busy */ - return whal_Reg_ReadPoll(reg->base, SPI_SR_REG, SPI_SR_BSY_Msk, 0, + return whal_Reg_ReadPoll(base, SPI_SR_REG, SPI_SR_BSY_Msk, 0, cfg->timeout); } diff --git a/src/spi/stm32h5_spi.c b/src/spi/stm32h5_spi.c index 23f4b73..d674bf2 100644 --- a/src/spi/stm32h5_spi.c +++ b/src/spi/stm32h5_spi.c @@ -117,22 +117,22 @@ static uint32_t Stm32h5_Spi_CalcMbr(size_t pclk, uint32_t targetBaud) whal_Error whal_Stm32h5_Spi_Init(whal_Spi *spiDev) { - const whal_Regmap *reg; + size_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; - reg = &spiDev->regmap; + base = spiDev->base; /* Disable SPI before configuring */ - whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); - whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SSI_Msk, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SSI_Msk, whal_SetBits(SPI_CR1_SSI_Msk, SPI_CR1_SSI_Pos, 1)); /* Master mode, software slave management, SSI high */ - whal_Reg_Update(reg->base, SPI_CFG2_REG, + whal_Reg_Update(base, SPI_CFG2_REG, SPI_CFG2_MASTER_Msk | SPI_CFG2_SSM_Msk, whal_SetBits(SPI_CFG2_MASTER_Msk, SPI_CFG2_MASTER_Pos, 1) | whal_SetBits(SPI_CFG2_SSM_Msk, SPI_CFG2_SSM_Pos, 1)); @@ -142,14 +142,14 @@ whal_Error whal_Stm32h5_Spi_Init(whal_Spi *spiDev) whal_Error whal_Stm32h5_Spi_Deinit(whal_Spi *spiDev) { - const whal_Regmap *reg; + size_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; - reg = &spiDev->regmap; + base = spiDev->base; - whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); return WHAL_SUCCESS; @@ -157,7 +157,7 @@ whal_Error whal_Stm32h5_Spi_Deinit(whal_Spi *spiDev) whal_Error whal_Stm32h5_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) { - const whal_Regmap *reg; + size_t base; whal_Stm32h5_Spi_Cfg *cfg; uint32_t cpol, cpha, mbr, dsize, fthlv; @@ -170,11 +170,11 @@ whal_Error whal_Stm32h5_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) if (comCfg->mode > 3 || comCfg->dataLines != 1 || comCfg->freq == 0) return WHAL_EINVAL; - reg = &spiDev->regmap; + base = spiDev->base; cfg = (whal_Stm32h5_Spi_Cfg *)spiDev->cfg; /* Disable SPE before reconfiguring */ - whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); mbr = Stm32h5_Spi_CalcMbr(cfg->pclk, comCfg->freq); @@ -184,27 +184,27 @@ whal_Error whal_Stm32h5_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) fthlv = 0; /* 1 data frame threshold */ /* Set baud rate, data size, FIFO threshold */ - whal_Reg_Update(reg->base, SPI_CFG1_REG, + whal_Reg_Update(base, SPI_CFG1_REG, SPI_CFG1_MBR_Msk | SPI_CFG1_DSIZE_Msk | SPI_CFG1_FTHLV_Msk, whal_SetBits(SPI_CFG1_MBR_Msk, SPI_CFG1_MBR_Pos, mbr) | whal_SetBits(SPI_CFG1_DSIZE_Msk, SPI_CFG1_DSIZE_Pos, dsize) | whal_SetBits(SPI_CFG1_FTHLV_Msk, SPI_CFG1_FTHLV_Pos, fthlv)); /* Set CPOL, CPHA */ - whal_Reg_Update(reg->base, SPI_CFG2_REG, + whal_Reg_Update(base, SPI_CFG2_REG, SPI_CFG2_CPOL_Msk | SPI_CFG2_CPHA_Msk, whal_SetBits(SPI_CFG2_CPOL_Msk, SPI_CFG2_CPOL_Pos, cpol) | whal_SetBits(SPI_CFG2_CPHA_Msk, SPI_CFG2_CPHA_Pos, cpha)); /* Endless transfer mode (TSIZE = 0) */ - whal_Reg_Update(reg->base, SPI_CR2_REG, SPI_CR2_TSIZE_Msk, 0); + whal_Reg_Update(base, SPI_CR2_REG, SPI_CR2_TSIZE_Msk, 0); /* Enable SPI */ - whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 1)); /* Start master transfer */ - whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_CSTART_Msk, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_CSTART_Msk, whal_SetBits(SPI_CR1_CSTART_Msk, SPI_CR1_CSTART_Pos, 1)); return WHAL_SUCCESS; @@ -212,19 +212,19 @@ whal_Error whal_Stm32h5_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) whal_Error whal_Stm32h5_Spi_EndCom(whal_Spi *spiDev) { - const whal_Regmap *reg; + size_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; - reg = &spiDev->regmap; + base = spiDev->base; /* Disable SPI */ - whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); /* Clear EOT and TXTF flags */ - whal_Reg_Write(reg->base, SPI_IFCR_REG, + whal_Reg_Write(base, SPI_IFCR_REG, SPI_IFCR_EOTC_Msk | SPI_IFCR_TXTFC_Msk); return WHAL_SUCCESS; @@ -236,7 +236,7 @@ whal_Error whal_Stm32h5_Spi_SendRecv(whal_Spi *spiDev, { const uint8_t *txBuf = (const uint8_t *)tx; uint8_t *rxBuf = (uint8_t *)rx; - const whal_Regmap *reg; + size_t base; whal_Stm32h5_Spi_Cfg *cfg; size_t totalLen; whal_Error err; @@ -245,13 +245,13 @@ whal_Error whal_Stm32h5_Spi_SendRecv(whal_Spi *spiDev, if (!spiDev || !spiDev->cfg || (!tx && txLen) || (!rx && rxLen)) return WHAL_EINVAL; - reg = &spiDev->regmap; + base = spiDev->base; cfg = (whal_Stm32h5_Spi_Cfg *)spiDev->cfg; totalLen = txLen > rxLen ? txLen : rxLen; for (size_t i = 0; i < totalLen; i++) { /* Wait for TXP (TX FIFO has space) */ - err = whal_Reg_ReadPoll(reg->base, SPI_SR_REG, + err = whal_Reg_ReadPoll(base, SPI_SR_REG, SPI_SR_TXP_Msk, SPI_SR_TXP_Msk, cfg->timeout); if (err) @@ -259,10 +259,10 @@ whal_Error whal_Stm32h5_Spi_SendRecv(whal_Spi *spiDev, /* Write TX data, pad with 0xFF when exhausted */ txByte = (txBuf && i < txLen) ? txBuf[i] : 0xFF; - *(volatile uint8_t *)(reg->base + SPI_TXDR_REG) = txByte; + *(volatile uint8_t *)(base + SPI_TXDR_REG) = txByte; /* Wait for RXP (RX FIFO has data) */ - err = whal_Reg_ReadPoll(reg->base, SPI_SR_REG, + err = whal_Reg_ReadPoll(base, SPI_SR_REG, SPI_SR_RXP_Msk, SPI_SR_RXP_Msk, cfg->timeout); if (err) @@ -270,9 +270,9 @@ whal_Error whal_Stm32h5_Spi_SendRecv(whal_Spi *spiDev, /* Read RX byte */ if (rxBuf && i < rxLen) - rxBuf[i] = *(volatile uint8_t *)(reg->base + SPI_RXDR_REG); + rxBuf[i] = *(volatile uint8_t *)(base + SPI_RXDR_REG); else - (void)*(volatile uint8_t *)(reg->base + SPI_RXDR_REG); + (void)*(volatile uint8_t *)(base + SPI_RXDR_REG); } return WHAL_SUCCESS; diff --git a/src/spi/stm32wb_spi.c b/src/spi/stm32wb_spi.c index 06dfc43..e114233 100644 --- a/src/spi/stm32wb_spi.c +++ b/src/spi/stm32wb_spi.c @@ -94,16 +94,16 @@ static uint32_t whal_Stm32wb_Spi_CalcBr(size_t pclk, uint32_t targetBaud) whal_Error whal_Stm32wb_Spi_Init(whal_Spi *spiDev) { - const whal_Regmap *reg; + size_t base; if (!spiDev || !spiDev->cfg) { return WHAL_EINVAL; } - reg = &spiDev->regmap; + base = spiDev->base; /* Master mode with software slave management */ - whal_Reg_Update(reg->base, SPI_CR1_REG, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_MSTR_Msk | SPI_CR1_SSM_Msk | SPI_CR1_SSI_Msk, whal_SetBits(SPI_CR1_MSTR_Msk, SPI_CR1_MSTR_Pos, 1) | whal_SetBits(SPI_CR1_SSM_Msk, SPI_CR1_SSM_Pos, 1) | @@ -114,16 +114,16 @@ whal_Error whal_Stm32wb_Spi_Init(whal_Spi *spiDev) whal_Error whal_Stm32wb_Spi_Deinit(whal_Spi *spiDev) { - const whal_Regmap *reg; + size_t base; if (!spiDev || !spiDev->cfg) { return WHAL_EINVAL; } - reg = &spiDev->regmap; + base = spiDev->base; /* Disable SPI */ - whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); return WHAL_SUCCESS; @@ -131,7 +131,7 @@ whal_Error whal_Stm32wb_Spi_Deinit(whal_Spi *spiDev) whal_Error whal_Stm32wb_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) { - const whal_Regmap *reg; + size_t base; whal_Stm32wb_Spi_Cfg *cfg; uint32_t cpol, cpha, br, ds, frxth; @@ -148,7 +148,7 @@ whal_Error whal_Stm32wb_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) return WHAL_EINVAL; } - reg = &spiDev->regmap; + base = spiDev->base; cfg = (whal_Stm32wb_Spi_Cfg *)spiDev->cfg; br = whal_Stm32wb_Spi_CalcBr(cfg->pclk, comCfg->freq); @@ -159,24 +159,24 @@ whal_Error whal_Stm32wb_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) frxth = (comCfg->wordSz <= 8) ? 1 : 0; /* Disable SPE before reconfiguring */ - whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); /* Set mode and baud rate */ - whal_Reg_Update(reg->base, SPI_CR1_REG, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_CPOL_Msk | SPI_CR1_CPHA_Msk | SPI_CR1_BR_Msk, whal_SetBits(SPI_CR1_CPOL_Msk, SPI_CR1_CPOL_Pos, cpol) | whal_SetBits(SPI_CR1_CPHA_Msk, SPI_CR1_CPHA_Pos, cpha) | whal_SetBits(SPI_CR1_BR_Msk, SPI_CR1_BR_Pos, br)); /* Set data size and FIFO receive threshold */ - whal_Reg_Update(reg->base, SPI_CR2_REG, + whal_Reg_Update(base, SPI_CR2_REG, SPI_CR2_DS_Msk | SPI_CR2_FRXTH_Msk, whal_SetBits(SPI_CR2_DS_Msk, SPI_CR2_DS_Pos, ds) | whal_SetBits(SPI_CR2_FRXTH_Msk, SPI_CR2_FRXTH_Pos, frxth)); /* Enable SPE */ - whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 1)); return WHAL_SUCCESS; @@ -184,16 +184,16 @@ whal_Error whal_Stm32wb_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) whal_Error whal_Stm32wb_Spi_EndCom(whal_Spi *spiDev) { - const whal_Regmap *reg; + size_t base; if (!spiDev || !spiDev->cfg) { return WHAL_EINVAL; } - reg = &spiDev->regmap; + base = spiDev->base; /* Disable SPE */ - whal_Reg_Update(reg->base, SPI_CR1_REG, SPI_CR1_SPE_Msk, + whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); return WHAL_SUCCESS; @@ -205,7 +205,7 @@ whal_Error whal_Stm32wb_Spi_SendRecv(whal_Spi *spiDev, { const uint8_t *txBuf = (const uint8_t *)tx; uint8_t *rxBuf = (uint8_t *)rx; - const whal_Regmap *reg; + size_t base; whal_Stm32wb_Spi_Cfg *cfg; size_t totalLen; whal_Error err; @@ -215,13 +215,13 @@ whal_Error whal_Stm32wb_Spi_SendRecv(whal_Spi *spiDev, return WHAL_EINVAL; } - reg = &spiDev->regmap; + base = spiDev->base; cfg = (whal_Stm32wb_Spi_Cfg *)spiDev->cfg; totalLen = txLen > rxLen ? txLen : rxLen; for (size_t i = 0; i < totalLen; i++) { /* Wait for TX buffer empty */ - err = whal_Reg_ReadPoll(reg->base, SPI_SR_REG, + err = whal_Reg_ReadPoll(base, SPI_SR_REG, SPI_SR_TXE_Msk, SPI_SR_TXE_Msk, cfg->timeout); if (err) @@ -229,10 +229,10 @@ whal_Error whal_Stm32wb_Spi_SendRecv(whal_Spi *spiDev, /* Write TX data, pad with 0xFF when tx is exhausted or NULL */ txByte = (txBuf && i < txLen) ? txBuf[i] : 0xFF; - *(volatile uint8_t *)(reg->base + SPI_DR_REG) = txByte; + *(volatile uint8_t *)(base + SPI_DR_REG) = txByte; /* Wait for RX byte */ - err = whal_Reg_ReadPoll(reg->base, SPI_SR_REG, + err = whal_Reg_ReadPoll(base, SPI_SR_REG, SPI_SR_RXNE_Msk, SPI_SR_RXNE_Msk, cfg->timeout); if (err) @@ -240,13 +240,13 @@ whal_Error whal_Stm32wb_Spi_SendRecv(whal_Spi *spiDev, /* Store or discard received byte */ if (rxBuf && i < rxLen) - rxBuf[i] = *(volatile uint8_t *)(reg->base + SPI_DR_REG); + rxBuf[i] = *(volatile uint8_t *)(base + SPI_DR_REG); else - (void)*(volatile uint8_t *)(reg->base + SPI_DR_REG); + (void)*(volatile uint8_t *)(base + SPI_DR_REG); } /* Wait for not busy */ - return whal_Reg_ReadPoll(reg->base, SPI_SR_REG, SPI_SR_BSY_Msk, 0, + return whal_Reg_ReadPoll(base, SPI_SR_REG, SPI_SR_BSY_Msk, 0, cfg->timeout); } diff --git a/src/timer/systick.c b/src/timer/systick.c index 03cbd36..bde5c8b 100644 --- a/src/timer/systick.c +++ b/src/timer/systick.c @@ -1,4 +1,5 @@ #include +#include #include #include #include @@ -31,22 +32,22 @@ whal_Error whal_SysTick_Init(whal_Timer *timerDev) { whal_SysTick_Cfg *cfg; - const whal_Regmap *reg; + size_t base; if (!timerDev || !timerDev->cfg) { return WHAL_EINVAL; } - reg = &timerDev->regmap; + base = timerDev->base; cfg = (whal_SysTick_Cfg *)timerDev->cfg; - whal_Reg_Update(reg->base, SYSTICK_CSR_REG, + whal_Reg_Update(base, SYSTICK_CSR_REG, SYSTICK_CSR_CLKSOURCE_Msk | SYSTICK_CSR_TICKINT_Msk, whal_SetBits(SYSTICK_CSR_CLKSOURCE_Msk, SYSTICK_CSR_CLKSOURCE_Pos, cfg->clkSrc) | whal_SetBits(SYSTICK_CSR_TICKINT_Msk, SYSTICK_CSR_TICKINT_Pos, cfg->tickInt)); - whal_Reg_Update(reg->base, SYSTICK_RVR_REG, + whal_Reg_Update(base, SYSTICK_RVR_REG, SYSTICK_RVR_RELOAD_Msk, whal_SetBits(SYSTICK_RVR_RELOAD_Msk, SYSTICK_RVR_RELOAD_Pos, cfg->cyclesPerTick)); @@ -64,15 +65,15 @@ whal_Error whal_SysTick_Deinit(whal_Timer *timerDev) whal_Error whal_SysTick_Start(whal_Timer *timerDev) { - const whal_Regmap *reg; + size_t base; if (!timerDev || !timerDev->cfg) { return WHAL_EINVAL; } - reg = &timerDev->regmap; + base = timerDev->base; - whal_Reg_Update(reg->base, SYSTICK_CSR_REG, SYSTICK_CSR_ENABLE_Msk, + whal_Reg_Update(base, SYSTICK_CSR_REG, SYSTICK_CSR_ENABLE_Msk, whal_SetBits(SYSTICK_CSR_ENABLE_Msk, SYSTICK_CSR_ENABLE_Pos, 1)); return WHAL_SUCCESS; @@ -80,15 +81,15 @@ whal_Error whal_SysTick_Start(whal_Timer *timerDev) whal_Error whal_SysTick_Stop(whal_Timer *timerDev) { - const whal_Regmap *reg; + size_t base; if (!timerDev || !timerDev->cfg) { return WHAL_EINVAL; } - reg = &timerDev->regmap; + base = timerDev->base; - whal_Reg_Update(reg->base, SYSTICK_CSR_REG, SYSTICK_CSR_ENABLE_Msk, + whal_Reg_Update(base, SYSTICK_CSR_REG, SYSTICK_CSR_ENABLE_Msk, whal_SetBits(SYSTICK_CSR_ENABLE_Msk, SYSTICK_CSR_ENABLE_Pos, 0)); return WHAL_SUCCESS; diff --git a/src/uart/pic32cz_uart.c b/src/uart/pic32cz_uart.c index b1678f7..6fee1ed 100644 --- a/src/uart/pic32cz_uart.c +++ b/src/uart/pic32cz_uart.c @@ -172,17 +172,17 @@ whal_Error whal_Pic32cz_Uart_Init(whal_Uart *uartDev) { whal_Error err; whal_Pic32cz_Uart_Cfg *cfg; - const whal_Regmap *reg; + size_t base; if (!uartDev || !uartDev->cfg) { return WHAL_EINVAL; } - reg = &uartDev->regmap; + base = uartDev->base; cfg = (whal_Pic32cz_Uart_Cfg *)uartDev->cfg; /* Configure CTRLA: internal clock, async mode, LSB first, 16x sampling */ - whal_Reg_Update(reg->base, USART_CTRLA_REG, + whal_Reg_Update(base, USART_CTRLA_REG, USART_CTRLA_MODE_Msk | USART_CTRLA_SAMPR_Msk | USART_CTRLA_TXPO_Msk | @@ -199,7 +199,7 @@ whal_Error whal_Pic32cz_Uart_Init(whal_Uart *uartDev) whal_SetBits(USART_CTRLA_DORD_Msk, USART_CTRLA_DORD_Pos, 1)); /* LSB first */ /* Configure CTRLB: 8-bit char size, 1 stop bit, no parity */ - whal_Reg_Update(reg->base, USART_CTRLB_REG, + whal_Reg_Update(base, USART_CTRLB_REG, USART_CTRLB_CHSIZE_Msk | USART_CTRLB_SBMODE_Msk | USART_CTRLB_PMODE_Msk, @@ -208,35 +208,35 @@ whal_Error whal_Pic32cz_Uart_Init(whal_Uart *uartDev) whal_SetBits(USART_CTRLB_PMODE_Msk, USART_CTRLB_PMODE_Pos, 0)); /* Wait for CTRLB sync */ - err = whal_Reg_ReadPoll(reg->base, USART_SYNCBUSY_REG, + err = whal_Reg_ReadPoll(base, USART_SYNCBUSY_REG, USART_SYNCBUSY_CTRLB_Msk, 0, cfg->timeout); if (err != WHAL_SUCCESS) return err; /* Set baud rate */ - whal_Reg_Update(reg->base, USART_BAUD_REG, + whal_Reg_Update(base, USART_BAUD_REG, 0xFFFF, cfg->baud); /* Enable transmitter and receiver */ - whal_Reg_Update(reg->base, USART_CTRLB_REG, + whal_Reg_Update(base, USART_CTRLB_REG, USART_CTRLB_TXEN_Msk | USART_CTRLB_RXEN_Msk, whal_SetBits(USART_CTRLB_TXEN_Msk, USART_CTRLB_TXEN_Pos, 1) | whal_SetBits(USART_CTRLB_RXEN_Msk, USART_CTRLB_RXEN_Pos, 1)); /* Wait for CTRLB sync */ - err = whal_Reg_ReadPoll(reg->base, USART_SYNCBUSY_REG, + err = whal_Reg_ReadPoll(base, USART_SYNCBUSY_REG, USART_SYNCBUSY_CTRLB_Msk, 0, cfg->timeout); if (err != WHAL_SUCCESS) return err; /* Enable SERCOM USART */ - whal_Reg_Update(reg->base, USART_CTRLA_REG, + whal_Reg_Update(base, USART_CTRLA_REG, USART_CTRLA_ENABLE_Msk, whal_SetBits(USART_CTRLA_ENABLE_Msk, USART_CTRLA_ENABLE_Pos, 1)); /* Wait for enable sync */ - err = whal_Reg_ReadPoll(reg->base, USART_SYNCBUSY_REG, + err = whal_Reg_ReadPoll(base, USART_SYNCBUSY_REG, USART_SYNCBUSY_ENABLE_Msk, 0, cfg->timeout); if (err != WHAL_SUCCESS) return err; @@ -247,35 +247,35 @@ whal_Error whal_Pic32cz_Uart_Init(whal_Uart *uartDev) whal_Error whal_Pic32cz_Uart_Deinit(whal_Uart *uartDev) { whal_Error err; - const whal_Regmap *reg; + size_t base; whal_Pic32cz_Uart_Cfg *cfg; if (!uartDev || !uartDev->cfg) { return WHAL_EINVAL; } - reg = &uartDev->regmap; + base = uartDev->base; cfg = (whal_Pic32cz_Uart_Cfg *)uartDev->cfg; /* Disable SERCOM USART */ - whal_Reg_Update(reg->base, USART_CTRLA_REG, + whal_Reg_Update(base, USART_CTRLA_REG, USART_CTRLA_ENABLE_Msk, whal_SetBits(USART_CTRLA_ENABLE_Msk, USART_CTRLA_ENABLE_Pos, 0)); /* Wait for disable sync */ - err = whal_Reg_ReadPoll(reg->base, USART_SYNCBUSY_REG, + err = whal_Reg_ReadPoll(base, USART_SYNCBUSY_REG, USART_SYNCBUSY_ENABLE_Msk, 0, cfg->timeout); if (err != WHAL_SUCCESS) return err; /* Disable transmitter and receiver */ - whal_Reg_Update(reg->base, USART_CTRLB_REG, + whal_Reg_Update(base, USART_CTRLB_REG, USART_CTRLB_TXEN_Msk | USART_CTRLB_RXEN_Msk, whal_SetBits(USART_CTRLB_TXEN_Msk, USART_CTRLB_TXEN_Pos, 0) | whal_SetBits(USART_CTRLB_RXEN_Msk, USART_CTRLB_RXEN_Pos, 0)); /* Wait for CTRLB sync */ - err = whal_Reg_ReadPoll(reg->base, USART_SYNCBUSY_REG, + err = whal_Reg_ReadPoll(base, USART_SYNCBUSY_REG, USART_SYNCBUSY_CTRLB_Msk, 0, cfg->timeout); if (err != WHAL_SUCCESS) return err; @@ -285,7 +285,7 @@ whal_Error whal_Pic32cz_Uart_Deinit(whal_Uart *uartDev) whal_Error whal_Pic32cz_Uart_Send(whal_Uart *uartDev, const void *data, size_t dataSz) { - const whal_Regmap *reg; + size_t base; whal_Pic32cz_Uart_Cfg *cfg; const uint8_t *buf = data; whal_Error err; @@ -294,32 +294,32 @@ whal_Error whal_Pic32cz_Uart_Send(whal_Uart *uartDev, const void *data, size_t d return WHAL_EINVAL; } - reg = &uartDev->regmap; + base = uartDev->base; cfg = (whal_Pic32cz_Uart_Cfg *)uartDev->cfg; for (size_t i = 0; i < dataSz; ++i) { /* Wait for data register to be empty */ - err = whal_Reg_ReadPoll(reg->base, USART_INTFLAG_REG, + err = whal_Reg_ReadPoll(base, USART_INTFLAG_REG, USART_INTFLAG_DRE_Msk, USART_INTFLAG_DRE_Msk, cfg->timeout); if (err) return err; /* Write data to transmit register */ - whal_Reg_Update(reg->base, USART_DATA_REG, + whal_Reg_Update(base, USART_DATA_REG, USART_DATA_Msk, whal_SetBits(USART_DATA_Msk, USART_DATA_Pos, buf[i])); } /* Wait for transmission complete */ - err = whal_Reg_ReadPoll(reg->base, USART_INTFLAG_REG, + err = whal_Reg_ReadPoll(base, USART_INTFLAG_REG, USART_INTFLAG_TXC_Msk, USART_INTFLAG_TXC_Msk, cfg->timeout); if (err) return err; /* Clear TXC flag by writing 1 */ - whal_Reg_Update(reg->base, USART_INTFLAG_REG, + whal_Reg_Update(base, USART_INTFLAG_REG, USART_INTFLAG_TXC_Msk, whal_SetBits(USART_INTFLAG_TXC_Msk, USART_INTFLAG_TXC_Pos, 1)); @@ -328,7 +328,7 @@ whal_Error whal_Pic32cz_Uart_Send(whal_Uart *uartDev, const void *data, size_t d whal_Error whal_Pic32cz_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) { - const whal_Regmap *reg; + size_t base; whal_Pic32cz_Uart_Cfg *cfg; uint8_t *buf = data; @@ -336,7 +336,7 @@ whal_Error whal_Pic32cz_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) return WHAL_EINVAL; } - reg = &uartDev->regmap; + base = uartDev->base; cfg = (whal_Pic32cz_Uart_Cfg *)uartDev->cfg; for (size_t i = 0; i < dataSz; ++i) { @@ -344,14 +344,14 @@ whal_Error whal_Pic32cz_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) whal_Error err; /* Wait for receive complete */ - err = whal_Reg_ReadPoll(reg->base, USART_INTFLAG_REG, + err = whal_Reg_ReadPoll(base, USART_INTFLAG_REG, USART_INTFLAG_RXC_Msk, USART_INTFLAG_RXC_Msk, cfg->timeout); if (err) return err; /* Read received data */ - whal_Reg_Get(reg->base, USART_DATA_REG, + whal_Reg_Get(base, USART_DATA_REG, USART_DATA_Msk, USART_DATA_Pos, &rxData); buf[i] = (uint8_t)rxData; diff --git a/src/uart/stm32f0_uart.c b/src/uart/stm32f0_uart.c index 7c62153..34b8a83 100644 --- a/src/uart/stm32f0_uart.c +++ b/src/uart/stm32f0_uart.c @@ -47,19 +47,19 @@ whal_Error whal_Stm32f0_Uart_Init(whal_Uart *uartDev) { whal_Stm32f0_Uart_Cfg *cfg; - const whal_Regmap *reg; + size_t base; if (!uartDev || !uartDev->cfg) return WHAL_EINVAL; - reg = &uartDev->regmap; + base = uartDev->base; cfg = (whal_Stm32f0_Uart_Cfg *)uartDev->cfg; - whal_Reg_Update(reg->base, UART_BRR_REG, UART_BRR_Msk, + whal_Reg_Update(base, UART_BRR_REG, UART_BRR_Msk, whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, cfg->brr)); /* Enable UE, RE, TE — no FIFOEN on STM32F0 */ - whal_Reg_Update(reg->base, UART_CR1_REG, + whal_Reg_Update(base, UART_CR1_REG, UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 1) | whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 1) | @@ -70,20 +70,20 @@ whal_Error whal_Stm32f0_Uart_Init(whal_Uart *uartDev) whal_Error whal_Stm32f0_Uart_Deinit(whal_Uart *uartDev) { - const whal_Regmap *reg; + size_t base; if (!uartDev) return WHAL_EINVAL; - reg = &uartDev->regmap; + base = uartDev->base; - whal_Reg_Update(reg->base, UART_CR1_REG, + whal_Reg_Update(base, UART_CR1_REG, UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 0) | whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 0) | whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 0)); - whal_Reg_Update(reg->base, UART_BRR_REG, UART_BRR_Msk, + whal_Reg_Update(base, UART_BRR_REG, UART_BRR_Msk, whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, 0)); return WHAL_SUCCESS; @@ -92,22 +92,22 @@ whal_Error whal_Stm32f0_Uart_Deinit(whal_Uart *uartDev) whal_Error whal_Stm32f0_Uart_Send(whal_Uart *uartDev, const void *data, size_t dataSz) { - const whal_Regmap *reg; + size_t base; whal_Stm32f0_Uart_Cfg *cfg; const uint8_t *buf = data; if (!uartDev || !uartDev->cfg || !data) return WHAL_EINVAL; - reg = &uartDev->regmap; + base = uartDev->base; cfg = (whal_Stm32f0_Uart_Cfg *)uartDev->cfg; for (size_t i = 0; i < dataSz; ++i) { whal_Error err; - whal_Reg_Update(reg->base, UART_TDR_REG, UART_TDR_Msk, + whal_Reg_Update(base, UART_TDR_REG, UART_TDR_Msk, whal_SetBits(UART_TDR_Msk, UART_TDR_Pos, buf[i])); - err = whal_Reg_ReadPoll(reg->base, UART_ISR_REG, UART_ISR_TC_Msk, + err = whal_Reg_ReadPoll(base, UART_ISR_REG, UART_ISR_TC_Msk, UART_ISR_TC_Msk, cfg->timeout); if (err) return err; @@ -118,25 +118,25 @@ whal_Error whal_Stm32f0_Uart_Send(whal_Uart *uartDev, const void *data, whal_Error whal_Stm32f0_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) { - const whal_Regmap *reg; + size_t base; whal_Stm32f0_Uart_Cfg *cfg; uint8_t *buf = data; if (!uartDev || !uartDev->cfg || !data) return WHAL_EINVAL; - reg = &uartDev->regmap; + base = uartDev->base; cfg = (whal_Stm32f0_Uart_Cfg *)uartDev->cfg; for (size_t i = 0; i < dataSz; ++i) { size_t d; - whal_Error err = whal_Reg_ReadPoll(reg->base, UART_ISR_REG, + whal_Error err = whal_Reg_ReadPoll(base, UART_ISR_REG, UART_ISR_RXNE_Msk, UART_ISR_RXNE_Msk, cfg->timeout); if (err) return err; - whal_Reg_Get(reg->base, UART_RDR_REG, UART_RDR_Msk, UART_RDR_Pos, &d); + whal_Reg_Get(base, UART_RDR_REG, UART_RDR_Msk, UART_RDR_Pos, &d); buf[i] = d; } diff --git a/src/uart/stm32f4_uart.c b/src/uart/stm32f4_uart.c index e59373b..4f496e1 100644 --- a/src/uart/stm32f4_uart.c +++ b/src/uart/stm32f4_uart.c @@ -58,24 +58,24 @@ whal_Error whal_Stm32f4_Uart_Init(whal_Uart *uartDev) { whal_Stm32f4_Uart_Cfg *cfg; - const whal_Regmap *reg; + size_t base; uint32_t brr; if (!uartDev || !uartDev->cfg) return WHAL_EINVAL; - reg = &uartDev->regmap; + base = uartDev->base; cfg = (whal_Stm32f4_Uart_Cfg *)uartDev->cfg; brr = cfg->brr; /* Set baud rate */ - whal_Reg_Update(reg->base, UART_BRR_REG, + whal_Reg_Update(base, UART_BRR_REG, UART_BRR_Msk, whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, brr)); /* Enable USART, transmitter, and receiver */ - whal_Reg_Update(reg->base, UART_CR1_REG, + whal_Reg_Update(base, UART_CR1_REG, UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 1) | whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 1) | @@ -86,22 +86,22 @@ whal_Error whal_Stm32f4_Uart_Init(whal_Uart *uartDev) whal_Error whal_Stm32f4_Uart_Deinit(whal_Uart *uartDev) { - const whal_Regmap *reg; + size_t base; if (!uartDev) return WHAL_EINVAL; - reg = &uartDev->regmap; + base = uartDev->base; /* Disable USART, transmitter, and receiver */ - whal_Reg_Update(reg->base, UART_CR1_REG, + whal_Reg_Update(base, UART_CR1_REG, UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 0) | whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 0) | whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 0)); /* Clear baud rate */ - whal_Reg_Update(reg->base, UART_BRR_REG, + whal_Reg_Update(base, UART_BRR_REG, UART_BRR_Msk, whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, 0)); @@ -110,27 +110,27 @@ whal_Error whal_Stm32f4_Uart_Deinit(whal_Uart *uartDev) whal_Error whal_Stm32f4_Uart_Send(whal_Uart *uartDev, const void *data, size_t dataSz) { - const whal_Regmap *reg; + size_t base; whal_Stm32f4_Uart_Cfg *cfg; const uint8_t *buf = data; if (!uartDev || !uartDev->cfg || !data) return WHAL_EINVAL; - reg = &uartDev->regmap; + base = uartDev->base; cfg = (whal_Stm32f4_Uart_Cfg *)uartDev->cfg; for (size_t i = 0; i < dataSz; ++i) { whal_Error err; /* Wait for transmit data register empty */ - err = whal_Reg_ReadPoll(reg->base, UART_SR_REG, UART_SR_TXE_Msk, + err = whal_Reg_ReadPoll(base, UART_SR_REG, UART_SR_TXE_Msk, UART_SR_TXE_Msk, cfg->timeout); if (err) return err; /* Write byte to data register (must not read DR — use pure write) */ - whal_Reg_Write(reg->base, UART_DR_REG, buf[i]); + whal_Reg_Write(base, UART_DR_REG, buf[i]); } return WHAL_SUCCESS; @@ -138,27 +138,27 @@ whal_Error whal_Stm32f4_Uart_Send(whal_Uart *uartDev, const void *data, size_t d whal_Error whal_Stm32f4_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) { - const whal_Regmap *reg; + size_t base; whal_Stm32f4_Uart_Cfg *cfg; uint8_t *buf = data; if (!uartDev || !uartDev->cfg || !data) return WHAL_EINVAL; - reg = &uartDev->regmap; + base = uartDev->base; cfg = (whal_Stm32f4_Uart_Cfg *)uartDev->cfg; size_t d; for (size_t i = 0; i < dataSz; ++i) { /* Wait for receive data register not empty */ - whal_Error err = whal_Reg_ReadPoll(reg->base, UART_SR_REG, + whal_Error err = whal_Reg_ReadPoll(base, UART_SR_REG, UART_SR_RXNE_Msk, UART_SR_RXNE_Msk, cfg->timeout); if (err) return err; /* Read received byte */ - whal_Reg_Get(reg->base, UART_DR_REG, + whal_Reg_Get(base, UART_DR_REG, UART_DR_Msk, UART_DR_Pos, &d); buf[i] = d; diff --git a/src/uart/stm32wb_uart.c b/src/uart/stm32wb_uart.c index 2072c8c..ff8c48d 100644 --- a/src/uart/stm32wb_uart.c +++ b/src/uart/stm32wb_uart.c @@ -61,22 +61,22 @@ whal_Error whal_Stm32wb_Uart_Init(whal_Uart *uartDev) { whal_Stm32wb_Uart_Cfg *cfg; - const whal_Regmap *reg; + size_t base; uint32_t brr; if (!uartDev || !uartDev->cfg) { return WHAL_EINVAL; } - reg = &uartDev->regmap; + base = uartDev->base; cfg = (whal_Stm32wb_Uart_Cfg *)uartDev->cfg; brr = cfg->brr; - whal_Reg_Update(reg->base, UART_BRR_REG, + whal_Reg_Update(base, UART_BRR_REG, UART_BRR_Msk, whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, brr)); - whal_Reg_Update(reg->base, UART_CR1_REG, + whal_Reg_Update(base, UART_CR1_REG, UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk | UART_CR1_FIFOEN_Msk, whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 1) | @@ -89,21 +89,21 @@ whal_Error whal_Stm32wb_Uart_Init(whal_Uart *uartDev) whal_Error whal_Stm32wb_Uart_Deinit(whal_Uart *uartDev) { - const whal_Regmap *reg; + size_t base; if (!uartDev) { return WHAL_EINVAL; } - reg = &uartDev->regmap; + base = uartDev->base; - whal_Reg_Update(reg->base, UART_CR1_REG, + whal_Reg_Update(base, UART_CR1_REG, UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, whal_SetBits(UART_CR1_UE_Msk, UART_CR1_UE_Pos, 0) | whal_SetBits(UART_CR1_RE_Msk, UART_CR1_RE_Pos, 0) | whal_SetBits(UART_CR1_TE_Msk, UART_CR1_TE_Pos, 0)); - whal_Reg_Update(reg->base, UART_BRR_REG, + whal_Reg_Update(base, UART_BRR_REG, UART_BRR_Msk, whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, 0)); @@ -112,7 +112,7 @@ whal_Error whal_Stm32wb_Uart_Deinit(whal_Uart *uartDev) whal_Error whal_Stm32wb_Uart_Send(whal_Uart *uartDev, const void *data, size_t dataSz) { - const whal_Regmap *reg; + size_t base; whal_Stm32wb_Uart_Cfg *cfg; const uint8_t *buf = data; @@ -120,15 +120,15 @@ whal_Error whal_Stm32wb_Uart_Send(whal_Uart *uartDev, const void *data, size_t d return WHAL_EINVAL; } - reg = &uartDev->regmap; + base = uartDev->base; cfg = (whal_Stm32wb_Uart_Cfg *)uartDev->cfg; for (size_t i = 0; i < dataSz; ++i) { whal_Error err; - whal_Reg_Update(reg->base, UART_TDR_REG, UART_TDR_Msk, + whal_Reg_Update(base, UART_TDR_REG, UART_TDR_Msk, whal_SetBits(UART_TDR_Msk, UART_TDR_Pos, buf[i])); - err = whal_Reg_ReadPoll(reg->base, UART_ISR_REG, UART_ISR_TC_Msk, + err = whal_Reg_ReadPoll(base, UART_ISR_REG, UART_ISR_TC_Msk, UART_ISR_TC_Msk, cfg->timeout); if (err) return err; @@ -139,7 +139,7 @@ whal_Error whal_Stm32wb_Uart_Send(whal_Uart *uartDev, const void *data, size_t d whal_Error whal_Stm32wb_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) { - const whal_Regmap *reg; + size_t base; whal_Stm32wb_Uart_Cfg *cfg; uint8_t *buf = data; @@ -147,18 +147,18 @@ whal_Error whal_Stm32wb_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) return WHAL_EINVAL; } - reg = &uartDev->regmap; + base = uartDev->base; cfg = (whal_Stm32wb_Uart_Cfg *)uartDev->cfg; size_t d; for (size_t i = 0; i < dataSz; ++i) { - whal_Error err = whal_Reg_ReadPoll(reg->base, UART_ISR_REG, + whal_Error err = whal_Reg_ReadPoll(base, UART_ISR_REG, UART_ISR_RXFNE_Msk, UART_ISR_RXFNE_Msk, cfg->timeout); if (err) return err; - whal_Reg_Get(reg->base, UART_RDR_REG, + whal_Reg_Get(base, UART_RDR_REG, UART_RDR_Msk, UART_RDR_Pos, &d); buf[i] = d; diff --git a/src/uart/stm32wb_uart_dma.c b/src/uart/stm32wb_uart_dma.c index 3ad6c88..6e3e8a7 100644 --- a/src/uart/stm32wb_uart_dma.c +++ b/src/uart/stm32wb_uart_dma.c @@ -39,7 +39,7 @@ whal_Error whal_Stm32wb_UartDma_SendAsync(whal_Uart *uartDev, const void *data, size_t dataSz) { whal_Stm32wb_UartDma_Cfg *cfg; - const whal_Regmap *reg; + size_t base; whal_Error err; if (!uartDev || !uartDev->cfg || !data || dataSz > UINT16_MAX) @@ -53,10 +53,10 @@ whal_Error whal_Stm32wb_UartDma_SendAsync(whal_Uart *uartDev, const void *data, if (cfg->txResult == WHAL_ENOTREADY) return WHAL_ENOTREADY; - reg = &uartDev->regmap; + base = uartDev->base; cfg->txChCfg->srcAddr = (uint32_t)(uintptr_t)data; - cfg->txChCfg->dstAddr = (uint32_t)(reg->base + UART_TDR_REG); + cfg->txChCfg->dstAddr = (uint32_t)(base + UART_TDR_REG); cfg->txChCfg->length = dataSz; cfg->txResult = WHAL_ENOTREADY; @@ -67,12 +67,12 @@ whal_Error whal_Stm32wb_UartDma_SendAsync(whal_Uart *uartDev, const void *data, return err; } - whal_Reg_Update(reg->base, UART_CR3_REG, UART_CR3_DMAT_Msk, + whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAT_Msk, UART_CR3_DMAT_Msk); err = whal_Dma_Start(cfg->dma, cfg->txCh); if (err) { - whal_Reg_Update(reg->base, UART_CR3_REG, UART_CR3_DMAT_Msk, 0); + whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAT_Msk, 0); cfg->txResult = err; return err; } @@ -84,7 +84,7 @@ whal_Error whal_Stm32wb_UartDma_RecvAsync(whal_Uart *uartDev, void *data, size_t dataSz) { whal_Stm32wb_UartDma_Cfg *cfg; - const whal_Regmap *reg; + size_t base; whal_Error err; if (!uartDev || !uartDev->cfg || !data || dataSz > UINT16_MAX) @@ -98,9 +98,9 @@ whal_Error whal_Stm32wb_UartDma_RecvAsync(whal_Uart *uartDev, void *data, if (cfg->rxResult == WHAL_ENOTREADY) return WHAL_ENOTREADY; - reg = &uartDev->regmap; + base = uartDev->base; - cfg->rxChCfg->srcAddr = (uint32_t)(reg->base + UART_RDR_REG); + cfg->rxChCfg->srcAddr = (uint32_t)(base + UART_RDR_REG); cfg->rxChCfg->dstAddr = (uint32_t)(uintptr_t)data; cfg->rxChCfg->length = dataSz; @@ -112,12 +112,12 @@ whal_Error whal_Stm32wb_UartDma_RecvAsync(whal_Uart *uartDev, void *data, return err; } - whal_Reg_Update(reg->base, UART_CR3_REG, UART_CR3_DMAR_Msk, + whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, UART_CR3_DMAR_Msk); err = whal_Dma_Start(cfg->dma, cfg->rxCh); if (err) { - whal_Reg_Update(reg->base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); + whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); cfg->rxResult = err; return err; } @@ -150,12 +150,12 @@ whal_Error whal_Stm32wb_UartDma_Send(whal_Uart *uartDev, const void *data, goto cleanup; } - err = whal_Reg_ReadPoll(uartDev->regmap.base, UART_ISR_REG, + err = whal_Reg_ReadPoll(uartDev->base, UART_ISR_REG, UART_ISR_TC_Msk, UART_ISR_TC_Msk, cfg->base.timeout); cleanup: whal_Dma_Stop(cfg->dma, cfg->txCh); - whal_Reg_Update(uartDev->regmap.base, UART_CR3_REG, UART_CR3_DMAT_Msk, 0); + whal_Reg_Update(uartDev->base, UART_CR3_REG, UART_CR3_DMAT_Msk, 0); cfg->txResult = err; return err; @@ -185,7 +185,7 @@ whal_Error whal_Stm32wb_UartDma_Recv(whal_Uart *uartDev, void *data, cleanup: whal_Dma_Stop(cfg->dma, cfg->rxCh); - whal_Reg_Update(uartDev->regmap.base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); + whal_Reg_Update(uartDev->base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); cfg->rxResult = err; return err; diff --git a/src/uart/stm32wba_uart_dma.c b/src/uart/stm32wba_uart_dma.c index b4aa678..d73616e 100644 --- a/src/uart/stm32wba_uart_dma.c +++ b/src/uart/stm32wba_uart_dma.c @@ -28,7 +28,7 @@ whal_Error whal_Stm32wba_UartDma_SendAsync(whal_Uart *uartDev, const void *data, size_t dataSz) { whal_Stm32wba_UartDma_Cfg *cfg; - const whal_Regmap *reg; + size_t base; whal_Error err; if (!uartDev || !uartDev->cfg || !data || dataSz > 0xFFFF) @@ -42,7 +42,7 @@ whal_Error whal_Stm32wba_UartDma_SendAsync(whal_Uart *uartDev, const void *data, if (cfg->txResult == WHAL_ENOTREADY) return WHAL_ENOTREADY; - reg = &uartDev->regmap; + base = uartDev->base; /* Single-byte DMA from flash fails on GPDMA — bounce through SRAM */ static volatile uint8_t txBounce; @@ -52,7 +52,7 @@ whal_Error whal_Stm32wba_UartDma_SendAsync(whal_Uart *uartDev, const void *data, } else { cfg->txChCfg->srcAddr = (size_t)data; } - cfg->txChCfg->dstAddr = reg->base + UART_TDR_REG; + cfg->txChCfg->dstAddr = base + UART_TDR_REG; cfg->txChCfg->nbytes = dataSz; cfg->txResult = WHAL_ENOTREADY; @@ -69,9 +69,9 @@ whal_Error whal_Stm32wba_UartDma_SendAsync(whal_Uart *uartDev, const void *data, return err; } - whal_Reg_Write(reg->base, UART_ICR_REG, UART_ICR_TCCF_Msk); + whal_Reg_Write(base, UART_ICR_REG, UART_ICR_TCCF_Msk); - whal_Reg_Update(reg->base, UART_CR3_REG, UART_CR3_DMAT_Msk, + whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAT_Msk, UART_CR3_DMAT_Msk); return WHAL_SUCCESS; @@ -81,7 +81,7 @@ whal_Error whal_Stm32wba_UartDma_RecvAsync(whal_Uart *uartDev, void *data, size_t dataSz) { whal_Stm32wba_UartDma_Cfg *cfg; - const whal_Regmap *reg; + size_t base; whal_Error err; if (!uartDev || !uartDev->cfg || !data || dataSz > 0xFFFF) @@ -95,9 +95,9 @@ whal_Error whal_Stm32wba_UartDma_RecvAsync(whal_Uart *uartDev, void *data, if (cfg->rxResult == WHAL_ENOTREADY) return WHAL_ENOTREADY; - reg = &uartDev->regmap; + base = uartDev->base; - cfg->rxChCfg->srcAddr = reg->base + UART_RDR_REG; + cfg->rxChCfg->srcAddr = base + UART_RDR_REG; cfg->rxChCfg->dstAddr = (size_t)data; cfg->rxChCfg->nbytes = dataSz; @@ -109,12 +109,12 @@ whal_Error whal_Stm32wba_UartDma_RecvAsync(whal_Uart *uartDev, void *data, return err; } - whal_Reg_Update(reg->base, UART_CR3_REG, UART_CR3_DMAR_Msk, + whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, UART_CR3_DMAR_Msk); err = whal_Dma_Start(cfg->dma, cfg->rxCh); if (err) { - whal_Reg_Update(reg->base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); + whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); cfg->rxResult = err; return err; } @@ -149,13 +149,13 @@ whal_Error whal_Stm32wba_UartDma_Send(whal_Uart *uartDev, const void *data, /* Wait for TC (transmission complete) so the last byte has shifted out * before we tear down the DMA channel */ - err = whal_Reg_ReadPoll(uartDev->regmap.base, UART_ISR_REG, + err = whal_Reg_ReadPoll(uartDev->base, UART_ISR_REG, UART_ISR_TC_Msk, UART_ISR_TC_Msk, cfg->base.timeout); cleanup: whal_Dma_Stop(cfg->dma, cfg->txCh); - whal_Reg_Update(uartDev->regmap.base, UART_CR3_REG, UART_CR3_DMAT_Msk, 0); + whal_Reg_Update(uartDev->base, UART_CR3_REG, UART_CR3_DMAT_Msk, 0); cfg->txResult = err; return err; @@ -185,7 +185,7 @@ whal_Error whal_Stm32wba_UartDma_Recv(whal_Uart *uartDev, void *data, cleanup: whal_Dma_Stop(cfg->dma, cfg->rxCh); - whal_Reg_Update(uartDev->regmap.base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); + whal_Reg_Update(uartDev->base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); cfg->rxResult = err; return err; diff --git a/src/watchdog/stm32f0_wwdg.c b/src/watchdog/stm32f0_wwdg.c index 67cf14b..83f04b6 100644 --- a/src/watchdog/stm32f0_wwdg.c +++ b/src/watchdog/stm32f0_wwdg.c @@ -34,7 +34,7 @@ whal_Error whal_Stm32f0_Wwdg_Init(whal_Watchdog *wdgDev) if (!wdgDev || !wdgDev->cfg) return WHAL_EINVAL; - base = wdgDev->regmap.base; + base = wdgDev->base; cfg = wdgDev->cfg; if (cfg->prescaler > 3 || cfg->window > 0x7F || cfg->counter > 0x7F) @@ -65,7 +65,7 @@ whal_Error whal_Stm32f0_Wwdg_Refresh(whal_Watchdog *wdgDev) if (!wdgDev || !wdgDev->cfg) return WHAL_EINVAL; - base = wdgDev->regmap.base; + base = wdgDev->base; cfg = wdgDev->cfg; whal_Reg_Write(base, CR_REG, CR_WDGA_Msk | cfg->counter); diff --git a/src/watchdog/stm32wb_iwdg.c b/src/watchdog/stm32wb_iwdg.c index c9a6a49..9c1df96 100644 --- a/src/watchdog/stm32wb_iwdg.c +++ b/src/watchdog/stm32wb_iwdg.c @@ -46,7 +46,7 @@ whal_Error whal_Stm32wb_Iwdg_Init(whal_Watchdog *wdgDev) { - const whal_Regmap *reg; + size_t base; whal_Stm32wb_Iwdg_Cfg *cfg; whal_Error err; @@ -54,7 +54,7 @@ whal_Error whal_Stm32wb_Iwdg_Init(whal_Watchdog *wdgDev) return WHAL_EINVAL; } - reg = &wdgDev->regmap; + base = wdgDev->base; cfg = wdgDev->cfg; if (cfg->prescaler > 6 || cfg->reload > 0xFFF) { @@ -62,26 +62,26 @@ whal_Error whal_Stm32wb_Iwdg_Init(whal_Watchdog *wdgDev) } /* Start the IWDG */ - whal_Reg_Write(reg->base, IWDG_KR_REG, IWDG_KEY_START); + whal_Reg_Write(base, IWDG_KR_REG, IWDG_KEY_START); /* Enable register access */ - whal_Reg_Write(reg->base, IWDG_KR_REG, IWDG_KEY_ACCESS); + whal_Reg_Write(base, IWDG_KR_REG, IWDG_KEY_ACCESS); /* Set prescaler */ - whal_Reg_Write(reg->base, IWDG_PR_REG, cfg->prescaler); + whal_Reg_Write(base, IWDG_PR_REG, cfg->prescaler); /* Set reload value */ - whal_Reg_Write(reg->base, IWDG_RLR_REG, cfg->reload); + whal_Reg_Write(base, IWDG_RLR_REG, cfg->reload); /* Wait for registers to update */ - err = whal_Reg_ReadPoll(reg->base, IWDG_SR_REG, + err = whal_Reg_ReadPoll(base, IWDG_SR_REG, IWDG_SR_PVU_Msk | IWDG_SR_RVU_Msk, 0, cfg->timeout); if (err) return err; /* Refresh counter with new reload value */ - whal_Reg_Write(reg->base, IWDG_KR_REG, IWDG_KEY_RELOAD); + whal_Reg_Write(base, IWDG_KR_REG, IWDG_KEY_RELOAD); return WHAL_SUCCESS; } @@ -101,7 +101,7 @@ whal_Error whal_Stm32wb_Iwdg_Refresh(whal_Watchdog *wdgDev) return WHAL_EINVAL; } - whal_Reg_Write(wdgDev->regmap.base, IWDG_KR_REG, IWDG_KEY_RELOAD); + whal_Reg_Write(wdgDev->base, IWDG_KR_REG, IWDG_KEY_RELOAD); return WHAL_SUCCESS; } diff --git a/src/watchdog/stm32wb_wwdg.c b/src/watchdog/stm32wb_wwdg.c index a179e7a..2a7adad 100644 --- a/src/watchdog/stm32wb_wwdg.c +++ b/src/watchdog/stm32wb_wwdg.c @@ -38,7 +38,7 @@ whal_Error whal_Stm32wb_Wwdg_Init(whal_Watchdog *wdgDev) if (!wdgDev || !wdgDev->cfg) return WHAL_EINVAL; - base = wdgDev->regmap.base; + base = wdgDev->base; cfg = wdgDev->cfg; if (cfg->prescaler > 7 || cfg->window > 0x7F || cfg->counter > 0x7F) @@ -74,7 +74,7 @@ whal_Error whal_Stm32wb_Wwdg_Refresh(whal_Watchdog *wdgDev) if (!wdgDev || !wdgDev->cfg) return WHAL_EINVAL; - base = wdgDev->regmap.base; + base = wdgDev->base; cfg = wdgDev->cfg; whal_Reg_Update(base, CR_REG, CR_T_Msk, diff --git a/tests/clock/test_pic32cz_clock.c b/tests/clock/test_pic32cz_clock.c index d63d2dd..8cf70fb 100644 --- a/tests/clock/test_pic32cz_clock.c +++ b/tests/clock/test_pic32cz_clock.c @@ -23,11 +23,11 @@ static void Test_Clock_EnableDisable(void) /* Save original state */ size_t origChen = 0; - whal_Reg_Get(g_whalClock.regmap.base, GCLK_PCHCTRL_OFFSET(25), + whal_Reg_Get(g_whalClock.base, GCLK_PCHCTRL_OFFSET(25), GCLK_PCHCTRL_CHEN_Msk, GCLK_PCHCTRL_CHEN_Pos, &origChen); size_t origMclk = 0; - whal_Reg_Get(g_whalClock.regmap.base, MCLK_CLKMSK_OFFSET(1), + whal_Reg_Get(g_whalClock.base, MCLK_CLKMSK_OFFSET(1), (1UL << 3), 3, &origMclk); size_t val = 0; @@ -35,18 +35,18 @@ static void Test_Clock_EnableDisable(void) /* Enable and verify */ WHAL_ASSERT_EQ(whal_Pic32cz_Clock_EnablePeriphClk(&g_whalClock, &testClk), WHAL_SUCCESS); - whal_Reg_Get(g_whalClock.regmap.base, GCLK_PCHCTRL_OFFSET(25), + whal_Reg_Get(g_whalClock.base, GCLK_PCHCTRL_OFFSET(25), GCLK_PCHCTRL_CHEN_Msk, GCLK_PCHCTRL_CHEN_Pos, &val); WHAL_ASSERT_EQ(val, 1); - whal_Reg_Get(g_whalClock.regmap.base, MCLK_CLKMSK_OFFSET(1), + whal_Reg_Get(g_whalClock.base, MCLK_CLKMSK_OFFSET(1), (1UL << 3), 3, &val); WHAL_ASSERT_EQ(val, 1); /* Disable and verify */ WHAL_ASSERT_EQ(whal_Pic32cz_Clock_DisablePeriphClk(&g_whalClock, &testClk), WHAL_SUCCESS); - whal_Reg_Get(g_whalClock.regmap.base, GCLK_PCHCTRL_OFFSET(25), + whal_Reg_Get(g_whalClock.base, GCLK_PCHCTRL_OFFSET(25), GCLK_PCHCTRL_CHEN_Msk, GCLK_PCHCTRL_CHEN_Pos, &val); WHAL_ASSERT_EQ(val, 0); diff --git a/tests/clock/test_stm32wb_clock.c b/tests/clock/test_stm32wb_clock.c index 77e2690..7ca8382 100644 --- a/tests/clock/test_stm32wb_clock.c +++ b/tests/clock/test_stm32wb_clock.c @@ -11,19 +11,19 @@ static void Test_Clock_EnableDisable(void) /* Save original state */ size_t origVal = 0; - whal_Reg_Get(g_whalClock.regmap.base, 0x4C, (1 << 0), 0, &origVal); + whal_Reg_Get(g_whalClock.base, 0x4C, (1 << 0), 0, &origVal); /* Enable and verify */ WHAL_ASSERT_EQ(whal_Stm32wb_Rcc_EnablePeriphClk(&g_whalClock, &testClk), WHAL_SUCCESS); size_t val = 0; - whal_Reg_Get(g_whalClock.regmap.base, 0x4C, (1 << 0), 0, &val); + whal_Reg_Get(g_whalClock.base, 0x4C, (1 << 0), 0, &val); WHAL_ASSERT_EQ(val, 1); /* Disable and verify */ WHAL_ASSERT_EQ(whal_Stm32wb_Rcc_DisablePeriphClk(&g_whalClock, &testClk), WHAL_SUCCESS); - whal_Reg_Get(g_whalClock.regmap.base, 0x4C, (1 << 0), 0, &val); + whal_Reg_Get(g_whalClock.base, 0x4C, (1 << 0), 0, &val); WHAL_ASSERT_EQ(val, 0); /* Restore original state */ diff --git a/tests/eth/test_stm32n6_eth.c b/tests/eth/test_stm32n6_eth.c index 4957a71..abe4bc0 100644 --- a/tests/eth/test_stm32n6_eth.c +++ b/tests/eth/test_stm32n6_eth.c @@ -2,7 +2,6 @@ #include #include #include -#include #include "board.h" #include "test.h" @@ -45,7 +44,7 @@ static void Test_Eth_Loopback(void) }; uint8_t rxFrame[1536]; size_t rxLen = sizeof(rxFrame); - size_t base = g_whalEth.regmap.base; + size_t base = g_whalEth.base; whal_Stm32n6_Eth_Cfg *ethCfg = (whal_Stm32n6_Eth_Cfg *)g_whalEth.cfg; whal_Error err; uint16_t bcr = 0; diff --git a/tests/flash/test_stm32wb_flash.c b/tests/flash/test_stm32wb_flash.c index 28cf2f1..0ef6e83 100644 --- a/tests/flash/test_stm32wb_flash.c +++ b/tests/flash/test_stm32wb_flash.c @@ -16,7 +16,7 @@ static void Test_Flash_LockReadback(void) WHAL_ASSERT_EQ(whal_Flash_Lock(&g_whalFlash, 0, 0), WHAL_SUCCESS); size_t val = 0; - whal_Reg_Get(g_whalFlash.regmap.base, FLASH_CR_REG, + whal_Reg_Get(g_whalFlash.base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, &val); WHAL_ASSERT_EQ(val, 1); } diff --git a/tests/gpio/test_pic32cz_gpio.c b/tests/gpio/test_pic32cz_gpio.c index f86aebd..7a767b5 100644 --- a/tests/gpio/test_pic32cz_gpio.c +++ b/tests/gpio/test_pic32cz_gpio.c @@ -19,7 +19,7 @@ static void Test_Gpio_DirRegister(void) { /* PB21 should be configured as output (bit 21 set in DIR register) */ size_t val = 0; - whal_Reg_Get(g_whalGpio.regmap.base, PORT_DIR_REG(LED_PORT), + whal_Reg_Get(g_whalGpio.base, PORT_DIR_REG(LED_PORT), (1UL << LED_HW_PIN), LED_HW_PIN, &val); WHAL_ASSERT_EQ(val, 1); } @@ -30,7 +30,7 @@ static void Test_Gpio_SetHighReg(void) /* Readback OUT register bit 21 */ size_t val = 0; - whal_Reg_Get(g_whalGpio.regmap.base, PORT_OUT_REG(LED_PORT), + whal_Reg_Get(g_whalGpio.base, PORT_OUT_REG(LED_PORT), (1UL << LED_HW_PIN), LED_HW_PIN, &val); WHAL_ASSERT_EQ(val, 1); } @@ -40,7 +40,7 @@ static void Test_Gpio_SetLowReg(void) WHAL_ASSERT_EQ(whal_Gpio_Set(&g_whalGpio, BOARD_LED_PIN, 0), WHAL_SUCCESS); size_t val = 0; - whal_Reg_Get(g_whalGpio.regmap.base, PORT_OUT_REG(LED_PORT), + whal_Reg_Get(g_whalGpio.base, PORT_OUT_REG(LED_PORT), (1UL << LED_HW_PIN), LED_HW_PIN, &val); WHAL_ASSERT_EQ(val, 0); } diff --git a/tests/gpio/test_stm32wb_gpio.c b/tests/gpio/test_stm32wb_gpio.c index 3596e4b..fce5da2 100644 --- a/tests/gpio/test_stm32wb_gpio.c +++ b/tests/gpio/test_stm32wb_gpio.c @@ -17,7 +17,7 @@ static inline size_t Board_LedPortBase(void) { whal_Stm32wb_Gpio_Cfg *cfg = (whal_Stm32wb_Gpio_Cfg *)g_whalGpio.cfg; whal_Stm32wb_Gpio_PinCfg led = cfg->pinCfg[BOARD_LED_PIN]; - return g_whalGpio.regmap.base + WHAL_STM32WB_GPIO_GET_PORT(led) * GPIOx_STRIDE; + return g_whalGpio.base + WHAL_STM32WB_GPIO_GET_PORT(led) * GPIOx_STRIDE; } static inline size_t Board_LedPinNum(void) diff --git a/wolfHAL/block/block.h b/wolfHAL/block/block.h index 79c6553..1c0c18b 100644 --- a/wolfHAL/block/block.h +++ b/wolfHAL/block/block.h @@ -2,7 +2,6 @@ #define WHAL_BLOCK_H #include -#include #include #include @@ -37,7 +36,7 @@ typedef struct { * @brief Block device instance tying configuration to a driver implementation. */ struct whal_Block { - const whal_Regmap regmap; + const size_t base; const whal_BlockDriver *driver; void *cfg; }; diff --git a/wolfHAL/clock/clock.h b/wolfHAL/clock/clock.h index 4b28dfe..da7d1db 100644 --- a/wolfHAL/clock/clock.h +++ b/wolfHAL/clock/clock.h @@ -1,7 +1,7 @@ #ifndef WHAL_CLOCK_H #define WHAL_CLOCK_H -#include +#include /* * @file clock.h @@ -14,7 +14,7 @@ * provides a typed handle so those helpers have something to take. */ typedef struct { - const whal_Regmap regmap; + const size_t base; } whal_Clock; #endif /* WHAL_CLOCK_H */ diff --git a/wolfHAL/crypto/crypto.h b/wolfHAL/crypto/crypto.h index 65eed4b..f4ff670 100644 --- a/wolfHAL/crypto/crypto.h +++ b/wolfHAL/crypto/crypto.h @@ -3,7 +3,6 @@ #include #include -#include #include /* @@ -169,7 +168,7 @@ typedef struct { * @brief Crypto device instance tying a register map, driver, and configuration. */ struct whal_Crypto { - const whal_Regmap regmap; + const size_t base; const whal_CryptoDriver *driver; const void *cfg; }; diff --git a/wolfHAL/dma/dma.h b/wolfHAL/dma/dma.h index 483a409..336f289 100644 --- a/wolfHAL/dma/dma.h +++ b/wolfHAL/dma/dma.h @@ -2,7 +2,6 @@ #define WHAL_DMA_H #include -#include #include /* @@ -46,7 +45,7 @@ typedef struct { * @brief DMA device instance containing driver and configuration data. */ struct whal_Dma { - const whal_Regmap regmap; + const size_t base; const whal_DmaDriver *driver; const void *cfg; }; diff --git a/wolfHAL/eth/eth.h b/wolfHAL/eth/eth.h index 843eef3..9faff0a 100644 --- a/wolfHAL/eth/eth.h +++ b/wolfHAL/eth/eth.h @@ -2,7 +2,6 @@ #define WHAL_ETH_H #include -#include #include #include @@ -53,7 +52,7 @@ typedef struct { * @brief Ethernet device instance tying a register map and driver. */ struct whal_Eth { - const whal_Regmap regmap; + const size_t base; const whal_EthDriver *driver; void *cfg; uint8_t macAddr[6]; diff --git a/wolfHAL/flash/flash.h b/wolfHAL/flash/flash.h index 42c4a32..902ac8c 100644 --- a/wolfHAL/flash/flash.h +++ b/wolfHAL/flash/flash.h @@ -2,7 +2,6 @@ #define WHAL_FLASH_H #include -#include #include #include @@ -37,7 +36,7 @@ typedef struct { * @brief Flash device instance tying configuration to a driver implementation. */ struct whal_Flash { - const whal_Regmap regmap; + const size_t base; const whal_FlashDriver *driver; void *cfg; }; diff --git a/wolfHAL/gpio/gpio.h b/wolfHAL/gpio/gpio.h index 94d789c..9425c35 100644 --- a/wolfHAL/gpio/gpio.h +++ b/wolfHAL/gpio/gpio.h @@ -2,7 +2,6 @@ #define WHAL_GPIO_H #include -#include #include /* @@ -30,7 +29,7 @@ typedef struct { * @brief GPIO device instance containing driver and configuration data. */ struct whal_Gpio { - const whal_Regmap regmap; + const size_t base; const whal_GpioDriver *driver; const void *cfg; }; diff --git a/wolfHAL/i2c/i2c.h b/wolfHAL/i2c/i2c.h index 0aa2d6b..4cf9718 100644 --- a/wolfHAL/i2c/i2c.h +++ b/wolfHAL/i2c/i2c.h @@ -2,7 +2,6 @@ #define WHAL_I2C_H #include -#include #include #include @@ -66,7 +65,7 @@ typedef struct { * @brief I2C device instance tying a register map and driver. */ struct whal_I2c { - const whal_Regmap regmap; + const size_t base; const whal_I2cDriver *driver; void *cfg; }; diff --git a/wolfHAL/ipc/ipc.h b/wolfHAL/ipc/ipc.h index a9b2870..8b92142 100644 --- a/wolfHAL/ipc/ipc.h +++ b/wolfHAL/ipc/ipc.h @@ -3,7 +3,6 @@ #include #include -#include #include /* @@ -31,7 +30,7 @@ typedef struct { * @brief IPC device instance tying a register map and driver. */ struct whal_Ipc { - const whal_Regmap regmap; + const size_t base; const whal_IpcDriver *driver; void *cfg; }; diff --git a/wolfHAL/irq/irq.h b/wolfHAL/irq/irq.h index dd80745..c637321 100644 --- a/wolfHAL/irq/irq.h +++ b/wolfHAL/irq/irq.h @@ -2,7 +2,6 @@ #define WHAL_IRQ_H #include -#include #include /* @@ -35,7 +34,7 @@ typedef struct { * @brief Interrupt controller device instance. */ struct whal_Irq { - const whal_Regmap regmap; + const size_t base; const whal_IrqDriver *driver; const void *cfg; }; diff --git a/wolfHAL/platform/arm/cortex_m0.h b/wolfHAL/platform/arm/cortex_m0.h index fc6bc26..fefd652 100644 --- a/wolfHAL/platform/arm/cortex_m0.h +++ b/wolfHAL/platform/arm/cortex_m0.h @@ -3,9 +3,7 @@ #include -#define WHAL_CORTEX_M0_SYSTICK_REGMAP \ - .base = 0xE000E010, \ - .size = 0x400 +#define WHAL_CORTEX_M0_SYSTICK_BASE 0xE000E010 #define WHAL_CORTEX_M0_SYSTICK_DRIVER &whal_SysTick_Driver #endif /* WHAL_CORTEX_M0_H */ diff --git a/wolfHAL/platform/arm/cortex_m0plus.h b/wolfHAL/platform/arm/cortex_m0plus.h index f97dcb3..784ac8b 100644 --- a/wolfHAL/platform/arm/cortex_m0plus.h +++ b/wolfHAL/platform/arm/cortex_m0plus.h @@ -3,9 +3,7 @@ #include -#define WHAL_CORTEX_M0PLUS_SYSTICK_REGMAP \ - .base = 0xE000E010, \ - .size = 0x400 +#define WHAL_CORTEX_M0PLUS_SYSTICK_BASE 0xE000E010 #define WHAL_CORTEX_M0PLUS_SYSTICK_DRIVER &whal_SysTick_Driver #endif /* WHAL_CORTEX_M0PLUS_H */ diff --git a/wolfHAL/platform/arm/cortex_m3.h b/wolfHAL/platform/arm/cortex_m3.h index c3ee8b5..020edbc 100644 --- a/wolfHAL/platform/arm/cortex_m3.h +++ b/wolfHAL/platform/arm/cortex_m3.h @@ -4,14 +4,10 @@ #include #include -#define WHAL_CORTEX_M3_SYSTICK_REGMAP \ - .base = 0xE000E010, \ - .size = 0x400 +#define WHAL_CORTEX_M3_SYSTICK_BASE 0xE000E010 #define WHAL_CORTEX_M3_SYSTICK_DRIVER &whal_SysTick_Driver -#define WHAL_CORTEX_M3_NVIC_REGMAP \ - .base = 0xE000E100, \ - .size = 0x400 +#define WHAL_CORTEX_M3_NVIC_BASE 0xE000E100 #define WHAL_CORTEX_M3_NVIC_DRIVER &whal_Nvic_Driver #endif /* WHAL_CORTEX_M3_H */ diff --git a/wolfHAL/platform/arm/cortex_m33.h b/wolfHAL/platform/arm/cortex_m33.h index 18f70be..4f854a2 100644 --- a/wolfHAL/platform/arm/cortex_m33.h +++ b/wolfHAL/platform/arm/cortex_m33.h @@ -4,14 +4,10 @@ #include #include -#define WHAL_CORTEX_M33_SYSTICK_REGMAP \ - .base = 0xE000E010, \ - .size = 0x400 +#define WHAL_CORTEX_M33_SYSTICK_BASE 0xE000E010 #define WHAL_CORTEX_M33_SYSTICK_DRIVER &whal_SysTick_Driver -#define WHAL_CORTEX_M33_NVIC_REGMAP \ - .base = 0xE000E100, \ - .size = 0x400 +#define WHAL_CORTEX_M33_NVIC_BASE 0xE000E100 #define WHAL_CORTEX_M33_NVIC_DRIVER &whal_Nvic_Driver #endif /* WHAL_CORTEX_M33_H */ diff --git a/wolfHAL/platform/arm/cortex_m4.h b/wolfHAL/platform/arm/cortex_m4.h index b60dd92..e6b9cd0 100644 --- a/wolfHAL/platform/arm/cortex_m4.h +++ b/wolfHAL/platform/arm/cortex_m4.h @@ -4,14 +4,10 @@ #include #include -#define WHAL_CORTEX_M4_SYSTICK_REGMAP \ - .base = 0xE000E010, \ - .size = 0x400 +#define WHAL_CORTEX_M4_SYSTICK_BASE 0xE000E010 #define WHAL_CORTEX_M4_SYSTICK_DRIVER &whal_SysTick_Driver -#define WHAL_CORTEX_M4_NVIC_REGMAP \ - .base = 0xE000E100, \ - .size = 0x400 +#define WHAL_CORTEX_M4_NVIC_BASE 0xE000E100 #define WHAL_CORTEX_M4_NVIC_DRIVER &whal_Nvic_Driver #endif /* WHAL_CORTEX_M4_H */ diff --git a/wolfHAL/platform/arm/cortex_m55.h b/wolfHAL/platform/arm/cortex_m55.h index 490e10f..091dd0b 100644 --- a/wolfHAL/platform/arm/cortex_m55.h +++ b/wolfHAL/platform/arm/cortex_m55.h @@ -4,14 +4,10 @@ #include #include -#define WHAL_CORTEX_M55_SYSTICK_REGMAP \ - .base = 0xE000E010, \ - .size = 0x400 +#define WHAL_CORTEX_M55_SYSTICK_BASE 0xE000E010 #define WHAL_CORTEX_M55_SYSTICK_DRIVER &whal_SysTick_Driver -#define WHAL_CORTEX_M55_NVIC_REGMAP \ - .base = 0xE000E100, \ - .size = 0x400 +#define WHAL_CORTEX_M55_NVIC_BASE 0xE000E100 #define WHAL_CORTEX_M55_NVIC_DRIVER &whal_Nvic_Driver #endif /* WHAL_CORTEX_M55_H */ diff --git a/wolfHAL/platform/arm/cortex_m7.h b/wolfHAL/platform/arm/cortex_m7.h index 5583100..c94aefc 100644 --- a/wolfHAL/platform/arm/cortex_m7.h +++ b/wolfHAL/platform/arm/cortex_m7.h @@ -3,9 +3,7 @@ #include -#define WHAL_CORTEX_M7_SYSTICK_REGMAP \ - .base = 0xE000E010, \ - .size = 0x400 +#define WHAL_CORTEX_M7_SYSTICK_BASE 0xE000E010 #define WHAL_CORTEX_M7_SYSTICK_DRIVER &whal_SysTick_Driver #endif /* WHAL_CORTEX_M7_H */ diff --git a/wolfHAL/platform/microchip/pic32cz.h b/wolfHAL/platform/microchip/pic32cz.h index 6ff1222..9ee6c6e 100644 --- a/wolfHAL/platform/microchip/pic32cz.h +++ b/wolfHAL/platform/microchip/pic32cz.h @@ -8,27 +8,17 @@ #include #include -#define WHAL_PIC32CZ_FLASH_REGMAP \ - .base = 0x44002000, \ - .size = 0x4000 +#define WHAL_PIC32CZ_FLASH_BASE 0x44002000 #define WHAL_PIC32CZ_FLASH_DRIVER &whal_Pic32cz_Flash_Driver -#define WHAL_PIC32CZ_SUPC_REGMAP \ - .base = 0x44020000, \ - .size = 0x2000 +#define WHAL_PIC32CZ_SUPC_BASE 0x44020000 -#define WHAL_PIC32CZ_CLOCK_REGMAP \ - .base = 0x44040000, \ - .size = 0x14000 +#define WHAL_PIC32CZ_CLOCK_BASE 0x44040000 -#define WHAL_PIC32CZ_GPIO_REGMAP \ - .base = 0x44840000, \ - .size = 0x2000 +#define WHAL_PIC32CZ_GPIO_BASE 0x44840000 #define WHAL_PIC32CZ_GPIO_DRIVER &whal_Pic32cz_Gpio_Driver -#define WHAL_PIC32CZ_SERCOM4_UART_REGMAP \ - .base = 0x46004000, \ - .size = 0x2000 +#define WHAL_PIC32CZ_SERCOM4_UART_BASE 0x46004000 #define WHAL_PIC32CZ_SERCOM4_UART_DRIVER &whal_Pic32cz_Uart_Driver #define WHAL_PIC32CZ_SUPC_PLL \ diff --git a/wolfHAL/platform/st/stm32c031xx.h b/wolfHAL/platform/st/stm32c031xx.h index efcfd7e..16dd6a9 100644 --- a/wolfHAL/platform/st/stm32c031xx.h +++ b/wolfHAL/platform/st/stm32c031xx.h @@ -25,33 +25,21 @@ /* --- Device macros --- */ -#define WHAL_STM32C031_RCC_REGMAP \ - .base = 0x40021000, \ - .size = 0x400 +#define WHAL_STM32C031_RCC_BASE 0x40021000 -#define WHAL_STM32C031_GPIO_REGMAP \ - .base = 0x50000000, \ - .size = 0x1800 +#define WHAL_STM32C031_GPIO_BASE 0x50000000 #define WHAL_STM32C031_GPIO_DRIVER &whal_Stm32c0_Gpio_Driver -#define WHAL_STM32C031_USART1_REGMAP \ - .base = 0x40013800, \ - .size = 0x400 +#define WHAL_STM32C031_USART1_BASE 0x40013800 #define WHAL_STM32C031_USART1_DRIVER &whal_Stm32c0_Uart_Driver -#define WHAL_STM32C031_USART2_REGMAP \ - .base = 0x40004400, \ - .size = 0x400 +#define WHAL_STM32C031_USART2_BASE 0x40004400 #define WHAL_STM32C031_USART2_DRIVER &whal_Stm32c0_Uart_Driver -#define WHAL_STM32C031_SPI1_REGMAP \ - .base = 0x40013000, \ - .size = 0x400 +#define WHAL_STM32C031_SPI1_BASE 0x40013000 #define WHAL_STM32C031_SPI1_DRIVER &whal_Stm32c0_Spi_Driver -#define WHAL_STM32C031_FLASH_REGMAP \ - .base = 0x40022000, \ - .size = 0x400 +#define WHAL_STM32C031_FLASH_BASE 0x40022000 #define WHAL_STM32C031_FLASH_DRIVER &whal_Stm32c0_Flash_Driver /* --- Clock gate macros --- */ diff --git a/wolfHAL/platform/st/stm32f091xx.h b/wolfHAL/platform/st/stm32f091xx.h index 24cf965..26f60c1 100644 --- a/wolfHAL/platform/st/stm32f091xx.h +++ b/wolfHAL/platform/st/stm32f091xx.h @@ -28,63 +28,39 @@ /* --- Device macros --- */ -#define WHAL_STM32F091_RCC_REGMAP \ - .base = 0x40021000, \ - .size = 0x400 +#define WHAL_STM32F091_RCC_BASE 0x40021000 -#define WHAL_STM32F091_GPIO_REGMAP \ - .base = 0x48000000, \ - .size = 0x1800 +#define WHAL_STM32F091_GPIO_BASE 0x48000000 #define WHAL_STM32F091_GPIO_DRIVER &whal_Stm32f0_Gpio_Driver -#define WHAL_STM32F091_USART1_REGMAP \ - .base = 0x40013800, \ - .size = 0x400 +#define WHAL_STM32F091_USART1_BASE 0x40013800 #define WHAL_STM32F091_USART1_DRIVER &whal_Stm32f0_Uart_Driver -#define WHAL_STM32F091_USART2_REGMAP \ - .base = 0x40004400, \ - .size = 0x400 +#define WHAL_STM32F091_USART2_BASE 0x40004400 #define WHAL_STM32F091_USART2_DRIVER &whal_Stm32f0_Uart_Driver -#define WHAL_STM32F091_USART3_REGMAP \ - .base = 0x40004800, \ - .size = 0x400 +#define WHAL_STM32F091_USART3_BASE 0x40004800 #define WHAL_STM32F091_USART3_DRIVER &whal_Stm32f0_Uart_Driver -#define WHAL_STM32F091_SPI1_REGMAP \ - .base = 0x40013000, \ - .size = 0x400 +#define WHAL_STM32F091_SPI1_BASE 0x40013000 #define WHAL_STM32F091_SPI1_DRIVER &whal_Stm32f0_Spi_Driver -#define WHAL_STM32F091_SPI2_REGMAP \ - .base = 0x40003800, \ - .size = 0x400 +#define WHAL_STM32F091_SPI2_BASE 0x40003800 #define WHAL_STM32F091_SPI2_DRIVER &whal_Stm32f0_Spi_Driver -#define WHAL_STM32F091_I2C1_REGMAP \ - .base = 0x40005400, \ - .size = 0x400 +#define WHAL_STM32F091_I2C1_BASE 0x40005400 #define WHAL_STM32F091_I2C1_DRIVER &whal_Stm32f0_I2c_Driver -#define WHAL_STM32F091_I2C2_REGMAP \ - .base = 0x40005800, \ - .size = 0x400 +#define WHAL_STM32F091_I2C2_BASE 0x40005800 #define WHAL_STM32F091_I2C2_DRIVER &whal_Stm32f0_I2c_Driver -#define WHAL_STM32F091_FLASH_REGMAP \ - .base = 0x40022000, \ - .size = 0x400 +#define WHAL_STM32F091_FLASH_BASE 0x40022000 #define WHAL_STM32F091_FLASH_DRIVER &whal_Stm32f0_Flash_Driver -#define WHAL_STM32F091_IWDG_REGMAP \ - .base = 0x40003000, \ - .size = 0x400 +#define WHAL_STM32F091_IWDG_BASE 0x40003000 #define WHAL_STM32F091_IWDG_DRIVER &whal_Stm32f0_Iwdg_Driver -#define WHAL_STM32F091_WWDG_REGMAP \ - .base = 0x40002C00, \ - .size = 0x400 +#define WHAL_STM32F091_WWDG_BASE 0x40002C00 #define WHAL_STM32F091_WWDG_DRIVER &whal_Stm32f0_Wwdg_Driver /* --- Clock gate macros --- */ diff --git a/wolfHAL/platform/st/stm32f302r8.h b/wolfHAL/platform/st/stm32f302r8.h index 91b96e0..8cd31ee 100644 --- a/wolfHAL/platform/st/stm32f302r8.h +++ b/wolfHAL/platform/st/stm32f302r8.h @@ -30,68 +30,42 @@ /* --- Device macros --- */ -#define WHAL_STM32F302_RCC_REGMAP \ - .base = 0x40021000, \ - .size = 0x400 +#define WHAL_STM32F302_RCC_BASE 0x40021000 -#define WHAL_STM32F302_GPIO_REGMAP \ - .base = 0x48000000, \ - .size = 0x1800 +#define WHAL_STM32F302_GPIO_BASE 0x48000000 #define WHAL_STM32F302_GPIO_DRIVER &whal_Stm32f3_Gpio_Driver -#define WHAL_STM32F302_USART1_REGMAP \ - .base = 0x40013800, \ - .size = 0x400 +#define WHAL_STM32F302_USART1_BASE 0x40013800 #define WHAL_STM32F302_USART1_DRIVER &whal_Stm32f3_Uart_Driver -#define WHAL_STM32F302_USART2_REGMAP \ - .base = 0x40004400, \ - .size = 0x400 +#define WHAL_STM32F302_USART2_BASE 0x40004400 #define WHAL_STM32F302_USART2_DRIVER &whal_Stm32f3_Uart_Driver -#define WHAL_STM32F302_USART3_REGMAP \ - .base = 0x40004800, \ - .size = 0x400 +#define WHAL_STM32F302_USART3_BASE 0x40004800 #define WHAL_STM32F302_USART3_DRIVER &whal_Stm32f3_Uart_Driver -#define WHAL_STM32F302_SPI2_REGMAP \ - .base = 0x40003800, \ - .size = 0x400 +#define WHAL_STM32F302_SPI2_BASE 0x40003800 #define WHAL_STM32F302_SPI2_DRIVER &whal_Stm32f3_Spi_Driver -#define WHAL_STM32F302_SPI3_REGMAP \ - .base = 0x40003C00, \ - .size = 0x400 +#define WHAL_STM32F302_SPI3_BASE 0x40003C00 #define WHAL_STM32F302_SPI3_DRIVER &whal_Stm32f3_Spi_Driver -#define WHAL_STM32F302_I2C1_REGMAP \ - .base = 0x40005400, \ - .size = 0x400 +#define WHAL_STM32F302_I2C1_BASE 0x40005400 #define WHAL_STM32F302_I2C1_DRIVER &whal_Stm32f3_I2c_Driver -#define WHAL_STM32F302_I2C2_REGMAP \ - .base = 0x40005800, \ - .size = 0x400 +#define WHAL_STM32F302_I2C2_BASE 0x40005800 #define WHAL_STM32F302_I2C2_DRIVER &whal_Stm32f3_I2c_Driver -#define WHAL_STM32F302_I2C3_REGMAP \ - .base = 0x40007800, \ - .size = 0x400 +#define WHAL_STM32F302_I2C3_BASE 0x40007800 #define WHAL_STM32F302_I2C3_DRIVER &whal_Stm32f3_I2c_Driver -#define WHAL_STM32F302_FLASH_REGMAP \ - .base = 0x40022000, \ - .size = 0x400 +#define WHAL_STM32F302_FLASH_BASE 0x40022000 #define WHAL_STM32F302_FLASH_DRIVER &whal_Stm32f3_Flash_Driver -#define WHAL_STM32F302_IWDG_REGMAP \ - .base = 0x40003000, \ - .size = 0x400 +#define WHAL_STM32F302_IWDG_BASE 0x40003000 #define WHAL_STM32F302_IWDG_DRIVER &whal_Stm32f3_Iwdg_Driver -#define WHAL_STM32F302_WWDG_REGMAP \ - .base = 0x40002C00, \ - .size = 0x400 +#define WHAL_STM32F302_WWDG_BASE 0x40002C00 #define WHAL_STM32F302_WWDG_DRIVER &whal_Stm32f3_Wwdg_Driver /* --- Clock gate macros --- */ diff --git a/wolfHAL/platform/st/stm32f411xx.h b/wolfHAL/platform/st/stm32f411xx.h index 3863b7b..25a4b08 100644 --- a/wolfHAL/platform/st/stm32f411xx.h +++ b/wolfHAL/platform/st/stm32f411xx.h @@ -28,28 +28,18 @@ /* --- Device macros --- */ -#define WHAL_STM32F411_RCC_REGMAP \ - .base = 0x40023800, \ - .size = 0x400 +#define WHAL_STM32F411_RCC_BASE 0x40023800 -#define WHAL_STM32F411_GPIO_REGMAP \ - .base = 0x40020000, \ - .size = 0x2000 +#define WHAL_STM32F411_GPIO_BASE 0x40020000 #define WHAL_STM32F411_GPIO_DRIVER &whal_Stm32f4_Gpio_Driver -#define WHAL_STM32F411_USART1_REGMAP \ - .base = 0x40011000, \ - .size = 0x400 +#define WHAL_STM32F411_USART1_BASE 0x40011000 #define WHAL_STM32F411_USART1_DRIVER &whal_Stm32f4_Uart_Driver -#define WHAL_STM32F411_USART2_REGMAP \ - .base = 0x40004400, \ - .size = 0x400 +#define WHAL_STM32F411_USART2_BASE 0x40004400 #define WHAL_STM32F411_USART2_DRIVER &whal_Stm32f4_Uart_Driver -#define WHAL_STM32F411_USART6_REGMAP \ - .base = 0x40011400, \ - .size = 0x400 +#define WHAL_STM32F411_USART6_BASE 0x40011400 #define WHAL_STM32F411_USART6_DRIVER &whal_Stm32f4_Uart_Driver /* --- Clock gate macros --- */ @@ -123,21 +113,15 @@ /* SPI device macros */ -#define WHAL_STM32F411_SPI1_REGMAP \ - .base = 0x40013000, \ - .size = 0x400 +#define WHAL_STM32F411_SPI1_BASE 0x40013000 #define WHAL_STM32F411_SPI1_DRIVER &whal_Stm32f4_Spi_Driver -#define WHAL_STM32F411_SPI2_REGMAP \ - .base = 0x40003800, \ - .size = 0x400 +#define WHAL_STM32F411_SPI2_BASE 0x40003800 #define WHAL_STM32F411_SPI2_DRIVER &whal_Stm32f4_Spi_Driver /* Flash device macros */ -#define WHAL_STM32F411_FLASH_REGMAP \ - .base = 0x40023C00, \ - .size = 0x400 +#define WHAL_STM32F411_FLASH_BASE 0x40023C00 #define WHAL_STM32F411_FLASH_DRIVER &whal_Stm32f4_Flash_Driver #endif /* WHAL_STM32F411XX_H */ diff --git a/wolfHAL/platform/st/stm32h563xx.h b/wolfHAL/platform/st/stm32h563xx.h index 8d15263..ff4842d 100644 --- a/wolfHAL/platform/st/stm32h563xx.h +++ b/wolfHAL/platform/st/stm32h563xx.h @@ -27,28 +27,18 @@ /* --- Device macros --- */ -#define WHAL_STM32H563_RCC_REGMAP \ - .base = 0x44020C00, \ - .size = 0x400 +#define WHAL_STM32H563_RCC_BASE 0x44020C00 -#define WHAL_STM32H563_GPIO_REGMAP \ - .base = 0x42020000, \ - .size = 0x2400 +#define WHAL_STM32H563_GPIO_BASE 0x42020000 #define WHAL_STM32H563_GPIO_DRIVER &whal_Stm32h5_Gpio_Driver -#define WHAL_STM32H563_USART1_REGMAP \ - .base = 0x40013800, \ - .size = 0x400 +#define WHAL_STM32H563_USART1_BASE 0x40013800 #define WHAL_STM32H563_USART1_DRIVER &whal_Stm32h5_Uart_Driver -#define WHAL_STM32H563_USART2_REGMAP \ - .base = 0x40004400, \ - .size = 0x400 +#define WHAL_STM32H563_USART2_BASE 0x40004400 #define WHAL_STM32H563_USART2_DRIVER &whal_Stm32h5_Uart_Driver -#define WHAL_STM32H563_USART3_REGMAP \ - .base = 0x40004800, \ - .size = 0x400 +#define WHAL_STM32H563_USART3_BASE 0x40004800 #define WHAL_STM32H563_USART3_DRIVER &whal_Stm32h5_Uart_Driver /* --- Clock gate macros --- */ @@ -132,16 +122,12 @@ /* SPI device macros */ -#define WHAL_STM32H563_SPI1_REGMAP \ - .base = 0x40013000, \ - .size = 0x400 +#define WHAL_STM32H563_SPI1_BASE 0x40013000 #define WHAL_STM32H563_SPI1_DRIVER &whal_Stm32h5_Spi_Driver /* RNG device macros */ -#define WHAL_STM32H563_RNG_REGMAP \ - .base = 0x420C0800, \ - .size = 0x400 +#define WHAL_STM32H563_RNG_BASE 0x420C0800 #define WHAL_STM32H563_RNG_DRIVER &whal_Stm32h5_Rng_Driver /* RCC_AHB2ENR (offset 0x08C), bit 18 */ @@ -152,9 +138,7 @@ /* Flash device macros */ -#define WHAL_STM32H563_FLASH_REGMAP \ - .base = 0x40022000, \ - .size = 0x400 +#define WHAL_STM32H563_FLASH_BASE 0x40022000 #define WHAL_STM32H563_FLASH_DRIVER &whal_Stm32h5_Flash_Driver /* RCC_APB3ENR (offset 0x0A8), bit 1 */ @@ -165,9 +149,7 @@ /* Ethernet device macros */ -#define WHAL_STM32H563_ETH_REGMAP \ - .base = 0x40028000, \ - .size = 0x1200 +#define WHAL_STM32H563_ETH_BASE 0x40028000 #define WHAL_STM32H563_ETH_DRIVER &whal_Stm32h5_Eth_Driver /* RCC_AHB1ENR (offset 0x088), bit 19 */ diff --git a/wolfHAL/platform/st/stm32l152re.h b/wolfHAL/platform/st/stm32l152re.h index fa74832..82289cd 100644 --- a/wolfHAL/platform/st/stm32l152re.h +++ b/wolfHAL/platform/st/stm32l152re.h @@ -31,73 +31,45 @@ /* --- Device macros --- */ -#define WHAL_STM32L152_RCC_REGMAP \ - .base = 0x40023800, \ - .size = 0x400 +#define WHAL_STM32L152_RCC_BASE 0x40023800 -#define WHAL_STM32L152_GPIO_REGMAP \ - .base = 0x40020000, \ - .size = 0x2000 +#define WHAL_STM32L152_GPIO_BASE 0x40020000 #define WHAL_STM32L152_GPIO_DRIVER &whal_Stm32l1_Gpio_Driver -#define WHAL_STM32L152_USART1_REGMAP \ - .base = 0x40013800, \ - .size = 0x400 +#define WHAL_STM32L152_USART1_BASE 0x40013800 #define WHAL_STM32L152_USART1_DRIVER &whal_Stm32l1_Uart_Driver -#define WHAL_STM32L152_USART2_REGMAP \ - .base = 0x40004400, \ - .size = 0x400 +#define WHAL_STM32L152_USART2_BASE 0x40004400 #define WHAL_STM32L152_USART2_DRIVER &whal_Stm32l1_Uart_Driver -#define WHAL_STM32L152_USART3_REGMAP \ - .base = 0x40004800, \ - .size = 0x400 +#define WHAL_STM32L152_USART3_BASE 0x40004800 #define WHAL_STM32L152_USART3_DRIVER &whal_Stm32l1_Uart_Driver -#define WHAL_STM32L152_SPI1_REGMAP \ - .base = 0x40013000, \ - .size = 0x400 +#define WHAL_STM32L152_SPI1_BASE 0x40013000 #define WHAL_STM32L152_SPI1_DRIVER &whal_Stm32l1_Spi_Driver -#define WHAL_STM32L152_SPI2_REGMAP \ - .base = 0x40003800, \ - .size = 0x400 +#define WHAL_STM32L152_SPI2_BASE 0x40003800 #define WHAL_STM32L152_SPI2_DRIVER &whal_Stm32l1_Spi_Driver -#define WHAL_STM32L152_SPI3_REGMAP \ - .base = 0x40003C00, \ - .size = 0x400 +#define WHAL_STM32L152_SPI3_BASE 0x40003C00 #define WHAL_STM32L152_SPI3_DRIVER &whal_Stm32l1_Spi_Driver -#define WHAL_STM32L152_I2C1_REGMAP \ - .base = 0x40005400, \ - .size = 0x400 +#define WHAL_STM32L152_I2C1_BASE 0x40005400 #define WHAL_STM32L152_I2C1_DRIVER &whal_Stm32l1_I2c_Driver -#define WHAL_STM32L152_I2C2_REGMAP \ - .base = 0x40005800, \ - .size = 0x400 +#define WHAL_STM32L152_I2C2_BASE 0x40005800 #define WHAL_STM32L152_I2C2_DRIVER &whal_Stm32l1_I2c_Driver -#define WHAL_STM32L152_FLASH_REGMAP \ - .base = 0x40023C00, \ - .size = 0x400 +#define WHAL_STM32L152_FLASH_BASE 0x40023C00 #define WHAL_STM32L152_FLASH_DRIVER &whal_Stm32l1_Flash_Driver -#define WHAL_STM32L152_IWDG_REGMAP \ - .base = 0x40003000, \ - .size = 0x400 +#define WHAL_STM32L152_IWDG_BASE 0x40003000 #define WHAL_STM32L152_IWDG_DRIVER &whal_Stm32l1_Iwdg_Driver -#define WHAL_STM32L152_WWDG_REGMAP \ - .base = 0x40002C00, \ - .size = 0x400 +#define WHAL_STM32L152_WWDG_BASE 0x40002C00 #define WHAL_STM32L152_WWDG_DRIVER &whal_Stm32l1_Wwdg_Driver -#define WHAL_STM32L152_PWR_REGMAP \ - .base = 0x40007000, \ - .size = 0x400 +#define WHAL_STM32L152_PWR_BASE 0x40007000 /* --- Clock gate macros --- */ diff --git a/wolfHAL/platform/st/stm32n657a0.h b/wolfHAL/platform/st/stm32n657a0.h index 0ed18b7..42ce45c 100644 --- a/wolfHAL/platform/st/stm32n657a0.h +++ b/wolfHAL/platform/st/stm32n657a0.h @@ -41,78 +41,48 @@ /* --- Regmap and driver macros --- */ -#define WHAL_STM32N657_RCC_REGMAP \ - .base = 0x46028000, \ - .size = 0x800 +#define WHAL_STM32N657_RCC_BASE 0x46028000 -#define WHAL_STM32N657_GPIO_REGMAP \ - .base = 0x46020000, \ - .size = 0x4400 +#define WHAL_STM32N657_GPIO_BASE 0x46020000 #define WHAL_STM32N657_GPIO_DRIVER &whal_Stm32n6_Gpio_Driver -#define WHAL_STM32N657_USART1_REGMAP \ - .base = 0x42001000, \ - .size = 0x400 +#define WHAL_STM32N657_USART1_BASE 0x42001000 #define WHAL_STM32N657_USART1_DRIVER &whal_Stm32n6_Uart_Driver -#define WHAL_STM32N657_USART2_REGMAP \ - .base = 0x40004400, \ - .size = 0x400 +#define WHAL_STM32N657_USART2_BASE 0x40004400 #define WHAL_STM32N657_USART2_DRIVER &whal_Stm32n6_Uart_Driver -#define WHAL_STM32N657_USART3_REGMAP \ - .base = 0x40004800, \ - .size = 0x400 +#define WHAL_STM32N657_USART3_BASE 0x40004800 #define WHAL_STM32N657_USART3_DRIVER &whal_Stm32n6_Uart_Driver -#define WHAL_STM32N657_SPI1_REGMAP \ - .base = 0x42003000, \ - .size = 0x400 +#define WHAL_STM32N657_SPI1_BASE 0x42003000 #define WHAL_STM32N657_SPI1_DRIVER &whal_Stm32n6_Spi_Driver -#define WHAL_STM32N657_I2C1_REGMAP \ - .base = 0x40005400, \ - .size = 0x400 +#define WHAL_STM32N657_I2C1_BASE 0x40005400 #define WHAL_STM32N657_I2C1_DRIVER &whal_Stm32n6_I2c_Driver -#define WHAL_STM32N657_I2C4_REGMAP \ - .base = 0x46001C00, \ - .size = 0x400 +#define WHAL_STM32N657_I2C4_BASE 0x46001C00 #define WHAL_STM32N657_I2C4_DRIVER &whal_Stm32n6_I2c_Driver -#define WHAL_STM32N657_RNG_REGMAP \ - .base = 0x44020000, \ - .size = 0x400 +#define WHAL_STM32N657_RNG_BASE 0x44020000 #define WHAL_STM32N657_RNG_DRIVER &whal_Stm32n6_Rng_Driver -#define WHAL_STM32N657_CRYP_REGMAP \ - .base = 0x44020800, \ - .size = 0x400 +#define WHAL_STM32N657_CRYP_BASE 0x44020800 #define WHAL_STM32N657_CRYP_DRIVER &whal_Stm32n6_Cryp_Driver -#define WHAL_STM32N657_HASH_REGMAP \ - .base = 0x44020400, \ - .size = 0x400 +#define WHAL_STM32N657_HASH_BASE 0x44020400 #define WHAL_STM32N657_HASH_DRIVER &whal_Stm32n6_Hash_Driver -#define WHAL_STM32N657_GPDMA1_REGMAP \ - .base = 0x40021000, \ - .size = 0x1000 +#define WHAL_STM32N657_GPDMA1_BASE 0x40021000 #define WHAL_STM32N657_GPDMA1_DRIVER &whal_Stm32n6_Gpdma_Driver -#define WHAL_STM32N657_IWDG_REGMAP \ - .base = 0x46004800, \ - .size = 0x400 +#define WHAL_STM32N657_IWDG_BASE 0x46004800 #define WHAL_STM32N657_IWDG_DRIVER &whal_Stm32n6_Iwdg_Driver -#define WHAL_STM32N657_WWDG_REGMAP \ - .base = 0x40002C00, \ - .size = 0x400 +#define WHAL_STM32N657_WWDG_BASE 0x40002C00 #define WHAL_STM32N657_WWDG_DRIVER &whal_Stm32n6_Wwdg_Driver -#define WHAL_STM32N657_ETH_REGMAP \ - .base = 0x48036000, \ - .size = 0x2000 +#define WHAL_STM32N657_ETH_BASE 0x48036000 #define WHAL_STM32N657_ETH_DRIVER &whal_Stm32n6_Eth_Driver /* --- Clock gate macros --- */ diff --git a/wolfHAL/platform/st/stm32wb55xx.h b/wolfHAL/platform/st/stm32wb55xx.h index 6baf1d6..a8debed 100644 --- a/wolfHAL/platform/st/stm32wb55xx.h +++ b/wolfHAL/platform/st/stm32wb55xx.h @@ -21,73 +21,45 @@ * @brief Convenience initializers for STM32WB55xx device instances. */ -#define WHAL_STM32WB55_LPUART1_REGMAP \ - .base = 0x40008000, \ - .size = 0x400 +#define WHAL_STM32WB55_LPUART1_BASE 0x40008000 #define WHAL_STM32WB55_LPUART1_DRIVER &whal_Stm32wb_Uart_Driver -#define WHAL_STM32WB55_SPI1_REGMAP \ - .base = 0x40013000, \ - .size = 0x400 +#define WHAL_STM32WB55_SPI1_BASE 0x40013000 #define WHAL_STM32WB55_SPI1_DRIVER &whal_Stm32wb_Spi_Driver -#define WHAL_STM32WB55_UART1_REGMAP \ - .base = 0x40013800, \ - .size = 0x400 +#define WHAL_STM32WB55_UART1_BASE 0x40013800 #define WHAL_STM32WB55_UART1_DRIVER &whal_Stm32wb_Uart_Driver -#define WHAL_STM32WB55_GPIO_REGMAP \ - .base = 0x48000000, \ - .size = 0x400 +#define WHAL_STM32WB55_GPIO_BASE 0x48000000 #define WHAL_STM32WB55_GPIO_DRIVER &whal_Stm32wb_Gpio_Driver -#define WHAL_STM32WB55_RCC_REGMAP \ - .base = 0x58000000, \ - .size = 0x400 +#define WHAL_STM32WB55_RCC_BASE 0x58000000 -#define WHAL_STM32WB55_RNG_REGMAP \ - .base = 0x58001000, \ - .size = 0x400 +#define WHAL_STM32WB55_RNG_BASE 0x58001000 #define WHAL_STM32WB55_RNG_DRIVER &whal_Stm32wb_Rng_Driver -#define WHAL_STM32WB55_AES1_REGMAP \ - .base = 0x50060000, \ - .size = 0x400 +#define WHAL_STM32WB55_AES1_BASE 0x50060000 #define WHAL_STM32WB55_AES1_DRIVER &whal_Stm32wb_Aes_Driver -#define WHAL_STM32WB55_I2C1_REGMAP \ - .base = 0x40005400, \ - .size = 0x400 +#define WHAL_STM32WB55_I2C1_BASE 0x40005400 #define WHAL_STM32WB55_I2C1_DRIVER &whal_Stm32wb_I2c_Driver -#define WHAL_STM32WB55_I2C3_REGMAP \ - .base = 0x40005C00, \ - .size = 0x400 +#define WHAL_STM32WB55_I2C3_BASE 0x40005C00 #define WHAL_STM32WB55_I2C3_DRIVER &whal_Stm32wb_I2c_Driver -#define WHAL_STM32WB55_IWDG_REGMAP \ - .base = 0x40003000, \ - .size = 0x400 +#define WHAL_STM32WB55_IWDG_BASE 0x40003000 #define WHAL_STM32WB55_IWDG_DRIVER &whal_Stm32wb_Iwdg_Driver -#define WHAL_STM32WB55_WWDG_REGMAP \ - .base = 0x40002C00, \ - .size = 0x400 +#define WHAL_STM32WB55_WWDG_BASE 0x40002C00 #define WHAL_STM32WB55_WWDG_DRIVER &whal_Stm32wb_Wwdg_Driver -#define WHAL_STM32WB55_FLASH_REGMAP \ - .base = 0x58004000, \ - .size = 0x400 +#define WHAL_STM32WB55_FLASH_BASE 0x58004000 #define WHAL_STM32WB55_FLASH_DRIVER &whal_Stm32wb_Flash_Driver -#define WHAL_STM32WB55_DMA1_REGMAP \ - .base = 0x40020000, \ - .size = 0x400 +#define WHAL_STM32WB55_DMA1_BASE 0x40020000 #define WHAL_STM32WB55_DMA1_DRIVER &whal_Stm32wb_Dma_Driver -#define WHAL_STM32WB55_DMA2_REGMAP \ - .base = 0x40020400, \ - .size = 0x400 +#define WHAL_STM32WB55_DMA2_BASE 0x40020400 #define WHAL_STM32WB55_DMA2_DRIVER &whal_Stm32wb_Dma_Driver #define WHAL_STM32WB55_DMA1_CFG \ diff --git a/wolfHAL/platform/st/stm32wba55cg.h b/wolfHAL/platform/st/stm32wba55cg.h index a49027a..b7fcc67 100644 --- a/wolfHAL/platform/st/stm32wba55cg.h +++ b/wolfHAL/platform/st/stm32wba55cg.h @@ -34,78 +34,48 @@ /* --- Regmap and driver macros --- */ -#define WHAL_STM32WBA55_RCC_REGMAP \ - .base = 0x46020C00, \ - .size = 0x400 +#define WHAL_STM32WBA55_RCC_BASE 0x46020C00 -#define WHAL_STM32WBA55_GPIO_REGMAP \ - .base = 0x42020000, \ - .size = 0x2000 +#define WHAL_STM32WBA55_GPIO_BASE 0x42020000 #define WHAL_STM32WBA55_GPIO_DRIVER &whal_Stm32wba_Gpio_Driver -#define WHAL_STM32WBA55_USART1_REGMAP \ - .base = 0x40013800, \ - .size = 0x400 +#define WHAL_STM32WBA55_USART1_BASE 0x40013800 #define WHAL_STM32WBA55_USART1_DRIVER &whal_Stm32wba_Uart_Driver -#define WHAL_STM32WBA55_USART2_REGMAP \ - .base = 0x40004400, \ - .size = 0x400 +#define WHAL_STM32WBA55_USART2_BASE 0x40004400 #define WHAL_STM32WBA55_USART2_DRIVER &whal_Stm32wba_Uart_Driver -#define WHAL_STM32WBA55_LPUART1_REGMAP \ - .base = 0x46002400, \ - .size = 0x400 +#define WHAL_STM32WBA55_LPUART1_BASE 0x46002400 #define WHAL_STM32WBA55_LPUART1_DRIVER &whal_Stm32wba_Uart_Driver -#define WHAL_STM32WBA55_SPI1_REGMAP \ - .base = 0x40013000, \ - .size = 0x400 +#define WHAL_STM32WBA55_SPI1_BASE 0x40013000 #define WHAL_STM32WBA55_SPI1_DRIVER &whal_Stm32wba_Spi_Driver -#define WHAL_STM32WBA55_I2C1_REGMAP \ - .base = 0x40005400, \ - .size = 0x400 +#define WHAL_STM32WBA55_I2C1_BASE 0x40005400 #define WHAL_STM32WBA55_I2C1_DRIVER &whal_Stm32wba_I2c_Driver -#define WHAL_STM32WBA55_I2C3_REGMAP \ - .base = 0x46002800, \ - .size = 0x400 +#define WHAL_STM32WBA55_I2C3_BASE 0x46002800 #define WHAL_STM32WBA55_I2C3_DRIVER &whal_Stm32wba_I2c_Driver -#define WHAL_STM32WBA55_FLASH_REGMAP \ - .base = 0x40022000, \ - .size = 0x400 +#define WHAL_STM32WBA55_FLASH_BASE 0x40022000 #define WHAL_STM32WBA55_FLASH_DRIVER &whal_Stm32wba_Flash_Driver -#define WHAL_STM32WBA55_RNG_REGMAP \ - .base = 0x420C0800, \ - .size = 0x400 +#define WHAL_STM32WBA55_RNG_BASE 0x420C0800 #define WHAL_STM32WBA55_RNG_DRIVER &whal_Stm32wba_Rng_Driver -#define WHAL_STM32WBA55_GPDMA1_REGMAP \ - .base = 0x40020000, \ - .size = 0x1000 +#define WHAL_STM32WBA55_GPDMA1_BASE 0x40020000 #define WHAL_STM32WBA55_GPDMA1_DRIVER &whal_Stm32wba_Gpdma_Driver -#define WHAL_STM32WBA55_AES_REGMAP \ - .base = 0x420C0000, \ - .size = 0x400 +#define WHAL_STM32WBA55_AES_BASE 0x420C0000 #define WHAL_STM32WBA55_AES_DRIVER &whal_Stm32wba_Aes_Driver -#define WHAL_STM32WBA55_HASH_REGMAP \ - .base = 0x420C0400, \ - .size = 0x400 +#define WHAL_STM32WBA55_HASH_BASE 0x420C0400 #define WHAL_STM32WBA55_HASH_DRIVER &whal_Stm32wba_Hash_Driver -#define WHAL_STM32WBA55_IWDG_REGMAP \ - .base = 0x40003000, \ - .size = 0x400 +#define WHAL_STM32WBA55_IWDG_BASE 0x40003000 #define WHAL_STM32WBA55_IWDG_DRIVER &whal_Stm32wba_Iwdg_Driver -#define WHAL_STM32WBA55_WWDG_REGMAP \ - .base = 0x40002C00, \ - .size = 0x400 +#define WHAL_STM32WBA55_WWDG_BASE 0x40002C00 #define WHAL_STM32WBA55_WWDG_DRIVER &whal_Stm32wba_Wwdg_Driver /* --- Clock gate macros --- */ diff --git a/wolfHAL/power/pic32cz_supc.h b/wolfHAL/power/pic32cz_supc.h index 6404bf6..9ba2660 100644 --- a/wolfHAL/power/pic32cz_supc.h +++ b/wolfHAL/power/pic32cz_supc.h @@ -3,6 +3,7 @@ #include #include +#include #include /* diff --git a/wolfHAL/power/power.h b/wolfHAL/power/power.h index 137c04b..8c5e7e1 100644 --- a/wolfHAL/power/power.h +++ b/wolfHAL/power/power.h @@ -1,7 +1,7 @@ #ifndef WHAL_POWER_H #define WHAL_POWER_H -#include +#include /* * @file power.h @@ -17,7 +17,7 @@ * Board_() wrappers. */ typedef struct { - const whal_Regmap regmap; + const size_t base; } whal_Power; #endif /* WHAL_POWER_H */ diff --git a/wolfHAL/regmap.h b/wolfHAL/regmap.h index e53a0a4..2d9d10d 100644 --- a/wolfHAL/regmap.h +++ b/wolfHAL/regmap.h @@ -11,14 +11,6 @@ * @brief Helpers for accessing and manipulating memory-mapped registers. */ -/* - * @brief Description of a contiguous register map. - */ -typedef struct whal_Regmap { - size_t base; - size_t size; -} whal_Regmap; - /* * @brief Update a masked field within a memory-mapped register. * diff --git a/wolfHAL/rng/rng.h b/wolfHAL/rng/rng.h index 5386162..9f065e1 100644 --- a/wolfHAL/rng/rng.h +++ b/wolfHAL/rng/rng.h @@ -3,7 +3,6 @@ #include #include -#include #include /* @@ -29,7 +28,7 @@ typedef struct { * @brief RNG device instance tying a register map and driver. */ struct whal_Rng { - const whal_Regmap regmap; + const size_t base; const whal_RngDriver *driver; void *cfg; }; diff --git a/wolfHAL/spi/spi.h b/wolfHAL/spi/spi.h index 3342829..5e72edd 100644 --- a/wolfHAL/spi/spi.h +++ b/wolfHAL/spi/spi.h @@ -2,7 +2,6 @@ #define WHAL_SPI_H #include -#include #include #include @@ -53,7 +52,7 @@ typedef struct { * @brief SPI device instance tying a register map and driver. */ struct whal_Spi { - const whal_Regmap regmap; + const size_t base; const whal_SpiDriver *driver; void *cfg; }; diff --git a/wolfHAL/timer/timer.h b/wolfHAL/timer/timer.h index 09297c9..8ae4ca8 100644 --- a/wolfHAL/timer/timer.h +++ b/wolfHAL/timer/timer.h @@ -2,7 +2,6 @@ #define WHAL_TIMER_H #include -#include #include /* @@ -32,7 +31,7 @@ typedef struct { * @brief Timer device instance pairing configuration with a driver. */ struct whal_Timer{ - const whal_Regmap regmap; + const size_t base; const whal_TimerDriver *driver; void *cfg; }; diff --git a/wolfHAL/uart/uart.h b/wolfHAL/uart/uart.h index 985fc78..0f42b8a 100644 --- a/wolfHAL/uart/uart.h +++ b/wolfHAL/uart/uart.h @@ -3,7 +3,6 @@ #include #include -#include #include /* @@ -35,7 +34,7 @@ typedef struct { * @brief UART device instance tying a register map and driver. */ struct whal_Uart { - const whal_Regmap regmap; + const size_t base; const whal_UartDriver *driver; void *cfg; }; diff --git a/wolfHAL/watchdog/stm32wb_iwdg.h b/wolfHAL/watchdog/stm32wb_iwdg.h index 2c5a881..b7b457b 100644 --- a/wolfHAL/watchdog/stm32wb_iwdg.h +++ b/wolfHAL/watchdog/stm32wb_iwdg.h @@ -3,6 +3,7 @@ #include #include +#include #include /* diff --git a/wolfHAL/watchdog/watchdog.h b/wolfHAL/watchdog/watchdog.h index 62a0840..08d88d3 100644 --- a/wolfHAL/watchdog/watchdog.h +++ b/wolfHAL/watchdog/watchdog.h @@ -2,7 +2,6 @@ #define WHAL_WATCHDOG_H #include -#include #include #include @@ -34,7 +33,7 @@ typedef struct { * @brief Watchdog device instance tying a register map and driver. */ struct whal_Watchdog { - const whal_Regmap regmap; + const size_t base; const whal_WatchdogDriver *driver; void *cfg; }; From e7845519409431eb39e15cad714fbf3e8e625787 Mon Sep 17 00:00:00 2001 From: Alex Lanzano Date: Tue, 5 May 2026 15:02:06 -0400 Subject: [PATCH 3/7] [regmap] move whal_Reg_ReadPoll out of the regmap.h and into regmap.c --- src/regmap.c | 16 ++++++++++++++++ wolfHAL/regmap.h | 17 +++-------------- 2 files changed, 19 insertions(+), 14 deletions(-) create mode 100644 src/regmap.c diff --git a/src/regmap.c b/src/regmap.c new file mode 100644 index 0000000..cee4ada --- /dev/null +++ b/src/regmap.c @@ -0,0 +1,16 @@ +#include + +whal_Error whal_Reg_ReadPoll(size_t base, size_t offset, + size_t mask, size_t value, + whal_Timeout *timeout) +{ +#ifdef WHAL_CFG_NO_TIMEOUT + (void)(timeout); +#endif + WHAL_TIMEOUT_START(timeout); + while ((whal_Reg_Read(base, offset) & mask) != value) { + if (WHAL_TIMEOUT_EXPIRED(timeout)) + return WHAL_ETIMEOUT; + } + return WHAL_SUCCESS; +} diff --git a/wolfHAL/regmap.h b/wolfHAL/regmap.h index 2d9d10d..68e10de 100644 --- a/wolfHAL/regmap.h +++ b/wolfHAL/regmap.h @@ -83,19 +83,8 @@ static inline size_t whal_Reg_Read(size_t base, size_t offset) * @param value Expected value of the masked field. * @param timeout Timeout instance (NULL for unbounded wait). */ -static inline whal_Error whal_Reg_ReadPoll(size_t base, size_t offset, - size_t mask, size_t value, - whal_Timeout *timeout) -{ -#ifdef WHAL_CFG_NO_TIMEOUT - (void)(timeout); -#endif - WHAL_TIMEOUT_START(timeout); - while ((whal_Reg_Read(base, offset) & mask) != value) { - if (WHAL_TIMEOUT_EXPIRED(timeout)) - return WHAL_ETIMEOUT; - } - return WHAL_SUCCESS; -} +whal_Error whal_Reg_ReadPoll(size_t base, size_t offset, + size_t mask, size_t value, + whal_Timeout *timeout); #endif /* WHAL_REGMAP_H */ From 78054480c799d842a911c82be1b3eb6ec47113bb Mon Sep 17 00:00:00 2001 From: Alex Lanzano Date: Tue, 5 May 2026 15:34:25 -0400 Subject: [PATCH 4/7] [boards] use -Os and other code size trimming compiler flags in board.mk --- boards/pic32cz_curiosity_ultra/board.mk | 4 ++-- boards/stm32c031_nucleo/board.mk | 4 ++-- boards/stm32f091rc_nucleo/board.mk | 4 ++-- boards/stm32f302r8_nucleo/board.mk | 4 ++-- boards/stm32f411_blackpill/board.mk | 4 ++-- boards/stm32h563zi_nucleo/board.mk | 4 ++-- boards/stm32l152re_nucleo/board.mk | 4 ++-- boards/stm32n657a0_nucleo/board.mk | 4 ++-- boards/stm32wb55xx_nucleo/board.mk | 4 ++-- boards/stm32wba55cg_nucleo/board.mk | 4 ++-- 10 files changed, 20 insertions(+), 20 deletions(-) diff --git a/boards/pic32cz_curiosity_ultra/board.mk b/boards/pic32cz_curiosity_ultra/board.mk index fb50b23..b28b7b8 100644 --- a/boards/pic32cz_curiosity_ultra/board.mk +++ b/boards/pic32cz_curiosity_ultra/board.mk @@ -7,13 +7,13 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ +CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m7 \ -DPLATFORM_PIC32CZ -MMD -MP \ -DWHAL_CFG_PIC32CZ_GPIO_DIRECT_API_MAPPING \ -DWHAL_CFG_PIC32CZ_CLOCK_DIRECT_API_MAPPING \ -DWHAL_CFG_PIC32CZ_UART_DIRECT_API_MAPPING -LDFLAGS = --omagic -static +LDFLAGS = --omagic -static --gc-sections LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld diff --git a/boards/stm32c031_nucleo/board.mk b/boards/stm32c031_nucleo/board.mk index b9628c3..eccdc9b 100644 --- a/boards/stm32c031_nucleo/board.mk +++ b/boards/stm32c031_nucleo/board.mk @@ -7,7 +7,7 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-gcc OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ +CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m0plus -mthumb \ -DPLATFORM_STM32C0 -MMD -MP \ -DWHAL_CFG_STM32C0_GPIO_DIRECT_API_MAPPING \ @@ -15,7 +15,7 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ -DWHAL_CFG_STM32C0_UART_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32C0_SPI_DIRECT_API_MAPPING LDFLAGS = -mcpu=cortex-m0plus -mthumb -ffreestanding -nostartfiles \ - -Wl,--omagic -static + -Wl,--omagic -Wl,--gc-sections -static LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld diff --git a/boards/stm32f091rc_nucleo/board.mk b/boards/stm32f091rc_nucleo/board.mk index feebe41..f8d972c 100644 --- a/boards/stm32f091rc_nucleo/board.mk +++ b/boards/stm32f091rc_nucleo/board.mk @@ -7,7 +7,7 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-gcc OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ +CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m0 -mthumb \ -DPLATFORM_STM32F0 -MMD -MP \ -DWHAL_CFG_STM32F0_GPIO_DIRECT_API_MAPPING \ @@ -17,7 +17,7 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ -DWHAL_CFG_STM32F0_I2C_DIRECT_API_MAPPING \ $(if $(filter iwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_IWDG) LDFLAGS = -mcpu=cortex-m0 -mthumb -ffreestanding -nostartfiles \ - -Wl,--omagic -static + -Wl,--omagic -Wl,--gc-sections -static LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld diff --git a/boards/stm32f302r8_nucleo/board.mk b/boards/stm32f302r8_nucleo/board.mk index e448b3d..8736e48 100644 --- a/boards/stm32f302r8_nucleo/board.mk +++ b/boards/stm32f302r8_nucleo/board.mk @@ -7,7 +7,7 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-gcc OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ +CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib \ -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 \ -DPLATFORM_STM32F3 -MMD -MP \ @@ -19,7 +19,7 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ $(if $(filter iwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_IWDG) \ $(if $(filter wwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_WWDG) LDFLAGS = -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 \ - -ffreestanding -nostartfiles -Wl,--omagic -static + -ffreestanding -nostartfiles -Wl,--omagic -Wl,--gc-sections -static LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld diff --git a/boards/stm32f411_blackpill/board.mk b/boards/stm32f411_blackpill/board.mk index 087846d..e9f49b4 100644 --- a/boards/stm32f411_blackpill/board.mk +++ b/boards/stm32f411_blackpill/board.mk @@ -7,7 +7,7 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ +CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m4 -mfloat-abi=hard \ -mfpu=fpv4-sp-d16 -mthumb \ -DPLATFORM_STM32F4 -MMD -MP \ @@ -15,7 +15,7 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ -DWHAL_CFG_STM32F4_RCC_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32F4_UART_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32F4_SPI_DIRECT_API_MAPPING -LDFLAGS = --omagic -static +LDFLAGS = --omagic -static --gc-sections LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld diff --git a/boards/stm32h563zi_nucleo/board.mk b/boards/stm32h563zi_nucleo/board.mk index 5d0fcfd..a0a6365 100644 --- a/boards/stm32h563zi_nucleo/board.mk +++ b/boards/stm32h563zi_nucleo/board.mk @@ -7,7 +7,7 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ +CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m33 \ -DPLATFORM_STM32H5 -MMD -MP \ -DWHAL_CFG_STM32H5_GPIO_DIRECT_API_MAPPING \ @@ -18,7 +18,7 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ -DWHAL_CFG_STM32H5_RNG_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32H5_ETH_DIRECT_API_MAPPING \ -DWHAL_CFG_LAN8742A_ETH_PHY_DIRECT_API_MAPPING -LDFLAGS = --omagic -static +LDFLAGS = --omagic -static --gc-sections LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld diff --git a/boards/stm32l152re_nucleo/board.mk b/boards/stm32l152re_nucleo/board.mk index 026be6b..ce84336 100644 --- a/boards/stm32l152re_nucleo/board.mk +++ b/boards/stm32l152re_nucleo/board.mk @@ -7,7 +7,7 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-gcc OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ +CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib \ -mcpu=cortex-m3 -mthumb \ -DPLATFORM_STM32L1 -MMD -MP \ @@ -19,7 +19,7 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ $(if $(filter iwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_IWDG) \ $(if $(filter wwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_WWDG) LDFLAGS = -mcpu=cortex-m3 -mthumb \ - -ffreestanding -nostartfiles -Wl,--omagic -static + -ffreestanding -nostartfiles -Wl,--omagic -Wl,--gc-sections -static LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld diff --git a/boards/stm32n657a0_nucleo/board.mk b/boards/stm32n657a0_nucleo/board.mk index fe29b02..6b078c9 100644 --- a/boards/stm32n657a0_nucleo/board.mk +++ b/boards/stm32n657a0_nucleo/board.mk @@ -7,7 +7,7 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ +CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m55 -mthumb \ -DPLATFORM_STM32N6 -MMD -MP \ $(if $(DMA),-DBOARD_DMA) \ @@ -29,7 +29,7 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ -DWHAL_CFG_CRYPTO_SHA1 -DWHAL_CFG_CRYPTO_SHA224 \ -DWHAL_CFG_CRYPTO_SHA256 -DWHAL_CFG_CRYPTO_HMAC_SHA1 \ -DWHAL_CFG_CRYPTO_HMAC_SHA224 -DWHAL_CFG_CRYPTO_HMAC_SHA256 -LDFLAGS = --omagic -static +LDFLAGS = --omagic -static --gc-sections LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld diff --git a/boards/stm32wb55xx_nucleo/board.mk b/boards/stm32wb55xx_nucleo/board.mk index 01c1396..e1d58a4 100644 --- a/boards/stm32wb55xx_nucleo/board.mk +++ b/boards/stm32wb55xx_nucleo/board.mk @@ -7,7 +7,7 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ +CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m4 \ -DPLATFORM_STM32WB -MMD -MP \ $(if $(DMA),-DBOARD_DMA) \ @@ -24,7 +24,7 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ -DWHAL_CFG_CRYPTO_AES_ECB -DWHAL_CFG_CRYPTO_AES_CBC \ -DWHAL_CFG_CRYPTO_AES_CTR -DWHAL_CFG_CRYPTO_AES_GCM \ -DWHAL_CFG_CRYPTO_AES_GMAC -DWHAL_CFG_CRYPTO_AES_CCM -LDFLAGS = --omagic -static +LDFLAGS = --omagic -static --gc-sections LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld diff --git a/boards/stm32wba55cg_nucleo/board.mk b/boards/stm32wba55cg_nucleo/board.mk index efa5ebd..28f2b54 100644 --- a/boards/stm32wba55cg_nucleo/board.mk +++ b/boards/stm32wba55cg_nucleo/board.mk @@ -7,7 +7,7 @@ GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy -CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ +CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m33 -mthumb \ -DPLATFORM_STM32WBA -MMD -MP \ -DWHAL_CFG_STM32WBA_RCC_PLL_DRIVER \ @@ -20,7 +20,7 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 \ -DWHAL_CFG_CRYPTO_SHA1 -DWHAL_CFG_CRYPTO_SHA224 \ -DWHAL_CFG_CRYPTO_SHA256 -DWHAL_CFG_CRYPTO_HMAC_SHA1 \ -DWHAL_CFG_CRYPTO_HMAC_SHA224 -DWHAL_CFG_CRYPTO_HMAC_SHA256 -LDFLAGS = --omagic -static +LDFLAGS = --omagic -static --gc-sections LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld From c85c2db24bc751dcafbffd76d8c0fbba1372db9a Mon Sep 17 00:00:00 2001 From: Alex Lanzano Date: Wed, 6 May 2026 17:42:14 -0400 Subject: [PATCH 5/7] [crypto] Refactor crypto interface and drivers --- .claude/skills/port-stm32-platform/SKILL.md | 4 +- boards/stm32n657a0_nucleo/board.c | 79 +- boards/stm32n657a0_nucleo/board.h | 14 + boards/stm32n657a0_nucleo/board.mk | 20 +- boards/stm32wb55xx_nucleo/board.c | 38 +- boards/stm32wb55xx_nucleo/board.h | 6 + boards/stm32wb55xx_nucleo/board.mk | 14 +- boards/stm32wba55cg_nucleo/board.c | 86 +- boards/stm32wba55cg_nucleo/board.h | 14 + boards/stm32wba55cg_nucleo/board.mk | 22 +- docs/writing_a_driver.md | 438 +++++- src/clock/clock.c | 7 - src/crypto/aes_cbc.c | 28 + src/crypto/aes_ccm.c | 42 + src/crypto/aes_ctr.c | 28 + src/crypto/aes_ecb.c | 26 + src/crypto/aes_gcm.c | 40 + src/crypto/aes_gmac.c | 13 + src/crypto/crypto.c | 54 +- src/crypto/hmac_sha1.c | 35 + src/crypto/hmac_sha224.c | 35 + src/crypto/hmac_sha256.c | 35 + src/crypto/sha1.c | 31 + src/crypto/sha224.c | 32 + src/crypto/sha256.c | 32 + src/crypto/stm32n6_cryp.c | 1215 +++++++++++----- src/crypto/stm32wb_aes.c | 1430 +++++++++++++------ src/crypto/stm32wba_aes.c | 23 + src/crypto/stm32wba_hash.c | 987 ++++++++++--- tests/crypto/gen_test_vectors.py | 145 ++ tests/crypto/test_aes_cbc.c | 84 ++ tests/crypto/test_aes_ccm.c | 271 ++++ tests/crypto/test_aes_ctr.c | 84 ++ tests/crypto/test_aes_ecb.c | 74 + tests/crypto/test_aes_gcm.c | 324 +++++ tests/crypto/test_aes_gmac.c | 88 ++ tests/crypto/test_crypto.c | 724 +--------- tests/crypto/test_hmac_sha1.c | 89 ++ tests/crypto/test_hmac_sha224.c | 91 ++ tests/crypto/test_hmac_sha256.c | 91 ++ tests/crypto/test_sha1.c | 75 + tests/crypto/test_sha224.c | 78 + tests/crypto/test_sha256.c | 78 + tests/main.c | 96 ++ wolfHAL/crypto/crypto.h | 1166 +++++---------- wolfHAL/crypto/stm32n6_cryp.h | 428 +++++- wolfHAL/crypto/stm32n6_hash.h | 20 +- wolfHAL/crypto/stm32wb_aes.h | 413 +++++- wolfHAL/crypto/stm32wba_aes.h | 22 +- wolfHAL/crypto/stm32wba_hash.h | 404 +++++- wolfHAL/platform/st/stm32n657a0.h | 2 - wolfHAL/platform/st/stm32wb55xx.h | 2 +- wolfHAL/platform/st/stm32wba55cg.h | 2 - 53 files changed, 6862 insertions(+), 2817 deletions(-) delete mode 100644 src/clock/clock.c create mode 100644 src/crypto/aes_cbc.c create mode 100644 src/crypto/aes_ccm.c create mode 100644 src/crypto/aes_ctr.c create mode 100644 src/crypto/aes_ecb.c create mode 100644 src/crypto/aes_gcm.c create mode 100644 src/crypto/aes_gmac.c create mode 100644 src/crypto/hmac_sha1.c create mode 100644 src/crypto/hmac_sha224.c create mode 100644 src/crypto/hmac_sha256.c create mode 100644 src/crypto/sha1.c create mode 100644 src/crypto/sha224.c create mode 100644 src/crypto/sha256.c create mode 100644 tests/crypto/gen_test_vectors.py create mode 100644 tests/crypto/test_aes_cbc.c create mode 100644 tests/crypto/test_aes_ccm.c create mode 100644 tests/crypto/test_aes_ctr.c create mode 100644 tests/crypto/test_aes_ecb.c create mode 100644 tests/crypto/test_aes_gcm.c create mode 100644 tests/crypto/test_aes_gmac.c create mode 100644 tests/crypto/test_hmac_sha1.c create mode 100644 tests/crypto/test_hmac_sha224.c create mode 100644 tests/crypto/test_hmac_sha256.c create mode 100644 tests/crypto/test_sha1.c create mode 100644 tests/crypto/test_sha224.c create mode 100644 tests/crypto/test_sha256.c diff --git a/.claude/skills/port-stm32-platform/SKILL.md b/.claude/skills/port-stm32-platform/SKILL.md index a6d7055..e020440 100644 --- a/.claude/skills/port-stm32-platform/SKILL.md +++ b/.claude/skills/port-stm32-platform/SKILL.md @@ -51,7 +51,9 @@ For each device type, decide **reuse existing driver (with alias)** OR **write a The clock driver is almost always new per family. GPIO, I2C, and IWDG/WWDG are almost always reusable. UART, flash, RNG, DMA require careful diffing. -**Clock is the architectural exception.** Unlike every other driver type, the clock subsystem has no `whal_ClockDriver` vtable and no generic `whal_Clock_Init`/`Enable`/`Disable` API. Chip clock drivers expose imperative `Enable*`/`Disable*`/`Set*` helpers (e.g. `whal__Rcc_EnableOsc`, `EnablePll`, `SetSysClock`, `EnablePeriphClk`) and boards call them directly. See `docs/writing_a_driver.md` "Clock" section. The platform header does NOT define a `WHAL__RCC_DRIVER` macro, and the chip's `g_whalClock` global has only `.base = ...` — no `.driver`, no `.cfg`. Reference: `wolfHAL/clock/stm32wb_rcc.h` and `boards/stm32wb55xx_nucleo/board.c`. +**Clock is an architectural exception.** Unlike most driver types, the clock subsystem has no `whal_ClockDriver` vtable and no generic `whal_Clock_Init`/`Enable`/`Disable` API. Chip clock drivers expose imperative `Enable*`/`Disable*`/`Set*` helpers (e.g. `whal__Rcc_EnableOsc`, `EnablePll`, `SetSysClock`, `EnablePeriphClk`) and boards call them directly. See `docs/writing_a_driver.md` "Clock" section. The platform header does NOT define a `WHAL__RCC_DRIVER` macro, and the chip's `g_whalClock` global has only `.base = ...` — no `.driver`, no `.cfg`. Reference: `wolfHAL/clock/stm32wb_rcc.h` and `boards/stm32wb55xx_nucleo/board.c`. + +**Crypto is also an architectural exception.** Crypto uses per-algorithm device structs (`whal_AesGcm`, `whal_Sha256`, etc.) instead of a single `whal_Crypto` with generic dispatch. Each algo struct has `.crypto` (pointer to the hardware device), `.driver` (per-algo vtable with Oneshot/Start/Process/Finalize), and `.state` (driver-managed streaming state). `whal_Crypto` itself is a platform driver with just Init/Deinit for hardware lifecycle. Direct API mapping is per-algorithm (e.g. `WHAL_CFG_STM32WB_AES_GCM_DIRECT_API_MAPPING`), not per-device-type. See `docs/writing_a_driver.md` "Crypto" section. Reference: `wolfHAL/crypto/stm32wb_aes.h` and `wolfHAL/crypto/stm32wba_hash.h`. ## Phase 2 — Platform header diff --git a/boards/stm32n657a0_nucleo/board.c b/boards/stm32n657a0_nucleo/board.c index d73d5dd..59c346e 100644 --- a/boards/stm32n657a0_nucleo/board.c +++ b/boards/stm32n657a0_nucleo/board.c @@ -239,23 +239,98 @@ whal_Rng g_whalRng = { /* Crypto (CRYP hardware accelerator) */ whal_Crypto g_whalCrypto = { .base = WHAL_STM32N657_CRYP_BASE, - .driver = WHAL_STM32N657_CRYP_DRIVER, + .driver = &whal_Stm32n6_Cryp_CryptoDriver, .cfg = &(whal_Stm32n6_Cryp_Cfg) { .timeout = &g_whalTimeout, }, }; +whal_AesEcb g_whalAesEcb = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ +}; + +whal_AesCbc g_whalAesCbc = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ +}; + +whal_AesCtr g_whalAesCtr = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ +}; + +static whal_Stm32n6_AesGcm_State g_aesGcmState; + +whal_AesGcm g_whalAesGcm = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ + .state = &g_aesGcmState, +}; + +whal_AesGmac g_whalAesGmac = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ +}; + +static whal_Stm32n6_AesCcm_State g_aesCcmState; + +whal_AesCcm g_whalAesCcm = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ + .state = &g_aesCcmState, +}; + /* Hash (HASH hardware accelerator) */ whal_Crypto g_whalHash = { .base = WHAL_STM32N657_HASH_BASE, - .driver = WHAL_STM32N657_HASH_DRIVER, + .driver = &whal_Stm32n6_Hash_CryptoDriver, .cfg = &(whal_Stm32n6_Hash_Cfg) { .timeout = &g_whalTimeout, }, }; +whal_Sha1 g_whalSha1 = { + .crypto = &g_whalHash, + /* .driver: direct API mapping */ +}; + +whal_Sha224 g_whalSha224 = { + .crypto = &g_whalHash, + /* .driver: direct API mapping */ +}; + +whal_Sha256 g_whalSha256 = { + .crypto = &g_whalHash, + /* .driver: direct API mapping */ +}; + +static whal_Stm32n6_HmacSha1_State g_hmacSha1State; + +whal_HmacSha1 g_whalHmacSha1 = { + .crypto = &g_whalHash, + /* .driver: direct API mapping */ + .state = &g_hmacSha1State, +}; + +static whal_Stm32n6_HmacSha224_State g_hmacSha224State; + +whal_HmacSha224 g_whalHmacSha224 = { + .crypto = &g_whalHash, + /* .driver: direct API mapping */ + .state = &g_hmacSha224State, +}; + +static whal_Stm32n6_HmacSha256_State g_hmacSha256State; + +whal_HmacSha256 g_whalHmacSha256 = { + .crypto = &g_whalHash, + /* .driver: direct API mapping */ + .state = &g_hmacSha256State, +}; + #ifdef BOARD_WATCHDOG_IWDG whal_Watchdog g_whalWatchdog = { .base = WHAL_STM32N657_IWDG_BASE, diff --git a/boards/stm32n657a0_nucleo/board.h b/boards/stm32n657a0_nucleo/board.h index 5751bb4..e349226 100644 --- a/boards/stm32n657a0_nucleo/board.h +++ b/boards/stm32n657a0_nucleo/board.h @@ -4,6 +4,8 @@ #include #include #include +#include +#include extern whal_Clock g_whalClock; extern whal_Gpio g_whalGpio; @@ -13,7 +15,19 @@ extern whal_Spi g_whalSpi; extern whal_Rng g_whalRng; extern whal_I2c g_whalI2c; extern whal_Crypto g_whalCrypto; +extern whal_AesEcb g_whalAesEcb; +extern whal_AesCbc g_whalAesCbc; +extern whal_AesCtr g_whalAesCtr; +extern whal_AesGcm g_whalAesGcm; +extern whal_AesGmac g_whalAesGmac; +extern whal_AesCcm g_whalAesCcm; extern whal_Crypto g_whalHash; +extern whal_Sha1 g_whalSha1; +extern whal_Sha224 g_whalSha224; +extern whal_Sha256 g_whalSha256; +extern whal_HmacSha1 g_whalHmacSha1; +extern whal_HmacSha224 g_whalHmacSha224; +extern whal_HmacSha256 g_whalHmacSha256; extern whal_Irq g_whalIrq; extern whal_Watchdog g_whalWatchdog; extern whal_Eth g_whalEth; diff --git a/boards/stm32n657a0_nucleo/board.mk b/boards/stm32n657a0_nucleo/board.mk index 6b078c9..01b39cd 100644 --- a/boards/stm32n657a0_nucleo/board.mk +++ b/boards/stm32n657a0_nucleo/board.mk @@ -1,7 +1,7 @@ _BOARD_DIR := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST)))) PLATFORM = stm32n6 -TESTS ?= clock gpio timer rng eth uart spi i2c irq crypto +TESTS ?= clock gpio timer rng eth uart spi i2c irq crypto aes_ecb aes_cbc aes_ctr aes_gcm aes_gmac aes_ccm sha1 sha224 sha256 hmac_sha1 hmac_sha224 hmac_sha256 GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld @@ -23,12 +23,18 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -DWHAL_CFG_STM32N6_GPDMA_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32N6_ETH_DIRECT_API_MAPPING \ -DWHAL_CFG_LAN8742A_ETH_PHY_DIRECT_API_MAPPING \ - -DWHAL_CFG_CRYPTO_AES_ECB -DWHAL_CFG_CRYPTO_AES_CBC \ - -DWHAL_CFG_CRYPTO_AES_CTR -DWHAL_CFG_CRYPTO_AES_GCM \ - -DWHAL_CFG_CRYPTO_AES_GMAC -DWHAL_CFG_CRYPTO_AES_CCM \ - -DWHAL_CFG_CRYPTO_SHA1 -DWHAL_CFG_CRYPTO_SHA224 \ - -DWHAL_CFG_CRYPTO_SHA256 -DWHAL_CFG_CRYPTO_HMAC_SHA1 \ - -DWHAL_CFG_CRYPTO_HMAC_SHA224 -DWHAL_CFG_CRYPTO_HMAC_SHA256 + -DWHAL_CFG_STM32N6_CRYP_ECB_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32N6_CRYP_CBC_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32N6_CRYP_CTR_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32N6_CRYP_GCM_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32N6_CRYP_GMAC_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32N6_CRYP_CCM_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32N6_HASH_SHA1_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32N6_HASH_SHA224_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32N6_HASH_SHA256_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32N6_HASH_HMAC_SHA1_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32N6_HASH_HMAC_SHA224_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32N6_HASH_HMAC_SHA256_DIRECT_API_MAPPING LDFLAGS = --omagic -static --gc-sections LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld diff --git a/boards/stm32wb55xx_nucleo/board.c b/boards/stm32wb55xx_nucleo/board.c index 5f25420..df76bbb 100644 --- a/boards/stm32wb55xx_nucleo/board.c +++ b/boards/stm32wb55xx_nucleo/board.c @@ -221,12 +221,47 @@ whal_Rng g_whalRng = { whal_Crypto g_whalCrypto = { .base = WHAL_STM32WB55_AES1_BASE, /* .driver: direct API mapping */ - .cfg = &(whal_Stm32wb_Aes_Cfg) { .timeout = &g_whalTimeout, }, }; +whal_AesEcb g_whalAesEcb = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ +}; + +whal_AesCbc g_whalAesCbc = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ +}; + +whal_AesCtr g_whalAesCtr = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ +}; + +static whal_Stm32wb_AesGcm_State g_aesGcmState; + +whal_AesGcm g_whalAesGcm = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ + .state = &g_aesGcmState, +}; + +whal_AesGmac g_whalAesGmac = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ +}; + +static whal_Stm32wb_AesCcm_State g_aesCcmState; + +whal_AesCcm g_whalAesCcm = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ + .state = &g_aesCcmState, +}; + #ifdef BOARD_WATCHDOG_IWDG whal_Watchdog g_whalWatchdog = { .base = WHAL_STM32WB55_IWDG_BASE, @@ -401,6 +436,7 @@ whal_Error Board_Deinit(void) return err; } + err = whal_Crypto_Deinit(&g_whalCrypto); if (err) { return err; diff --git a/boards/stm32wb55xx_nucleo/board.h b/boards/stm32wb55xx_nucleo/board.h index e3ae039..16c928d 100644 --- a/boards/stm32wb55xx_nucleo/board.h +++ b/boards/stm32wb55xx_nucleo/board.h @@ -13,6 +13,12 @@ extern whal_Spi g_whalSpi; extern whal_Flash g_whalFlash; extern whal_Rng g_whalRng; extern whal_Crypto g_whalCrypto; +extern whal_AesEcb g_whalAesEcb; +extern whal_AesCbc g_whalAesCbc; +extern whal_AesCtr g_whalAesCtr; +extern whal_AesGcm g_whalAesGcm; +extern whal_AesGmac g_whalAesGmac; +extern whal_AesCcm g_whalAesCcm; extern whal_I2c g_whalI2c; extern whal_Irq g_whalIrq; extern whal_Watchdog g_whalWatchdog; diff --git a/boards/stm32wb55xx_nucleo/board.mk b/boards/stm32wb55xx_nucleo/board.mk index e1d58a4..1e606e2 100644 --- a/boards/stm32wb55xx_nucleo/board.mk +++ b/boards/stm32wb55xx_nucleo/board.mk @@ -1,7 +1,7 @@ _BOARD_DIR := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST)))) PLATFORM = stm32wb -TESTS ?= clock gpio flash timer rng crypto block uart i2c dma irq +TESTS ?= clock gpio flash timer rng crypto aes_ecb aes_cbc aes_ctr aes_gcm aes_gmac aes_ccm block uart i2c dma irq GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld @@ -20,10 +20,13 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -DWHAL_CFG_STM32WB_RCC_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32WB_RNG_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32WB_DMA_DIRECT_API_MAPPING \ - -DWHAL_CFG_STM32WB_AES_DIRECT_API_MAPPING \ - -DWHAL_CFG_CRYPTO_AES_ECB -DWHAL_CFG_CRYPTO_AES_CBC \ - -DWHAL_CFG_CRYPTO_AES_CTR -DWHAL_CFG_CRYPTO_AES_GCM \ - -DWHAL_CFG_CRYPTO_AES_GMAC -DWHAL_CFG_CRYPTO_AES_CCM + -DWHAL_CFG_STM32WB_AES_INIT_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32WB_AES_ECB_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32WB_AES_CBC_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32WB_AES_CTR_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32WB_AES_GCM_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32WB_AES_GMAC_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32WB_AES_CCM_DIRECT_API_MAPPING LDFLAGS = --omagic -static --gc-sections LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld @@ -33,7 +36,6 @@ INCLUDE += -I$(_BOARD_DIR) -I$(WHAL_DIR)/boards/peripheral BOARD_SOURCE = $(_BOARD_DIR)/ivt.c BOARD_SOURCE += $(_BOARD_DIR)/board.c BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*.c) -BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/crypto.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/timer.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/flash.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/sensor.c) diff --git a/boards/stm32wba55cg_nucleo/board.c b/boards/stm32wba55cg_nucleo/board.c index 815db56..5deefd4 100644 --- a/boards/stm32wba55cg_nucleo/board.c +++ b/boards/stm32wba55cg_nucleo/board.c @@ -233,23 +233,97 @@ whal_Rng g_whalRng = { /* Crypto (AES hardware accelerator) */ whal_Crypto g_whalCrypto = { .base = WHAL_STM32WBA55_AES_BASE, - .driver = WHAL_STM32WBA55_AES_DRIVER, .cfg = &(whal_Stm32wba_Aes_Cfg) { .timeout = &g_whalTimeout, }, }; +whal_AesEcb g_whalAesEcb = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ +}; + +whal_AesCbc g_whalAesCbc = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ +}; + +whal_AesCtr g_whalAesCtr = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ +}; + +static whal_Stm32wba_AesGcm_State g_aesGcmState; + +whal_AesGcm g_whalAesGcm = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ + .state = &g_aesGcmState, +}; + +whal_AesGmac g_whalAesGmac = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ +}; + +static whal_Stm32wba_AesCcm_State g_aesCcmState; + +whal_AesCcm g_whalAesCcm = { + .crypto = &g_whalCrypto, + /* .driver: direct API mapping */ + .state = &g_aesCcmState, +}; + /* Hash (HASH hardware accelerator) */ whal_Crypto g_whalHash = { .base = WHAL_STM32WBA55_HASH_BASE, - .driver = WHAL_STM32WBA55_HASH_DRIVER, + .driver = &whal_Stm32wba_Hash_CryptoDriver, .cfg = &(whal_Stm32wba_Hash_Cfg) { .timeout = &g_whalTimeout, }, }; +whal_Sha1 g_whalSha1 = { + .crypto = &g_whalHash, + /* .driver: direct API mapping */ +}; + +whal_Sha224 g_whalSha224 = { + .crypto = &g_whalHash, + /* .driver: direct API mapping */ +}; + +whal_Sha256 g_whalSha256 = { + .crypto = &g_whalHash, + /* .driver: direct API mapping */ +}; + +static whal_Stm32wba_HmacSha1_State g_hmacSha1State; + +whal_HmacSha1 g_whalHmacSha1 = { + .crypto = &g_whalHash, + /* .driver: direct API mapping */ + .state = &g_hmacSha1State, +}; + +static whal_Stm32wba_HmacSha224_State g_hmacSha224State; + +whal_HmacSha224 g_whalHmacSha224 = { + .crypto = &g_whalHash, + /* .driver: direct API mapping */ + .state = &g_hmacSha224State, +}; + +static whal_Stm32wba_HmacSha256_State g_hmacSha256State; + +whal_HmacSha256 g_whalHmacSha256 = { + .crypto = &g_whalHash, + /* .driver: direct API mapping */ + .state = &g_hmacSha256State, +}; + #ifdef BOARD_WATCHDOG_IWDG whal_Watchdog g_whalWatchdog = { .base = WHAL_STM32WBA55_IWDG_BASE, @@ -421,10 +495,6 @@ whal_Error Board_Init(void) if (err) return err; - err = whal_Crypto_Init(&g_whalCrypto); - if (err) - return err; - err = whal_Crypto_Init(&g_whalHash); if (err) return err; @@ -464,10 +534,6 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Crypto_Deinit(&g_whalCrypto); - if (err) - return err; - err = whal_Rng_Deinit(&g_whalRng); if (err) return err; diff --git a/boards/stm32wba55cg_nucleo/board.h b/boards/stm32wba55cg_nucleo/board.h index b520446..de040f6 100644 --- a/boards/stm32wba55cg_nucleo/board.h +++ b/boards/stm32wba55cg_nucleo/board.h @@ -4,6 +4,8 @@ #include #include #include +#include +#include extern whal_Clock g_whalClock; extern whal_Gpio g_whalGpio; @@ -14,7 +16,19 @@ extern whal_Flash g_whalFlash; extern whal_Rng g_whalRng; extern whal_I2c g_whalI2c; extern whal_Crypto g_whalCrypto; +extern whal_AesEcb g_whalAesEcb; +extern whal_AesCbc g_whalAesCbc; +extern whal_AesCtr g_whalAesCtr; +extern whal_AesGcm g_whalAesGcm; +extern whal_AesGmac g_whalAesGmac; +extern whal_AesCcm g_whalAesCcm; extern whal_Crypto g_whalHash; +extern whal_Sha1 g_whalSha1; +extern whal_Sha224 g_whalSha224; +extern whal_Sha256 g_whalSha256; +extern whal_HmacSha1 g_whalHmacSha1; +extern whal_HmacSha224 g_whalHmacSha224; +extern whal_HmacSha256 g_whalHmacSha256; extern whal_Irq g_whalIrq; extern whal_Watchdog g_whalWatchdog; #ifdef BOARD_DMA diff --git a/boards/stm32wba55cg_nucleo/board.mk b/boards/stm32wba55cg_nucleo/board.mk index 28f2b54..4e9fd86 100644 --- a/boards/stm32wba55cg_nucleo/board.mk +++ b/boards/stm32wba55cg_nucleo/board.mk @@ -1,7 +1,7 @@ _BOARD_DIR := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST)))) PLATFORM = stm32wba -TESTS ?= clock gpio flash timer rng crypto uart spi i2c irq +TESTS ?= clock gpio flash timer rng crypto aes_ecb aes_cbc aes_ctr aes_gcm aes_gmac aes_ccm sha1 sha224 sha256 hmac_sha1 hmac_sha224 hmac_sha256 uart spi i2c irq GCC = $(GCC_PATH)arm-none-eabi-gcc LD = $(GCC_PATH)arm-none-eabi-ld @@ -11,15 +11,21 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m33 -mthumb \ -DPLATFORM_STM32WBA -MMD -MP \ -DWHAL_CFG_STM32WBA_RCC_PLL_DRIVER \ + -DWHAL_CFG_STM32WBA_AES_ECB_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32WBA_AES_CBC_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32WBA_AES_CTR_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32WBA_AES_GCM_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32WBA_AES_GMAC_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32WBA_AES_CCM_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32WBA_HASH_SHA1_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32WBA_HASH_SHA224_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32WBA_HASH_SHA256_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32WBA_HASH_HMAC_SHA1_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32WBA_HASH_HMAC_SHA224_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32WBA_HASH_HMAC_SHA256_DIRECT_API_MAPPING \ $(if $(DMA),-DBOARD_DMA) \ $(if $(filter iwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_IWDG) \ - $(if $(filter wwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_WWDG) \ - -DWHAL_CFG_CRYPTO_AES_ECB -DWHAL_CFG_CRYPTO_AES_CBC \ - -DWHAL_CFG_CRYPTO_AES_CTR -DWHAL_CFG_CRYPTO_AES_GCM \ - -DWHAL_CFG_CRYPTO_AES_GMAC -DWHAL_CFG_CRYPTO_AES_CCM \ - -DWHAL_CFG_CRYPTO_SHA1 -DWHAL_CFG_CRYPTO_SHA224 \ - -DWHAL_CFG_CRYPTO_SHA256 -DWHAL_CFG_CRYPTO_HMAC_SHA1 \ - -DWHAL_CFG_CRYPTO_HMAC_SHA224 -DWHAL_CFG_CRYPTO_HMAC_SHA256 + $(if $(filter wwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_WWDG) LDFLAGS = --omagic -static --gc-sections LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld diff --git a/docs/writing_a_driver.md b/docs/writing_a_driver.md index c3a3f25..b1673d4 100644 --- a/docs/writing_a_driver.md +++ b/docs/writing_a_driver.md @@ -953,12 +953,22 @@ consumption and avoid unnecessary entropy source wear. Header: `wolfHAL/crypto/crypto.h` -The crypto driver provides access to hardware cryptographic accelerators -(ciphers, hashes, MACs, and public key operations). The driver vtable uses a -unified **StartOp / Process / EndOp** pattern that supports both one-shot and -streaming use cases. +The crypto subsystem provides access to hardware cryptographic accelerators +(ciphers, hashes, MACs). Unlike other device types, crypto uses a two-level +device model: a **hardware device** (`whal_Crypto`) for peripheral lifecycle, +and **per-algorithm device structs** (`whal_AesGcm`, `whal_Sha256`, etc.) +that carry typed vtables with direct function arguments. -### Device Struct +### Architecture + +`whal_Crypto` is a platform driver representing a crypto hardware peripheral. +It provides only `Init` and `Deinit` for hardware lifecycle (enable/disable +the peripheral, clear error flags). Each algorithm gets its own typed device +struct that references the underlying `whal_Crypto` and a per-algorithm +driver vtable. There is no `opId`, no `void*` casting, and no args structs +in the dispatch path. + +### Hardware Device ```c struct whal_Crypto { @@ -966,91 +976,407 @@ struct whal_Crypto { const whal_CryptoDriver *driver; const void *cfg; }; + +typedef struct { + whal_Error (*Init)(whal_Crypto *dev); + whal_Error (*Deinit)(whal_Crypto *dev); +} whal_CryptoDriver; ``` -### Driver Vtable +The board must enable the peripheral clock before calling `whal_Crypto_Init`. +`whal_Crypto_Deinit` disables the crypto accelerator peripheral. + +### Per-Algorithm Device Structs + +Each algorithm has its own device struct with a typed vtable. The struct +shape varies by algorithm category: + +**Block ciphers (ECB, CBC, CTR)** — no streaming state needed: + +```c +struct whal_AesCbc { + whal_Crypto *crypto; + const whal_AesCbcDriver *driver; +}; +``` + +**AEAD modes (GCM, CCM) and HMAC** — streaming state for multi-phase ops: + +```c +struct whal_AesGcm { + whal_Crypto *crypto; + const whal_AesGcmDriver *driver; + void *state; +}; +``` + +**Hash algorithms (SHA-1, SHA-224, SHA-256)** — no streaming state (the +hardware retains intermediate context internally): + +```c +struct whal_Sha256 { + whal_Crypto *crypto; + const whal_Sha256Driver *driver; +}; +``` + +The `.crypto` field points to the underlying hardware device. The `.driver` +field points to the per-algorithm vtable. The `.state` field, when present, +points to a driver-defined struct that the driver uses to carry data between +streaming phases (e.g., accumulated AAD/data sizes for GCM's final GHASH, or +the HMAC key for the outer hash pass). + +### Per-Algorithm Vtables + +Each algorithm defines a vtable with typed function pointers. The available +operations depend on the algorithm category: + +**Block ciphers** have `Oneshot`, `Start`, and `Process`: ```c typedef struct { - whal_Error (*Init)(whal_Crypto *cryptoDev); - whal_Error (*Deinit)(whal_Crypto *cryptoDev); - whal_Error (*StartOp)(whal_Crypto *cryptoDev, size_t opId, void *opArgs); - whal_Error (*Process)(whal_Crypto *cryptoDev, size_t opId, void *opArgs); - whal_Error (*EndOp)(whal_Crypto *cryptoDev, size_t opId, void *opArgs); -} whal_CryptoDriver; + whal_Error (*Oneshot)(whal_AesCbc *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, + const void *in, void *out, size_t sz); + whal_Error (*Start)(whal_AesCbc *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv); + whal_Error (*Process)(whal_AesCbc *dev, + const void *in, void *out, size_t sz); +} whal_AesCbcDriver; +``` + +**AEAD modes** add `Finalize` for tag generation: + +```c +typedef struct { + whal_Error (*Oneshot)(whal_AesGcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz, + const void *in, void *out, size_t sz, + void *tag, size_t tagSz); + whal_Error (*Start)(whal_AesGcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz); + whal_Error (*Process)(whal_AesGcm *dev, + const void *in, void *out, size_t sz); + whal_Error (*Finalize)(whal_AesGcm *dev, + void *tag, size_t tagSz); +} whal_AesGcmDriver; ``` -The `opId` parameter is a framework-defined enum value (e.g. `WHAL_CRYPTO_AES_GCM`, -`WHAL_CRYPTO_SHA256`). The `opArgs` parameter is a pointer to an -algorithm-specific argument struct (e.g., `whal_Crypto_AesGcmArgs`, -`whal_Crypto_HashArgs`). The driver casts it to the correct type based on -`opId`. See `wolfHAL/crypto/crypto.h` for the full set of argument structs and -operation IDs. +**Hash algorithms** have `Oneshot`, `Start`, `Process`, and `Finalize`: + +```c +typedef struct { + whal_Error (*Oneshot)(whal_Sha256 *dev, + const void *in, size_t inSz, + void *digest, size_t digestSz); + whal_Error (*Start)(whal_Sha256 *dev); + whal_Error (*Process)(whal_Sha256 *dev, const void *in, size_t inSz); + whal_Error (*Finalize)(whal_Sha256 *dev, void *digest, size_t digestSz); +} whal_Sha256Driver; +``` -### Init / Deinit +**HMAC** adds key parameters to `Oneshot` and `Start`: -The board must enable the peripheral clock before calling Init. Deinit should -disable the crypto accelerator peripheral. +```c +typedef struct { + whal_Error (*Oneshot)(whal_HmacSha256 *dev, + const void *key, size_t keySz, + const void *in, size_t inSz, + void *digest, size_t digestSz); + whal_Error (*Start)(whal_HmacSha256 *dev, + const void *key, size_t keySz); + whal_Error (*Process)(whal_HmacSha256 *dev, + const void *in, size_t inSz); + whal_Error (*Finalize)(whal_HmacSha256 *dev, + void *digest, size_t digestSz); +} whal_HmacSha256Driver; +``` + +**Oneshot-only algorithms** (e.g., GMAC) have only `Oneshot`: + +```c +typedef struct { + whal_Error (*Oneshot)(whal_AesGmac *dev, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz, + void *tag, size_t tagSz); +} whal_AesGmacDriver; +``` ### Operations -Each crypto operation is split into three phases: +- **Oneshot** — Performs the entire operation in a single call. Handles key + loading, data processing, and finalization internally. +- **Start** — Begin a streaming session. Load the key (and IV/AAD for modes + that need them). For AEAD modes, this covers the init and header phases. +- **Process** — Feed data through an active session. May be called multiple + times. For block ciphers this processes blocks of ciphertext/plaintext. + For hash/HMAC this feeds message data. +- **Finalize** — End a streaming session and produce the final output (tag + for AEAD, digest for hash/HMAC). Only present on algorithms that need a + finalization step. Block ciphers (ECB, CBC, CTR) do not have Finalize + because each Process call produces complete output. + +Unsupported parameter combinations (e.g. AES-192 on hardware that only +supports 128/256) return `WHAL_ENOTSUP`. + +### The .state Field + +AEAD (GCM, CCM) and HMAC device structs include a `void *state` field that +points to a driver-defined struct. The driver uses this to carry data between +`Start`, `Process`, and `Finalize` calls. For example: + +- **AES-GCM**: e.g. `whal_Stm32wb_AesGcm_State` tracks accumulated AAD and + data sizes for the final-phase GHASH computation. +- **AES-CCM**: e.g. `whal_Stm32wb_AesCcm_State` tracks accumulated AAD and + data sizes for tag construction. +- **HMAC**: driver-specific state retains the key pointer for the outer hash + pass (e.g., `whal_Stm32wba_HmacSha256_State`). + +Block ciphers and plain hash algorithms do not need `.state` because the +hardware retains all necessary context internally. + +### API Usage + +One-shot: + +```c +whal_AesGcm_Oneshot(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, + key, 32, iv, 12, aad, aadSz, + pt, ct, ptSz, tag, 16); +``` + +Streaming (AEAD): + +```c +whal_AesGcm_Start(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, + key, 32, iv, 12, aad, aadSz); +whal_AesGcm_Process(&g_whalAesGcm, chunk1, out1, chunk1Sz); +whal_AesGcm_Process(&g_whalAesGcm, chunk2, out2, chunk2Sz); +whal_AesGcm_Finalize(&g_whalAesGcm, tag, 16); +``` + +Streaming (hash): -- **StartOp** — Configure hardware, load key/IV, process AAD for AEAD modes. -- **Process** — Feed data through the hardware. May be called multiple times - for streaming. Optional for single-shot operations (e.g. GMAC has no - payload). -- **EndOp** — Finalize the operation, read output (tag, digest), release - hardware. On StartOp failure, the driver cleans up internally and EndOp - should not be called. +```c +whal_Sha256_Start(&g_whalSha256); +whal_Sha256_Process(&g_whalSha256, chunk1, chunk1Sz); +whal_Sha256_Process(&g_whalSha256, chunk2, chunk2Sz); +whal_Sha256_Finalize(&g_whalSha256, digest, 32); +``` + +Streaming (block cipher): + +```c +whal_AesCbc_Start(&g_whalAesCbc, WHAL_CRYPTO_ENCRYPT, key, 32, iv); +whal_AesCbc_Process(&g_whalAesCbc, block1, out1, 16); +whal_AesCbc_Process(&g_whalAesCbc, block2, out2, 16); +``` + +### Writing a Crypto Driver + +A single platform driver file typically implements multiple algorithms that +share the same hardware peripheral. For example, `stm32wb_aes.c` implements +AES-ECB, AES-CBC, AES-CTR, AES-GCM, AES-GMAC, and AES-CCM. Functions for +all operations of a single algorithm should be grouped together, not spread +by operation type. + +The driver must: + +1. Implement the `whal_CryptoDriver` vtable (`Init`/`Deinit`) for the + hardware peripheral. +2. Implement per-algorithm vtables for each supported algorithm. +3. Define any streaming state structs needed for AEAD/HMAC. + +#### Hardware Init/Deinit + +These go through the `whal_CryptoDriver` vtable on `whal_Crypto`. They +handle peripheral enable/disable, clearing error flags, etc. + +```c +whal_Error whal_Myplatform_Aes_Init(whal_Crypto *dev) +{ + /* Enable peripheral, clear flags */ +} + +whal_Error whal_Myplatform_Aes_Deinit(whal_Crypto *dev) +{ + /* Disable peripheral */ +} +``` + +#### Per-Algorithm Functions + +Each algorithm function receives the per-algorithm device struct. To access +hardware registers, dereference `dev->crypto->base`. To access the config, +cast `dev->crypto->cfg`. + +```c +whal_Error whal_Myplatform_AesGcm_Oneshot(whal_AesGcm *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz, + const void *in, void *out, size_t sz, + void *tag, size_t tagSz) +{ + size_t base = dev->crypto->base; + whal_Myplatform_Aes_Cfg *cfg = + (whal_Myplatform_Aes_Cfg *)dev->crypto->cfg; + /* Load key, IV, process AAD, encrypt/decrypt, compute tag */ +} +``` + +For streaming state, the driver reads and writes `dev->state`: + +```c +whal_Error whal_Myplatform_AesGcm_Start(whal_AesGcm *dev, ...) +{ + whal_Myplatform_AesGcm_State *st = (whal_Myplatform_AesGcm_State *)dev->state; + st->aadSz = aadSz; + st->dataSz = 0; + /* Load key, IV, process AAD header */ +} + +whal_Error whal_Myplatform_AesGcm_Process(whal_AesGcm *dev, + const void *in, void *out, size_t sz) +{ + whal_Myplatform_AesGcm_State *st = (whal_Myplatform_AesGcm_State *)dev->state; + st->dataSz += sz; + /* Process payload blocks */ +} -Unsupported `opId` values return `WHAL_ENOTSUP`. Unsupported parameter -combinations (e.g. AES-192 on hardware that only supports 128/256) also -return `WHAL_ENOTSUP`. +whal_Error whal_Myplatform_AesGcm_Finalize(whal_AesGcm *dev, + void *tag, size_t tagSz) +{ + whal_Myplatform_AesGcm_State *st = (whal_Myplatform_AesGcm_State *)dev->state; + /* Use st->aadSz and st->dataSz for final GHASH, produce tag */ +} +``` -### Convenience Wrappers +#### Vtable Definitions -`crypto.h` provides typed inline wrappers for each algorithm. One-shot -wrappers call all three phases in sequence: +Define one vtable per algorithm, plus one `whal_CryptoDriver` for +Init/Deinit. Wrap each in `#ifndef` for the corresponding direct API +mapping flag: ```c -whal_Crypto_AesGcmArgs args = { - .dir = WHAL_CRYPTO_ENCRYPT, .key = key, .keySz = 32, - .iv = iv, .ivSz = 12, - .in = plaintext, .out = ct, .sz = sizeof(plaintext), - .aad = aad, .aadSz = sizeof(aad), - .tag = tag, .tagSz = 16, +#ifndef WHAL_CFG_MYPLATFORM_AES_INIT_DIRECT_API_MAPPING +const whal_CryptoDriver whal_Myplatform_Aes_CryptoDriver = { + .Init = whal_Myplatform_Aes_Init, + .Deinit = whal_Myplatform_Aes_Deinit, }; -whal_Crypto_AesGcm(&g_whalCrypto, &args); +#endif + +#ifndef WHAL_CFG_MYPLATFORM_AES_GCM_DIRECT_API_MAPPING +const whal_AesGcmDriver whal_Myplatform_Aes_GcmDriver = { + .Oneshot = whal_Myplatform_AesGcm_Oneshot, + .Start = whal_Myplatform_AesGcm_Start, + .Process = whal_Myplatform_AesGcm_Process, + .Finalize = whal_Myplatform_AesGcm_Finalize, +}; +#endif ``` -Streaming wrappers expose each phase individually with typed parameters: +### Direct API Mapping + +Crypto uses per-algorithm direct API mapping flags. Each algorithm can be +independently mapped. The flags follow the pattern +`WHAL_CFG___DIRECT_API_MAPPING`: ```c -whal_Crypto_Sha256_Start(&g_whalHash); -whal_Crypto_Sha256_Update(&g_whalHash, chunk1, chunk1Sz); -whal_Crypto_Sha256_Update(&g_whalHash, chunk2, chunk2Sz); -whal_Crypto_Sha256_Finalize(&g_whalHash, digest, 32); +/* In the driver header */ +#ifdef WHAL_CFG_MYPLATFORM_AES_GCM_DIRECT_API_MAPPING +#define whal_Myplatform_AesGcm_Oneshot whal_AesGcm_Oneshot +#define whal_Myplatform_AesGcm_Start whal_AesGcm_Start +#define whal_Myplatform_AesGcm_Process whal_AesGcm_Process +#define whal_Myplatform_AesGcm_Finalize whal_AesGcm_Finalize +#endif + +#ifdef WHAL_CFG_MYPLATFORM_AES_INIT_DIRECT_API_MAPPING +#define whal_Myplatform_Aes_Init whal_Crypto_Init +#define whal_Myplatform_Aes_Deinit whal_Crypto_Deinit +#endif ``` -Both wrapper styles are guarded by `WHAL_CFG_CRYPTO_` defines (e.g. -`WHAL_CFG_CRYPTO_AES_GCM`, `WHAL_CFG_CRYPTO_SHA256`). +The Init/Deinit mapping maps to `whal_Crypto_Init`/`whal_Crypto_Deinit` +(the hardware device API). Each algorithm mapping maps to that algorithm's +top-level API (e.g., `whal_AesGcm_Oneshot`). + +### Adding a New Algorithm + +To add support for a new algorithm (e.g., ChaCha20-Poly1305): + +1. Add the per-algorithm device struct, vtable typedef, and API function + declarations to `wolfHAL/crypto/crypto.h`. Include a `.state` field if + the algorithm needs streaming state. +2. Add the dispatch functions to `src/crypto/crypto.c`. +3. Implement the vtable functions in the platform driver (e.g., + `src/crypto/myplatform_aes.c`). +4. Add direct API mapping guards in the driver header. +5. Add `WHAL_CFG_` config guards around the new API functions. ### Board Integration -The board enables supported algorithms via `-D` flags in `board.mk` and -instantiates the crypto device: +The board instantiates one `whal_Crypto` device per hardware peripheral, plus +one per-algorithm device for each algorithm it uses. The per-algorithm device +structs reference the `whal_Crypto` instance, the appropriate driver vtable, +and (for AEAD/HMAC) a state struct: ```c +/* Hardware device */ whal_Crypto g_whalCrypto = { - .base = WHAL_STM32WB55_AES1_BASE, - .cfg = &(whal_Stm32wb_Aes_Cfg) { .timeout = &g_whalTimeout }, + .base = WHAL_MYPLATFORM_AES1_BASE, + .driver = &whal_Myplatform_Aes_CryptoDriver, + .cfg = &(whal_Myplatform_Aes_Cfg) { .timeout = &g_whalTimeout }, +}; + +/* Block cipher — no state */ +whal_AesCbc g_whalAesCbc = { + .crypto = &g_whalCrypto, + .driver = &whal_Myplatform_Aes_CbcDriver, +}; + +/* AEAD — with state for streaming */ +static whal_Myplatform_AesGcm_State g_aesGcmState; +whal_AesGcm g_whalAesGcm = { + .crypto = &g_whalCrypto, + .driver = &whal_Myplatform_Aes_GcmDriver, + .state = &g_aesGcmState, +}; + +/* Hash — no state (hardware retains context) */ +whal_Sha256 g_whalSha256 = { + .crypto = &g_whalHash, + .driver = &whal_Myplatform_Hash_Sha256Driver, +}; + +/* HMAC — with driver-specific state */ +static whal_Myplatform_HmacSha256_State g_hmacState; +whal_HmacSha256 g_whalHmacSha256 = { + .crypto = &g_whalHash, + .driver = &whal_Myplatform_Hash_HmacSha256Driver, + .state = &g_hmacState, }; ``` -When API mapping is active (e.g. `-DWHAL_CFG_CRYPTO_API_MAPPING_STM32WB_AES`), -the driver functions are mapped directly to the top-level API, eliminating the -vtable indirection. +When direct API mapping is active for an algorithm, the `.driver` field is +omitted from that per-algorithm device. When Init/Deinit mapping is active, +the `.driver` field is omitted from the `whal_Crypto` device. + +### Reference Implementations + +- **AES (ECB/CBC/CTR/GCM/GMAC/CCM)**: `wolfHAL/crypto/stm32wb_aes.h` and + `src/crypto/stm32wb_aes.c` +- **Hash/HMAC (SHA-1/SHA-224/SHA-256, HMAC variants)**: + `wolfHAL/crypto/stm32wba_hash.h` and `src/crypto/stm32wba_hash.c` --- diff --git a/src/clock/clock.c b/src/clock/clock.c deleted file mode 100644 index e4c8650..0000000 --- a/src/clock/clock.c +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Intentionally empty. - * - * The generic clock API has been removed. clock.h now declares only the - * whal_Clock typed handle; each chip's clock driver provides imperative - * helpers in its own .c file. - */ diff --git a/src/crypto/aes_cbc.c b/src/crypto/aes_cbc.c new file mode 100644 index 0000000..7ccf77a --- /dev/null +++ b/src/crypto/aes_cbc.c @@ -0,0 +1,28 @@ +#include + +whal_Error whal_AesCbc_Oneshot(whal_AesCbc *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, + const void *in, void *out, size_t sz) +{ + if (!dev || !dev->driver || !dev->driver->Oneshot) + return WHAL_ENOTSUP; + return dev->driver->Oneshot(dev, dir, key, keySz, iv, in, out, sz); +} + +whal_Error whal_AesCbc_Start(whal_AesCbc *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv) +{ + if (!dev || !dev->driver || !dev->driver->Start) + return WHAL_ENOTSUP; + return dev->driver->Start(dev, dir, key, keySz, iv); +} + +whal_Error whal_AesCbc_Process(whal_AesCbc *dev, + const void *in, void *out, size_t sz) +{ + if (!dev || !dev->driver || !dev->driver->Process) + return WHAL_ENOTSUP; + return dev->driver->Process(dev, in, out, sz); +} diff --git a/src/crypto/aes_ccm.c b/src/crypto/aes_ccm.c new file mode 100644 index 0000000..f580e9e --- /dev/null +++ b/src/crypto/aes_ccm.c @@ -0,0 +1,42 @@ +#include + +whal_Error whal_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *nonce, size_t nonceSz, + const void *aad, size_t aadSz, + const void *in, void *out, size_t sz, + void *tag, size_t tagSz) +{ + if (!dev || !dev->driver || !dev->driver->Oneshot) + return WHAL_ENOTSUP; + return dev->driver->Oneshot(dev, dir, key, keySz, nonce, nonceSz, + aad, aadSz, in, out, sz, tag, tagSz); +} + +whal_Error whal_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *nonce, size_t nonceSz, + const void *aad, size_t aadSz, + size_t tagSz, size_t sz) +{ + if (!dev || !dev->driver || !dev->driver->Start) + return WHAL_ENOTSUP; + return dev->driver->Start(dev, dir, key, keySz, nonce, nonceSz, + aad, aadSz, tagSz, sz); +} + +whal_Error whal_AesCcm_Process(whal_AesCcm *dev, + const void *in, void *out, size_t sz) +{ + if (!dev || !dev->driver || !dev->driver->Process) + return WHAL_ENOTSUP; + return dev->driver->Process(dev, in, out, sz); +} + +whal_Error whal_AesCcm_Finalize(whal_AesCcm *dev, + void *tag, size_t tagSz) +{ + if (!dev || !dev->driver || !dev->driver->Finalize) + return WHAL_ENOTSUP; + return dev->driver->Finalize(dev, tag, tagSz); +} diff --git a/src/crypto/aes_ctr.c b/src/crypto/aes_ctr.c new file mode 100644 index 0000000..8f82c03 --- /dev/null +++ b/src/crypto/aes_ctr.c @@ -0,0 +1,28 @@ +#include + +whal_Error whal_AesCtr_Oneshot(whal_AesCtr *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, + const void *in, void *out, size_t sz) +{ + if (!dev || !dev->driver || !dev->driver->Oneshot) + return WHAL_ENOTSUP; + return dev->driver->Oneshot(dev, dir, key, keySz, iv, in, out, sz); +} + +whal_Error whal_AesCtr_Start(whal_AesCtr *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv) +{ + if (!dev || !dev->driver || !dev->driver->Start) + return WHAL_ENOTSUP; + return dev->driver->Start(dev, dir, key, keySz, iv); +} + +whal_Error whal_AesCtr_Process(whal_AesCtr *dev, + const void *in, void *out, size_t sz) +{ + if (!dev || !dev->driver || !dev->driver->Process) + return WHAL_ENOTSUP; + return dev->driver->Process(dev, in, out, sz); +} diff --git a/src/crypto/aes_ecb.c b/src/crypto/aes_ecb.c new file mode 100644 index 0000000..e74ab6a --- /dev/null +++ b/src/crypto/aes_ecb.c @@ -0,0 +1,26 @@ +#include + +whal_Error whal_AesEcb_Oneshot(whal_AesEcb *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *in, void *out, size_t sz) +{ + if (!dev || !dev->driver || !dev->driver->Oneshot) + return WHAL_ENOTSUP; + return dev->driver->Oneshot(dev, dir, key, keySz, in, out, sz); +} + +whal_Error whal_AesEcb_Start(whal_AesEcb *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz) +{ + if (!dev || !dev->driver || !dev->driver->Start) + return WHAL_ENOTSUP; + return dev->driver->Start(dev, dir, key, keySz); +} + +whal_Error whal_AesEcb_Process(whal_AesEcb *dev, + const void *in, void *out, size_t sz) +{ + if (!dev || !dev->driver || !dev->driver->Process) + return WHAL_ENOTSUP; + return dev->driver->Process(dev, in, out, sz); +} diff --git a/src/crypto/aes_gcm.c b/src/crypto/aes_gcm.c new file mode 100644 index 0000000..69928e7 --- /dev/null +++ b/src/crypto/aes_gcm.c @@ -0,0 +1,40 @@ +#include + +whal_Error whal_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz, + const void *in, void *out, size_t sz, + void *tag, size_t tagSz) +{ + if (!dev || !dev->driver || !dev->driver->Oneshot) + return WHAL_ENOTSUP; + return dev->driver->Oneshot(dev, dir, key, keySz, iv, ivSz, + aad, aadSz, in, out, sz, tag, tagSz); +} + +whal_Error whal_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz) +{ + if (!dev || !dev->driver || !dev->driver->Start) + return WHAL_ENOTSUP; + return dev->driver->Start(dev, dir, key, keySz, iv, ivSz, aad, aadSz); +} + +whal_Error whal_AesGcm_Process(whal_AesGcm *dev, + const void *in, void *out, size_t sz) +{ + if (!dev || !dev->driver || !dev->driver->Process) + return WHAL_ENOTSUP; + return dev->driver->Process(dev, in, out, sz); +} + +whal_Error whal_AesGcm_Finalize(whal_AesGcm *dev, + void *tag, size_t tagSz) +{ + if (!dev || !dev->driver || !dev->driver->Finalize) + return WHAL_ENOTSUP; + return dev->driver->Finalize(dev, tag, tagSz); +} diff --git a/src/crypto/aes_gmac.c b/src/crypto/aes_gmac.c new file mode 100644 index 0000000..f46646d --- /dev/null +++ b/src/crypto/aes_gmac.c @@ -0,0 +1,13 @@ +#include + +whal_Error whal_AesGmac_Oneshot(whal_AesGmac *dev, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz, + void *tag, size_t tagSz) +{ + if (!dev || !dev->driver || !dev->driver->Oneshot) + return WHAL_ENOTSUP; + return dev->driver->Oneshot(dev, key, keySz, iv, ivSz, + aad, aadSz, tag, tagSz); +} diff --git a/src/crypto/crypto.c b/src/crypto/crypto.c index eb4e80d..37e18d0 100644 --- a/src/crypto/crypto.c +++ b/src/crypto/crypto.c @@ -1,57 +1,19 @@ #include -#include -#ifndef WHAL_CFG_STM32WB_AES_DIRECT_API_MAPPING -whal_Error whal_Crypto_Init(whal_Crypto *cryptoDev) +whal_Error whal_Crypto_Init(whal_Crypto *dev) { - if (!cryptoDev) + if (!dev) return WHAL_EINVAL; - if (!cryptoDev->driver || !cryptoDev->driver->Init) + if (!dev->driver || !dev->driver->Init) return WHAL_ENOTSUP; - - return cryptoDev->driver->Init(cryptoDev); -} - -whal_Error whal_Crypto_Deinit(whal_Crypto *cryptoDev) -{ - if (!cryptoDev) - return WHAL_EINVAL; - if (!cryptoDev->driver || !cryptoDev->driver->Deinit) - return WHAL_ENOTSUP; - - return cryptoDev->driver->Deinit(cryptoDev); -} - -whal_Error whal_Crypto_StartOp(whal_Crypto *cryptoDev, size_t opId, - void *opArgs) -{ - if (!cryptoDev || !opArgs) - return WHAL_EINVAL; - if (!cryptoDev->driver || !cryptoDev->driver->StartOp) - return WHAL_ENOTSUP; - - return cryptoDev->driver->StartOp(cryptoDev, opId, opArgs); -} - -whal_Error whal_Crypto_Process(whal_Crypto *cryptoDev, size_t opId, - void *opArgs) -{ - if (!cryptoDev || !opArgs) - return WHAL_EINVAL; - if (!cryptoDev->driver || !cryptoDev->driver->Process) - return WHAL_ENOTSUP; - - return cryptoDev->driver->Process(cryptoDev, opId, opArgs); + return dev->driver->Init(dev); } -whal_Error whal_Crypto_EndOp(whal_Crypto *cryptoDev, size_t opId, - void *opArgs) +whal_Error whal_Crypto_Deinit(whal_Crypto *dev) { - if (!cryptoDev || !opArgs) + if (!dev) return WHAL_EINVAL; - if (!cryptoDev->driver || !cryptoDev->driver->EndOp) + if (!dev->driver || !dev->driver->Deinit) return WHAL_ENOTSUP; - - return cryptoDev->driver->EndOp(cryptoDev, opId, opArgs); + return dev->driver->Deinit(dev); } -#endif diff --git a/src/crypto/hmac_sha1.c b/src/crypto/hmac_sha1.c new file mode 100644 index 0000000..03f432a --- /dev/null +++ b/src/crypto/hmac_sha1.c @@ -0,0 +1,35 @@ +#include + +whal_Error whal_HmacSha1_Oneshot(whal_HmacSha1 *dev, + const void *key, size_t keySz, + const void *in, size_t inSz, + void *digest, size_t digestSz) +{ + if (!dev || !dev->driver || !dev->driver->Oneshot) + return WHAL_ENOTSUP; + return dev->driver->Oneshot(dev, key, keySz, in, inSz, digest, digestSz); +} + +whal_Error whal_HmacSha1_Start(whal_HmacSha1 *dev, + const void *key, size_t keySz) +{ + if (!dev || !dev->driver || !dev->driver->Start) + return WHAL_ENOTSUP; + return dev->driver->Start(dev, key, keySz); +} + +whal_Error whal_HmacSha1_Process(whal_HmacSha1 *dev, + const void *in, size_t inSz) +{ + if (!dev || !dev->driver || !dev->driver->Process) + return WHAL_ENOTSUP; + return dev->driver->Process(dev, in, inSz); +} + +whal_Error whal_HmacSha1_Finalize(whal_HmacSha1 *dev, + void *digest, size_t digestSz) +{ + if (!dev || !dev->driver || !dev->driver->Finalize) + return WHAL_ENOTSUP; + return dev->driver->Finalize(dev, digest, digestSz); +} diff --git a/src/crypto/hmac_sha224.c b/src/crypto/hmac_sha224.c new file mode 100644 index 0000000..7a1af8d --- /dev/null +++ b/src/crypto/hmac_sha224.c @@ -0,0 +1,35 @@ +#include + +whal_Error whal_HmacSha224_Oneshot(whal_HmacSha224 *dev, + const void *key, size_t keySz, + const void *in, size_t inSz, + void *digest, size_t digestSz) +{ + if (!dev || !dev->driver || !dev->driver->Oneshot) + return WHAL_ENOTSUP; + return dev->driver->Oneshot(dev, key, keySz, in, inSz, digest, digestSz); +} + +whal_Error whal_HmacSha224_Start(whal_HmacSha224 *dev, + const void *key, size_t keySz) +{ + if (!dev || !dev->driver || !dev->driver->Start) + return WHAL_ENOTSUP; + return dev->driver->Start(dev, key, keySz); +} + +whal_Error whal_HmacSha224_Process(whal_HmacSha224 *dev, + const void *in, size_t inSz) +{ + if (!dev || !dev->driver || !dev->driver->Process) + return WHAL_ENOTSUP; + return dev->driver->Process(dev, in, inSz); +} + +whal_Error whal_HmacSha224_Finalize(whal_HmacSha224 *dev, + void *digest, size_t digestSz) +{ + if (!dev || !dev->driver || !dev->driver->Finalize) + return WHAL_ENOTSUP; + return dev->driver->Finalize(dev, digest, digestSz); +} diff --git a/src/crypto/hmac_sha256.c b/src/crypto/hmac_sha256.c new file mode 100644 index 0000000..24e100e --- /dev/null +++ b/src/crypto/hmac_sha256.c @@ -0,0 +1,35 @@ +#include + +whal_Error whal_HmacSha256_Oneshot(whal_HmacSha256 *dev, + const void *key, size_t keySz, + const void *in, size_t inSz, + void *digest, size_t digestSz) +{ + if (!dev || !dev->driver || !dev->driver->Oneshot) + return WHAL_ENOTSUP; + return dev->driver->Oneshot(dev, key, keySz, in, inSz, digest, digestSz); +} + +whal_Error whal_HmacSha256_Start(whal_HmacSha256 *dev, + const void *key, size_t keySz) +{ + if (!dev || !dev->driver || !dev->driver->Start) + return WHAL_ENOTSUP; + return dev->driver->Start(dev, key, keySz); +} + +whal_Error whal_HmacSha256_Process(whal_HmacSha256 *dev, + const void *in, size_t inSz) +{ + if (!dev || !dev->driver || !dev->driver->Process) + return WHAL_ENOTSUP; + return dev->driver->Process(dev, in, inSz); +} + +whal_Error whal_HmacSha256_Finalize(whal_HmacSha256 *dev, + void *digest, size_t digestSz) +{ + if (!dev || !dev->driver || !dev->driver->Finalize) + return WHAL_ENOTSUP; + return dev->driver->Finalize(dev, digest, digestSz); +} diff --git a/src/crypto/sha1.c b/src/crypto/sha1.c new file mode 100644 index 0000000..b605e9f --- /dev/null +++ b/src/crypto/sha1.c @@ -0,0 +1,31 @@ +#include + +whal_Error whal_Sha1_Oneshot(whal_Sha1 *dev, + const void *in, size_t inSz, + void *digest, size_t digestSz) +{ + if (!dev || !dev->driver || !dev->driver->Oneshot) + return WHAL_ENOTSUP; + return dev->driver->Oneshot(dev, in, inSz, digest, digestSz); +} + +whal_Error whal_Sha1_Start(whal_Sha1 *dev) +{ + if (!dev || !dev->driver || !dev->driver->Start) + return WHAL_ENOTSUP; + return dev->driver->Start(dev); +} + +whal_Error whal_Sha1_Process(whal_Sha1 *dev, const void *in, size_t inSz) +{ + if (!dev || !dev->driver || !dev->driver->Process) + return WHAL_ENOTSUP; + return dev->driver->Process(dev, in, inSz); +} + +whal_Error whal_Sha1_Finalize(whal_Sha1 *dev, void *digest, size_t digestSz) +{ + if (!dev || !dev->driver || !dev->driver->Finalize) + return WHAL_ENOTSUP; + return dev->driver->Finalize(dev, digest, digestSz); +} diff --git a/src/crypto/sha224.c b/src/crypto/sha224.c new file mode 100644 index 0000000..5a77203 --- /dev/null +++ b/src/crypto/sha224.c @@ -0,0 +1,32 @@ +#include + +whal_Error whal_Sha224_Oneshot(whal_Sha224 *dev, + const void *in, size_t inSz, + void *digest, size_t digestSz) +{ + if (!dev || !dev->driver || !dev->driver->Oneshot) + return WHAL_ENOTSUP; + return dev->driver->Oneshot(dev, in, inSz, digest, digestSz); +} + +whal_Error whal_Sha224_Start(whal_Sha224 *dev) +{ + if (!dev || !dev->driver || !dev->driver->Start) + return WHAL_ENOTSUP; + return dev->driver->Start(dev); +} + +whal_Error whal_Sha224_Process(whal_Sha224 *dev, const void *in, size_t inSz) +{ + if (!dev || !dev->driver || !dev->driver->Process) + return WHAL_ENOTSUP; + return dev->driver->Process(dev, in, inSz); +} + +whal_Error whal_Sha224_Finalize(whal_Sha224 *dev, + void *digest, size_t digestSz) +{ + if (!dev || !dev->driver || !dev->driver->Finalize) + return WHAL_ENOTSUP; + return dev->driver->Finalize(dev, digest, digestSz); +} diff --git a/src/crypto/sha256.c b/src/crypto/sha256.c new file mode 100644 index 0000000..21f8189 --- /dev/null +++ b/src/crypto/sha256.c @@ -0,0 +1,32 @@ +#include + +whal_Error whal_Sha256_Oneshot(whal_Sha256 *dev, + const void *in, size_t inSz, + void *digest, size_t digestSz) +{ + if (!dev || !dev->driver || !dev->driver->Oneshot) + return WHAL_ENOTSUP; + return dev->driver->Oneshot(dev, in, inSz, digest, digestSz); +} + +whal_Error whal_Sha256_Start(whal_Sha256 *dev) +{ + if (!dev || !dev->driver || !dev->driver->Start) + return WHAL_ENOTSUP; + return dev->driver->Start(dev); +} + +whal_Error whal_Sha256_Process(whal_Sha256 *dev, const void *in, size_t inSz) +{ + if (!dev || !dev->driver || !dev->driver->Process) + return WHAL_ENOTSUP; + return dev->driver->Process(dev, in, inSz); +} + +whal_Error whal_Sha256_Finalize(whal_Sha256 *dev, + void *digest, size_t digestSz) +{ + if (!dev || !dev->driver || !dev->driver->Finalize) + return WHAL_ENOTSUP; + return dev->driver->Finalize(dev, digest, digestSz); +} diff --git a/src/crypto/stm32n6_cryp.c b/src/crypto/stm32n6_cryp.c index 57bccf2..18364d8 100644 --- a/src/crypto/stm32n6_cryp.c +++ b/src/crypto/stm32n6_cryp.c @@ -217,35 +217,6 @@ static whal_Error KeySizeBits(size_t keySz, uint32_t *out) return WHAL_SUCCESS; } -#ifdef WHAL_CFG_STM32N6_CRYP_DIRECT_API_MAPPING -#define whal_Stm32n6_Cryp_Init whal_Crypto_Init -#define whal_Stm32n6_Cryp_Deinit whal_Crypto_Deinit -#define whal_Stm32n6_Cryp_StartOp whal_Crypto_StartOp -#define whal_Stm32n6_Cryp_Process whal_Crypto_Process -#define whal_Stm32n6_Cryp_EndOp whal_Crypto_EndOp -#endif /* WHAL_CFG_STM32N6_CRYP_DIRECT_API_MAPPING */ - -whal_Error whal_Stm32n6_Cryp_Init(whal_Crypto *cryptoDev) -{ - if (!cryptoDev || !cryptoDev->cfg) { - return WHAL_EINVAL; - } - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32n6_Cryp_Deinit(whal_Crypto *cryptoDev) -{ - if (!cryptoDev || !cryptoDev->cfg) { - return WHAL_EINVAL; - } - - Disable(cryptoDev->base); - return WHAL_SUCCESS; -} - -#if defined(WHAL_CFG_CRYPTO_AES_ECB) || defined(WHAL_CFG_CRYPTO_AES_CBC) || \ - defined(WHAL_CFG_CRYPTO_AES_CTR) || defined(WHAL_CFG_CRYPTO_AES_GCM) || \ - defined(WHAL_CFG_CRYPTO_AES_GMAC) || defined(WHAL_CFG_CRYPTO_AES_CCM) /* * Run the ECB/CBC decryption key-preparation pass. Required before performing * an ECB or CBC decryption: the hardware computes the last round key, then @@ -267,10 +238,7 @@ static whal_Error PrepareDecryptionKey(size_t base, const uint8_t *key, Enable(base); return WaitCrypEnClear(base, timeout); } -#endif -#if defined(WHAL_CFG_CRYPTO_AES_ECB) || defined(WHAL_CFG_CRYPTO_AES_CBC) || \ - defined(WHAL_CFG_CRYPTO_AES_CTR) static whal_Error Process_BlockCipher(whal_Crypto *cryptoDev, const uint8_t *in, uint8_t *out, size_t sz) @@ -300,129 +268,384 @@ static whal_Error Process_BlockCipher(whal_Crypto *cryptoDev, return WHAL_SUCCESS; } -static whal_Error EndOp_BlockCipher(whal_Crypto *cryptoDev) + +/* ---- Direct API mapping ---- */ + +#ifdef WHAL_CFG_STM32N6_CRYP_INIT_DIRECT_API_MAPPING +#define whal_Stm32n6_Cryp_Init whal_Crypto_Init +#define whal_Stm32n6_Cryp_Deinit whal_Crypto_Deinit +#endif +#ifdef WHAL_CFG_STM32N6_CRYP_ECB_DIRECT_API_MAPPING +#define whal_Stm32n6_CrypAesEcb_Oneshot whal_AesEcb_Oneshot +#define whal_Stm32n6_CrypAesEcb_Start whal_AesEcb_Start +#define whal_Stm32n6_CrypAesEcb_Process whal_AesEcb_Process +#endif +#ifdef WHAL_CFG_STM32N6_CRYP_CBC_DIRECT_API_MAPPING +#define whal_Stm32n6_CrypAesCbc_Oneshot whal_AesCbc_Oneshot +#define whal_Stm32n6_CrypAesCbc_Start whal_AesCbc_Start +#define whal_Stm32n6_CrypAesCbc_Process whal_AesCbc_Process +#endif +#ifdef WHAL_CFG_STM32N6_CRYP_CTR_DIRECT_API_MAPPING +#define whal_Stm32n6_CrypAesCtr_Oneshot whal_AesCtr_Oneshot +#define whal_Stm32n6_CrypAesCtr_Start whal_AesCtr_Start +#define whal_Stm32n6_CrypAesCtr_Process whal_AesCtr_Process +#endif +#ifdef WHAL_CFG_STM32N6_CRYP_GCM_DIRECT_API_MAPPING +#define whal_Stm32n6_CrypAesGcm_Oneshot whal_AesGcm_Oneshot +#define whal_Stm32n6_CrypAesGcm_Start whal_AesGcm_Start +#define whal_Stm32n6_CrypAesGcm_Process whal_AesGcm_Process +#define whal_Stm32n6_CrypAesGcm_Finalize whal_AesGcm_Finalize +#endif +#ifdef WHAL_CFG_STM32N6_CRYP_GMAC_DIRECT_API_MAPPING +#define whal_Stm32n6_CrypAesGmac_Oneshot whal_AesGmac_Oneshot +#endif +#ifdef WHAL_CFG_STM32N6_CRYP_CCM_DIRECT_API_MAPPING +#define whal_Stm32n6_CrypAesCcm_Oneshot whal_AesCcm_Oneshot +#define whal_Stm32n6_CrypAesCcm_Start whal_AesCcm_Start +#define whal_Stm32n6_CrypAesCcm_Process whal_AesCcm_Process +#define whal_Stm32n6_CrypAesCcm_Finalize whal_AesCcm_Finalize +#endif + + +/* ---- Init / Deinit ---- */ + +whal_Error whal_Stm32n6_Cryp_Init(whal_Crypto *dev) { - Disable(cryptoDev->base); + if (!dev) + return WHAL_EINVAL; return WHAL_SUCCESS; } -#endif /* AES_ECB || AES_CBC || AES_CTR */ -#ifdef WHAL_CFG_CRYPTO_AES_ECB -static whal_Error StartOp_AesEcb(whal_Crypto *cryptoDev, void *opArgs) +whal_Error whal_Stm32n6_Cryp_Deinit(whal_Crypto *dev) { - whal_Crypto_AesEcbArgs *args = (whal_Crypto_AesEcbArgs *)opArgs; - const whal_Stm32n6_Cryp_Cfg *cfg = - (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; + if (!dev) + return WHAL_EINVAL; + Disable(dev->base); + return WHAL_SUCCESS; +} + +const whal_CryptoDriver whal_Stm32n6_Cryp_CryptoDriver = { + .Init = whal_Stm32n6_Cryp_Init, + .Deinit = whal_Stm32n6_Cryp_Deinit, +}; + + +/* ---- AES-ECB ---- */ + +whal_Error whal_Stm32n6_CrypAesEcb_Oneshot(whal_AesEcb *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *in, void *out, + size_t sz) +{ + whal_Crypto *crypto; + const whal_Stm32n6_Cryp_Cfg *cfg; + size_t base; uint32_t keySizeBits; whal_Error err; - if (!args->key) + if (!dev || !dev->crypto || !dev->crypto->cfg || !key) return WHAL_EINVAL; - err = KeySizeBits(args->keySz, &keySizeBits); + crypto = dev->crypto; + cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; + base = crypto->base; + + err = KeySizeBits(keySz, &keySizeBits); if (err) return err; - if (args->dir == WHAL_CRYPTO_DECRYPT) { - err = PrepareDecryptionKey(base, args->key, args->keySz, keySizeBits, + if (dir == WHAL_CRYPTO_DECRYPT) { + err = PrepareDecryptionKey(base, key, keySz, keySizeBits, cfg->timeout); if (err) return err; ConfigureMode(base, CRYP_ALGOMODE_AES_ECB, CRYP_ALGODIR_DECRYPT, keySizeBits, 0, 0, 0); Enable(base); - return WHAL_SUCCESS; + } else { + DisableAndFlush(base); + ConfigureMode(base, CRYP_ALGOMODE_AES_ECB, CRYP_ALGODIR_ENCRYPT, + keySizeBits, 0, 0, 0); + WriteKey(base, key, keySz); + err = WaitKeyValid(base, cfg->timeout); + if (err) + return err; + Enable(base); } - DisableAndFlush(base); - ConfigureMode(base, CRYP_ALGOMODE_AES_ECB, CRYP_ALGODIR_ENCRYPT, - keySizeBits, 0, 0, 0); - WriteKey(base, args->key, args->keySz); - err = WaitKeyValid(base, cfg->timeout); + err = Process_BlockCipher(crypto, in, out, sz); + Disable(base); + return err; +} + +whal_Error whal_Stm32n6_CrypAesEcb_Start(whal_AesEcb *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz) +{ + whal_Crypto *crypto; + const whal_Stm32n6_Cryp_Cfg *cfg; + size_t base; + uint32_t keySizeBits; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg || !key) + return WHAL_EINVAL; + + crypto = dev->crypto; + cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; + base = crypto->base; + + err = KeySizeBits(keySz, &keySizeBits); if (err) return err; - Enable(base); + + if (dir == WHAL_CRYPTO_DECRYPT) { + err = PrepareDecryptionKey(base, key, keySz, keySizeBits, + cfg->timeout); + if (err) + return err; + ConfigureMode(base, CRYP_ALGOMODE_AES_ECB, CRYP_ALGODIR_DECRYPT, + keySizeBits, 0, 0, 0); + Enable(base); + } else { + DisableAndFlush(base); + ConfigureMode(base, CRYP_ALGOMODE_AES_ECB, CRYP_ALGODIR_ENCRYPT, + keySizeBits, 0, 0, 0); + WriteKey(base, key, keySz); + err = WaitKeyValid(base, cfg->timeout); + if (err) + return err; + Enable(base); + } + return WHAL_SUCCESS; } -#endif /* WHAL_CFG_CRYPTO_AES_ECB */ -#ifdef WHAL_CFG_CRYPTO_AES_CBC -static whal_Error StartOp_AesCbc(whal_Crypto *cryptoDev, void *opArgs) +whal_Error whal_Stm32n6_CrypAesEcb_Process(whal_AesEcb *dev, + const void *in, void *out, + size_t sz) { - whal_Crypto_AesCbcArgs *args = (whal_Crypto_AesCbcArgs *)opArgs; - const whal_Stm32n6_Cryp_Cfg *cfg = - (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; + return Process_BlockCipher(dev->crypto, in, out, sz); +} + +const whal_AesEcbDriver whal_Stm32n6_Cryp_EcbDriver = { + .Oneshot = whal_Stm32n6_CrypAesEcb_Oneshot, + .Start = whal_Stm32n6_CrypAesEcb_Start, + .Process = whal_Stm32n6_CrypAesEcb_Process, +}; + + +/* ---- AES-CBC ---- */ + +whal_Error whal_Stm32n6_CrypAesCbc_Oneshot(whal_AesCbc *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, + const void *in, void *out, + size_t sz) +{ + whal_Crypto *crypto; + const whal_Stm32n6_Cryp_Cfg *cfg; + size_t base; uint32_t keySizeBits; whal_Error err; - if (!args->key || !args->iv) + if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) return WHAL_EINVAL; - err = KeySizeBits(args->keySz, &keySizeBits); + crypto = dev->crypto; + cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; + base = crypto->base; + + err = KeySizeBits(keySz, &keySizeBits); if (err) return err; - if (args->dir == WHAL_CRYPTO_DECRYPT) { - err = PrepareDecryptionKey(base, args->key, args->keySz, keySizeBits, + if (dir == WHAL_CRYPTO_DECRYPT) { + err = PrepareDecryptionKey(base, key, keySz, keySizeBits, cfg->timeout); if (err) return err; ConfigureMode(base, CRYP_ALGOMODE_AES_CBC, CRYP_ALGODIR_DECRYPT, keySizeBits, 0, 0, 0); - WriteIv16(base, (const uint8_t *)args->iv); + WriteIv16(base, (const uint8_t *)iv); + Enable(base); + } else { + DisableAndFlush(base); + ConfigureMode(base, CRYP_ALGOMODE_AES_CBC, CRYP_ALGODIR_ENCRYPT, + keySizeBits, 0, 0, 0); + WriteIv16(base, (const uint8_t *)iv); + WriteKey(base, key, keySz); + err = WaitKeyValid(base, cfg->timeout); + if (err) + return err; Enable(base); - return WHAL_SUCCESS; } + err = Process_BlockCipher(crypto, in, out, sz); + Disable(base); + return err; +} + +whal_Error whal_Stm32n6_CrypAesCbc_Start(whal_AesCbc *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv) +{ + whal_Crypto *crypto; + const whal_Stm32n6_Cryp_Cfg *cfg; + size_t base; + uint32_t keySizeBits; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) + return WHAL_EINVAL; + + crypto = dev->crypto; + cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; + base = crypto->base; + + err = KeySizeBits(keySz, &keySizeBits); + if (err) + return err; + + if (dir == WHAL_CRYPTO_DECRYPT) { + err = PrepareDecryptionKey(base, key, keySz, keySizeBits, + cfg->timeout); + if (err) + return err; + ConfigureMode(base, CRYP_ALGOMODE_AES_CBC, CRYP_ALGODIR_DECRYPT, + keySizeBits, 0, 0, 0); + WriteIv16(base, (const uint8_t *)iv); + Enable(base); + } else { + DisableAndFlush(base); + ConfigureMode(base, CRYP_ALGOMODE_AES_CBC, CRYP_ALGODIR_ENCRYPT, + keySizeBits, 0, 0, 0); + WriteIv16(base, (const uint8_t *)iv); + WriteKey(base, key, keySz); + err = WaitKeyValid(base, cfg->timeout); + if (err) + return err; + Enable(base); + } + + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32n6_CrypAesCbc_Process(whal_AesCbc *dev, + const void *in, void *out, + size_t sz) +{ + return Process_BlockCipher(dev->crypto, in, out, sz); +} + +const whal_AesCbcDriver whal_Stm32n6_Cryp_CbcDriver = { + .Oneshot = whal_Stm32n6_CrypAesCbc_Oneshot, + .Start = whal_Stm32n6_CrypAesCbc_Start, + .Process = whal_Stm32n6_CrypAesCbc_Process, +}; + + +/* ---- AES-CTR ---- */ + +whal_Error whal_Stm32n6_CrypAesCtr_Oneshot(whal_AesCtr *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, + const void *in, void *out, + size_t sz) +{ + whal_Crypto *crypto; + const whal_Stm32n6_Cryp_Cfg *cfg; + size_t base; + uint32_t keySizeBits; + uint32_t algoDir; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) + return WHAL_EINVAL; + + crypto = dev->crypto; + cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; + base = crypto->base; + + err = KeySizeBits(keySz, &keySizeBits); + if (err) + return err; + + algoDir = (dir == WHAL_CRYPTO_ENCRYPT) ? CRYP_ALGODIR_ENCRYPT + : CRYP_ALGODIR_DECRYPT; + DisableAndFlush(base); - ConfigureMode(base, CRYP_ALGOMODE_AES_CBC, CRYP_ALGODIR_ENCRYPT, - keySizeBits, 0, 0, 0); - WriteIv16(base, (const uint8_t *)args->iv); - WriteKey(base, args->key, args->keySz); + ConfigureMode(base, CRYP_ALGOMODE_AES_CTR, algoDir, keySizeBits, 0, 0, 0); + WriteIv16(base, (const uint8_t *)iv); + WriteKey(base, key, keySz); err = WaitKeyValid(base, cfg->timeout); if (err) return err; Enable(base); - return WHAL_SUCCESS; + + err = Process_BlockCipher(crypto, in, out, sz); + Disable(base); + return err; } -#endif /* WHAL_CFG_CRYPTO_AES_CBC */ -#ifdef WHAL_CFG_CRYPTO_AES_CTR -static whal_Error StartOp_AesCtr(whal_Crypto *cryptoDev, void *opArgs) +whal_Error whal_Stm32n6_CrypAesCtr_Start(whal_AesCtr *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv) { - whal_Crypto_AesCtrArgs *args = (whal_Crypto_AesCtrArgs *)opArgs; - const whal_Stm32n6_Cryp_Cfg *cfg = - (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; + whal_Crypto *crypto; + const whal_Stm32n6_Cryp_Cfg *cfg; + size_t base; uint32_t keySizeBits; uint32_t algoDir; whal_Error err; - if (!args->key || !args->iv) + if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) return WHAL_EINVAL; - err = KeySizeBits(args->keySz, &keySizeBits); + crypto = dev->crypto; + cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; + base = crypto->base; + + err = KeySizeBits(keySz, &keySizeBits); if (err) return err; - algoDir = (args->dir == WHAL_CRYPTO_ENCRYPT) ? CRYP_ALGODIR_ENCRYPT - : CRYP_ALGODIR_DECRYPT; + algoDir = (dir == WHAL_CRYPTO_ENCRYPT) ? CRYP_ALGODIR_ENCRYPT + : CRYP_ALGODIR_DECRYPT; DisableAndFlush(base); ConfigureMode(base, CRYP_ALGOMODE_AES_CTR, algoDir, keySizeBits, 0, 0, 0); - WriteIv16(base, (const uint8_t *)args->iv); - WriteKey(base, args->key, args->keySz); + WriteIv16(base, (const uint8_t *)iv); + WriteKey(base, key, keySz); err = WaitKeyValid(base, cfg->timeout); if (err) return err; Enable(base); + return WHAL_SUCCESS; } -#endif /* WHAL_CFG_CRYPTO_AES_CTR */ -#if defined(WHAL_CFG_CRYPTO_AES_GCM) || defined(WHAL_CFG_CRYPTO_AES_GMAC) +whal_Error whal_Stm32n6_CrypAesCtr_Process(whal_AesCtr *dev, + const void *in, void *out, + size_t sz) +{ + return Process_BlockCipher(dev->crypto, in, out, sz); +} + +const whal_AesCtrDriver whal_Stm32n6_Cryp_CtrDriver = { + .Oneshot = whal_Stm32n6_CrypAesCtr_Oneshot, + .Start = whal_Stm32n6_CrypAesCtr_Start, + .Process = whal_Stm32n6_CrypAesCtr_Process, +}; + + +/* ---- GCM helpers ---- */ + /* * Run GCM init phase: configure CR for GCM, load IV (12 bytes + counter=2) * and key, then enable CRYP and wait for the hash subkey computation to @@ -492,55 +715,182 @@ static whal_Error GcmHeaderPhase(whal_Crypto *cryptoDev, const uint8_t *aad, return err; return WHAL_SUCCESS; } -#endif /* AES_GCM || AES_GMAC */ -#ifdef WHAL_CFG_CRYPTO_AES_GCM -static whal_Error StartOp_AesGcm(whal_Crypto *cryptoDev, void *opArgs) + +/* ---- AES-GCM ---- */ + +whal_Error whal_Stm32n6_CrypAesGcm_Oneshot(whal_AesGcm *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz, + const void *in, void *out, + size_t sz, + void *tag, size_t tagSz) { - whal_Crypto_AesGcmArgs *args = (whal_Crypto_AesGcmArgs *)opArgs; + whal_Crypto *crypto; + const whal_Stm32n6_Cryp_Cfg *cfg; + size_t base; uint32_t keySizeBits; uint32_t algoDir; + uint8_t tagBuf[16]; + uint64_t aadBits; + uint64_t payloadBits; whal_Error err; + size_t i; - if (!args->key || !args->iv) + if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) return WHAL_EINVAL; - if (args->ivSz != 12) + if (ivSz != 12) return WHAL_ENOTSUP; - if (args->aadSz > 0 && !args->aad) + if (aadSz > 0 && !aad) return WHAL_EINVAL; - if (args->sz > 0 && (!args->in || !args->out)) + if (sz > 0 && (!in || !out)) return WHAL_EINVAL; + if (!tag || tagSz == 0 || tagSz > 16) + return WHAL_EINVAL; + + crypto = dev->crypto; + cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; + base = crypto->base; - err = KeySizeBits(args->keySz, &keySizeBits); + err = KeySizeBits(keySz, &keySizeBits); if (err) return err; - algoDir = (args->dir == WHAL_CRYPTO_ENCRYPT) ? CRYP_ALGODIR_ENCRYPT - : CRYP_ALGODIR_DECRYPT; + algoDir = (dir == WHAL_CRYPTO_ENCRYPT) ? CRYP_ALGODIR_ENCRYPT + : CRYP_ALGODIR_DECRYPT; + + /* Init phase */ + err = GcmInit(crypto, (const uint8_t *)key, keySz, + keySizeBits, algoDir, (const uint8_t *)iv); + if (err) + return err; - err = GcmInit(cryptoDev, (const uint8_t *)args->key, args->keySz, - keySizeBits, algoDir, (const uint8_t *)args->iv); + /* Header phase */ + err = GcmHeaderPhase(crypto, (const uint8_t *)aad, aadSz); if (err) return err; - return GcmHeaderPhase(cryptoDev, (const uint8_t *)args->aad, args->aadSz); + /* Payload phase */ + if (sz > 0) { + Disable(base); + whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, + whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, + CRYP_CR_GCM_CCMPH_Pos, + CRYP_GCM_CCMPH_PAYLOAD)); + Enable(base); + + for (i = 0; i < sz; i += 16) { + const uint8_t *inPtr = (const uint8_t *)in + i; + uint8_t *outPtr = (uint8_t *)out + i; + size_t remain = sz - i; + uint8_t blockIn[16] = {0}; + uint8_t blockOut[16]; + size_t j; + + if (remain >= 16) { + WriteBlock(base, inPtr); + } else { + if (dir == WHAL_CRYPTO_ENCRYPT) { + whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_NPBLB_Msk, + whal_SetBits(CRYP_CR_NPBLB_Msk, + CRYP_CR_NPBLB_Pos, + 16 - remain)); + } + for (j = 0; j < remain; j++) + blockIn[j] = inPtr[j]; + WriteBlock(base, blockIn); + } + + err = WaitOutputReady(base, cfg->timeout); + if (err) { + Disable(base); + return err; + } + + if (remain >= 16) { + ReadBlock(base, outPtr); + } else { + ReadBlock(base, blockOut); + for (j = 0; j < remain; j++) + outPtr[j] = blockOut[j]; + } + } + } + + /* Final phase */ + Disable(base); + whal_Reg_Update(base, CRYP_CR_REG, + CRYP_CR_GCM_CCMPH_Msk | CRYP_CR_ALGODIR_Msk, + whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, + CRYP_CR_GCM_CCMPH_Pos, + CRYP_GCM_CCMPH_FINAL)); + Enable(base); + + aadBits = (uint64_t)aadSz * 8; + payloadBits = (uint64_t)sz * 8; + whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)(aadBits >> 32)); + whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)aadBits); + whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)(payloadBits >> 32)); + whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)payloadBits); + + err = WaitOutputReady(base, cfg->timeout); + if (err) { + Disable(base); + return err; + } + + ReadBlock(base, tagBuf); + for (i = 0; i < tagSz; i++) + ((uint8_t *)tag)[i] = tagBuf[i]; + + Disable(base); + return WHAL_SUCCESS; } -static whal_Error Process_AesGcm(whal_Crypto *cryptoDev, void *opArgs) +whal_Error whal_Stm32n6_CrypAesGcm_Start(whal_AesGcm *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz) { - whal_Crypto_AesGcmArgs *args = (whal_Crypto_AesGcmArgs *)opArgs; - const whal_Stm32n6_Cryp_Cfg *cfg = - (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; + whal_Crypto *crypto; + size_t base; + uint32_t keySizeBits; + uint32_t algoDir; whal_Error err; - size_t i; - if (args->sz == 0) - return WHAL_SUCCESS; + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state || !key || !iv) + return WHAL_EINVAL; - if (!args->in || !args->out) + crypto = dev->crypto; + if (ivSz != 12) + return WHAL_ENOTSUP; + if (aadSz > 0 && !aad) return WHAL_EINVAL; + base = crypto->base; + + err = KeySizeBits(keySz, &keySizeBits); + if (err) + return err; + + algoDir = (dir == WHAL_CRYPTO_ENCRYPT) ? CRYP_ALGODIR_ENCRYPT + : CRYP_ALGODIR_DECRYPT; + + /* Init phase */ + err = GcmInit(crypto, (const uint8_t *)key, keySz, + keySizeBits, algoDir, (const uint8_t *)iv); + if (err) + return err; + + /* Header phase */ + err = GcmHeaderPhase(crypto, (const uint8_t *)aad, aadSz); + if (err) + return err; + + /* Transition to payload phase */ Disable(base); whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, @@ -548,26 +898,53 @@ static whal_Error Process_AesGcm(whal_Crypto *cryptoDev, void *opArgs) CRYP_GCM_CCMPH_PAYLOAD)); Enable(base); - for (i = 0; i < args->sz; i += 16) { - const uint8_t *in = (const uint8_t *)args->in + i; - uint8_t *out = (uint8_t *)args->out + i; - size_t remain = args->sz - i; - uint8_t blockIn[16] = {0}; - uint8_t blockOut[16]; + { + whal_Stm32n6_AesGcm_State *st = (whal_Stm32n6_AesGcm_State *)dev->state; + st->aadSz = aadSz; + st->dataSz = 0; + } + + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32n6_CrypAesGcm_Process(whal_AesGcm *dev, + const void *in, void *out, + size_t sz) +{ + whal_Crypto *crypto; + const whal_Stm32n6_Cryp_Cfg *cfg; + size_t base; + whal_Stm32n6_AesGcm_State *st; + size_t i; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) + return WHAL_EINVAL; + + crypto = dev->crypto; + cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; + base = crypto->base; + st = (whal_Stm32n6_AesGcm_State *)dev->state; + + if (sz == 0) + return WHAL_SUCCESS; + + if (!in || !out) + return WHAL_EINVAL; + + for (i = 0; i < sz; i += 16) { + const uint8_t *inPtr = (const uint8_t *)in + i; + uint8_t *outPtr = (uint8_t *)out + i; + size_t remain = sz - i; + uint8_t block[16] = {0}; size_t j; if (remain >= 16) { - WriteBlock(base, in); + WriteBlock(base, inPtr); } else { - if (args->dir == WHAL_CRYPTO_ENCRYPT) { - whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_NPBLB_Msk, - whal_SetBits(CRYP_CR_NPBLB_Msk, - CRYP_CR_NPBLB_Pos, - 16 - remain)); - } for (j = 0; j < remain; j++) - blockIn[j] = in[j]; - WriteBlock(base, blockIn); + block[j] = inPtr[j]; + WriteBlock(base, block); } err = WaitOutputReady(base, cfg->timeout); @@ -577,32 +954,44 @@ static whal_Error Process_AesGcm(whal_Crypto *cryptoDev, void *opArgs) } if (remain >= 16) { - ReadBlock(base, out); + ReadBlock(base, outPtr); } else { - ReadBlock(base, blockOut); + ReadBlock(base, block); for (j = 0; j < remain; j++) - out[j] = blockOut[j]; + outPtr[j] = block[j]; } } + st->dataSz += sz; + return WHAL_SUCCESS; } -static whal_Error EndOp_AesGcm(whal_Crypto *cryptoDev, void *opArgs) +whal_Error whal_Stm32n6_CrypAesGcm_Finalize(whal_AesGcm *dev, + void *tag, size_t tagSz) { - whal_Crypto_AesGcmArgs *args = (whal_Crypto_AesGcmArgs *)opArgs; - const whal_Stm32n6_Cryp_Cfg *cfg = - (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; + whal_Crypto *crypto; + const whal_Stm32n6_Cryp_Cfg *cfg; + size_t base; + whal_Stm32n6_AesGcm_State *st; uint8_t tagBuf[16]; uint64_t aadBits; uint64_t payloadBits; - whal_Error err; size_t i; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) + return WHAL_EINVAL; + + crypto = dev->crypto; + cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; + base = crypto->base; + st = (whal_Stm32n6_AesGcm_State *)dev->state; - if (!args->tag || args->tagSz == 0 || args->tagSz > 16) + if (!tag || tagSz == 0 || tagSz > 16) return WHAL_EINVAL; + /* Final phase */ Disable(base); whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk | CRYP_CR_ALGODIR_Msk, @@ -611,8 +1000,8 @@ static whal_Error EndOp_AesGcm(whal_Crypto *cryptoDev, void *opArgs) CRYP_GCM_CCMPH_FINAL)); Enable(base); - aadBits = (uint64_t)args->aadSz * 8; - payloadBits = (uint64_t)args->sz * 8; + aadBits = (uint64_t)st->aadSz * 8; + payloadBits = (uint64_t)st->dataSz * 8; whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)(aadBits >> 32)); whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)aadBits); whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)(payloadBits >> 32)); @@ -625,55 +1014,68 @@ static whal_Error EndOp_AesGcm(whal_Crypto *cryptoDev, void *opArgs) } ReadBlock(base, tagBuf); - for (i = 0; i < args->tagSz; i++) - ((uint8_t *)args->tag)[i] = tagBuf[i]; + for (i = 0; i < tagSz; i++) + ((uint8_t *)tag)[i] = tagBuf[i]; Disable(base); return WHAL_SUCCESS; } -#endif /* WHAL_CFG_CRYPTO_AES_GCM */ -#ifdef WHAL_CFG_CRYPTO_AES_GMAC -static whal_Error StartOp_AesGmac(whal_Crypto *cryptoDev, void *opArgs) +const whal_AesGcmDriver whal_Stm32n6_Cryp_GcmDriver = { + .Oneshot = whal_Stm32n6_CrypAesGcm_Oneshot, + .Start = whal_Stm32n6_CrypAesGcm_Start, + .Process = whal_Stm32n6_CrypAesGcm_Process, + .Finalize = whal_Stm32n6_CrypAesGcm_Finalize, +}; + + +/* ---- AES-GMAC ---- */ + +whal_Error whal_Stm32n6_CrypAesGmac_Oneshot(whal_AesGmac *dev, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz, + void *tag, size_t tagSz) { - whal_Crypto_AesGmacArgs *args = (whal_Crypto_AesGmacArgs *)opArgs; + whal_Crypto *crypto; + const whal_Stm32n6_Cryp_Cfg *cfg; + size_t base; uint32_t keySizeBits; + uint8_t tagBuf[16]; + uint64_t aadBits; whal_Error err; + size_t i; - if (!args->key || !args->iv) + if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) return WHAL_EINVAL; - if (args->ivSz != 12) + if (ivSz != 12) return WHAL_ENOTSUP; - if (args->aadSz > 0 && !args->aad) + if (aadSz > 0 && !aad) + return WHAL_EINVAL; + if (!tag || tagSz == 0 || tagSz > 16) return WHAL_EINVAL; - err = KeySizeBits(args->keySz, &keySizeBits); + crypto = dev->crypto; + cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; + base = crypto->base; + + err = KeySizeBits(keySz, &keySizeBits); if (err) return err; - err = GcmInit(cryptoDev, (const uint8_t *)args->key, args->keySz, + /* Init phase */ + err = GcmInit(crypto, (const uint8_t *)key, keySz, keySizeBits, CRYP_ALGODIR_ENCRYPT, - (const uint8_t *)args->iv); + (const uint8_t *)iv); if (err) return err; - return GcmHeaderPhase(cryptoDev, (const uint8_t *)args->aad, args->aadSz); -} - -static whal_Error EndOp_AesGmac(whal_Crypto *cryptoDev, void *opArgs) -{ - whal_Crypto_AesGmacArgs *args = (whal_Crypto_AesGmacArgs *)opArgs; - const whal_Stm32n6_Cryp_Cfg *cfg = - (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; - uint8_t tagBuf[16]; - uint64_t aadBits; - whal_Error err; - size_t i; - - if (!args->tag || args->tagSz == 0 || args->tagSz > 16) - return WHAL_EINVAL; + /* Header phase */ + err = GcmHeaderPhase(crypto, (const uint8_t *)aad, aadSz); + if (err) + return err; + /* Final phase */ Disable(base); whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk | CRYP_CR_ALGODIR_Msk, @@ -682,7 +1084,7 @@ static whal_Error EndOp_AesGmac(whal_Crypto *cryptoDev, void *opArgs) CRYP_GCM_CCMPH_FINAL)); Enable(base); - aadBits = (uint64_t)args->aadSz * 8; + aadBits = (uint64_t)aadSz * 8; whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)(aadBits >> 32)); whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)aadBits); whal_Reg_Write(base, CRYP_DINR_REG, 0); @@ -695,15 +1097,20 @@ static whal_Error EndOp_AesGmac(whal_Crypto *cryptoDev, void *opArgs) } ReadBlock(base, tagBuf); - for (i = 0; i < args->tagSz; i++) - ((uint8_t *)args->tag)[i] = tagBuf[i]; + for (i = 0; i < tagSz; i++) + ((uint8_t *)tag)[i] = tagBuf[i]; Disable(base); return WHAL_SUCCESS; } -#endif /* WHAL_CFG_CRYPTO_AES_GMAC */ -#ifdef WHAL_CFG_CRYPTO_AES_CCM +const whal_AesGmacDriver whal_Stm32n6_Cryp_GmacDriver = { + .Oneshot = whal_Stm32n6_CrypAesGmac_Oneshot, +}; + + +/* ---- AES-CCM ---- */ + /* * Build the 16-byte CCM B0 first authentication block from the user nonce, * tag length, and message length per NIST SP 800-38C Appendix A. @@ -726,61 +1133,76 @@ static void CcmBuildB0(const uint8_t *nonce, size_t nonceSz, size_t tagSz, } } -static whal_Error StartOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) +whal_Error whal_Stm32n6_CrypAesCcm_Oneshot(whal_AesCcm *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *nonce, size_t nonceSz, + const void *aad, size_t aadSz, + const void *in, void *out, + size_t sz, + void *tag, size_t tagSz) { - whal_Crypto_AesCcmArgs *args = (whal_Crypto_AesCcmArgs *)opArgs; - whal_Stm32n6_Cryp_Cfg *cfg = (whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; + whal_Crypto *crypto; + const whal_Stm32n6_Cryp_Cfg *cfg; + size_t base; uint32_t keySizeBits; uint32_t algoDir; uint8_t b0[16]; + uint8_t ctr0[16]; uint8_t ctr1[16]; + uint8_t tagBuf[16]; size_t q; size_t i; whal_Error err; - if (!args->key || !args->nonce) + if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !nonce) return WHAL_EINVAL; - if (args->nonceSz < 7 || args->nonceSz > 13) + if (nonceSz < 7 || nonceSz > 13) return WHAL_EINVAL; - if (args->tagSz < 4 || args->tagSz > 16 || (args->tagSz & 1) != 0) + if (tagSz < 4 || tagSz > 16 || (tagSz & 1) != 0) return WHAL_EINVAL; - if (args->aadSz > 0 && !args->aad) + if (aadSz > 0 && !aad) return WHAL_EINVAL; - if (args->sz > 0 && (!args->in || !args->out)) + if (sz > 0 && (!in || !out)) return WHAL_EINVAL; + if (!tag) + return WHAL_EINVAL; + + crypto = dev->crypto; + cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; + base = crypto->base; - err = KeySizeBits(args->keySz, &keySizeBits); + err = KeySizeBits(keySz, &keySizeBits); if (err) return err; - algoDir = (args->dir == WHAL_CRYPTO_ENCRYPT) ? CRYP_ALGODIR_ENCRYPT - : CRYP_ALGODIR_DECRYPT; + algoDir = (dir == WHAL_CRYPTO_ENCRYPT) ? CRYP_ALGODIR_ENCRYPT + : CRYP_ALGODIR_DECRYPT; - q = 15 - args->nonceSz; - CcmBuildB0((const uint8_t *)args->nonce, args->nonceSz, args->tagSz, - args->sz, args->aadSz > 0, b0); + q = 15 - nonceSz; + CcmBuildB0((const uint8_t *)nonce, nonceSz, tagSz, + sz, aadSz > 0, b0); /* CTR0 = B0 with the top-5 flag bits cleared and the message-length - * bytes (last q bytes) zeroed. Saved on cfg for use in EndOp to encrypt - * the tag (the streaming Finalize wrapper drops the nonce). */ + * bytes (last q bytes) zeroed. Replayed in the final phase below. */ for (i = 0; i < 16; i++) - cfg->ccmCtr0[i] = b0[i]; - cfg->ccmCtr0[0] &= 0x07; + ctr0[i] = b0[i]; + ctr0[0] &= 0x07; for (i = 16 - q; i < 16; i++) - cfg->ccmCtr0[i] = 0; + ctr0[i] = 0; /* CTR1 = CTR0 with bit 0 set (counter = 1). Per RM0486 Table 421 this * is what the IV registers receive at init time. */ for (i = 0; i < 16; i++) - ctr1[i] = cfg->ccmCtr0[i]; + ctr1[i] = ctr0[i]; ctr1[15] |= 0x01; + /* Init phase */ DisableAndFlush(base); ConfigureMode(base, CRYP_ALGOMODE_AES_CCM, algoDir, keySizeBits, CRYP_GCM_CCMPH_INIT, 0, 0); WriteIv16(base, ctr1); - WriteKey(base, args->key, args->keySz); + WriteKey(base, key, keySz); err = WaitKeyValid(base, cfg->timeout); if (err) return err; @@ -792,8 +1214,9 @@ static whal_Error StartOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) if (err) return err; - if (args->aadSz > 0) { - const uint8_t *aad = (const uint8_t *)args->aad; + /* Header phase (AAD) */ + if (aadSz > 0) { + const uint8_t *aadPtr = (const uint8_t *)aad; uint8_t hdr[16] = {0}; size_t hdrOff; size_t aadOff = 0; @@ -804,18 +1227,18 @@ static whal_Error StartOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) CRYP_GCM_CCMPH_HEADER)); Enable(base); - hdr[0] = (uint8_t)(args->aadSz >> 8); - hdr[1] = (uint8_t)args->aadSz; + hdr[0] = (uint8_t)(aadSz >> 8); + hdr[1] = (uint8_t)aadSz; hdrOff = 2; - while (hdrOff < 16 && aadOff < args->aadSz) - hdr[hdrOff++] = aad[aadOff++]; + while (hdrOff < 16 && aadOff < aadSz) + hdr[hdrOff++] = aadPtr[aadOff++]; WriteBlock(base, hdr); - while (aadOff < args->aadSz) { + while (aadOff < aadSz) { uint8_t blk[16] = {0}; size_t j; - for (j = 0; j < 16 && aadOff < args->aadSz; j++) - blk[j] = aad[aadOff++]; + for (j = 0; j < 16 && aadOff < aadSz; j++) + blk[j] = aadPtr[aadOff++]; WriteBlock(base, blk); } @@ -824,24 +1247,182 @@ static whal_Error StartOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) return err; } + /* Payload phase */ + if (sz > 0) { + Disable(base); + whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, + whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, + CRYP_CR_GCM_CCMPH_Pos, + CRYP_GCM_CCMPH_PAYLOAD)); + Enable(base); + + for (i = 0; i < sz; i += 16) { + const uint8_t *inPtr = (const uint8_t *)in + i; + uint8_t *outPtr = (uint8_t *)out + i; + size_t remain = sz - i; + uint8_t blockIn[16] = {0}; + uint8_t blockOut[16]; + size_t j; + + if (remain >= 16) { + WriteBlock(base, inPtr); + } else { + if (dir == WHAL_CRYPTO_DECRYPT) { + whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_NPBLB_Msk, + whal_SetBits(CRYP_CR_NPBLB_Msk, + CRYP_CR_NPBLB_Pos, + 16 - remain)); + } + for (j = 0; j < remain; j++) + blockIn[j] = inPtr[j]; + WriteBlock(base, blockIn); + } + + err = WaitOutputReady(base, cfg->timeout); + if (err) { + Disable(base); + return err; + } + + if (remain >= 16) { + ReadBlock(base, outPtr); + } else { + ReadBlock(base, blockOut); + for (j = 0; j < remain; j++) + outPtr[j] = blockOut[j]; + } + } + } + + /* Final phase */ + Disable(base); + whal_Reg_Update(base, CRYP_CR_REG, + CRYP_CR_GCM_CCMPH_Msk | CRYP_CR_ALGODIR_Msk, + whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, + CRYP_CR_GCM_CCMPH_Pos, + CRYP_GCM_CCMPH_FINAL)); + Enable(base); + + WriteBlock(base, ctr0); + + err = WaitOutputReady(base, cfg->timeout); + if (err) { + Disable(base); + return err; + } + + ReadBlock(base, tagBuf); + for (i = 0; i < tagSz; i++) + ((uint8_t *)tag)[i] = tagBuf[i]; + + Disable(base); return WHAL_SUCCESS; } -static whal_Error Process_AesCcm(whal_Crypto *cryptoDev, void *opArgs) +whal_Error whal_Stm32n6_CrypAesCcm_Start(whal_AesCcm *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *nonce, size_t nonceSz, + const void *aad, size_t aadSz, + size_t tagSz, size_t sz) { - whal_Crypto_AesCcmArgs *args = (whal_Crypto_AesCcmArgs *)opArgs; - const whal_Stm32n6_Cryp_Cfg *cfg = - (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; - whal_Error err; + whal_Crypto *crypto; + const whal_Stm32n6_Cryp_Cfg *cfg; + whal_Stm32n6_AesCcm_State *st; + size_t base; + uint32_t keySizeBits; + uint32_t algoDir; + uint8_t b0[16]; + uint8_t ctr1[16]; + size_t q; size_t i; + whal_Error err; - if (args->sz == 0) - return WHAL_SUCCESS; - - if (!args->in || !args->out) + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state || !key || !nonce) return WHAL_EINVAL; + if (nonceSz < 7 || nonceSz > 13) + return WHAL_EINVAL; + if (tagSz < 4 || tagSz > 16 || (tagSz & 1) != 0) + return WHAL_EINVAL; + if (aadSz > 0 && !aad) + return WHAL_EINVAL; + + crypto = dev->crypto; + cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; + st = (whal_Stm32n6_AesCcm_State *)dev->state; + base = crypto->base; + + err = KeySizeBits(keySz, &keySizeBits); + if (err) + return err; + algoDir = (dir == WHAL_CRYPTO_ENCRYPT) ? CRYP_ALGODIR_ENCRYPT + : CRYP_ALGODIR_DECRYPT; + + q = 15 - nonceSz; + CcmBuildB0((const uint8_t *)nonce, nonceSz, tagSz, + sz, aadSz > 0, b0); + + for (i = 0; i < 16; i++) + st->ccmCtr0[i] = b0[i]; + st->ccmCtr0[0] &= 0x07; + for (i = 16 - q; i < 16; i++) + st->ccmCtr0[i] = 0; + + for (i = 0; i < 16; i++) + ctr1[i] = st->ccmCtr0[i]; + ctr1[15] |= 0x01; + + /* Init phase */ + DisableAndFlush(base); + ConfigureMode(base, CRYP_ALGOMODE_AES_CCM, algoDir, keySizeBits, + CRYP_GCM_CCMPH_INIT, 0, 0); + WriteIv16(base, ctr1); + WriteKey(base, key, keySz); + err = WaitKeyValid(base, cfg->timeout); + if (err) + return err; + Enable(base); + + WriteBlock(base, b0); + err = WaitCrypEnClear(base, cfg->timeout); + if (err) + return err; + + /* Header phase (AAD) */ + if (aadSz > 0) { + const uint8_t *aadPtr = (const uint8_t *)aad; + uint8_t hdr[16] = {0}; + size_t hdrOff; + size_t aadOff = 0; + + whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, + whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, + CRYP_CR_GCM_CCMPH_Pos, + CRYP_GCM_CCMPH_HEADER)); + Enable(base); + + hdr[0] = (uint8_t)(aadSz >> 8); + hdr[1] = (uint8_t)aadSz; + hdrOff = 2; + while (hdrOff < 16 && aadOff < aadSz) + hdr[hdrOff++] = aadPtr[aadOff++]; + WriteBlock(base, hdr); + + while (aadOff < aadSz) { + uint8_t blk[16] = {0}; + size_t j; + for (j = 0; j < 16 && aadOff < aadSz; j++) + blk[j] = aadPtr[aadOff++]; + WriteBlock(base, blk); + } + + err = WaitBusyClear(base, cfg->timeout); + if (err) + return err; + } + + /* Transition to payload phase */ Disable(base); whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk, whal_SetBits(CRYP_CR_GCM_CCMPH_Msk, @@ -849,26 +1430,61 @@ static whal_Error Process_AesCcm(whal_Crypto *cryptoDev, void *opArgs) CRYP_GCM_CCMPH_PAYLOAD)); Enable(base); - for (i = 0; i < args->sz; i += 16) { - const uint8_t *in = (const uint8_t *)args->in + i; - uint8_t *out = (uint8_t *)args->out + i; - size_t remain = args->sz - i; - uint8_t blockIn[16] = {0}; + st->aadSz = aadSz; + st->dataSz = 0; + + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32n6_CrypAesCcm_Process(whal_AesCcm *dev, + const void *in, void *out, + size_t sz) +{ + whal_Crypto *crypto; + const whal_Stm32n6_Cryp_Cfg *cfg; + size_t base; + whal_Stm32n6_AesCcm_State *st; + uint32_t algoDir; + size_t i; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) + return WHAL_EINVAL; + + crypto = dev->crypto; + cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; + base = crypto->base; + st = (whal_Stm32n6_AesCcm_State *)dev->state; + + if (sz == 0) + return WHAL_SUCCESS; + + if (!in || !out) + return WHAL_EINVAL; + + algoDir = whal_GetBits(CRYP_CR_ALGODIR_Msk, CRYP_CR_ALGODIR_Pos, + whal_Reg_Read(base, CRYP_CR_REG)); + + for (i = 0; i < sz; i += 16) { + const uint8_t *inPtr = (const uint8_t *)in + i; + uint8_t *outPtr = (uint8_t *)out + i; + size_t remain = sz - i; + uint8_t block[16] = {0}; uint8_t blockOut[16]; size_t j; if (remain >= 16) { - WriteBlock(base, in); + WriteBlock(base, inPtr); } else { - if (args->dir == WHAL_CRYPTO_DECRYPT) { + if (algoDir == CRYP_ALGODIR_DECRYPT) { whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_NPBLB_Msk, whal_SetBits(CRYP_CR_NPBLB_Msk, CRYP_CR_NPBLB_Pos, 16 - remain)); } for (j = 0; j < remain; j++) - blockIn[j] = in[j]; - WriteBlock(base, blockIn); + block[j] = inPtr[j]; + WriteBlock(base, block); } err = WaitOutputReady(base, cfg->timeout); @@ -878,31 +1494,40 @@ static whal_Error Process_AesCcm(whal_Crypto *cryptoDev, void *opArgs) } if (remain >= 16) { - ReadBlock(base, out); + ReadBlock(base, outPtr); } else { ReadBlock(base, blockOut); for (j = 0; j < remain; j++) - out[j] = blockOut[j]; + outPtr[j] = blockOut[j]; } } + st->dataSz += sz; + return WHAL_SUCCESS; } -static whal_Error EndOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) +whal_Error whal_Stm32n6_CrypAesCcm_Finalize(whal_AesCcm *dev, + void *tag, size_t tagSz) { - whal_Crypto_AesCcmArgs *args = (whal_Crypto_AesCcmArgs *)opArgs; - const whal_Stm32n6_Cryp_Cfg *cfg = - (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; + whal_Crypto *crypto; + const whal_Stm32n6_Cryp_Cfg *cfg; + whal_Stm32n6_AesCcm_State *st; + size_t base; uint8_t tagBuf[16]; - whal_Error err; size_t i; + whal_Error err; - if (!args->tag || args->tagSz < 4 || args->tagSz > 16 || - (args->tagSz & 1) != 0) + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state || + !tag || tagSz < 4 || tagSz > 16 || (tagSz & 1) != 0) return WHAL_EINVAL; + crypto = dev->crypto; + cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; + st = (whal_Stm32n6_AesCcm_State *)dev->state; + base = crypto->base; + + /* Final phase */ Disable(base); whal_Reg_Update(base, CRYP_CR_REG, CRYP_CR_GCM_CCMPH_Msk | CRYP_CR_ALGODIR_Msk, @@ -911,7 +1536,7 @@ static whal_Error EndOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) CRYP_GCM_CCMPH_FINAL)); Enable(base); - WriteBlock(base, cfg->ccmCtr0); + WriteBlock(base, st->ccmCtr0); err = WaitOutputReady(base, cfg->timeout); if (err) { @@ -920,134 +1545,16 @@ static whal_Error EndOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) } ReadBlock(base, tagBuf); - for (i = 0; i < args->tagSz; i++) - ((uint8_t *)args->tag)[i] = tagBuf[i]; + for (i = 0; i < tagSz; i++) + ((uint8_t *)tag)[i] = tagBuf[i]; Disable(base); return WHAL_SUCCESS; } -#endif /* WHAL_CFG_CRYPTO_AES_CCM */ - -whal_Error whal_Stm32n6_Cryp_StartOp(whal_Crypto *cryptoDev, size_t opId, - void *opArgs) -{ - if (!cryptoDev || !opArgs) - return WHAL_EINVAL; - - switch (opId) { -#ifdef WHAL_CFG_CRYPTO_AES_ECB - case WHAL_CRYPTO_AES_ECB: - return StartOp_AesEcb(cryptoDev, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CBC - case WHAL_CRYPTO_AES_CBC: - return StartOp_AesCbc(cryptoDev, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CTR - case WHAL_CRYPTO_AES_CTR: - return StartOp_AesCtr(cryptoDev, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_GCM - case WHAL_CRYPTO_AES_GCM: - return StartOp_AesGcm(cryptoDev, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_GMAC - case WHAL_CRYPTO_AES_GMAC: - return StartOp_AesGmac(cryptoDev, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CCM - case WHAL_CRYPTO_AES_CCM: - return StartOp_AesCcm(cryptoDev, opArgs); -#endif - default: - return WHAL_ENOTSUP; - } -} - -whal_Error whal_Stm32n6_Cryp_Process(whal_Crypto *cryptoDev, size_t opId, - void *opArgs) -{ - if (!cryptoDev || !opArgs) - return WHAL_EINVAL; - - switch (opId) { -#ifdef WHAL_CFG_CRYPTO_AES_ECB - case WHAL_CRYPTO_AES_ECB: { - whal_Crypto_AesEcbArgs *args = (whal_Crypto_AesEcbArgs *)opArgs; - return Process_BlockCipher(cryptoDev, args->in, args->out, args->sz); - } -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CBC - case WHAL_CRYPTO_AES_CBC: { - whal_Crypto_AesCbcArgs *args = (whal_Crypto_AesCbcArgs *)opArgs; - return Process_BlockCipher(cryptoDev, args->in, args->out, args->sz); - } -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CTR - case WHAL_CRYPTO_AES_CTR: { - whal_Crypto_AesCtrArgs *args = (whal_Crypto_AesCtrArgs *)opArgs; - return Process_BlockCipher(cryptoDev, args->in, args->out, args->sz); - } -#endif -#ifdef WHAL_CFG_CRYPTO_AES_GCM - case WHAL_CRYPTO_AES_GCM: - return Process_AesGcm(cryptoDev, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_GMAC - case WHAL_CRYPTO_AES_GMAC: - return WHAL_SUCCESS; -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CCM - case WHAL_CRYPTO_AES_CCM: - return Process_AesCcm(cryptoDev, opArgs); -#endif - default: - return WHAL_ENOTSUP; - } -} - -whal_Error whal_Stm32n6_Cryp_EndOp(whal_Crypto *cryptoDev, size_t opId, - void *opArgs) -{ - if (!cryptoDev || !opArgs) - return WHAL_EINVAL; - - switch (opId) { -#ifdef WHAL_CFG_CRYPTO_AES_ECB - case WHAL_CRYPTO_AES_ECB: - return EndOp_BlockCipher(cryptoDev); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CBC - case WHAL_CRYPTO_AES_CBC: - return EndOp_BlockCipher(cryptoDev); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CTR - case WHAL_CRYPTO_AES_CTR: - return EndOp_BlockCipher(cryptoDev); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_GCM - case WHAL_CRYPTO_AES_GCM: - return EndOp_AesGcm(cryptoDev, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_GMAC - case WHAL_CRYPTO_AES_GMAC: - return EndOp_AesGmac(cryptoDev, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CCM - case WHAL_CRYPTO_AES_CCM: - return EndOp_AesCcm(cryptoDev, opArgs); -#endif - default: - return WHAL_ENOTSUP; - } -} -#ifndef WHAL_CFG_STM32N6_CRYP_DIRECT_API_MAPPING -const whal_CryptoDriver whal_Stm32n6_Cryp_Driver = { - .Init = whal_Stm32n6_Cryp_Init, - .Deinit = whal_Stm32n6_Cryp_Deinit, - .StartOp = whal_Stm32n6_Cryp_StartOp, - .Process = whal_Stm32n6_Cryp_Process, - .EndOp = whal_Stm32n6_Cryp_EndOp, +const whal_AesCcmDriver whal_Stm32n6_Cryp_CcmDriver = { + .Oneshot = whal_Stm32n6_CrypAesCcm_Oneshot, + .Start = whal_Stm32n6_CrypAesCcm_Start, + .Process = whal_Stm32n6_CrypAesCcm_Process, + .Finalize = whal_Stm32n6_CrypAesCcm_Finalize, }; -#endif /* !WHAL_CFG_STM32N6_CRYP_DIRECT_API_MAPPING */ diff --git a/src/crypto/stm32wb_aes.c b/src/crypto/stm32wb_aes.c index 7a7ff27..4418118 100644 --- a/src/crypto/stm32wb_aes.c +++ b/src/crypto/stm32wb_aes.c @@ -142,52 +142,171 @@ static whal_Error WaitForCCF(size_t base, whal_Timeout *timeout) return WHAL_SUCCESS; } +static whal_Error ProcessBlockCipher(whal_Crypto *cryptoDev, + const uint8_t *in, uint8_t *out, + size_t sz) +{ + const whal_Stm32wb_Aes_Cfg *cfg = + (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; + size_t base = cryptoDev->base; + whal_Error err; + size_t i; + + if (sz == 0) + return WHAL_SUCCESS; -#ifdef WHAL_CFG_STM32WB_AES_DIRECT_API_MAPPING -#define whal_Stm32wb_Aes_Init whal_Crypto_Init -#define whal_Stm32wb_Aes_Deinit whal_Crypto_Deinit -#define whal_Stm32wb_Aes_StartOp whal_Crypto_StartOp -#define whal_Stm32wb_Aes_Process whal_Crypto_Process -#define whal_Stm32wb_Aes_EndOp whal_Crypto_EndOp -#endif /* WHAL_CFG_STM32WB_AES_DIRECT_API_MAPPING */ + if (!in || !out) + return WHAL_EINVAL; -whal_Error whal_Stm32wb_Aes_Init(whal_Crypto *cryptoDev) -{ - if (!cryptoDev || !cryptoDev->cfg) { + if ((sz & 0xF) != 0) return WHAL_EINVAL; + + for (i = 0; i < sz; i += 16) { + WriteBlock(base, in + i); + err = WaitForCCF(base, cfg->timeout); + if (err) { + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + return err; + } + ReadBlock(base, out + i); } return WHAL_SUCCESS; } -whal_Error whal_Stm32wb_Aes_Deinit(whal_Crypto *cryptoDev) +static void DisableAes(whal_Crypto *cryptoDev) { - if (!cryptoDev || !cryptoDev->cfg) { - return WHAL_EINVAL; - } + whal_Reg_Update(cryptoDev->base, AES_CR_REG, AES_CR_EN_Msk, 0); +} + + +/* ---- Direct API mapping ---- */ - whal_Reg_Update(cryptoDev->base, AES_CR_REG, AES_CR_EN_Msk, - whal_SetBits(AES_CR_EN_Msk, AES_CR_EN_Pos, 0)); +#ifdef WHAL_CFG_STM32WB_AES_INIT_DIRECT_API_MAPPING +#define whal_Stm32wb_Aes_Init whal_Crypto_Init +#define whal_Stm32wb_Aes_Deinit whal_Crypto_Deinit +#endif +#ifdef WHAL_CFG_STM32WB_AES_ECB_DIRECT_API_MAPPING +#define whal_Stm32wb_AesEcb_Oneshot whal_AesEcb_Oneshot +#define whal_Stm32wb_AesEcb_Start whal_AesEcb_Start +#define whal_Stm32wb_AesEcb_Process whal_AesEcb_Process +#endif +#ifdef WHAL_CFG_STM32WB_AES_CBC_DIRECT_API_MAPPING +#define whal_Stm32wb_AesCbc_Oneshot whal_AesCbc_Oneshot +#define whal_Stm32wb_AesCbc_Start whal_AesCbc_Start +#define whal_Stm32wb_AesCbc_Process whal_AesCbc_Process +#endif +#ifdef WHAL_CFG_STM32WB_AES_CTR_DIRECT_API_MAPPING +#define whal_Stm32wb_AesCtr_Oneshot whal_AesCtr_Oneshot +#define whal_Stm32wb_AesCtr_Start whal_AesCtr_Start +#define whal_Stm32wb_AesCtr_Process whal_AesCtr_Process +#endif +#ifdef WHAL_CFG_STM32WB_AES_GCM_DIRECT_API_MAPPING +#define whal_Stm32wb_AesGcm_Oneshot whal_AesGcm_Oneshot +#define whal_Stm32wb_AesGcm_Start whal_AesGcm_Start +#define whal_Stm32wb_AesGcm_Process whal_AesGcm_Process +#define whal_Stm32wb_AesGcm_Finalize whal_AesGcm_Finalize +#endif +#ifdef WHAL_CFG_STM32WB_AES_GMAC_DIRECT_API_MAPPING +#define whal_Stm32wb_AesGmac_Oneshot whal_AesGmac_Oneshot +#endif +#ifdef WHAL_CFG_STM32WB_AES_CCM_DIRECT_API_MAPPING +#define whal_Stm32wb_AesCcm_Oneshot whal_AesCcm_Oneshot +#define whal_Stm32wb_AesCcm_Start whal_AesCcm_Start +#define whal_Stm32wb_AesCcm_Process whal_AesCcm_Process +#define whal_Stm32wb_AesCcm_Finalize whal_AesCcm_Finalize +#endif + +/* ---- Init / Deinit ---- */ + +whal_Error whal_Stm32wb_Aes_Init(whal_Crypto *dev) +{ + if (!dev) + return WHAL_EINVAL; return WHAL_SUCCESS; } -#ifdef WHAL_CFG_CRYPTO_AES_ECB -static whal_Error StartOp_AesEcb(whal_Crypto *cryptoDev, void *opArgs) +whal_Error whal_Stm32wb_Aes_Deinit(whal_Crypto *dev) { - whal_Crypto_AesEcbArgs *args = (whal_Crypto_AesEcbArgs *)opArgs; - size_t base = cryptoDev->base; + if (!dev) + return WHAL_EINVAL; + DisableAes(dev); + return WHAL_SUCCESS; +} + +const whal_CryptoDriver whal_Stm32wb_Aes_CryptoDriver = { + .Init = whal_Stm32wb_Aes_Init, + .Deinit = whal_Stm32wb_Aes_Deinit, +}; + + +/* ---- AES-ECB ---- */ + +whal_Error whal_Stm32wb_AesEcb_Oneshot(whal_AesEcb *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *in, void *out, size_t sz) +{ + whal_Crypto *crypto; + size_t base; + size_t mode; + size_t keySizeBit; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg || !key) + return WHAL_EINVAL; + + crypto = dev->crypto; + base = crypto->base; + + if (keySz != 16 && keySz != 32) + return WHAL_ENOTSUP; + + keySizeBit = (keySz == 32) ? 1 : 0; + mode = (dir == WHAL_CRYPTO_ENCRYPT) + ? AES_MODE_ENCRYPT : AES_MODE_KEYDERIV_DECRYPT; + + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + + whal_Reg_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_ECB) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit)); + + WriteKey(base, key, keySz); + + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + + err = ProcessBlockCipher(crypto, in, out, sz); + DisableAes(crypto); + return err; +} + +whal_Error whal_Stm32wb_AesEcb_Start(whal_AesEcb *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz) +{ + whal_Crypto *crypto; + size_t base; size_t mode; size_t keySizeBit; - if (!args->key) + if (!dev || !dev->crypto || !dev->crypto->cfg || !key) return WHAL_EINVAL; - if (args->keySz != 16 && args->keySz != 32) + crypto = dev->crypto; + base = crypto->base; + + if (keySz != 16 && keySz != 32) return WHAL_ENOTSUP; - keySizeBit = (args->keySz == 32) ? 1 : 0; - mode = (args->dir == WHAL_CRYPTO_ENCRYPT) + keySizeBit = (keySz == 32) ? 1 : 0; + mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_KEYDERIV_DECRYPT; whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); @@ -203,30 +322,50 @@ static whal_Error StartOp_AesEcb(whal_Crypto *cryptoDev, void *opArgs) whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, keySizeBit)); - WriteKey(base, args->key, args->keySz); + WriteKey(base, key, keySz); whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); return WHAL_SUCCESS; } -#endif /* WHAL_CFG_CRYPTO_AES_ECB */ -#ifdef WHAL_CFG_CRYPTO_AES_CBC -static whal_Error StartOp_AesCbc(whal_Crypto *cryptoDev, void *opArgs) +whal_Error whal_Stm32wb_AesEcb_Process(whal_AesEcb *dev, + const void *in, void *out, size_t sz) { - whal_Crypto_AesCbcArgs *args = (whal_Crypto_AesCbcArgs *)opArgs; - size_t base = cryptoDev->base; + return ProcessBlockCipher(dev->crypto, in, out, sz); +} + +const whal_AesEcbDriver whal_Stm32wb_Aes_EcbDriver = { + .Oneshot = whal_Stm32wb_AesEcb_Oneshot, + .Start = whal_Stm32wb_AesEcb_Start, + .Process = whal_Stm32wb_AesEcb_Process, +}; + + +/* ---- AES-CBC ---- */ + +whal_Error whal_Stm32wb_AesCbc_Oneshot(whal_AesCbc *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, + const void *in, void *out, size_t sz) +{ + whal_Crypto *crypto; + size_t base; size_t mode; size_t keySizeBit; + whal_Error err; - if (!args->key || !args->iv) + if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) return WHAL_EINVAL; - if (args->keySz != 16 && args->keySz != 32) + crypto = dev->crypto; + base = crypto->base; + + if (keySz != 16 && keySz != 32) return WHAL_ENOTSUP; - keySizeBit = (args->keySz == 32) ? 1 : 0; - mode = (args->dir == WHAL_CRYPTO_ENCRYPT) + keySizeBit = (keySz == 32) ? 1 : 0; + mode = (dir == WHAL_CRYPTO_ENCRYPT) ? AES_MODE_ENCRYPT : AES_MODE_KEYDERIV_DECRYPT; whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); @@ -242,29 +381,137 @@ static whal_Error StartOp_AesCbc(whal_Crypto *cryptoDev, void *opArgs) whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, keySizeBit)); - WriteKey(base, args->key, args->keySz); - WriteIv(base, args->iv); + WriteKey(base, key, keySz); + WriteIv(base, iv); + + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + + err = ProcessBlockCipher(crypto, in, out, sz); + DisableAes(crypto); + return err; +} + +whal_Error whal_Stm32wb_AesCbc_Start(whal_AesCbc *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv) +{ + whal_Crypto *crypto; + size_t base; + size_t mode; + size_t keySizeBit; + + if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) + return WHAL_EINVAL; + + crypto = dev->crypto; + base = crypto->base; + + if (keySz != 16 && keySz != 32) + return WHAL_ENOTSUP; + + keySizeBit = (keySz == 32) ? 1 : 0; + mode = (dir == WHAL_CRYPTO_ENCRYPT) + ? AES_MODE_ENCRYPT : AES_MODE_KEYDERIV_DECRYPT; + + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + + whal_Reg_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_CBC) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit)); + + WriteKey(base, key, keySz); + WriteIv(base, iv); whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); return WHAL_SUCCESS; } -#endif /* WHAL_CFG_CRYPTO_AES_CBC */ -#ifdef WHAL_CFG_CRYPTO_AES_CTR -static whal_Error StartOp_AesCtr(whal_Crypto *cryptoDev, void *opArgs) +whal_Error whal_Stm32wb_AesCbc_Process(whal_AesCbc *dev, + const void *in, void *out, size_t sz) { - whal_Crypto_AesCtrArgs *args = (whal_Crypto_AesCtrArgs *)opArgs; - size_t base = cryptoDev->base; + return ProcessBlockCipher(dev->crypto, in, out, sz); +} + +const whal_AesCbcDriver whal_Stm32wb_Aes_CbcDriver = { + .Oneshot = whal_Stm32wb_AesCbc_Oneshot, + .Start = whal_Stm32wb_AesCbc_Start, + .Process = whal_Stm32wb_AesCbc_Process, +}; + + +/* ---- AES-CTR ---- */ + +whal_Error whal_Stm32wb_AesCtr_Oneshot(whal_AesCtr *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, + const void *in, void *out, size_t sz) +{ + whal_Crypto *crypto; + size_t base; + size_t keySizeBit; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) + return WHAL_EINVAL; + + crypto = dev->crypto; + base = crypto->base; + + if (keySz != 16 && keySz != 32) + return WHAL_ENOTSUP; + + keySizeBit = (keySz == 32) ? 1 : 0; + + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + + whal_Reg_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_CTR) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit)); + + WriteKey(base, key, keySz); + WriteIv(base, iv); + + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + + err = ProcessBlockCipher(crypto, in, out, sz); + DisableAes(crypto); + return err; +} + +whal_Error whal_Stm32wb_AesCtr_Start(whal_AesCtr *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv) +{ + whal_Crypto *crypto; + size_t base; size_t keySizeBit; - if (!args->key || !args->iv) + if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) return WHAL_EINVAL; - if (args->keySz != 16 && args->keySz != 32) + crypto = dev->crypto; + base = crypto->base; + + if (keySz != 16 && keySz != 32) return WHAL_ENOTSUP; - keySizeBit = (args->keySz == 32) ? 1 : 0; + keySizeBit = (keySz == 32) ? 1 : 0; whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); @@ -280,90 +527,247 @@ static whal_Error StartOp_AesCtr(whal_Crypto *cryptoDev, void *opArgs) whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, keySizeBit)); - WriteKey(base, args->key, args->keySz); - WriteIv(base, args->iv); + WriteKey(base, key, keySz); + WriteIv(base, iv); whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); return WHAL_SUCCESS; } -#endif /* WHAL_CFG_CRYPTO_AES_CTR */ -#if defined(WHAL_CFG_CRYPTO_AES_ECB) || defined(WHAL_CFG_CRYPTO_AES_CBC) || \ - defined(WHAL_CFG_CRYPTO_AES_CTR) -static whal_Error Process_BlockCipher(whal_Crypto *cryptoDev, - const uint8_t *in, uint8_t *out, - size_t sz) +whal_Error whal_Stm32wb_AesCtr_Process(whal_AesCtr *dev, + const void *in, void *out, size_t sz) { - const whal_Stm32wb_Aes_Cfg *cfg = - (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; - whal_Error err; + return ProcessBlockCipher(dev->crypto, in, out, sz); +} + +const whal_AesCtrDriver whal_Stm32wb_Aes_CtrDriver = { + .Oneshot = whal_Stm32wb_AesCtr_Oneshot, + .Start = whal_Stm32wb_AesCtr_Start, + .Process = whal_Stm32wb_AesCtr_Process, +}; + + +/* ---- AES-GCM ---- */ + +whal_Error whal_Stm32wb_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz, + const void *in, void *out, size_t sz, + void *tag, size_t tagSz) +{ + whal_Crypto *crypto; + const whal_Stm32wb_Aes_Cfg *cfg; + size_t base; + const uint8_t *ivBytes = (const uint8_t *)iv; + const uint8_t *aadBytes = (const uint8_t *)aad; + size_t keySizeBit; + size_t mode; size_t i; + uint8_t tagBuf[16]; + whal_Error err; - if (sz == 0) - return WHAL_SUCCESS; + if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) + return WHAL_EINVAL; - if (!in || !out) + crypto = dev->crypto; + cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + base = crypto->base; + + if (keySz != 16 && keySz != 32) + return WHAL_ENOTSUP; + + if (ivSz != 12) + return WHAL_ENOTSUP; + + if (sz > 0 && (!in || !out)) return WHAL_EINVAL; - if ((sz & 0xF) != 0) + if (aadSz > 0 && !aad) return WHAL_EINVAL; - for (i = 0; i < sz; i += 16) { - WriteBlock(base, in + i); - err = WaitForCCF(base, cfg->timeout); - if (err) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - return err; + if (!tag || tagSz == 0 || tagSz > 16) + return WHAL_EINVAL; + + keySizeBit = (keySz == 32) ? 1 : 0; + + /* Init phase */ + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + + whal_Reg_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | + AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_GCM) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_INIT)); + + WriteKey(base, key, keySz); + + whal_Reg_Write(base, AES_IVR3_REG, whal_LoadBe32(ivBytes)); + whal_Reg_Write(base, AES_IVR2_REG, whal_LoadBe32(ivBytes + 4)); + whal_Reg_Write(base, AES_IVR1_REG, whal_LoadBe32(ivBytes + 8)); + whal_Reg_Write(base, AES_IVR0_REG, 0x00000002); + + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + + err = WaitForCCF(base, cfg->timeout); + if (err) + goto cleanup; + + /* Header phase (AAD) */ + if (aadSz > 0) { + whal_Reg_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_HEADER)); + + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + + for (i = 0; i < aadSz; i += 16) { + const uint8_t *blkAad = aadBytes + i; + size_t remain = aadSz - i; + uint8_t block[16] = {0}; + size_t j; + + if (remain >= 16) { + WriteBlock(base, blkAad); + } else { + for (j = 0; j < remain; j++) + block[j] = blkAad[j]; + WriteBlock(base, block); + } + + err = WaitForCCF(base, cfg->timeout); + if (err) + goto cleanup; } - ReadBlock(base, out + i); } - return WHAL_SUCCESS; -} + /* Payload phase */ + if (sz > 0) { + mode = (dir == WHAL_CRYPTO_ENCRYPT) + ? AES_MODE_ENCRYPT : AES_MODE_DECRYPT; -static whal_Error EndOp_BlockCipher(whal_Crypto *cryptoDev) -{ - whal_Reg_Update(cryptoDev->base, AES_CR_REG, AES_CR_EN_Msk, 0); + whal_Reg_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + mode) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_PAYLOAD)); - return WHAL_SUCCESS; + if (aadSz == 0) + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + + for (i = 0; i < sz; i += 16) { + const uint8_t *inBlk = (const uint8_t *)in + i; + uint8_t *outBlk = (uint8_t *)out + i; + size_t remain = sz - i; + uint8_t block[16] = {0}; + size_t j; + + if (remain >= 16) { + WriteBlock(base, inBlk); + } else { + if (mode == AES_MODE_ENCRYPT) { + whal_Reg_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_NPBLB_Msk, + AES_CR_NPBLB_Pos, + 16 - remain)); + } + for (j = 0; j < remain; j++) + block[j] = inBlk[j]; + WriteBlock(base, block); + } + + err = WaitForCCF(base, cfg->timeout); + if (err) + goto cleanup; + + if (remain >= 16) { + ReadBlock(base, outBlk); + } else { + ReadBlock(base, block); + for (j = 0; j < remain; j++) + outBlk[j] = block[j]; + } + } + } + + /* Final phase (tag) */ + whal_Reg_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_FINAL)); + + if (aadSz == 0 && sz == 0) + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + + whal_Reg_Write(base, AES_DINR_REG, 0); + whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(aadSz * 8)); + whal_Reg_Write(base, AES_DINR_REG, 0); + whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(sz * 8)); + + err = WaitForCCF(base, cfg->timeout); + if (err) + goto cleanup; + + ReadBlock(base, tagBuf); + + for (i = 0; i < tagSz; i++) + ((uint8_t *)tag)[i] = tagBuf[i]; + +cleanup: + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + return err; } -#endif /* WHAL_CFG_CRYPTO_AES_ECB || CBC || CTR */ -#ifdef WHAL_CFG_CRYPTO_AES_GCM -static whal_Error StartOp_AesGcm(whal_Crypto *cryptoDev, void *opArgs) +whal_Error whal_Stm32wb_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz) { - whal_Error err; - whal_Crypto_AesGcmArgs *args = (whal_Crypto_AesGcmArgs *)opArgs; - const whal_Stm32wb_Aes_Cfg *cfg = - (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; - const uint8_t *iv; - const uint8_t *aad; + whal_Crypto *crypto; + const whal_Stm32wb_Aes_Cfg *cfg; + size_t base; + const uint8_t *ivBytes = (const uint8_t *)iv; + const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; + size_t mode; size_t i; + whal_Error err; - if (!args->key || !args->iv) + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state || !key || !iv) return WHAL_EINVAL; - iv = (const uint8_t *)args->iv; - aad = (const uint8_t *)args->aad; + crypto = dev->crypto; + cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + base = crypto->base; - if (args->keySz != 16 && args->keySz != 32) + if (keySz != 16 && keySz != 32) return WHAL_ENOTSUP; - if (args->ivSz != 12) + if (ivSz != 12) return WHAL_ENOTSUP; - if (args->sz > 0 && (!args->in || !args->out)) + if (aadSz > 0 && !aad) return WHAL_EINVAL; - if (args->aadSz > 0 && !args->aad) - return WHAL_EINVAL; - - keySizeBit = (args->keySz == 32) ? 1 : 0; + keySizeBit = (keySz == 32) ? 1 : 0; + /* Init phase */ whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); whal_Reg_Update(base, AES_CR_REG, @@ -381,11 +785,11 @@ static whal_Error StartOp_AesGcm(whal_Crypto *cryptoDev, void *opArgs) whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, AES_GCMPH_INIT)); - WriteKey(base, args->key, args->keySz); + WriteKey(base, key, keySz); - whal_Reg_Write(base, AES_IVR3_REG, whal_LoadBe32(iv)); - whal_Reg_Write(base, AES_IVR2_REG, whal_LoadBe32(iv + 4)); - whal_Reg_Write(base, AES_IVR1_REG, whal_LoadBe32(iv + 8)); + whal_Reg_Write(base, AES_IVR3_REG, whal_LoadBe32(ivBytes)); + whal_Reg_Write(base, AES_IVR2_REG, whal_LoadBe32(ivBytes + 4)); + whal_Reg_Write(base, AES_IVR1_REG, whal_LoadBe32(ivBytes + 8)); whal_Reg_Write(base, AES_IVR0_REG, 0x00000002); whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); @@ -394,7 +798,8 @@ static whal_Error StartOp_AesGcm(whal_Crypto *cryptoDev, void *opArgs) if (err) goto cleanup; - if (args->aadSz > 0) { + /* Header phase (AAD) */ + if (aadSz > 0) { whal_Reg_Update(base, AES_CR_REG, AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, @@ -404,9 +809,9 @@ static whal_Error StartOp_AesGcm(whal_Crypto *cryptoDev, void *opArgs) whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); - for (i = 0; i < args->aadSz; i += 16) { - const uint8_t *blkAad = aad + i; - size_t remain = args->aadSz - i; + for (i = 0; i < aadSz; i += 16) { + const uint8_t *blkAad = aadBytes + i; + size_t remain = aadSz - i; uint8_t block[16] = {0}; size_t j; @@ -424,6 +829,25 @@ static whal_Error StartOp_AesGcm(whal_Crypto *cryptoDev, void *opArgs) } } + /* Transition to payload phase */ + mode = (dir == WHAL_CRYPTO_ENCRYPT) + ? AES_MODE_ENCRYPT : AES_MODE_DECRYPT; + + whal_Reg_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_PAYLOAD)); + + if (aadSz == 0) + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + + { + whal_Stm32wb_AesGcm_State *st = (whal_Stm32wb_AesGcm_State *)dev->state; + st->aadSz = aadSz; + st->dataSz = 0; + } + return WHAL_SUCCESS; cleanup: @@ -431,87 +855,238 @@ static whal_Error StartOp_AesGcm(whal_Crypto *cryptoDev, void *opArgs) return err; } -static whal_Error Process_AesGcm(whal_Crypto *cryptoDev, void *opArgs) +whal_Error whal_Stm32wb_AesGcm_Process(whal_AesGcm *dev, + const void *in, void *out, size_t sz) { - whal_Crypto_AesGcmArgs *args = (whal_Crypto_AesGcmArgs *)opArgs; - const whal_Stm32wb_Aes_Cfg *cfg = - (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; + whal_Crypto *crypto; + const whal_Stm32wb_Aes_Cfg *cfg; + size_t base; + whal_Stm32wb_AesGcm_State *st; size_t mode; - whal_Error err; size_t i; + whal_Error err; - if (args->sz == 0) + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) + return WHAL_EINVAL; + + crypto = dev->crypto; + cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + base = crypto->base; + st = (whal_Stm32wb_AesGcm_State *)dev->state; + + if (sz == 0) return WHAL_SUCCESS; - if (!args->in || !args->out) + if (!in || !out) return WHAL_EINVAL; - mode = (args->dir == WHAL_CRYPTO_ENCRYPT) - ? AES_MODE_ENCRYPT : AES_MODE_DECRYPT; + mode = whal_GetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + whal_Reg_Read(base, AES_CR_REG)); + + for (i = 0; i < sz; i += 16) { + const uint8_t *inBlk = (const uint8_t *)in + i; + uint8_t *outBlk = (uint8_t *)out + i; + size_t remain = sz - i; + uint8_t block[16] = {0}; + size_t j; + + if (remain >= 16) { + WriteBlock(base, inBlk); + } else { + if (mode == AES_MODE_ENCRYPT) { + whal_Reg_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_NPBLB_Msk, + AES_CR_NPBLB_Pos, + 16 - remain)); + } + for (j = 0; j < remain; j++) + block[j] = inBlk[j]; + WriteBlock(base, block); + } + + err = WaitForCCF(base, cfg->timeout); + if (err) { + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + return err; + } + + if (remain >= 16) { + ReadBlock(base, outBlk); + } else { + ReadBlock(base, block); + for (j = 0; j < remain; j++) + outBlk[j] = block[j]; + } + } + + st->dataSz += sz; + + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32wb_AesGcm_Finalize(whal_AesGcm *dev, + void *tag, size_t tagSz) +{ + whal_Crypto *crypto; + const whal_Stm32wb_Aes_Cfg *cfg; + size_t base; + whal_Stm32wb_AesGcm_State *st; + uint8_t tagBuf[16]; + size_t i; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) + return WHAL_EINVAL; + + crypto = dev->crypto; + cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + base = crypto->base; + st = (whal_Stm32wb_AesGcm_State *)dev->state; + + if (!tag || tagSz == 0 || tagSz > 16) + return WHAL_EINVAL; + /* Final phase (tag) */ whal_Reg_Update(base, AES_CR_REG, AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_PAYLOAD)); + AES_GCMPH_FINAL)); + + if (st->aadSz == 0 && st->dataSz == 0) + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + + whal_Reg_Write(base, AES_DINR_REG, 0); + whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(st->aadSz * 8)); + whal_Reg_Write(base, AES_DINR_REG, 0); + whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(st->dataSz * 8)); + + err = WaitForCCF(base, cfg->timeout); + if (err) { + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + return err; + } + + ReadBlock(base, tagBuf); + + for (i = 0; i < tagSz; i++) + ((uint8_t *)tag)[i] = tagBuf[i]; + + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + return WHAL_SUCCESS; +} + +const whal_AesGcmDriver whal_Stm32wb_Aes_GcmDriver = { + .Oneshot = whal_Stm32wb_AesGcm_Oneshot, + .Start = whal_Stm32wb_AesGcm_Start, + .Process = whal_Stm32wb_AesGcm_Process, + .Finalize = whal_Stm32wb_AesGcm_Finalize, +}; + + +/* ---- AES-GMAC ---- */ + +whal_Error whal_Stm32wb_AesGmac_Oneshot(whal_AesGmac *dev, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz, + void *tag, size_t tagSz) +{ + whal_Crypto *crypto; + const whal_Stm32wb_Aes_Cfg *cfg; + size_t base; + const uint8_t *ivBytes = (const uint8_t *)iv; + const uint8_t *aadBytes = (const uint8_t *)aad; + size_t keySizeBit; + size_t i; + uint8_t tagBuf[16]; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) + return WHAL_EINVAL; + + crypto = dev->crypto; + cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + base = crypto->base; + + if (keySz != 16 && keySz != 32) + return WHAL_ENOTSUP; + + if (ivSz != 12) + return WHAL_ENOTSUP; + + if (aadSz > 0 && !aad) + return WHAL_EINVAL; + + if (!tag || tagSz == 0 || tagSz > 16) + return WHAL_EINVAL; + + keySizeBit = (keySz == 32) ? 1 : 0; + + /* Init phase */ + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + + whal_Reg_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_CHMOD_Msk | AES_CR_CHMOD2_Msk | + AES_CR_DATATYPE_Msk | AES_CR_KEYSIZE_Msk | + AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, + AES_CHMOD_GCM) | + whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, + AES_DATATYPE_NONE) | + whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, + keySizeBit) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_INIT)); + + WriteKey(base, key, keySz); + + whal_Reg_Write(base, AES_IVR3_REG, whal_LoadBe32(ivBytes)); + whal_Reg_Write(base, AES_IVR2_REG, whal_LoadBe32(ivBytes + 4)); + whal_Reg_Write(base, AES_IVR1_REG, whal_LoadBe32(ivBytes + 8)); + whal_Reg_Write(base, AES_IVR0_REG, 0x00000002); + + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + + err = WaitForCCF(base, cfg->timeout); + if (err) + goto cleanup; + + /* Header phase (AAD) */ + if (aadSz > 0) { + whal_Reg_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + AES_MODE_ENCRYPT) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_HEADER)); - if (args->aadSz == 0) whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); - for (i = 0; i < args->sz; i += 16) { - const uint8_t *in = (const uint8_t *)args->in + i; - uint8_t *out = (uint8_t *)args->out + i; - size_t remain = args->sz - i; - uint8_t block[16] = {0}; - size_t j; + for (i = 0; i < aadSz; i += 16) { + const uint8_t *blkAad = aadBytes + i; + size_t remain = aadSz - i; + uint8_t block[16] = {0}; + size_t j; - if (remain >= 16) { - WriteBlock(base, in); - } else { - if (mode == AES_MODE_ENCRYPT) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_NPBLB_Msk, AES_CR_NPBLB_Pos, 16 - remain)); + if (remain >= 16) { + WriteBlock(base, blkAad); + } else { + for (j = 0; j < remain; j++) + block[j] = blkAad[j]; + WriteBlock(base, block); } - for (j = 0; j < remain; j++) - block[j] = in[j]; - WriteBlock(base, block); - } - - err = WaitForCCF(base, cfg->timeout); - if (err) { - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - return err; - } - if (remain >= 16) { - ReadBlock(base, out); - } else { - ReadBlock(base, block); - for (j = 0; j < remain; j++) - out[j] = block[j]; + err = WaitForCCF(base, cfg->timeout); + if (err) + goto cleanup; } } - return WHAL_SUCCESS; -} - -static whal_Error EndOp_AesGcm(whal_Crypto *cryptoDev, void *opArgs) -{ - whal_Crypto_AesGcmArgs *args = (whal_Crypto_AesGcmArgs *)opArgs; - const whal_Stm32wb_Aes_Cfg *cfg = - (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; - uint8_t *tag; - whal_Error err; - uint8_t tagBuf[16]; - size_t i; - - if (!args->tag || args->tagSz == 0 || args->tagSz > 16) - return WHAL_EINVAL; - - tag = (uint8_t *)args->tag; - + /* Final phase (tag) -- no payload for GMAC */ whal_Reg_Update(base, AES_CR_REG, AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, @@ -519,13 +1094,13 @@ static whal_Error EndOp_AesGcm(whal_Crypto *cryptoDev, void *opArgs) whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, AES_GCMPH_FINAL)); - if (args->aadSz == 0 && args->sz == 0) + if (aadSz == 0) whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); whal_Reg_Write(base, AES_DINR_REG, 0); - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(args->aadSz * 8)); + whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(aadSz * 8)); + whal_Reg_Write(base, AES_DINR_REG, 0); whal_Reg_Write(base, AES_DINR_REG, 0); - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(args->sz * 8)); err = WaitForCCF(base, cfg->timeout); if (err) @@ -533,46 +1108,86 @@ static whal_Error EndOp_AesGcm(whal_Crypto *cryptoDev, void *opArgs) ReadBlock(base, tagBuf); - for (i = 0; i < args->tagSz; i++) - tag[i] = tagBuf[i]; + for (i = 0; i < tagSz; i++) + ((uint8_t *)tag)[i] = tagBuf[i]; cleanup: whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - return err; } -#endif /* WHAL_CFG_CRYPTO_AES_GCM */ -#ifdef WHAL_CFG_CRYPTO_AES_GMAC -static whal_Error StartOp_AesGmac(whal_Crypto *cryptoDev, void *opArgs) +const whal_AesGmacDriver whal_Stm32wb_Aes_GmacDriver = { + .Oneshot = whal_Stm32wb_AesGmac_Oneshot, +}; + + +/* ---- AES-CCM ---- */ + +whal_Error whal_Stm32wb_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *nonce, size_t nonceSz, + const void *aad, size_t aadSz, + const void *in, void *out, size_t sz, + void *tag, size_t tagSz) { - whal_Error err; - whal_Crypto_AesGmacArgs *args = (whal_Crypto_AesGmacArgs *)opArgs; - const whal_Stm32wb_Aes_Cfg *cfg = - (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; - const uint8_t *iv; - const uint8_t *aad; + whal_Crypto *crypto; + const whal_Stm32wb_Aes_Cfg *cfg; + size_t base; + const uint8_t *nonceBytes = (const uint8_t *)nonce; + const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; + size_t mode; size_t i; + uint8_t b0[16]; + uint8_t tagBuf[16]; + whal_Error err; - if (!args->key || !args->iv) + if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !nonce) return WHAL_EINVAL; - iv = (const uint8_t *)args->iv; - aad = (const uint8_t *)args->aad; + crypto = dev->crypto; + cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + base = crypto->base; - if (args->keySz != 16 && args->keySz != 32) + if (keySz != 16 && keySz != 32) return WHAL_ENOTSUP; - if (args->ivSz != 12) - return WHAL_ENOTSUP; + if (nonceSz < 7 || nonceSz > 13) + return WHAL_EINVAL; - if (args->aadSz > 0 && !args->aad) + if (sz > 0 && (!in || !out)) return WHAL_EINVAL; - keySizeBit = (args->keySz == 32) ? 1 : 0; + if (aadSz > 0 && !aad) + return WHAL_EINVAL; + + if (!tag || tagSz < 4 || tagSz > 16 || (tagSz & 1) != 0) + return WHAL_EINVAL; + + keySizeBit = (keySz == 32) ? 1 : 0; + + /* Build B0 */ + { + size_t q = 15 - nonceSz; + size_t t = tagSz; + uint8_t flags = (uint8_t)(((aadSz > 0) ? 0x40 : 0) | + (((t - 2) / 2) << 3) | + (q - 1)); + b0[0] = flags; + for (i = 0; i < nonceSz; i++) + b0[1 + i] = nonceBytes[i]; + + { + size_t msgLen = sz; + size_t j; + for (j = 0; j < q; j++) { + b0[15 - j] = (uint8_t)(msgLen & 0xFF); + msgLen >>= 8; + } + } + } + /* Init phase */ whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); whal_Reg_Update(base, AES_CR_REG, @@ -581,8 +1196,8 @@ static whal_Error StartOp_AesGmac(whal_Crypto *cryptoDev, void *opArgs) AES_CR_GCMPH_Msk | AES_CR_NPBLB_Msk, whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, AES_MODE_ENCRYPT) | - whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, - AES_CHMOD_GCM) | + whal_SetBits(AES_CR_CHMOD_Msk, AES_CR_CHMOD_Pos, 0) | + AES_CR_CHMOD2_Msk | whal_SetBits(AES_CR_DATATYPE_Msk, AES_CR_DATATYPE_Pos, AES_DATATYPE_NONE) | whal_SetBits(AES_CR_KEYSIZE_Msk, AES_CR_KEYSIZE_Pos, @@ -590,12 +1205,8 @@ static whal_Error StartOp_AesGmac(whal_Crypto *cryptoDev, void *opArgs) whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, AES_GCMPH_INIT)); - WriteKey(base, args->key, args->keySz); - - whal_Reg_Write(base, AES_IVR3_REG, whal_LoadBe32(iv)); - whal_Reg_Write(base, AES_IVR2_REG, whal_LoadBe32(iv + 4)); - whal_Reg_Write(base, AES_IVR1_REG, whal_LoadBe32(iv + 8)); - whal_Reg_Write(base, AES_IVR0_REG, 0x00000002); + WriteKey(base, key, keySz); + WriteIv(base, b0); whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); @@ -603,7 +1214,8 @@ static whal_Error StartOp_AesGmac(whal_Crypto *cryptoDev, void *opArgs) if (err) goto cleanup; - if (args->aadSz > 0) { + /* Header phase (AAD) */ + if (aadSz > 0) { whal_Reg_Update(base, AES_CR_REG, AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, @@ -613,49 +1225,90 @@ static whal_Error StartOp_AesGmac(whal_Crypto *cryptoDev, void *opArgs) whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); - for (i = 0; i < args->aadSz; i += 16) { - const uint8_t *blkAad = aad + i; - size_t remain = args->aadSz - i; - uint8_t block[16] = {0}; + { + uint8_t hdrBuf[16] = {0}; + size_t hdrOff = 0; + size_t aadOff = 0; size_t j; - if (remain >= 16) { - WriteBlock(base, blkAad); - } else { - for (j = 0; j < remain; j++) - block[j] = blkAad[j]; - WriteBlock(base, block); + hdrBuf[0] = (uint8_t)(aadSz >> 8); + hdrBuf[1] = (uint8_t)(aadSz); + hdrOff = 2; + + while (hdrOff < 16 && aadOff < aadSz) { + hdrBuf[hdrOff++] = aadBytes[aadOff++]; } + WriteBlock(base, hdrBuf); err = WaitForCCF(base, cfg->timeout); if (err) goto cleanup; + + while (aadOff < aadSz) { + uint8_t block[16] = {0}; + + for (j = 0; j < 16 && aadOff < aadSz; j++) + block[j] = aadBytes[aadOff++]; + + WriteBlock(base, block); + err = WaitForCCF(base, cfg->timeout); + if (err) + goto cleanup; + } } } - return WHAL_SUCCESS; + /* Payload phase */ + if (sz > 0) { + mode = (dir == WHAL_CRYPTO_ENCRYPT) + ? AES_MODE_ENCRYPT : AES_MODE_DECRYPT; -cleanup: - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - return err; -} + whal_Reg_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + mode) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_PAYLOAD)); -static whal_Error EndOp_AesGmac(whal_Crypto *cryptoDev, void *opArgs) -{ - whal_Crypto_AesGmacArgs *args = (whal_Crypto_AesGmacArgs *)opArgs; - const whal_Stm32wb_Aes_Cfg *cfg = - (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; - uint8_t *tag; - whal_Error err; - uint8_t tagBuf[16]; - size_t i; + if (aadSz == 0) + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); - if (!args->tag || args->tagSz == 0 || args->tagSz > 16) - return WHAL_EINVAL; + for (i = 0; i < sz; i += 16) { + const uint8_t *inBlk = (const uint8_t *)in + i; + uint8_t *outBlk = (uint8_t *)out + i; + size_t remain = sz - i; + uint8_t block[16] = {0}; + size_t j; + + if (remain >= 16) { + WriteBlock(base, inBlk); + } else { + if (mode == AES_MODE_DECRYPT) { + whal_Reg_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, + whal_SetBits(AES_CR_NPBLB_Msk, + AES_CR_NPBLB_Pos, + 16 - remain)); + } + for (j = 0; j < remain; j++) + block[j] = inBlk[j]; + WriteBlock(base, block); + } + + err = WaitForCCF(base, cfg->timeout); + if (err) + goto cleanup; - tag = (uint8_t *)args->tag; + if (remain >= 16) { + ReadBlock(base, outBlk); + } else { + ReadBlock(base, block); + for (j = 0; j < remain; j++) + outBlk[j] = block[j]; + } + } + } + /* Final phase (tag) */ whal_Reg_Update(base, AES_CR_REG, AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, @@ -663,11 +1316,11 @@ static whal_Error EndOp_AesGmac(whal_Crypto *cryptoDev, void *opArgs) whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, AES_GCMPH_FINAL)); - if (args->aadSz == 0) + if (aadSz == 0 && sz == 0) whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); whal_Reg_Write(base, AES_DINR_REG, 0); - whal_Reg_Write(base, AES_DINR_REG, (uint32_t)(args->aadSz * 8)); + whal_Reg_Write(base, AES_DINR_REG, 0); whal_Reg_Write(base, AES_DINR_REG, 0); whal_Reg_Write(base, AES_DINR_REG, 0); @@ -677,62 +1330,65 @@ static whal_Error EndOp_AesGmac(whal_Crypto *cryptoDev, void *opArgs) ReadBlock(base, tagBuf); - for (i = 0; i < args->tagSz; i++) - tag[i] = tagBuf[i]; + for (i = 0; i < tagSz; i++) + ((uint8_t *)tag)[i] = tagBuf[i]; cleanup: whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - return err; } -#endif /* WHAL_CFG_CRYPTO_AES_GMAC */ -#ifdef WHAL_CFG_CRYPTO_AES_CCM -static whal_Error StartOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) +whal_Error whal_Stm32wb_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *nonce, size_t nonceSz, + const void *aad, size_t aadSz, + size_t tagSz, size_t sz) { - whal_Error err; - whal_Crypto_AesCcmArgs *args = (whal_Crypto_AesCcmArgs *)opArgs; - const whal_Stm32wb_Aes_Cfg *cfg = - (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; - const uint8_t *nonce = (const uint8_t *)args->nonce; - const uint8_t *aad = (const uint8_t *)args->aad; + whal_Crypto *crypto; + const whal_Stm32wb_Aes_Cfg *cfg; + size_t base; + const uint8_t *nonceBytes = (const uint8_t *)nonce; + const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; + size_t mode; size_t i; uint8_t b0[16]; + whal_Error err; - if (!args->key || !args->nonce) + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state || !key || !nonce) return WHAL_EINVAL; - if (args->keySz != 16 && args->keySz != 32) - return WHAL_ENOTSUP; + crypto = dev->crypto; + cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + base = crypto->base; - if (args->nonceSz < 7 || args->nonceSz > 13) - return WHAL_EINVAL; + if (keySz != 16 && keySz != 32) + return WHAL_ENOTSUP; - if (args->sz > 0 && (!args->in || !args->out)) + if (nonceSz < 7 || nonceSz > 13) return WHAL_EINVAL; - if (args->aadSz > 0 && !args->aad) + if (aadSz > 0 && !aad) return WHAL_EINVAL; - if (args->tagSz < 4 || args->tagSz > 16 || (args->tagSz & 1) != 0) + if (tagSz < 4 || tagSz > 16 || (tagSz & 1) != 0) return WHAL_EINVAL; - keySizeBit = (args->keySz == 32) ? 1 : 0; + keySizeBit = (keySz == 32) ? 1 : 0; + /* Build B0 */ { - size_t q = 15 - args->nonceSz; - size_t t = args->tagSz; - uint8_t flags = (uint8_t)(((args->aadSz > 0) ? 0x40 : 0) | + size_t q = 15 - nonceSz; + size_t t = tagSz; + uint8_t flags = (uint8_t)(((aadSz > 0) ? 0x40 : 0) | (((t - 2) / 2) << 3) | (q - 1)); b0[0] = flags; - for (i = 0; i < args->nonceSz; i++) - b0[1 + i] = nonce[i]; + for (i = 0; i < nonceSz; i++) + b0[1 + i] = nonceBytes[i]; { - size_t msgLen = args->sz; + size_t msgLen = sz; size_t j; for (j = 0; j < q; j++) { b0[15 - j] = (uint8_t)(msgLen & 0xFF); @@ -741,6 +1397,7 @@ static whal_Error StartOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) } } + /* Init phase */ whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); whal_Reg_Update(base, AES_CR_REG, @@ -758,7 +1415,7 @@ static whal_Error StartOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, AES_GCMPH_INIT)); - WriteKey(base, args->key, args->keySz); + WriteKey(base, key, keySz); WriteIv(base, b0); whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); @@ -767,7 +1424,8 @@ static whal_Error StartOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) if (err) goto cleanup; - if (args->aadSz > 0) { + /* Header phase (AAD) */ + if (aadSz > 0) { whal_Reg_Update(base, AES_CR_REG, AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, @@ -783,12 +1441,12 @@ static whal_Error StartOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) size_t aadOff = 0; size_t j; - hdrBuf[0] = (uint8_t)(args->aadSz >> 8); - hdrBuf[1] = (uint8_t)(args->aadSz); + hdrBuf[0] = (uint8_t)(aadSz >> 8); + hdrBuf[1] = (uint8_t)(aadSz); hdrOff = 2; - while (hdrOff < 16 && aadOff < args->aadSz) { - hdrBuf[hdrOff++] = aad[aadOff++]; + while (hdrOff < 16 && aadOff < aadSz) { + hdrBuf[hdrOff++] = aadBytes[aadOff++]; } WriteBlock(base, hdrBuf); @@ -796,11 +1454,11 @@ static whal_Error StartOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) if (err) goto cleanup; - while (aadOff < args->aadSz) { + while (aadOff < aadSz) { uint8_t block[16] = {0}; - for (j = 0; j < 16 && aadOff < args->aadSz; j++) - block[j] = aad[aadOff++]; + for (j = 0; j < 16 && aadOff < aadSz; j++) + block[j] = aadBytes[aadOff++]; WriteBlock(base, block); err = WaitForCCF(base, cfg->timeout); @@ -810,6 +1468,25 @@ static whal_Error StartOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) } } + /* Transition to payload phase */ + mode = (dir == WHAL_CRYPTO_ENCRYPT) + ? AES_MODE_ENCRYPT : AES_MODE_DECRYPT; + + whal_Reg_Update(base, AES_CR_REG, + AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, + whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | + whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, + AES_GCMPH_PAYLOAD)); + + if (aadSz == 0) + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + + { + whal_Stm32wb_AesCcm_State *st = (whal_Stm32wb_AesCcm_State *)dev->state; + st->aadSz = aadSz; + st->dataSz = 0; + } + return WHAL_SUCCESS; cleanup: @@ -817,50 +1494,52 @@ static whal_Error StartOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) return err; } -static whal_Error Process_AesCcm(whal_Crypto *cryptoDev, void *opArgs) +whal_Error whal_Stm32wb_AesCcm_Process(whal_AesCcm *dev, + const void *in, void *out, size_t sz) { - whal_Crypto_AesCcmArgs *args = (whal_Crypto_AesCcmArgs *)opArgs; - const whal_Stm32wb_Aes_Cfg *cfg = - (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; + whal_Crypto *crypto; + const whal_Stm32wb_Aes_Cfg *cfg; + size_t base; + whal_Stm32wb_AesCcm_State *st; size_t mode; - whal_Error err; size_t i; + whal_Error err; - if (args->sz == 0) - return WHAL_SUCCESS; - - if (!args->in || !args->out) + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) return WHAL_EINVAL; - mode = (args->dir == WHAL_CRYPTO_ENCRYPT) - ? AES_MODE_ENCRYPT : AES_MODE_DECRYPT; + crypto = dev->crypto; + cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + base = crypto->base; + st = (whal_Stm32wb_AesCcm_State *)dev->state; - whal_Reg_Update(base, AES_CR_REG, - AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, - whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, mode) | - whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, - AES_GCMPH_PAYLOAD)); + if (sz == 0) + return WHAL_SUCCESS; - if (args->aadSz == 0) - whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); + if (!in || !out) + return WHAL_EINVAL; - for (i = 0; i < args->sz; i += 16) { - const uint8_t *in = (const uint8_t *)args->in + i; - uint8_t *out = (uint8_t *)args->out + i; - size_t remain = args->sz - i; + mode = whal_GetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, + whal_Reg_Read(base, AES_CR_REG)); + + for (i = 0; i < sz; i += 16) { + const uint8_t *inBlk = (const uint8_t *)in + i; + uint8_t *outBlk = (uint8_t *)out + i; + size_t remain = sz - i; uint8_t block[16] = {0}; size_t j; if (remain >= 16) { - WriteBlock(base, in); + WriteBlock(base, inBlk); } else { if (mode == AES_MODE_DECRYPT) { whal_Reg_Update(base, AES_CR_REG, AES_CR_NPBLB_Msk, - whal_SetBits(AES_CR_NPBLB_Msk, AES_CR_NPBLB_Pos, 16 - remain)); + whal_SetBits(AES_CR_NPBLB_Msk, + AES_CR_NPBLB_Pos, + 16 - remain)); } for (j = 0; j < remain; j++) - block[j] = in[j]; + block[j] = inBlk[j]; WriteBlock(base, block); } @@ -871,34 +1550,42 @@ static whal_Error Process_AesCcm(whal_Crypto *cryptoDev, void *opArgs) } if (remain >= 16) { - ReadBlock(base, out); + ReadBlock(base, outBlk); } else { ReadBlock(base, block); for (j = 0; j < remain; j++) - out[j] = block[j]; + outBlk[j] = block[j]; } } + st->dataSz += sz; + return WHAL_SUCCESS; } -static whal_Error EndOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) +whal_Error whal_Stm32wb_AesCcm_Finalize(whal_AesCcm *dev, + void *tag, size_t tagSz) { - whal_Crypto_AesCcmArgs *args = (whal_Crypto_AesCcmArgs *)opArgs; - const whal_Stm32wb_Aes_Cfg *cfg = - (const whal_Stm32wb_Aes_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; - uint8_t *tag; - whal_Error err; + whal_Crypto *crypto; + const whal_Stm32wb_Aes_Cfg *cfg; + size_t base; + whal_Stm32wb_AesCcm_State *st; uint8_t tagBuf[16]; size_t i; + whal_Error err; - if (!args->tag || args->tagSz < 4 || args->tagSz > 16 || - (args->tagSz & 1) != 0) + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) return WHAL_EINVAL; - tag = (uint8_t *)args->tag; + crypto = dev->crypto; + cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + base = crypto->base; + st = (whal_Stm32wb_AesCcm_State *)dev->state; + if (!tag || tagSz < 4 || tagSz > 16 || (tagSz & 1) != 0) + return WHAL_EINVAL; + + /* Final phase (tag) */ whal_Reg_Update(base, AES_CR_REG, AES_CR_MODE_Msk | AES_CR_GCMPH_Msk, whal_SetBits(AES_CR_MODE_Msk, AES_CR_MODE_Pos, @@ -906,7 +1593,7 @@ static whal_Error EndOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) whal_SetBits(AES_CR_GCMPH_Msk, AES_CR_GCMPH_Pos, AES_GCMPH_FINAL)); - if (args->aadSz == 0 && args->sz == 0) + if (st->aadSz == 0 && st->dataSz == 0) whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); whal_Reg_Write(base, AES_DINR_REG, 0); @@ -915,142 +1602,23 @@ static whal_Error EndOp_AesCcm(whal_Crypto *cryptoDev, void *opArgs) whal_Reg_Write(base, AES_DINR_REG, 0); err = WaitForCCF(base, cfg->timeout); - if (err) - goto cleanup; + if (err) { + whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); + return err; + } ReadBlock(base, tagBuf); - for (i = 0; i < args->tagSz; i++) - tag[i] = tagBuf[i]; + for (i = 0; i < tagSz; i++) + ((uint8_t *)tag)[i] = tagBuf[i]; -cleanup: whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, 0); - - return err; -} -#endif /* WHAL_CFG_CRYPTO_AES_CCM */ - - -whal_Error whal_Stm32wb_Aes_StartOp(whal_Crypto *cryptoDev, size_t opId, - void *opArgs) -{ - if (!cryptoDev || !opArgs) - return WHAL_EINVAL; - - switch (opId) { -#ifdef WHAL_CFG_CRYPTO_AES_ECB - case WHAL_CRYPTO_AES_ECB: - return StartOp_AesEcb(cryptoDev, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CBC - case WHAL_CRYPTO_AES_CBC: - return StartOp_AesCbc(cryptoDev, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CTR - case WHAL_CRYPTO_AES_CTR: - return StartOp_AesCtr(cryptoDev, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_GCM - case WHAL_CRYPTO_AES_GCM: - return StartOp_AesGcm(cryptoDev, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_GMAC - case WHAL_CRYPTO_AES_GMAC: - return StartOp_AesGmac(cryptoDev, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CCM - case WHAL_CRYPTO_AES_CCM: - return StartOp_AesCcm(cryptoDev, opArgs); -#endif - default: - return WHAL_ENOTSUP; - } -} - -whal_Error whal_Stm32wb_Aes_Process(whal_Crypto *cryptoDev, size_t opId, - void *opArgs) -{ - if (!cryptoDev || !opArgs) - return WHAL_EINVAL; - - switch (opId) { -#ifdef WHAL_CFG_CRYPTO_AES_ECB - case WHAL_CRYPTO_AES_ECB: { - whal_Crypto_AesEcbArgs *args = (whal_Crypto_AesEcbArgs *)opArgs; - return Process_BlockCipher(cryptoDev, args->in, args->out, args->sz); - } -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CBC - case WHAL_CRYPTO_AES_CBC: { - whal_Crypto_AesCbcArgs *args = (whal_Crypto_AesCbcArgs *)opArgs; - return Process_BlockCipher(cryptoDev, args->in, args->out, args->sz); - } -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CTR - case WHAL_CRYPTO_AES_CTR: { - whal_Crypto_AesCtrArgs *args = (whal_Crypto_AesCtrArgs *)opArgs; - return Process_BlockCipher(cryptoDev, args->in, args->out, args->sz); - } -#endif -#ifdef WHAL_CFG_CRYPTO_AES_GCM - case WHAL_CRYPTO_AES_GCM: - return Process_AesGcm(cryptoDev, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_GMAC - case WHAL_CRYPTO_AES_GMAC: - return WHAL_SUCCESS; -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CCM - case WHAL_CRYPTO_AES_CCM: - return Process_AesCcm(cryptoDev, opArgs); -#endif - default: - return WHAL_ENOTSUP; - } -} - -whal_Error whal_Stm32wb_Aes_EndOp(whal_Crypto *cryptoDev, size_t opId, - void *opArgs) -{ - if (!cryptoDev || !opArgs) - return WHAL_EINVAL; - - switch (opId) { -#ifdef WHAL_CFG_CRYPTO_AES_ECB - case WHAL_CRYPTO_AES_ECB: - return EndOp_BlockCipher(cryptoDev); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CBC - case WHAL_CRYPTO_AES_CBC: - return EndOp_BlockCipher(cryptoDev); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CTR - case WHAL_CRYPTO_AES_CTR: - return EndOp_BlockCipher(cryptoDev); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_GCM - case WHAL_CRYPTO_AES_GCM: - return EndOp_AesGcm(cryptoDev, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_GMAC - case WHAL_CRYPTO_AES_GMAC: - return EndOp_AesGmac(cryptoDev, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CCM - case WHAL_CRYPTO_AES_CCM: - return EndOp_AesCcm(cryptoDev, opArgs); -#endif - default: - return WHAL_ENOTSUP; - } + return WHAL_SUCCESS; } -#ifndef WHAL_CFG_STM32WB_AES_DIRECT_API_MAPPING -const whal_CryptoDriver whal_Stm32wb_Aes_Driver = { - .Init = whal_Stm32wb_Aes_Init, - .Deinit = whal_Stm32wb_Aes_Deinit, - .StartOp = whal_Stm32wb_Aes_StartOp, - .Process = whal_Stm32wb_Aes_Process, - .EndOp = whal_Stm32wb_Aes_EndOp, +const whal_AesCcmDriver whal_Stm32wb_Aes_CcmDriver = { + .Oneshot = whal_Stm32wb_AesCcm_Oneshot, + .Start = whal_Stm32wb_AesCcm_Start, + .Process = whal_Stm32wb_AesCcm_Process, + .Finalize = whal_Stm32wb_AesCcm_Finalize, }; -#endif /* !WHAL_CFG_STM32WB_AES_DIRECT_API_MAPPING */ diff --git a/src/crypto/stm32wba_aes.c b/src/crypto/stm32wba_aes.c index c82b2f2..cc5d309 100644 --- a/src/crypto/stm32wba_aes.c +++ b/src/crypto/stm32wba_aes.c @@ -1 +1,24 @@ +/* Forward STM32WBA AES direct API mapping flags to STM32WB */ +#ifdef WHAL_CFG_STM32WBA_AES_INIT_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_AES_INIT_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32WBA_AES_ECB_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_AES_ECB_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32WBA_AES_CBC_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_AES_CBC_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32WBA_AES_CTR_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_AES_CTR_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32WBA_AES_GCM_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_AES_GCM_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32WBA_AES_GMAC_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_AES_GMAC_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32WBA_AES_CCM_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_AES_CCM_DIRECT_API_MAPPING +#endif + #include "stm32wb_aes.c" diff --git a/src/crypto/stm32wba_hash.c b/src/crypto/stm32wba_hash.c index f43ee11..c72e7b8 100644 --- a/src/crypto/stm32wba_hash.c +++ b/src/crypto/stm32wba_hash.c @@ -89,76 +89,334 @@ static void ReadDigest(size_t base, uint8_t *digest, size_t digestSz) whal_Reg_Read(base, HASH_HR_BASE_REG + i * 4)); } -static whal_Error Process_Hash(whal_Crypto *cryptoDev, const void *in, - size_t inSz) + + +/* ---- Direct API mapping ---- */ + +#if defined(WHAL_CFG_STM32WBA_HASH_INIT_DIRECT_API_MAPPING) || \ + defined(WHAL_CFG_STM32N6_HASH_INIT_DIRECT_API_MAPPING) +#define whal_Stm32wba_Hash_Init whal_Crypto_Init +#define whal_Stm32wba_Hash_Deinit whal_Crypto_Deinit +#endif + +#if defined(WHAL_CFG_STM32WBA_HASH_SHA1_DIRECT_API_MAPPING) || \ + defined(WHAL_CFG_STM32N6_HASH_SHA1_DIRECT_API_MAPPING) +#define whal_Stm32wba_Sha1_Oneshot whal_Sha1_Oneshot +#define whal_Stm32wba_Sha1_Start whal_Sha1_Start +#define whal_Stm32wba_Sha1_Process whal_Sha1_Process +#define whal_Stm32wba_Sha1_Finalize whal_Sha1_Finalize +#endif + +#if defined(WHAL_CFG_STM32WBA_HASH_SHA224_DIRECT_API_MAPPING) || \ + defined(WHAL_CFG_STM32N6_HASH_SHA224_DIRECT_API_MAPPING) +#define whal_Stm32wba_Sha224_Oneshot whal_Sha224_Oneshot +#define whal_Stm32wba_Sha224_Start whal_Sha224_Start +#define whal_Stm32wba_Sha224_Process whal_Sha224_Process +#define whal_Stm32wba_Sha224_Finalize whal_Sha224_Finalize +#endif + +#if defined(WHAL_CFG_STM32WBA_HASH_SHA256_DIRECT_API_MAPPING) || \ + defined(WHAL_CFG_STM32N6_HASH_SHA256_DIRECT_API_MAPPING) +#define whal_Stm32wba_Sha256_Oneshot whal_Sha256_Oneshot +#define whal_Stm32wba_Sha256_Start whal_Sha256_Start +#define whal_Stm32wba_Sha256_Process whal_Sha256_Process +#define whal_Stm32wba_Sha256_Finalize whal_Sha256_Finalize +#endif + +#if defined(WHAL_CFG_STM32WBA_HASH_HMAC_SHA1_DIRECT_API_MAPPING) || \ + defined(WHAL_CFG_STM32N6_HASH_HMAC_SHA1_DIRECT_API_MAPPING) +#define whal_Stm32wba_HmacSha1_Oneshot whal_HmacSha1_Oneshot +#define whal_Stm32wba_HmacSha1_Start whal_HmacSha1_Start +#define whal_Stm32wba_HmacSha1_Process whal_HmacSha1_Process +#define whal_Stm32wba_HmacSha1_Finalize whal_HmacSha1_Finalize +#endif + +#if defined(WHAL_CFG_STM32WBA_HASH_HMAC_SHA224_DIRECT_API_MAPPING) || \ + defined(WHAL_CFG_STM32N6_HASH_HMAC_SHA224_DIRECT_API_MAPPING) +#define whal_Stm32wba_HmacSha224_Oneshot whal_HmacSha224_Oneshot +#define whal_Stm32wba_HmacSha224_Start whal_HmacSha224_Start +#define whal_Stm32wba_HmacSha224_Process whal_HmacSha224_Process +#define whal_Stm32wba_HmacSha224_Finalize whal_HmacSha224_Finalize +#endif + +#if defined(WHAL_CFG_STM32WBA_HASH_HMAC_SHA256_DIRECT_API_MAPPING) || \ + defined(WHAL_CFG_STM32N6_HASH_HMAC_SHA256_DIRECT_API_MAPPING) +#define whal_Stm32wba_HmacSha256_Oneshot whal_HmacSha256_Oneshot +#define whal_Stm32wba_HmacSha256_Start whal_HmacSha256_Start +#define whal_Stm32wba_HmacSha256_Process whal_HmacSha256_Process +#define whal_Stm32wba_HmacSha256_Finalize whal_HmacSha256_Finalize +#endif + + +/* ---- Init / Deinit ---- */ + +whal_Error whal_Stm32wba_Hash_Init(whal_Crypto *dev) +{ + if (!dev) + return WHAL_EINVAL; + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32wba_Hash_Deinit(whal_Crypto *dev) +{ + if (!dev) + return WHAL_EINVAL; + return WHAL_SUCCESS; +} + +const whal_CryptoDriver whal_Stm32wba_Hash_CryptoDriver = { + .Init = whal_Stm32wba_Hash_Init, + .Deinit = whal_Stm32wba_Hash_Deinit, +}; + + +/* ---- SHA-1 ---- */ + +whal_Error whal_Stm32wba_Sha1_Oneshot(whal_Sha1 *dev, + const void *in, size_t inSz, + void *digest, size_t digestSz) { - if (inSz == 0) - return WHAL_SUCCESS; + const whal_Stm32wba_Hash_Cfg *cfg; + size_t base; + whal_Error err; - if (!in) + if (!dev || !dev->crypto || !dev->crypto->cfg) + return WHAL_EINVAL; + if (!digest || digestSz != 20) return WHAL_EINVAL; - WriteData(cryptoDev->base, (const uint8_t *)in, inSz); + cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; + base = dev->crypto->base; + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + + whal_Reg_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA1) | HASH_CR_INIT_Msk); + + if (inSz > 0) { + if (!in) + return WHAL_EINVAL; + WriteData(base, (const uint8_t *)in, inSz); + } + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + ReadDigest(base, (uint8_t *)digest, digestSz); return WHAL_SUCCESS; } +whal_Error whal_Stm32wba_Sha1_Start(whal_Sha1 *dev) +{ + size_t base; -#if defined(WHAL_CFG_STM32WBA_HASH_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32N6_HASH_DIRECT_API_MAPPING) -#define whal_Stm32wba_Hash_Init whal_Crypto_Init -#define whal_Stm32wba_Hash_Deinit whal_Crypto_Deinit -#define whal_Stm32wba_Hash_StartOp whal_Crypto_StartOp -#define whal_Stm32wba_Hash_Process whal_Crypto_Process -#define whal_Stm32wba_Hash_EndOp whal_Crypto_EndOp -#endif + if (!dev || !dev->crypto || !dev->crypto->cfg) + return WHAL_EINVAL; + + base = dev->crypto->base; + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); -whal_Error whal_Stm32wba_Hash_Init(whal_Crypto *cryptoDev) + whal_Reg_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA1) | HASH_CR_INIT_Msk); + + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32wba_Sha1_Process(whal_Sha1 *dev, + const void *in, size_t inSz) { - if (!cryptoDev || !cryptoDev->cfg) + if (!dev || !dev->crypto) return WHAL_EINVAL; - + if (inSz > 0) { + if (!in) + return WHAL_EINVAL; + WriteData(dev->crypto->base, (const uint8_t *)in, inSz); + } return WHAL_SUCCESS; } -whal_Error whal_Stm32wba_Hash_Deinit(whal_Crypto *cryptoDev) +whal_Error whal_Stm32wba_Sha1_Finalize(whal_Sha1 *dev, + void *digest, size_t digestSz) { - if (!cryptoDev || !cryptoDev->cfg) + const whal_Stm32wba_Hash_Cfg *cfg; + size_t base; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg) + return WHAL_EINVAL; + if (!digest || digestSz != 20) return WHAL_EINVAL; + cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; + base = dev->crypto->base; + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + ReadDigest(base, (uint8_t *)digest, digestSz); return WHAL_SUCCESS; } -/* --- SHA-1 / SHA-224 / SHA-256 --- */ +const whal_Sha1Driver whal_Stm32wba_Hash_Sha1Driver = { + .Oneshot = whal_Stm32wba_Sha1_Oneshot, + .Start = whal_Stm32wba_Sha1_Start, + .Process = whal_Stm32wba_Sha1_Process, + .Finalize = whal_Stm32wba_Sha1_Finalize, +}; + -#if defined(WHAL_CFG_CRYPTO_SHA1) || defined(WHAL_CFG_CRYPTO_SHA224) || \ - defined(WHAL_CFG_CRYPTO_SHA256) -static whal_Error StartOp_Hash(whal_Crypto *cryptoDev, size_t algo) +/* ---- SHA-224 ---- */ + +whal_Error whal_Stm32wba_Sha224_Oneshot(whal_Sha224 *dev, + const void *in, size_t inSz, + void *digest, size_t digestSz) { - size_t base = cryptoDev->base; + const whal_Stm32wba_Hash_Cfg *cfg; + size_t base; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg) + return WHAL_EINVAL; + if (!digest || digestSz != 28) + return WHAL_EINVAL; + + cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; + base = dev->crypto->base; whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); whal_Reg_Update(base, HASH_CR_REG, HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, - AlgoBits(algo) | HASH_CR_INIT_Msk); + AlgoBits(HASH_ALGO_SHA224) | HASH_CR_INIT_Msk); + + if (inSz > 0) { + if (!in) + return WHAL_EINVAL; + WriteData(base, (const uint8_t *)in, inSz); + } + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + ReadDigest(base, (uint8_t *)digest, digestSz); + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32wba_Sha224_Start(whal_Sha224 *dev) +{ + size_t base; + + if (!dev || !dev->crypto || !dev->crypto->cfg) + return WHAL_EINVAL; + + base = dev->crypto->base; + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + + whal_Reg_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA224) | HASH_CR_INIT_Msk); + + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32wba_Sha224_Process(whal_Sha224 *dev, + const void *in, size_t inSz) +{ + if (!dev || !dev->crypto) + return WHAL_EINVAL; + if (inSz > 0) { + if (!in) + return WHAL_EINVAL; + WriteData(dev->crypto->base, (const uint8_t *)in, inSz); + } + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32wba_Sha224_Finalize(whal_Sha224 *dev, + void *digest, size_t digestSz) +{ + const whal_Stm32wba_Hash_Cfg *cfg; + size_t base; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg) + return WHAL_EINVAL; + if (!digest || digestSz != 28) + return WHAL_EINVAL; + + cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; + base = dev->crypto->base; + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + ReadDigest(base, (uint8_t *)digest, digestSz); return WHAL_SUCCESS; } -static whal_Error EndOp_Hash(whal_Crypto *cryptoDev, size_t expectedDigestSz, - void *opArgs) +const whal_Sha224Driver whal_Stm32wba_Hash_Sha224Driver = { + .Oneshot = whal_Stm32wba_Sha224_Oneshot, + .Start = whal_Stm32wba_Sha224_Start, + .Process = whal_Stm32wba_Sha224_Process, + .Finalize = whal_Stm32wba_Sha224_Finalize, +}; + + +/* ---- SHA-256 ---- */ + +whal_Error whal_Stm32wba_Sha256_Oneshot(whal_Sha256 *dev, + const void *in, size_t inSz, + void *digest, size_t digestSz) { - whal_Crypto_HashArgs *args = (whal_Crypto_HashArgs *)opArgs; - const whal_Stm32wba_Hash_Cfg *cfg = - (const whal_Stm32wba_Hash_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; + const whal_Stm32wba_Hash_Cfg *cfg; + size_t base; whal_Error err; - if (!args->digest || args->digestSz != expectedDigestSz) + if (!dev || !dev->crypto || !dev->crypto->cfg) + return WHAL_EINVAL; + if (!digest || digestSz != 32) return WHAL_EINVAL; + cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; + base = dev->crypto->base; + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + + whal_Reg_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA256) | HASH_CR_INIT_Msk); + + if (inSz > 0) { + if (!in) + return WHAL_EINVAL; + WriteData(base, (const uint8_t *)in, inSz); + } + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -166,43 +424,111 @@ static whal_Error EndOp_Hash(whal_Crypto *cryptoDev, size_t expectedDigestSz, if (err) return err; - ReadDigest(base, (uint8_t *)args->digest, args->digestSz); + ReadDigest(base, (uint8_t *)digest, digestSz); + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32wba_Sha256_Start(whal_Sha256 *dev) +{ + size_t base; + + if (!dev || !dev->crypto || !dev->crypto->cfg) + return WHAL_EINVAL; + + base = dev->crypto->base; + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + + whal_Reg_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA256) | HASH_CR_INIT_Msk); return WHAL_SUCCESS; } -#endif /* WHAL_CFG_CRYPTO_SHA1 || SHA224 || SHA256 */ -/* --- HMAC-SHA-1 / HMAC-SHA-224 / HMAC-SHA-256 --- */ +whal_Error whal_Stm32wba_Sha256_Process(whal_Sha256 *dev, + const void *in, size_t inSz) +{ + if (!dev || !dev->crypto) + return WHAL_EINVAL; + if (inSz > 0) { + if (!in) + return WHAL_EINVAL; + WriteData(dev->crypto->base, (const uint8_t *)in, inSz); + } + return WHAL_SUCCESS; +} -#if defined(WHAL_CFG_CRYPTO_HMAC_SHA1) || defined(WHAL_CFG_CRYPTO_HMAC_SHA224) || \ - defined(WHAL_CFG_CRYPTO_HMAC_SHA256) -static whal_Error StartOp_Hmac(whal_Crypto *cryptoDev, size_t algo, - void *opArgs) +whal_Error whal_Stm32wba_Sha256_Finalize(whal_Sha256 *dev, + void *digest, size_t digestSz) { - whal_Crypto_HmacArgs *args = (whal_Crypto_HmacArgs *)opArgs; - const whal_Stm32wba_Hash_Cfg *cfg = - (const whal_Stm32wba_Hash_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; + const whal_Stm32wba_Hash_Cfg *cfg; + size_t base; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg) + return WHAL_EINVAL; + if (!digest || digestSz != 32) + return WHAL_EINVAL; + + cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; + base = dev->crypto->base; + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + ReadDigest(base, (uint8_t *)digest, digestSz); + return WHAL_SUCCESS; +} + +const whal_Sha256Driver whal_Stm32wba_Hash_Sha256Driver = { + .Oneshot = whal_Stm32wba_Sha256_Oneshot, + .Start = whal_Stm32wba_Sha256_Start, + .Process = whal_Stm32wba_Sha256_Process, + .Finalize = whal_Stm32wba_Sha256_Finalize, +}; + + +/* ---- HMAC-SHA-1 ---- */ + +whal_Error whal_Stm32wba_HmacSha1_Oneshot(whal_HmacSha1 *dev, + const void *key, size_t keySz, + const void *in, size_t inSz, + void *digest, size_t digestSz) +{ + const whal_Stm32wba_Hash_Cfg *cfg; + size_t base; size_t lkey; whal_Error err; - if (!args->key) + if (!dev || !dev->crypto || !dev->crypto->cfg) + return WHAL_EINVAL; + + cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; + base = dev->crypto->base; + if (!key || !digest || digestSz != 20) return WHAL_EINVAL; - lkey = (args->keySz > 64) ? 1 : 0; + lkey = (keySz > 64) ? 1 : 0; whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); whal_Reg_Update(base, HASH_CR_REG, HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, - AlgoBits(algo) | + AlgoBits(HASH_ALGO_SHA1) | whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, HASH_MODE_HMAC) | whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | HASH_CR_INIT_Msk); - WriteData(base, (const uint8_t *)args->key, args->keySz); + /* Inner key */ + WriteData(base, (const uint8_t *)key, keySz); whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -211,20 +537,65 @@ static whal_Error StartOp_Hmac(whal_Crypto *cryptoDev, size_t algo, if (err) return err; + /* Message */ + if (inSz > 0) { + if (!in) + return WHAL_EINVAL; + WriteData(base, (const uint8_t *)in, inSz); + } + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + /* Outer key */ + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + WriteData(base, (const uint8_t *)key, keySz); + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + ReadDigest(base, (uint8_t *)digest, digestSz); return WHAL_SUCCESS; } -static whal_Error EndOp_Hmac(whal_Crypto *cryptoDev, size_t expectedDigestSz, - void *opArgs) +whal_Error whal_Stm32wba_HmacSha1_Start(whal_HmacSha1 *dev, + const void *key, size_t keySz) { - whal_Crypto_HmacArgs *args = (whal_Crypto_HmacArgs *)opArgs; - const whal_Stm32wba_Hash_Cfg *cfg = - (const whal_Stm32wba_Hash_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; + const whal_Stm32wba_Hash_Cfg *cfg; + size_t base; + size_t lkey; whal_Error err; - if (!args->key || !args->digest || args->digestSz != expectedDigestSz) + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) return WHAL_EINVAL; + if (!key) + return WHAL_EINVAL; + + cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; + base = dev->crypto->base; + lkey = (keySz > 64) ? 1 : 0; + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + + whal_Reg_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA1) | + whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, + HASH_MODE_HMAC) | + whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | + HASH_CR_INIT_Msk); + + /* Inner key */ + WriteData(base, (const uint8_t *)key, keySz); whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -233,9 +604,48 @@ static whal_Error EndOp_Hmac(whal_Crypto *cryptoDev, size_t expectedDigestSz, if (err) return err; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - WriteData(base, (const uint8_t *)args->key, args->keySz); + /* Store key for outer-key phase in Finalize */ + { + whal_Stm32wba_HmacSha1_State *st = + (whal_Stm32wba_HmacSha1_State *)dev->state; + st->key = key; + st->keySz = keySz; + } + + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32wba_HmacSha1_Process(whal_HmacSha1 *dev, + const void *in, size_t inSz) +{ + if (!dev || !dev->crypto) + return WHAL_EINVAL; + if (inSz > 0) { + if (!in) + return WHAL_EINVAL; + WriteData(dev->crypto->base, (const uint8_t *)in, inSz); + } + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32wba_HmacSha1_Finalize(whal_HmacSha1 *dev, + void *digest, size_t digestSz) +{ + const whal_Stm32wba_Hash_Cfg *cfg; + const whal_Stm32wba_HmacSha1_State *st; + size_t base; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) + return WHAL_EINVAL; + if (!digest || digestSz != 20) + return WHAL_EINVAL; + + cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; + base = dev->crypto->base; + st = (const whal_Stm32wba_HmacSha1_State *)dev->state; + /* Message done */ whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -243,137 +653,388 @@ static whal_Error EndOp_Hmac(whal_Crypto *cryptoDev, size_t expectedDigestSz, if (err) return err; - ReadDigest(base, (uint8_t *)args->digest, args->digestSz); + /* Outer key */ + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + WriteData(base, (const uint8_t *)st->key, st->keySz); + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + ReadDigest(base, (uint8_t *)digest, digestSz); return WHAL_SUCCESS; } -#endif /* WHAL_CFG_CRYPTO_HMAC_SHA1 || HMAC_SHA224 || HMAC_SHA256 */ -/* --- Dispatch --- */ +const whal_HmacSha1Driver whal_Stm32wba_Hash_HmacSha1Driver = { + .Oneshot = whal_Stm32wba_HmacSha1_Oneshot, + .Start = whal_Stm32wba_HmacSha1_Start, + .Process = whal_Stm32wba_HmacSha1_Process, + .Finalize = whal_Stm32wba_HmacSha1_Finalize, +}; + -whal_Error whal_Stm32wba_Hash_StartOp(whal_Crypto *cryptoDev, size_t opId, - void *opArgs) +/* ---- HMAC-SHA-224 ---- */ + +whal_Error whal_Stm32wba_HmacSha224_Oneshot(whal_HmacSha224 *dev, + const void *key, size_t keySz, + const void *in, size_t inSz, + void *digest, size_t digestSz) { - if (!cryptoDev) + const whal_Stm32wba_Hash_Cfg *cfg; + size_t base; + size_t lkey; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg) return WHAL_EINVAL; - switch (opId) { -#ifdef WHAL_CFG_CRYPTO_SHA1 - case WHAL_CRYPTO_SHA1: - return StartOp_Hash(cryptoDev, HASH_ALGO_SHA1); -#endif -#ifdef WHAL_CFG_CRYPTO_SHA224 - case WHAL_CRYPTO_SHA224: - return StartOp_Hash(cryptoDev, HASH_ALGO_SHA224); -#endif -#ifdef WHAL_CFG_CRYPTO_SHA256 - case WHAL_CRYPTO_SHA256: - return StartOp_Hash(cryptoDev, HASH_ALGO_SHA256); -#endif -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA1 - case WHAL_CRYPTO_HMAC_SHA1: - return StartOp_Hmac(cryptoDev, HASH_ALGO_SHA1, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA224 - case WHAL_CRYPTO_HMAC_SHA224: - return StartOp_Hmac(cryptoDev, HASH_ALGO_SHA224, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA256 - case WHAL_CRYPTO_HMAC_SHA256: - return StartOp_Hmac(cryptoDev, HASH_ALGO_SHA256, opArgs); -#endif - default: - return WHAL_ENOTSUP; + cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; + base = dev->crypto->base; + if (!key || !digest || digestSz != 28) + return WHAL_EINVAL; + + lkey = (keySz > 64) ? 1 : 0; + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + + whal_Reg_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA224) | + whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, + HASH_MODE_HMAC) | + whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | + HASH_CR_INIT_Msk); + + /* Inner key */ + WriteData(base, (const uint8_t *)key, keySz); + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + /* Message */ + if (inSz > 0) { + if (!in) + return WHAL_EINVAL; + WriteData(base, (const uint8_t *)in, inSz); } + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + /* Outer key */ + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + WriteData(base, (const uint8_t *)key, keySz); + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + ReadDigest(base, (uint8_t *)digest, digestSz); + return WHAL_SUCCESS; } -whal_Error whal_Stm32wba_Hash_Process(whal_Crypto *cryptoDev, size_t opId, - void *opArgs) +whal_Error whal_Stm32wba_HmacSha224_Start(whal_HmacSha224 *dev, + const void *key, size_t keySz) { - if (!cryptoDev || !opArgs) + const whal_Stm32wba_Hash_Cfg *cfg; + size_t base; + size_t lkey; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) + return WHAL_EINVAL; + if (!key) return WHAL_EINVAL; - switch (opId) { -#ifdef WHAL_CFG_CRYPTO_SHA1 - case WHAL_CRYPTO_SHA1: -#endif -#ifdef WHAL_CFG_CRYPTO_SHA224 - case WHAL_CRYPTO_SHA224: -#endif -#ifdef WHAL_CFG_CRYPTO_SHA256 - case WHAL_CRYPTO_SHA256: -#endif -#if defined(WHAL_CFG_CRYPTO_SHA1) || defined(WHAL_CFG_CRYPTO_SHA224) || \ - defined(WHAL_CFG_CRYPTO_SHA256) + cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; + base = dev->crypto->base; + lkey = (keySz > 64) ? 1 : 0; + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + + whal_Reg_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA224) | + whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, + HASH_MODE_HMAC) | + whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | + HASH_CR_INIT_Msk); + + /* Inner key */ + WriteData(base, (const uint8_t *)key, keySz); + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + /* Store key for outer-key phase in Finalize */ { - whal_Crypto_HashArgs *args = (whal_Crypto_HashArgs *)opArgs; - return Process_Hash(cryptoDev, args->in, args->inSz); + whal_Stm32wba_HmacSha224_State *st = + (whal_Stm32wba_HmacSha224_State *)dev->state; + st->key = key; + st->keySz = keySz; } -#endif -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA1 - case WHAL_CRYPTO_HMAC_SHA1: -#endif -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA224 - case WHAL_CRYPTO_HMAC_SHA224: -#endif -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA256 - case WHAL_CRYPTO_HMAC_SHA256: -#endif -#if defined(WHAL_CFG_CRYPTO_HMAC_SHA1) || defined(WHAL_CFG_CRYPTO_HMAC_SHA224) || \ - defined(WHAL_CFG_CRYPTO_HMAC_SHA256) - { - whal_Crypto_HmacArgs *args = (whal_Crypto_HmacArgs *)opArgs; - return Process_Hash(cryptoDev, args->in, args->inSz); + + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32wba_HmacSha224_Process(whal_HmacSha224 *dev, + const void *in, size_t inSz) +{ + if (!dev || !dev->crypto) + return WHAL_EINVAL; + if (inSz > 0) { + if (!in) + return WHAL_EINVAL; + WriteData(dev->crypto->base, (const uint8_t *)in, inSz); } -#endif - default: - return WHAL_ENOTSUP; + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32wba_HmacSha224_Finalize(whal_HmacSha224 *dev, + void *digest, size_t digestSz) +{ + const whal_Stm32wba_Hash_Cfg *cfg; + const whal_Stm32wba_HmacSha224_State *st; + size_t base; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) + return WHAL_EINVAL; + if (!digest || digestSz != 28) + return WHAL_EINVAL; + + cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; + base = dev->crypto->base; + st = (const whal_Stm32wba_HmacSha224_State *)dev->state; + + /* Message done */ + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + /* Outer key */ + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + WriteData(base, (const uint8_t *)st->key, st->keySz); + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + ReadDigest(base, (uint8_t *)digest, digestSz); + return WHAL_SUCCESS; +} + +const whal_HmacSha224Driver whal_Stm32wba_Hash_HmacSha224Driver = { + .Oneshot = whal_Stm32wba_HmacSha224_Oneshot, + .Start = whal_Stm32wba_HmacSha224_Start, + .Process = whal_Stm32wba_HmacSha224_Process, + .Finalize = whal_Stm32wba_HmacSha224_Finalize, +}; + + +/* ---- HMAC-SHA-256 ---- */ + +whal_Error whal_Stm32wba_HmacSha256_Oneshot(whal_HmacSha256 *dev, + const void *key, size_t keySz, + const void *in, size_t inSz, + void *digest, size_t digestSz) +{ + const whal_Stm32wba_Hash_Cfg *cfg; + size_t base; + size_t lkey; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg) + return WHAL_EINVAL; + + cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; + base = dev->crypto->base; + if (!key || !digest || digestSz != 32) + return WHAL_EINVAL; + + lkey = (keySz > 64) ? 1 : 0; + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + + whal_Reg_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA256) | + whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, + HASH_MODE_HMAC) | + whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | + HASH_CR_INIT_Msk); + + /* Inner key */ + WriteData(base, (const uint8_t *)key, keySz); + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + /* Message */ + if (inSz > 0) { + if (!in) + return WHAL_EINVAL; + WriteData(base, (const uint8_t *)in, inSz); } + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + /* Outer key */ + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + WriteData(base, (const uint8_t *)key, keySz); + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + ReadDigest(base, (uint8_t *)digest, digestSz); + return WHAL_SUCCESS; } -whal_Error whal_Stm32wba_Hash_EndOp(whal_Crypto *cryptoDev, size_t opId, - void *opArgs) +whal_Error whal_Stm32wba_HmacSha256_Start(whal_HmacSha256 *dev, + const void *key, size_t keySz) { - if (!cryptoDev || !opArgs) + const whal_Stm32wba_Hash_Cfg *cfg; + size_t base; + size_t lkey; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) + return WHAL_EINVAL; + if (!key) return WHAL_EINVAL; - switch (opId) { -#ifdef WHAL_CFG_CRYPTO_SHA1 - case WHAL_CRYPTO_SHA1: - return EndOp_Hash(cryptoDev, 20, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_SHA224 - case WHAL_CRYPTO_SHA224: - return EndOp_Hash(cryptoDev, 28, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_SHA256 - case WHAL_CRYPTO_SHA256: - return EndOp_Hash(cryptoDev, 32, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA1 - case WHAL_CRYPTO_HMAC_SHA1: - return EndOp_Hmac(cryptoDev, 20, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA224 - case WHAL_CRYPTO_HMAC_SHA224: - return EndOp_Hmac(cryptoDev, 28, opArgs); -#endif -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA256 - case WHAL_CRYPTO_HMAC_SHA256: - return EndOp_Hmac(cryptoDev, 32, opArgs); -#endif - default: - return WHAL_ENOTSUP; + cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; + base = dev->crypto->base; + lkey = (keySz > 64) ? 1 : 0; + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + + whal_Reg_Update(base, HASH_CR_REG, + HASH_CR_ALGO_Msk | HASH_CR_DATATYPE_Msk | + HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, + AlgoBits(HASH_ALGO_SHA256) | + whal_SetBits(HASH_CR_MODE_Msk, HASH_CR_MODE_Pos, + HASH_MODE_HMAC) | + whal_SetBits(HASH_CR_LKEY_Msk, HASH_CR_LKEY_Pos, lkey) | + HASH_CR_INIT_Msk); + + /* Inner key */ + WriteData(base, (const uint8_t *)key, keySz); + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + /* Store key for outer-key phase in Finalize */ + { + whal_Stm32wba_HmacSha256_State *st = + (whal_Stm32wba_HmacSha256_State *)dev->state; + st->key = key; + st->keySz = keySz; } + + return WHAL_SUCCESS; } -#if !defined(WHAL_CFG_STM32WBA_HASH_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32N6_HASH_DIRECT_API_MAPPING) -const whal_CryptoDriver whal_Stm32wba_Hash_Driver = { - .Init = whal_Stm32wba_Hash_Init, - .Deinit = whal_Stm32wba_Hash_Deinit, - .StartOp = whal_Stm32wba_Hash_StartOp, - .Process = whal_Stm32wba_Hash_Process, - .EndOp = whal_Stm32wba_Hash_EndOp, +whal_Error whal_Stm32wba_HmacSha256_Process(whal_HmacSha256 *dev, + const void *in, size_t inSz) +{ + if (!dev || !dev->crypto) + return WHAL_EINVAL; + if (inSz > 0) { + if (!in) + return WHAL_EINVAL; + WriteData(dev->crypto->base, (const uint8_t *)in, inSz); + } + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32wba_HmacSha256_Finalize(whal_HmacSha256 *dev, + void *digest, size_t digestSz) +{ + const whal_Stm32wba_Hash_Cfg *cfg; + const whal_Stm32wba_HmacSha256_State *st; + size_t base; + whal_Error err; + + if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) + return WHAL_EINVAL; + if (!digest || digestSz != 32) + return WHAL_EINVAL; + + cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; + base = dev->crypto->base; + st = (const whal_Stm32wba_HmacSha256_State *)dev->state; + + /* Message done */ + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + /* Outer key */ + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); + WriteData(base, (const uint8_t *)st->key, st->keySz); + + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, + HASH_STR_DCAL_Msk); + + err = WaitForReady(base, cfg->timeout); + if (err) + return err; + + ReadDigest(base, (uint8_t *)digest, digestSz); + return WHAL_SUCCESS; +} + +const whal_HmacSha256Driver whal_Stm32wba_Hash_HmacSha256Driver = { + .Oneshot = whal_Stm32wba_HmacSha256_Oneshot, + .Start = whal_Stm32wba_HmacSha256_Start, + .Process = whal_Stm32wba_HmacSha256_Process, + .Finalize = whal_Stm32wba_HmacSha256_Finalize, }; -#endif /* !WHAL_CFG_STM32WBA_HASH_DIRECT_API_MAPPING */ diff --git a/tests/crypto/gen_test_vectors.py b/tests/crypto/gen_test_vectors.py new file mode 100644 index 0000000..2fb8dc3 --- /dev/null +++ b/tests/crypto/gen_test_vectors.py @@ -0,0 +1,145 @@ +#!/usr/bin/env python3 +"""Generate streaming-API test vectors for wolfHAL crypto tests. + +Computes expected outputs from fixed inputs using PyCA cryptography. The +purpose of this script is to keep humans (and LLMs) out of the trust loop +for the hex constants in tests/crypto/test_.c — every expected +ciphertext, tag, digest, or MAC committed there should originate here. + +Usage: + python3 tests/crypto/gen_test_vectors.py + +Then paste each printed section into the matching tests/crypto/test_.c. +Inputs (keys, IVs, AAD, plaintext, message) are reused from the existing +KAT tests where possible, with new per-streaming-test buffers added for +non-block-aligned payloads. +""" + +import sys + +try: + from cryptography.hazmat.primitives.ciphers.aead import AESGCM, AESCCM + from cryptography.hazmat.primitives import hashes, hmac as hmac_mod +except ImportError: + sys.exit("install cryptography: pip install cryptography") + + +def emit(name, data): + """Print a `static const uint8_t name[N] = { ... };` block.""" + print(f"static const uint8_t {name}[{len(data)}] = {{") + for i in range(0, len(data), 8): + chunk = data[i:i + 8] + line = " " + ", ".join(f"0x{b:02X}" for b in chunk) + "," + print(line) + print("};") + print() + + +def banner(text): + print(f"\n/* ==== {text} ==== */\n") + + +# Deterministic 100-byte buffer used as the plaintext / message for streaming +# tests. Length 100 is non-aligned for AES (16-byte block), SHA-1/224/256 +# (64-byte block), and gives room for split points anywhere. +LONG_BUF = bytes((i * 7 + 3) & 0xFF for i in range(100)) + +# 50-byte slice used as the AEAD streaming plaintext (3 full AES blocks + 2). +AEAD_PT = LONG_BUF[:50] + +# 20-byte AAD used in the with-AAD AEAD streaming tests. +AEAD_AAD = bytes((i * 11 + 5) & 0xFF for i in range(20)) + + +# ---- AES-GCM streaming ---- +# Reuses gcmKey/gcmIv from tests/crypto/test_aes_gcm.c (NIST GCM TC15). +gcm_key = bytes.fromhex( + "FEFFE9928665731C6D6A8F9467308308" + "FEFFE9928665731C6D6A8F9467308308" +) +gcm_iv = bytes.fromhex("CAFEBABEFACEDBADDECAF888") + +aesgcm = AESGCM(gcm_key) + +# Basic: AAD + payload +ct_full = aesgcm.encrypt(gcm_iv, AEAD_PT, AEAD_AAD) +gcm_ct, gcm_tag = ct_full[:-16], ct_full[-16:] + +# No-AAD: payload only +ct_full = aesgcm.encrypt(gcm_iv, AEAD_PT, None) +gcm_noaad_ct, gcm_noaad_tag = ct_full[:-16], ct_full[-16:] + +# No-payload: AAD only (GMAC-style — but via the GCM API) +ct_full = aesgcm.encrypt(gcm_iv, b"", AEAD_AAD) +gcm_nopt_tag = ct_full # no ciphertext, just the tag + +banner("test_aes_gcm.c — streaming vectors (paste alongside existing gcm* arrays)") +emit("gcmStreamAad", AEAD_AAD) +emit("gcmStreamPt", AEAD_PT) +emit("gcmStreamCt", gcm_ct) +emit("gcmStreamTag", gcm_tag) +emit("gcmStreamNoAadCt", gcm_noaad_ct) +emit("gcmStreamNoAadTag", gcm_noaad_tag) +emit("gcmStreamNoPtTag", gcm_nopt_tag) + + +# ---- AES-CCM streaming ---- +# Reuses ccmKey/ccmNonce from tests/crypto/test_aes_ccm.c. +ccm_key = bytes.fromhex( + "314A202F836F9F257E22D8C11757832A" + "E5131D357A72DF88F3EFF0FFCEE0DA4E" +) +ccm_nonce = bytes.fromhex("A544218DADD3C10583DB49CF39") + +aesccm = AESCCM(ccm_key, tag_length=16) + +ct_full = aesccm.encrypt(ccm_nonce, AEAD_PT, AEAD_AAD) +ccm_ct, ccm_tag = ct_full[:-16], ct_full[-16:] + +ct_full = aesccm.encrypt(ccm_nonce, AEAD_PT, None) +ccm_noaad_ct, ccm_noaad_tag = ct_full[:-16], ct_full[-16:] + +ct_full = aesccm.encrypt(ccm_nonce, b"", AEAD_AAD) +ccm_nopt_tag = ct_full + +banner("test_aes_ccm.c — streaming vectors") +emit("ccmStreamAad", AEAD_AAD) +emit("ccmStreamPt", AEAD_PT) +emit("ccmStreamCt", ccm_ct) +emit("ccmStreamTag", ccm_tag) +emit("ccmStreamNoAadCt", ccm_noaad_ct) +emit("ccmStreamNoAadTag", ccm_noaad_tag) +emit("ccmStreamNoPtTag", ccm_nopt_tag) + + +# ---- SHA streaming (100-byte message) ---- +def sha_digest(algo, data): + h = hashes.Hash(algo) + h.update(data) + return h.finalize() + + +banner("test_sha1.c / test_sha224.c / test_sha256.c — streaming vectors") +emit("streamMsg", LONG_BUF) +emit("sha1StreamDigest", sha_digest(hashes.SHA1(), LONG_BUF)) +emit("sha224StreamDigest", sha_digest(hashes.SHA224(), LONG_BUF)) +emit("sha256StreamDigest", sha_digest(hashes.SHA256(), LONG_BUF)) + + +# ---- HMAC streaming ---- +# Use the same 20-byte key as the existing HMAC KAT (RFC 2202/4231 TC1) so +# the file already has it; only the message and MAC change. +hmac_key = bytes([0x0B] * 20) + + +def hmac_mac(algo, key, data): + h = hmac_mod.HMAC(key, algo) + h.update(data) + return h.finalize() + + +banner("test_hmac_sha1.c / test_hmac_sha224.c / test_hmac_sha256.c — streaming vectors") +emit("hmacStreamMsg", LONG_BUF) +emit("hmacSha1StreamMac", hmac_mac(hashes.SHA1(), hmac_key, LONG_BUF)) +emit("hmacSha224StreamMac", hmac_mac(hashes.SHA224(), hmac_key, LONG_BUF)) +emit("hmacSha256StreamMac", hmac_mac(hashes.SHA256(), hmac_key, LONG_BUF)) diff --git a/tests/crypto/test_aes_cbc.c b/tests/crypto/test_aes_cbc.c new file mode 100644 index 0000000..af6501d --- /dev/null +++ b/tests/crypto/test_aes_cbc.c @@ -0,0 +1,84 @@ +#include +#include +#include "board.h" +#include "test.h" + +static const uint8_t key[32] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, +}; + +static const uint8_t iv[16] = { + 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, + 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, +}; + +static const uint8_t plaintext[32] = { + 0xDE, 0xAD, 0xBE, 0xEF, 0xCA, 0xFE, 0xBA, 0xBE, + 0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, + 0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10, + 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, +}; + +/* NIST SP 800-38A test vectors (AES-256, single block) */ +static const uint8_t nistKey[32] = { + 0x60, 0x3D, 0xEB, 0x10, 0x15, 0xCA, 0x71, 0xBE, + 0x2B, 0x73, 0xAE, 0xF0, 0x85, 0x7D, 0x77, 0x81, + 0x1F, 0x35, 0x2C, 0x07, 0x3B, 0x61, 0x08, 0xD7, + 0x2D, 0x98, 0x10, 0xA3, 0x09, 0x14, 0xDF, 0xF4, +}; + +static const uint8_t nistPt[16] = { + 0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96, + 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A, +}; + +/* NIST SP 800-38A F.2.5 AES-256-CBC expected ciphertext */ +static const uint8_t nistCbcIv[16] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, +}; + +static const uint8_t nistCbcCt[16] = { + 0xF5, 0x8C, 0x4C, 0x04, 0xD6, 0xE5, 0xF1, 0xBA, + 0x77, 0x9E, 0xAB, 0xFB, 0x5F, 0x7B, 0xFB, 0xD6, +}; + +static void Test_AesCbc_Basic(void) +{ + uint8_t ct[32] = {0}; + uint8_t pt[32] = {0}; + + WHAL_ASSERT_EQ(whal_AesCbc_Oneshot(&g_whalAesCbc, WHAL_CRYPTO_ENCRYPT, + key, 32, iv, plaintext, ct, + sizeof(plaintext)), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesCbc_Oneshot(&g_whalAesCbc, WHAL_CRYPTO_DECRYPT, + key, 32, iv, ct, pt, sizeof(ct)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(pt, plaintext, sizeof(plaintext)); +} + +static void Test_AesCbc_KnownAnswer(void) +{ + uint8_t ct[16] = {0}; + + WHAL_ASSERT_EQ(whal_AesCbc_Oneshot(&g_whalAesCbc, WHAL_CRYPTO_ENCRYPT, + nistKey, 32, nistCbcIv, nistPt, ct, + sizeof(nistPt)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(ct, nistCbcCt, sizeof(nistCbcCt)); +} + +void whal_Test_AesCbc(void) +{ + WHAL_TEST_SUITE_START("aes_cbc"); + WHAL_TEST(Test_AesCbc_Basic); + WHAL_TEST(Test_AesCbc_KnownAnswer); + WHAL_TEST_SUITE_END(); +} diff --git a/tests/crypto/test_aes_ccm.c b/tests/crypto/test_aes_ccm.c new file mode 100644 index 0000000..c9cfcfd --- /dev/null +++ b/tests/crypto/test_aes_ccm.c @@ -0,0 +1,271 @@ +#include +#include +#include "board.h" +#include "test.h" + +static const uint8_t key[32] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, +}; + +static const uint8_t nonce[12] = { + 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, + 0xB8, 0xB9, 0xBA, 0xBB, +}; + +static const uint8_t aad[16] = { + 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, + 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, +}; + +static const uint8_t plaintext[32] = { + 0xDE, 0xAD, 0xBE, 0xEF, 0xCA, 0xFE, 0xBA, 0xBE, + 0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, + 0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10, + 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, +}; + +/* NIST CAVP DVPT256.rsp: Alen=32, Plen=24, Nlen=13, Tlen=16, Count=225 */ +static const uint8_t ccmKey[32] = { + 0x31, 0x4A, 0x20, 0x2F, 0x83, 0x6F, 0x9F, 0x25, + 0x7E, 0x22, 0xD8, 0xC1, 0x17, 0x57, 0x83, 0x2A, + 0xE5, 0x13, 0x1D, 0x35, 0x7A, 0x72, 0xDF, 0x88, + 0xF3, 0xEF, 0xF0, 0xFF, 0xCE, 0xE0, 0xDA, 0x4E, +}; + +static const uint8_t ccmNonce[13] = { + 0xA5, 0x44, 0x21, 0x8D, 0xAD, 0xD3, 0xC1, 0x05, + 0x83, 0xDB, 0x49, 0xCF, 0x39, +}; + +static const uint8_t ccmAad[32] = { + 0x3C, 0x0E, 0x28, 0x15, 0xD3, 0x7D, 0x84, 0x4F, + 0x7A, 0xC2, 0x40, 0xBA, 0x9D, 0x6E, 0x3A, 0x0B, + 0x2A, 0x86, 0xF7, 0x06, 0xE8, 0x85, 0x95, 0x9E, + 0x09, 0xA1, 0x00, 0x5E, 0x02, 0x4F, 0x69, 0x07, +}; + +static const uint8_t ccmPt[24] = { + 0xE8, 0xDE, 0x97, 0x0F, 0x6E, 0xE8, 0xE8, 0x0E, + 0xDE, 0x93, 0x35, 0x81, 0xB5, 0xBC, 0xF4, 0xD8, + 0x37, 0xE2, 0xB7, 0x2B, 0xAA, 0x8B, 0x00, 0xC3, +}; + +static const uint8_t ccmCt[24] = { + 0x8D, 0x34, 0xCD, 0xCA, 0x37, 0xCE, 0x77, 0xBE, + 0x68, 0xF6, 0x5B, 0xAF, 0x33, 0x82, 0xE3, 0x1E, + 0xFA, 0x69, 0x3E, 0x63, 0xF9, 0x14, 0xA7, 0x81, +}; + +static const uint8_t ccmTag[16] = { + 0x36, 0x7F, 0x30, 0xF2, 0xEA, 0xAD, 0x8C, 0x06, + 0x3C, 0xA5, 0x07, 0x95, 0xAC, 0xD9, 0x02, 0x03, +}; + +static void Test_AesCcm_Basic(void) +{ + uint8_t ct[32] = {0}; + uint8_t pt[32] = {0}; + uint8_t encTag[16] = {0}; + uint8_t decTag[16] = {0}; + + WHAL_ASSERT_EQ(whal_AesCcm_Oneshot(&g_whalAesCcm, WHAL_CRYPTO_ENCRYPT, + key, 32, + nonce, sizeof(nonce), + aad, sizeof(aad), + plaintext, ct, sizeof(plaintext), + encTag, sizeof(encTag)), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesCcm_Oneshot(&g_whalAesCcm, WHAL_CRYPTO_DECRYPT, + key, 32, + nonce, sizeof(nonce), + aad, sizeof(aad), + ct, pt, sizeof(ct), + decTag, sizeof(decTag)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(pt, plaintext, sizeof(plaintext)); + WHAL_ASSERT_MEM_EQ(decTag, encTag, sizeof(encTag)); +} + +static void Test_AesCcm_KnownAnswer(void) +{ + uint8_t ct[24] = {0}; + uint8_t tag[16] = {0}; + + WHAL_ASSERT_EQ(whal_AesCcm_Oneshot(&g_whalAesCcm, WHAL_CRYPTO_ENCRYPT, + ccmKey, 32, + ccmNonce, sizeof(ccmNonce), + ccmAad, sizeof(ccmAad), + ccmPt, ct, sizeof(ccmPt), + tag, sizeof(tag)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(ct, ccmCt, sizeof(ccmCt)); + WHAL_ASSERT_MEM_EQ(tag, ccmTag, sizeof(ccmTag)); +} + +/* Streaming KAT vectors generated by tests/crypto/gen_test_vectors.py from + * ccmKey + ccmNonce above, AEAD_PT (50-byte deterministic plaintext) and + * AEAD_AAD (20-byte deterministic AAD). Re-run the script if these inputs + * are changed. */ +static const uint8_t ccmStreamAad[20] = { + 0x05, 0x10, 0x1B, 0x26, 0x31, 0x3C, 0x47, 0x52, + 0x5D, 0x68, 0x73, 0x7E, 0x89, 0x94, 0x9F, 0xAA, + 0xB5, 0xC0, 0xCB, 0xD6, +}; + +static const uint8_t ccmStreamPt[50] = { + 0x03, 0x0A, 0x11, 0x18, 0x1F, 0x26, 0x2D, 0x34, + 0x3B, 0x42, 0x49, 0x50, 0x57, 0x5E, 0x65, 0x6C, + 0x73, 0x7A, 0x81, 0x88, 0x8F, 0x96, 0x9D, 0xA4, + 0xAB, 0xB2, 0xB9, 0xC0, 0xC7, 0xCE, 0xD5, 0xDC, + 0xE3, 0xEA, 0xF1, 0xF8, 0xFF, 0x06, 0x0D, 0x14, + 0x1B, 0x22, 0x29, 0x30, 0x37, 0x3E, 0x45, 0x4C, + 0x53, 0x5A, +}; + +static const uint8_t ccmStreamCt[50] = { + 0x66, 0xE0, 0x4B, 0xDD, 0x46, 0x00, 0xB2, 0x84, + 0x8D, 0x27, 0x27, 0x7E, 0xD1, 0x60, 0x72, 0xAA, + 0xBE, 0xF1, 0x08, 0xC0, 0xDC, 0x09, 0x3A, 0xE6, + 0x3D, 0x4B, 0x0A, 0xD3, 0x2B, 0x24, 0xC4, 0xB7, + 0x1C, 0xC6, 0x63, 0x65, 0x15, 0x4C, 0x41, 0x6F, + 0xA4, 0x00, 0x31, 0xB0, 0x42, 0xDE, 0xFF, 0x95, + 0xAD, 0xA0, +}; + +static const uint8_t ccmStreamTag[16] = { + 0xD8, 0xBC, 0x77, 0x42, 0xDA, 0xCB, 0x5E, 0xD7, + 0x45, 0xE7, 0xFD, 0xA5, 0x77, 0xD3, 0xC2, 0xA6, +}; + +static const uint8_t ccmStreamNoAadTag[16] = { + 0xF4, 0xF7, 0xEE, 0x77, 0x41, 0xC8, 0xA0, 0x31, + 0x54, 0x3E, 0xA1, 0x68, 0x5F, 0x0F, 0x7F, 0x89, +}; + +static const uint8_t ccmStreamNoPtTag[16] = { + 0x89, 0x3C, 0x6D, 0x51, 0x9F, 0x6D, 0xD2, 0x59, + 0xF8, 0xE6, 0xF7, 0x9A, 0xB9, 0x20, 0x56, 0x47, +}; + +static void Test_AesCcm_Streaming(void) +{ + uint8_t ct[sizeof(ccmStreamPt)] = {0}; + uint8_t tag[16] = {0}; + const size_t split = 32; + + WHAL_ASSERT_EQ(whal_AesCcm_Start(&g_whalAesCcm, WHAL_CRYPTO_ENCRYPT, + ccmKey, 32, + ccmNonce, sizeof(ccmNonce), + ccmStreamAad, sizeof(ccmStreamAad), + sizeof(tag), sizeof(ccmStreamPt)), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesCcm_Process(&g_whalAesCcm, + ccmStreamPt, ct, split), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesCcm_Process(&g_whalAesCcm, + ccmStreamPt + split, ct + split, + sizeof(ccmStreamPt) - split), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesCcm_Finalize(&g_whalAesCcm, tag, sizeof(tag)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(ct, ccmStreamCt, sizeof(ccmStreamCt)); + WHAL_ASSERT_MEM_EQ(tag, ccmStreamTag, sizeof(ccmStreamTag)); +} + +static void Test_AesCcm_Streaming_NoAad(void) +{ + uint8_t ct[sizeof(ccmStreamPt)] = {0}; + uint8_t tag[16] = {0}; + const size_t split = 32; + + WHAL_ASSERT_EQ(whal_AesCcm_Start(&g_whalAesCcm, WHAL_CRYPTO_ENCRYPT, + ccmKey, 32, + ccmNonce, sizeof(ccmNonce), + NULL, 0, + sizeof(tag), sizeof(ccmStreamPt)), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesCcm_Process(&g_whalAesCcm, + ccmStreamPt, ct, split), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesCcm_Process(&g_whalAesCcm, + ccmStreamPt + split, ct + split, + sizeof(ccmStreamPt) - split), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesCcm_Finalize(&g_whalAesCcm, tag, sizeof(tag)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(ct, ccmStreamCt, sizeof(ccmStreamCt)); + WHAL_ASSERT_MEM_EQ(tag, ccmStreamNoAadTag, sizeof(ccmStreamNoAadTag)); +} + +static void Test_AesCcm_Streaming_NoPayload(void) +{ + uint8_t tag[16] = {0}; + + WHAL_ASSERT_EQ(whal_AesCcm_Start(&g_whalAesCcm, WHAL_CRYPTO_ENCRYPT, + ccmKey, 32, + ccmNonce, sizeof(ccmNonce), + ccmStreamAad, sizeof(ccmStreamAad), + sizeof(tag), 0), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesCcm_Finalize(&g_whalAesCcm, tag, sizeof(tag)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(tag, ccmStreamNoPtTag, sizeof(ccmStreamNoPtTag)); +} + +static void Test_AesCcm_Streaming_ThreeCall(void) +{ + uint8_t ct[sizeof(ccmStreamPt)] = {0}; + uint8_t tag[16] = {0}; + + WHAL_ASSERT_EQ(whal_AesCcm_Start(&g_whalAesCcm, WHAL_CRYPTO_ENCRYPT, + ccmKey, 32, + ccmNonce, sizeof(ccmNonce), + ccmStreamAad, sizeof(ccmStreamAad), + sizeof(tag), sizeof(ccmStreamPt)), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesCcm_Process(&g_whalAesCcm, + ccmStreamPt, ct, 16), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_AesCcm_Process(&g_whalAesCcm, + ccmStreamPt + 16, ct + 16, 16), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_AesCcm_Process(&g_whalAesCcm, + ccmStreamPt + 32, ct + 32, + sizeof(ccmStreamPt) - 32), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesCcm_Finalize(&g_whalAesCcm, tag, sizeof(tag)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(ct, ccmStreamCt, sizeof(ccmStreamCt)); + WHAL_ASSERT_MEM_EQ(tag, ccmStreamTag, sizeof(ccmStreamTag)); +} + +void whal_Test_AesCcm(void) +{ + WHAL_TEST_SUITE_START("aes_ccm"); + WHAL_TEST(Test_AesCcm_Basic); + WHAL_TEST(Test_AesCcm_KnownAnswer); + WHAL_TEST(Test_AesCcm_Streaming); + WHAL_TEST(Test_AesCcm_Streaming_NoAad); + WHAL_TEST(Test_AesCcm_Streaming_NoPayload); + WHAL_TEST(Test_AesCcm_Streaming_ThreeCall); + WHAL_TEST_SUITE_END(); +} diff --git a/tests/crypto/test_aes_ctr.c b/tests/crypto/test_aes_ctr.c new file mode 100644 index 0000000..5b11564 --- /dev/null +++ b/tests/crypto/test_aes_ctr.c @@ -0,0 +1,84 @@ +#include +#include +#include "board.h" +#include "test.h" + +static const uint8_t key[32] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, +}; + +static const uint8_t iv[16] = { + 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, + 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, +}; + +static const uint8_t plaintext[32] = { + 0xDE, 0xAD, 0xBE, 0xEF, 0xCA, 0xFE, 0xBA, 0xBE, + 0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, + 0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10, + 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, +}; + +/* NIST SP 800-38A test vectors (AES-256, single block) */ +static const uint8_t nistKey[32] = { + 0x60, 0x3D, 0xEB, 0x10, 0x15, 0xCA, 0x71, 0xBE, + 0x2B, 0x73, 0xAE, 0xF0, 0x85, 0x7D, 0x77, 0x81, + 0x1F, 0x35, 0x2C, 0x07, 0x3B, 0x61, 0x08, 0xD7, + 0x2D, 0x98, 0x10, 0xA3, 0x09, 0x14, 0xDF, 0xF4, +}; + +static const uint8_t nistPt[16] = { + 0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96, + 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A, +}; + +/* NIST SP 800-38A F.5.5 AES-256-CTR expected ciphertext */ +static const uint8_t nistCtrIv[16] = { + 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, + 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, +}; + +static const uint8_t nistCtrCt[16] = { + 0x60, 0x1E, 0xC3, 0x13, 0x77, 0x57, 0x89, 0xA5, + 0xB7, 0xA7, 0xF5, 0x04, 0xBB, 0xF3, 0xD2, 0x28, +}; + +static void Test_AesCtr_Basic(void) +{ + uint8_t ct[32] = {0}; + uint8_t pt[32] = {0}; + + WHAL_ASSERT_EQ(whal_AesCtr_Oneshot(&g_whalAesCtr, WHAL_CRYPTO_ENCRYPT, + key, 32, iv, plaintext, ct, + sizeof(plaintext)), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesCtr_Oneshot(&g_whalAesCtr, WHAL_CRYPTO_DECRYPT, + key, 32, iv, ct, pt, sizeof(ct)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(pt, plaintext, sizeof(plaintext)); +} + +static void Test_AesCtr_KnownAnswer(void) +{ + uint8_t ct[16] = {0}; + + WHAL_ASSERT_EQ(whal_AesCtr_Oneshot(&g_whalAesCtr, WHAL_CRYPTO_ENCRYPT, + nistKey, 32, nistCtrIv, nistPt, ct, + sizeof(nistPt)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(ct, nistCtrCt, sizeof(nistCtrCt)); +} + +void whal_Test_AesCtr(void) +{ + WHAL_TEST_SUITE_START("aes_ctr"); + WHAL_TEST(Test_AesCtr_Basic); + WHAL_TEST(Test_AesCtr_KnownAnswer); + WHAL_TEST_SUITE_END(); +} diff --git a/tests/crypto/test_aes_ecb.c b/tests/crypto/test_aes_ecb.c new file mode 100644 index 0000000..2896847 --- /dev/null +++ b/tests/crypto/test_aes_ecb.c @@ -0,0 +1,74 @@ +#include +#include +#include "board.h" +#include "test.h" + +static const uint8_t key[32] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, +}; + +static const uint8_t plaintext[32] = { + 0xDE, 0xAD, 0xBE, 0xEF, 0xCA, 0xFE, 0xBA, 0xBE, + 0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, + 0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10, + 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, +}; + +/* NIST SP 800-38A test vectors (AES-256, single block) */ +static const uint8_t nistKey[32] = { + 0x60, 0x3D, 0xEB, 0x10, 0x15, 0xCA, 0x71, 0xBE, + 0x2B, 0x73, 0xAE, 0xF0, 0x85, 0x7D, 0x77, 0x81, + 0x1F, 0x35, 0x2C, 0x07, 0x3B, 0x61, 0x08, 0xD7, + 0x2D, 0x98, 0x10, 0xA3, 0x09, 0x14, 0xDF, 0xF4, +}; + +static const uint8_t nistPt[16] = { + 0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96, + 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A, +}; + +/* NIST SP 800-38A F.1.5 AES-256-ECB expected ciphertext */ +static const uint8_t nistEcbCt[16] = { + 0xF3, 0xEE, 0xD1, 0xBD, 0xB5, 0xD2, 0xA0, 0x3C, + 0x06, 0x4B, 0x5A, 0x7E, 0x3D, 0xB1, 0x81, 0xF8, +}; + +static void Test_AesEcb_Basic(void) +{ + uint8_t ct[32] = {0}; + uint8_t pt[32] = {0}; + + WHAL_ASSERT_EQ(whal_AesEcb_Oneshot(&g_whalAesEcb, WHAL_CRYPTO_ENCRYPT, + key, 32, plaintext, ct, + sizeof(plaintext)), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesEcb_Oneshot(&g_whalAesEcb, WHAL_CRYPTO_DECRYPT, + key, 32, ct, pt, sizeof(ct)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(pt, plaintext, sizeof(plaintext)); +} + +static void Test_AesEcb_KnownAnswer(void) +{ + uint8_t ct[16] = {0}; + + WHAL_ASSERT_EQ(whal_AesEcb_Oneshot(&g_whalAesEcb, WHAL_CRYPTO_ENCRYPT, + nistKey, 32, nistPt, ct, + sizeof(nistPt)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(ct, nistEcbCt, sizeof(nistEcbCt)); +} + +void whal_Test_AesEcb(void) +{ + WHAL_TEST_SUITE_START("aes_ecb"); + WHAL_TEST(Test_AesEcb_Basic); + WHAL_TEST(Test_AesEcb_KnownAnswer); + WHAL_TEST_SUITE_END(); +} diff --git a/tests/crypto/test_aes_gcm.c b/tests/crypto/test_aes_gcm.c new file mode 100644 index 0000000..d7cc6fb --- /dev/null +++ b/tests/crypto/test_aes_gcm.c @@ -0,0 +1,324 @@ +#include +#include +#include "board.h" +#include "test.h" + +static const uint8_t key[32] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, +}; + +static const uint8_t nonce[12] = { + 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, + 0xB8, 0xB9, 0xBA, 0xBB, +}; + +static const uint8_t aad[16] = { + 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, + 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, +}; + +static const uint8_t plaintext[32] = { + 0xDE, 0xAD, 0xBE, 0xEF, 0xCA, 0xFE, 0xBA, 0xBE, + 0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, + 0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10, + 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, +}; + +/* GCM spec Test Case 15: AES-256-GCM, 64-byte payload, no AAD */ +static const uint8_t gcmKey[32] = { + 0xFE, 0xFF, 0xE9, 0x92, 0x86, 0x65, 0x73, 0x1C, + 0x6D, 0x6A, 0x8F, 0x94, 0x67, 0x30, 0x83, 0x08, + 0xFE, 0xFF, 0xE9, 0x92, 0x86, 0x65, 0x73, 0x1C, + 0x6D, 0x6A, 0x8F, 0x94, 0x67, 0x30, 0x83, 0x08, +}; + +static const uint8_t gcmIv[12] = { + 0xCA, 0xFE, 0xBA, 0xBE, 0xFA, 0xCE, 0xDB, 0xAD, + 0xDE, 0xCA, 0xF8, 0x88, +}; + +static const uint8_t gcmPt[64] = { + 0xD9, 0x31, 0x32, 0x25, 0xF8, 0x84, 0x06, 0xE5, + 0xA5, 0x59, 0x09, 0xC5, 0xAF, 0xF5, 0x26, 0x9A, + 0x86, 0xA7, 0xA9, 0x53, 0x15, 0x34, 0xF7, 0xDA, + 0x2E, 0x4C, 0x30, 0x3D, 0x8A, 0x31, 0x8A, 0x72, + 0x1C, 0x3C, 0x0C, 0x95, 0x95, 0x68, 0x09, 0x53, + 0x2F, 0xCF, 0x0E, 0x24, 0x49, 0xA6, 0xB5, 0x25, + 0xB1, 0x6A, 0xED, 0xF5, 0xAA, 0x0D, 0xE6, 0x57, + 0xBA, 0x63, 0x7B, 0x39, 0x1A, 0xAF, 0xD2, 0x55, +}; + +static const uint8_t gcmCt[64] = { + 0x52, 0x2D, 0xC1, 0xF0, 0x99, 0x56, 0x7D, 0x07, + 0xF4, 0x7F, 0x37, 0xA3, 0x2A, 0x84, 0x42, 0x7D, + 0x64, 0x3A, 0x8C, 0xDC, 0xBF, 0xE5, 0xC0, 0xC9, + 0x75, 0x98, 0xA2, 0xBD, 0x25, 0x55, 0xD1, 0xAA, + 0x8C, 0xB0, 0x8E, 0x48, 0x59, 0x0D, 0xBB, 0x3D, + 0xA7, 0xB0, 0x8B, 0x10, 0x56, 0x82, 0x88, 0x38, + 0xC5, 0xF6, 0x1E, 0x63, 0x93, 0xBA, 0x7A, 0x0A, + 0xBC, 0xC9, 0xF6, 0x62, 0x89, 0x80, 0x15, 0xAD, +}; + +static const uint8_t gcmTag[16] = { + 0xB0, 0x94, 0xDA, 0xC5, 0xD9, 0x34, 0x71, 0xBD, + 0xEC, 0x1A, 0x50, 0x22, 0x70, 0xE3, 0xCC, 0x6C, +}; + +/* GCM spec Test Case 16: AES-256-GCM, 60-byte payload, 20-byte AAD. + * Exercises partial last blocks on both AAD and payload. Reuses gcmKey/gcmIv. */ +static const uint8_t gcm16Pt[60] = { + 0xD9, 0x31, 0x32, 0x25, 0xF8, 0x84, 0x06, 0xE5, + 0xA5, 0x59, 0x09, 0xC5, 0xAF, 0xF5, 0x26, 0x9A, + 0x86, 0xA7, 0xA9, 0x53, 0x15, 0x34, 0xF7, 0xDA, + 0x2E, 0x4C, 0x30, 0x3D, 0x8A, 0x31, 0x8A, 0x72, + 0x1C, 0x3C, 0x0C, 0x95, 0x95, 0x68, 0x09, 0x53, + 0x2F, 0xCF, 0x0E, 0x24, 0x49, 0xA6, 0xB5, 0x25, + 0xB1, 0x6A, 0xED, 0xF5, 0xAA, 0x0D, 0xE6, 0x57, + 0xBA, 0x63, 0x7B, 0x39, +}; + +static const uint8_t gcm16Aad[20] = { + 0xFE, 0xED, 0xFA, 0xCE, 0xDE, 0xAD, 0xBE, 0xEF, + 0xFE, 0xED, 0xFA, 0xCE, 0xDE, 0xAD, 0xBE, 0xEF, + 0xAB, 0xAD, 0xDA, 0xD2, +}; + +static const uint8_t gcm16Ct[60] = { + 0x52, 0x2D, 0xC1, 0xF0, 0x99, 0x56, 0x7D, 0x07, + 0xF4, 0x7F, 0x37, 0xA3, 0x2A, 0x84, 0x42, 0x7D, + 0x64, 0x3A, 0x8C, 0xDC, 0xBF, 0xE5, 0xC0, 0xC9, + 0x75, 0x98, 0xA2, 0xBD, 0x25, 0x55, 0xD1, 0xAA, + 0x8C, 0xB0, 0x8E, 0x48, 0x59, 0x0D, 0xBB, 0x3D, + 0xA7, 0xB0, 0x8B, 0x10, 0x56, 0x82, 0x88, 0x38, + 0xC5, 0xF6, 0x1E, 0x63, 0x93, 0xBA, 0x7A, 0x0A, + 0xBC, 0xC9, 0xF6, 0x62, +}; + +static const uint8_t gcm16Tag[16] = { + 0x76, 0xFC, 0x6E, 0xCE, 0x0F, 0x4E, 0x17, 0x68, + 0xCD, 0xDF, 0x88, 0x53, 0xBB, 0x2D, 0x55, 0x1B, +}; + +static void Test_AesGcm_Basic(void) +{ + uint8_t ct[32] = {0}; + uint8_t pt[32] = {0}; + uint8_t encTag[16] = {0}; + uint8_t decTag[16] = {0}; + + WHAL_ASSERT_EQ(whal_AesGcm_Oneshot(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, + key, 32, + nonce, sizeof(nonce), + aad, sizeof(aad), + plaintext, ct, sizeof(plaintext), + encTag, sizeof(encTag)), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesGcm_Oneshot(&g_whalAesGcm, WHAL_CRYPTO_DECRYPT, + key, 32, + nonce, sizeof(nonce), + aad, sizeof(aad), + ct, pt, sizeof(ct), + decTag, sizeof(decTag)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(pt, plaintext, sizeof(plaintext)); + WHAL_ASSERT_MEM_EQ(decTag, encTag, sizeof(encTag)); +} + +static void Test_AesGcm_KnownAnswer(void) +{ + uint8_t ct[64] = {0}; + uint8_t tag[16] = {0}; + + WHAL_ASSERT_EQ(whal_AesGcm_Oneshot(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, + gcmKey, 32, + gcmIv, sizeof(gcmIv), + NULL, 0, + gcmPt, ct, sizeof(gcmPt), + tag, sizeof(tag)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(ct, gcmCt, sizeof(gcmCt)); + WHAL_ASSERT_MEM_EQ(tag, gcmTag, sizeof(gcmTag)); +} + +static void Test_AesGcm_KnownAnswer_PartialBlocks(void) +{ + uint8_t ct[sizeof(gcm16Pt)] = {0}; + uint8_t tag[16] = {0}; + + WHAL_ASSERT_EQ(whal_AesGcm_Oneshot(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, + gcmKey, 32, + gcmIv, sizeof(gcmIv), + gcm16Aad, sizeof(gcm16Aad), + gcm16Pt, ct, sizeof(gcm16Pt), + tag, sizeof(tag)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(ct, gcm16Ct, sizeof(gcm16Ct)); + WHAL_ASSERT_MEM_EQ(tag, gcm16Tag, sizeof(gcm16Tag)); +} + +/* Streaming KAT vectors generated by tests/crypto/gen_test_vectors.py from + * gcmKey + gcmIv above, AEAD_PT (50-byte deterministic plaintext) and + * AEAD_AAD (20-byte deterministic AAD). Re-run the script if these inputs + * are changed. */ +static const uint8_t gcmStreamAad[20] = { + 0x05, 0x10, 0x1B, 0x26, 0x31, 0x3C, 0x47, 0x52, + 0x5D, 0x68, 0x73, 0x7E, 0x89, 0x94, 0x9F, 0xAA, + 0xB5, 0xC0, 0xCB, 0xD6, +}; + +static const uint8_t gcmStreamPt[50] = { + 0x03, 0x0A, 0x11, 0x18, 0x1F, 0x26, 0x2D, 0x34, + 0x3B, 0x42, 0x49, 0x50, 0x57, 0x5E, 0x65, 0x6C, + 0x73, 0x7A, 0x81, 0x88, 0x8F, 0x96, 0x9D, 0xA4, + 0xAB, 0xB2, 0xB9, 0xC0, 0xC7, 0xCE, 0xD5, 0xDC, + 0xE3, 0xEA, 0xF1, 0xF8, 0xFF, 0x06, 0x0D, 0x14, + 0x1B, 0x22, 0x29, 0x30, 0x37, 0x3E, 0x45, 0x4C, + 0x53, 0x5A, +}; + +static const uint8_t gcmStreamCt[50] = { + 0x88, 0x16, 0xE2, 0xCD, 0x7E, 0xF4, 0x56, 0xD6, + 0x6A, 0x64, 0x77, 0x36, 0xD2, 0x2F, 0x01, 0x8B, + 0x91, 0xE7, 0xA4, 0x07, 0x25, 0x47, 0xAA, 0xB7, + 0xF0, 0x66, 0x2B, 0x40, 0x68, 0xAA, 0x8E, 0x04, + 0x73, 0x66, 0x73, 0x25, 0x33, 0x63, 0xBF, 0x7A, + 0x93, 0x5D, 0xAC, 0x04, 0x28, 0x1A, 0x78, 0x51, + 0x27, 0xC6, +}; + +static const uint8_t gcmStreamTag[16] = { + 0xDF, 0xB6, 0x81, 0x09, 0xD6, 0xD1, 0x0A, 0xEE, + 0x2E, 0xA9, 0xBD, 0x9F, 0x9C, 0x4E, 0x63, 0x97, +}; + +static const uint8_t gcmStreamNoAadTag[16] = { + 0x27, 0x99, 0x9F, 0xE0, 0xEB, 0xA9, 0x16, 0x72, + 0x50, 0x6F, 0xD9, 0xD0, 0x8F, 0x4E, 0x3F, 0x9A, +}; + +static const uint8_t gcmStreamNoPtTag[16] = { + 0x84, 0x16, 0xDF, 0xFE, 0x20, 0x34, 0xE6, 0xE6, + 0xD3, 0xB6, 0x6B, 0xE7, 0x99, 0x55, 0xB4, 0x56, +}; + +static void Test_AesGcm_Streaming(void) +{ + uint8_t ct[sizeof(gcmStreamPt)] = {0}; + uint8_t tag[16] = {0}; + const size_t split = 32; + + WHAL_ASSERT_EQ(whal_AesGcm_Start(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, + gcmKey, 32, + gcmIv, sizeof(gcmIv), + gcmStreamAad, sizeof(gcmStreamAad)), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesGcm_Process(&g_whalAesGcm, + gcmStreamPt, ct, split), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesGcm_Process(&g_whalAesGcm, + gcmStreamPt + split, ct + split, + sizeof(gcmStreamPt) - split), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesGcm_Finalize(&g_whalAesGcm, tag, sizeof(tag)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(ct, gcmStreamCt, sizeof(gcmStreamCt)); + WHAL_ASSERT_MEM_EQ(tag, gcmStreamTag, sizeof(gcmStreamTag)); +} + +static void Test_AesGcm_Streaming_NoAad(void) +{ + uint8_t ct[sizeof(gcmStreamPt)] = {0}; + uint8_t tag[16] = {0}; + const size_t split = 32; + + WHAL_ASSERT_EQ(whal_AesGcm_Start(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, + gcmKey, 32, + gcmIv, sizeof(gcmIv), + NULL, 0), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesGcm_Process(&g_whalAesGcm, + gcmStreamPt, ct, split), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesGcm_Process(&g_whalAesGcm, + gcmStreamPt + split, ct + split, + sizeof(gcmStreamPt) - split), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesGcm_Finalize(&g_whalAesGcm, tag, sizeof(tag)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(ct, gcmStreamCt, sizeof(gcmStreamCt)); + WHAL_ASSERT_MEM_EQ(tag, gcmStreamNoAadTag, sizeof(gcmStreamNoAadTag)); +} + +static void Test_AesGcm_Streaming_NoPayload(void) +{ + uint8_t tag[16] = {0}; + + WHAL_ASSERT_EQ(whal_AesGcm_Start(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, + gcmKey, 32, + gcmIv, sizeof(gcmIv), + gcmStreamAad, sizeof(gcmStreamAad)), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesGcm_Finalize(&g_whalAesGcm, tag, sizeof(tag)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(tag, gcmStreamNoPtTag, sizeof(gcmStreamNoPtTag)); +} + +static void Test_AesGcm_Streaming_ThreeCall(void) +{ + uint8_t ct[sizeof(gcmStreamPt)] = {0}; + uint8_t tag[16] = {0}; + + WHAL_ASSERT_EQ(whal_AesGcm_Start(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, + gcmKey, 32, + gcmIv, sizeof(gcmIv), + gcmStreamAad, sizeof(gcmStreamAad)), + WHAL_SUCCESS); + + /* 16 + 16 + 18: two full blocks then one block + 2 partial. */ + WHAL_ASSERT_EQ(whal_AesGcm_Process(&g_whalAesGcm, + gcmStreamPt, ct, 16), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_AesGcm_Process(&g_whalAesGcm, + gcmStreamPt + 16, ct + 16, 16), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_AesGcm_Process(&g_whalAesGcm, + gcmStreamPt + 32, ct + 32, + sizeof(gcmStreamPt) - 32), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesGcm_Finalize(&g_whalAesGcm, tag, sizeof(tag)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(ct, gcmStreamCt, sizeof(gcmStreamCt)); + WHAL_ASSERT_MEM_EQ(tag, gcmStreamTag, sizeof(gcmStreamTag)); +} + +void whal_Test_AesGcm(void) +{ + WHAL_TEST_SUITE_START("aes_gcm"); + WHAL_TEST(Test_AesGcm_Basic); + WHAL_TEST(Test_AesGcm_KnownAnswer); + WHAL_TEST(Test_AesGcm_KnownAnswer_PartialBlocks); + WHAL_TEST(Test_AesGcm_Streaming); + WHAL_TEST(Test_AesGcm_Streaming_NoAad); + WHAL_TEST(Test_AesGcm_Streaming_NoPayload); + WHAL_TEST(Test_AesGcm_Streaming_ThreeCall); + WHAL_TEST_SUITE_END(); +} diff --git a/tests/crypto/test_aes_gmac.c b/tests/crypto/test_aes_gmac.c new file mode 100644 index 0000000..b6437b0 --- /dev/null +++ b/tests/crypto/test_aes_gmac.c @@ -0,0 +1,88 @@ +#include +#include +#include "board.h" +#include "test.h" + +static const uint8_t key[32] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, +}; + +static const uint8_t nonce[12] = { + 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, + 0xB8, 0xB9, 0xBA, 0xBB, +}; + +static const uint8_t aad[16] = { + 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, + 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, +}; + +/* NIST CAVP gcmEncryptExtIV256.rsp: Keylen=256, IVlen=96, PTlen=0, AADlen=128, Taglen=128, Count=0 */ +static const uint8_t gmacKey[32] = { + 0x78, 0xDC, 0x4E, 0x0A, 0xAF, 0x52, 0xD9, 0x35, + 0xC3, 0xC0, 0x1E, 0xEA, 0x57, 0x42, 0x8F, 0x00, + 0xCA, 0x1F, 0xD4, 0x75, 0xF5, 0xDA, 0x86, 0xA4, + 0x9C, 0x8D, 0xD7, 0x3D, 0x68, 0xC8, 0xE2, 0x23, +}; + +static const uint8_t gmacIv[12] = { + 0xD7, 0x9C, 0xF2, 0x2D, 0x50, 0x4C, 0xC7, 0x93, + 0xC3, 0xFB, 0x6C, 0x8A, +}; + +static const uint8_t gmacAad[16] = { + 0xB9, 0x6B, 0xAA, 0x8C, 0x1C, 0x75, 0xA6, 0x71, + 0xBF, 0xB2, 0xD0, 0x8D, 0x06, 0xBE, 0x5F, 0x36, +}; + +static const uint8_t gmacTag[16] = { + 0x3E, 0x5D, 0x48, 0x6A, 0xA2, 0xE3, 0x0B, 0x22, + 0xE0, 0x40, 0xB8, 0x57, 0x23, 0xA0, 0x6E, 0x76, +}; + +static void Test_AesGmac_Basic(void) +{ + uint8_t tag1[16] = {0}; + uint8_t tag2[16] = {0}; + + WHAL_ASSERT_EQ(whal_AesGmac_Oneshot(&g_whalAesGmac, + key, 32, + nonce, sizeof(nonce), + aad, sizeof(aad), + tag1, sizeof(tag1)), + WHAL_SUCCESS); + + WHAL_ASSERT_EQ(whal_AesGmac_Oneshot(&g_whalAesGmac, + key, 32, + nonce, sizeof(nonce), + aad, sizeof(aad), + tag2, sizeof(tag2)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(tag1, tag2, sizeof(tag1)); +} + +static void Test_AesGmac_KnownAnswer(void) +{ + uint8_t tag[16] = {0}; + + WHAL_ASSERT_EQ(whal_AesGmac_Oneshot(&g_whalAesGmac, + gmacKey, 32, + gmacIv, sizeof(gmacIv), + gmacAad, sizeof(gmacAad), + tag, sizeof(tag)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(tag, gmacTag, sizeof(gmacTag)); +} + +void whal_Test_AesGmac(void) +{ + WHAL_TEST_SUITE_START("aes_gmac"); + WHAL_TEST(Test_AesGmac_Basic); + WHAL_TEST(Test_AesGmac_KnownAnswer); + WHAL_TEST_SUITE_END(); +} diff --git a/tests/crypto/test_crypto.c b/tests/crypto/test_crypto.c index 95374bc..23e7343 100644 --- a/tests/crypto/test_crypto.c +++ b/tests/crypto/test_crypto.c @@ -1,738 +1,16 @@ -#include #include #include "board.h" #include "test.h" -static const uint8_t key[32] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, -}; - -static const uint8_t iv[16] = { - 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, - 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, -}; - -static const uint8_t nonce[12] = { - 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, - 0xB8, 0xB9, 0xBA, 0xBB, -}; - -static const uint8_t aad[16] = { - 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, - 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, -}; - -static const uint8_t plaintext[32] = { - 0xDE, 0xAD, 0xBE, 0xEF, 0xCA, 0xFE, 0xBA, 0xBE, - 0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, - 0xFE, 0xDC, 0xBA, 0x98, 0x76, 0x54, 0x32, 0x10, - 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, -}; - -/* NIST SP 800-38A test vectors (AES-256, single block) */ -static const uint8_t nistKey[32] = { - 0x60, 0x3D, 0xEB, 0x10, 0x15, 0xCA, 0x71, 0xBE, - 0x2B, 0x73, 0xAE, 0xF0, 0x85, 0x7D, 0x77, 0x81, - 0x1F, 0x35, 0x2C, 0x07, 0x3B, 0x61, 0x08, 0xD7, - 0x2D, 0x98, 0x10, 0xA3, 0x09, 0x14, 0xDF, 0xF4, -}; - -static const uint8_t nistPt[16] = { - 0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96, - 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A, -}; - -#ifdef WHAL_CFG_CRYPTO_AES_ECB -/* NIST SP 800-38A F.1.5 AES-256-ECB expected ciphertext */ -static const uint8_t nistEcbCt[16] = { - 0xF3, 0xEE, 0xD1, 0xBD, 0xB5, 0xD2, 0xA0, 0x3C, - 0x06, 0x4B, 0x5A, 0x7E, 0x3D, 0xB1, 0x81, 0xF8, -}; - -#endif /* WHAL_CFG_CRYPTO_AES_ECB */ - -#ifdef WHAL_CFG_CRYPTO_AES_CBC -/* NIST SP 800-38A F.2.5 AES-256-CBC expected ciphertext */ -static const uint8_t nistCbcIv[16] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, -}; - -static const uint8_t nistCbcCt[16] = { - 0xF5, 0x8C, 0x4C, 0x04, 0xD6, 0xE5, 0xF1, 0xBA, - 0x77, 0x9E, 0xAB, 0xFB, 0x5F, 0x7B, 0xFB, 0xD6, -}; - -#endif /* WHAL_CFG_CRYPTO_AES_CBC */ - -#ifdef WHAL_CFG_CRYPTO_AES_CTR -/* NIST SP 800-38A F.5.5 AES-256-CTR expected ciphertext */ -static const uint8_t nistCtrIv[16] = { - 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, - 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, -}; - -static const uint8_t nistCtrCt[16] = { - 0x60, 0x1E, 0xC3, 0x13, 0x77, 0x57, 0x89, 0xA5, - 0xB7, 0xA7, 0xF5, 0x04, 0xBB, 0xF3, 0xD2, 0x28, -}; - -#endif /* WHAL_CFG_CRYPTO_AES_CTR */ - -#ifdef WHAL_CFG_CRYPTO_AES_GCM -/* GCM spec Test Case 15: AES-256-GCM, 64-byte payload, no AAD */ -static const uint8_t gcmKey[32] = { - 0xFE, 0xFF, 0xE9, 0x92, 0x86, 0x65, 0x73, 0x1C, - 0x6D, 0x6A, 0x8F, 0x94, 0x67, 0x30, 0x83, 0x08, - 0xFE, 0xFF, 0xE9, 0x92, 0x86, 0x65, 0x73, 0x1C, - 0x6D, 0x6A, 0x8F, 0x94, 0x67, 0x30, 0x83, 0x08, -}; - -static const uint8_t gcmIv[12] = { - 0xCA, 0xFE, 0xBA, 0xBE, 0xFA, 0xCE, 0xDB, 0xAD, - 0xDE, 0xCA, 0xF8, 0x88, -}; - -static const uint8_t gcmPt[64] = { - 0xD9, 0x31, 0x32, 0x25, 0xF8, 0x84, 0x06, 0xE5, - 0xA5, 0x59, 0x09, 0xC5, 0xAF, 0xF5, 0x26, 0x9A, - 0x86, 0xA7, 0xA9, 0x53, 0x15, 0x34, 0xF7, 0xDA, - 0x2E, 0x4C, 0x30, 0x3D, 0x8A, 0x31, 0x8A, 0x72, - 0x1C, 0x3C, 0x0C, 0x95, 0x95, 0x68, 0x09, 0x53, - 0x2F, 0xCF, 0x0E, 0x24, 0x49, 0xA6, 0xB5, 0x25, - 0xB1, 0x6A, 0xED, 0xF5, 0xAA, 0x0D, 0xE6, 0x57, - 0xBA, 0x63, 0x7B, 0x39, 0x1A, 0xAF, 0xD2, 0x55, -}; - -static const uint8_t gcmCt[64] = { - 0x52, 0x2D, 0xC1, 0xF0, 0x99, 0x56, 0x7D, 0x07, - 0xF4, 0x7F, 0x37, 0xA3, 0x2A, 0x84, 0x42, 0x7D, - 0x64, 0x3A, 0x8C, 0xDC, 0xBF, 0xE5, 0xC0, 0xC9, - 0x75, 0x98, 0xA2, 0xBD, 0x25, 0x55, 0xD1, 0xAA, - 0x8C, 0xB0, 0x8E, 0x48, 0x59, 0x0D, 0xBB, 0x3D, - 0xA7, 0xB0, 0x8B, 0x10, 0x56, 0x82, 0x88, 0x38, - 0xC5, 0xF6, 0x1E, 0x63, 0x93, 0xBA, 0x7A, 0x0A, - 0xBC, 0xC9, 0xF6, 0x62, 0x89, 0x80, 0x15, 0xAD, -}; - -static const uint8_t gcmTag[16] = { - 0xB0, 0x94, 0xDA, 0xC5, 0xD9, 0x34, 0x71, 0xBD, - 0xEC, 0x1A, 0x50, 0x22, 0x70, 0xE3, 0xCC, 0x6C, -}; - -/* GCM spec Test Case 16: AES-256-GCM, 60-byte payload, 20-byte AAD. - * Exercises partial last blocks on both AAD and payload. Reuses gcmKey/gcmIv. */ -static const uint8_t gcm16Pt[60] = { - 0xD9, 0x31, 0x32, 0x25, 0xF8, 0x84, 0x06, 0xE5, - 0xA5, 0x59, 0x09, 0xC5, 0xAF, 0xF5, 0x26, 0x9A, - 0x86, 0xA7, 0xA9, 0x53, 0x15, 0x34, 0xF7, 0xDA, - 0x2E, 0x4C, 0x30, 0x3D, 0x8A, 0x31, 0x8A, 0x72, - 0x1C, 0x3C, 0x0C, 0x95, 0x95, 0x68, 0x09, 0x53, - 0x2F, 0xCF, 0x0E, 0x24, 0x49, 0xA6, 0xB5, 0x25, - 0xB1, 0x6A, 0xED, 0xF5, 0xAA, 0x0D, 0xE6, 0x57, - 0xBA, 0x63, 0x7B, 0x39, -}; - -static const uint8_t gcm16Aad[20] = { - 0xFE, 0xED, 0xFA, 0xCE, 0xDE, 0xAD, 0xBE, 0xEF, - 0xFE, 0xED, 0xFA, 0xCE, 0xDE, 0xAD, 0xBE, 0xEF, - 0xAB, 0xAD, 0xDA, 0xD2, -}; - -static const uint8_t gcm16Ct[60] = { - 0x52, 0x2D, 0xC1, 0xF0, 0x99, 0x56, 0x7D, 0x07, - 0xF4, 0x7F, 0x37, 0xA3, 0x2A, 0x84, 0x42, 0x7D, - 0x64, 0x3A, 0x8C, 0xDC, 0xBF, 0xE5, 0xC0, 0xC9, - 0x75, 0x98, 0xA2, 0xBD, 0x25, 0x55, 0xD1, 0xAA, - 0x8C, 0xB0, 0x8E, 0x48, 0x59, 0x0D, 0xBB, 0x3D, - 0xA7, 0xB0, 0x8B, 0x10, 0x56, 0x82, 0x88, 0x38, - 0xC5, 0xF6, 0x1E, 0x63, 0x93, 0xBA, 0x7A, 0x0A, - 0xBC, 0xC9, 0xF6, 0x62, -}; - -static const uint8_t gcm16Tag[16] = { - 0x76, 0xFC, 0x6E, 0xCE, 0x0F, 0x4E, 0x17, 0x68, - 0xCD, 0xDF, 0x88, 0x53, 0xBB, 0x2D, 0x55, 0x1B, -}; - -#endif /* WHAL_CFG_CRYPTO_AES_GCM */ - -#ifdef WHAL_CFG_CRYPTO_AES_GMAC -/* NIST CAVP gcmEncryptExtIV256.rsp: Keylen=256, IVlen=96, PTlen=0, AADlen=128, Taglen=128, Count=0 */ -static const uint8_t gmacKey[32] = { - 0x78, 0xDC, 0x4E, 0x0A, 0xAF, 0x52, 0xD9, 0x35, - 0xC3, 0xC0, 0x1E, 0xEA, 0x57, 0x42, 0x8F, 0x00, - 0xCA, 0x1F, 0xD4, 0x75, 0xF5, 0xDA, 0x86, 0xA4, - 0x9C, 0x8D, 0xD7, 0x3D, 0x68, 0xC8, 0xE2, 0x23, -}; - -static const uint8_t gmacIv[12] = { - 0xD7, 0x9C, 0xF2, 0x2D, 0x50, 0x4C, 0xC7, 0x93, - 0xC3, 0xFB, 0x6C, 0x8A, -}; - -static const uint8_t gmacAad[16] = { - 0xB9, 0x6B, 0xAA, 0x8C, 0x1C, 0x75, 0xA6, 0x71, - 0xBF, 0xB2, 0xD0, 0x8D, 0x06, 0xBE, 0x5F, 0x36, -}; - -static const uint8_t gmacTag[16] = { - 0x3E, 0x5D, 0x48, 0x6A, 0xA2, 0xE3, 0x0B, 0x22, - 0xE0, 0x40, 0xB8, 0x57, 0x23, 0xA0, 0x6E, 0x76, -}; - -#endif /* WHAL_CFG_CRYPTO_AES_GMAC */ - -#ifdef WHAL_CFG_CRYPTO_AES_CCM -/* NIST CAVP DVPT256.rsp: Alen=32, Plen=24, Nlen=13, Tlen=16, Count=225 */ -static const uint8_t ccmKey[32] = { - 0x31, 0x4A, 0x20, 0x2F, 0x83, 0x6F, 0x9F, 0x25, - 0x7E, 0x22, 0xD8, 0xC1, 0x17, 0x57, 0x83, 0x2A, - 0xE5, 0x13, 0x1D, 0x35, 0x7A, 0x72, 0xDF, 0x88, - 0xF3, 0xEF, 0xF0, 0xFF, 0xCE, 0xE0, 0xDA, 0x4E, -}; - -static const uint8_t ccmNonce[13] = { - 0xA5, 0x44, 0x21, 0x8D, 0xAD, 0xD3, 0xC1, 0x05, - 0x83, 0xDB, 0x49, 0xCF, 0x39, -}; - -static const uint8_t ccmAad[32] = { - 0x3C, 0x0E, 0x28, 0x15, 0xD3, 0x7D, 0x84, 0x4F, - 0x7A, 0xC2, 0x40, 0xBA, 0x9D, 0x6E, 0x3A, 0x0B, - 0x2A, 0x86, 0xF7, 0x06, 0xE8, 0x85, 0x95, 0x9E, - 0x09, 0xA1, 0x00, 0x5E, 0x02, 0x4F, 0x69, 0x07, -}; - -static const uint8_t ccmPt[24] = { - 0xE8, 0xDE, 0x97, 0x0F, 0x6E, 0xE8, 0xE8, 0x0E, - 0xDE, 0x93, 0x35, 0x81, 0xB5, 0xBC, 0xF4, 0xD8, - 0x37, 0xE2, 0xB7, 0x2B, 0xAA, 0x8B, 0x00, 0xC3, -}; - -static const uint8_t ccmCt[24] = { - 0x8D, 0x34, 0xCD, 0xCA, 0x37, 0xCE, 0x77, 0xBE, - 0x68, 0xF6, 0x5B, 0xAF, 0x33, 0x82, 0xE3, 0x1E, - 0xFA, 0x69, 0x3E, 0x63, 0xF9, 0x14, 0xA7, 0x81, -}; - -static const uint8_t ccmTag[16] = { - 0x36, 0x7F, 0x30, 0xF2, 0xEA, 0xAD, 0x8C, 0x06, - 0x3C, 0xA5, 0x07, 0x95, 0xAC, 0xD9, 0x02, 0x03, -}; - -#endif /* WHAL_CFG_CRYPTO_AES_CCM */ - -#ifdef WHAL_CFG_CRYPTO_AES_ECB -static void Test_Crypto_AesEcb_Basic(void) -{ - uint8_t ct[32] = {0}; - uint8_t pt[32] = {0}; - - whal_Crypto_AesEcbArgs enc = { - .dir = WHAL_CRYPTO_ENCRYPT, .key = key, .keySz = 32, - .in = plaintext, .out = ct, .sz = sizeof(plaintext), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesEcb(&g_whalCrypto, &enc), - WHAL_SUCCESS); - - whal_Crypto_AesEcbArgs dec = { - .dir = WHAL_CRYPTO_DECRYPT, .key = key, .keySz = 32, - .in = ct, .out = pt, .sz = sizeof(ct), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesEcb(&g_whalCrypto, &dec), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(pt, plaintext, sizeof(plaintext)); -} - -static void Test_Crypto_AesEcb_KnownAnswer(void) -{ - uint8_t ct[16] = {0}; - - whal_Crypto_AesEcbArgs enc = { - .dir = WHAL_CRYPTO_ENCRYPT, .key = nistKey, .keySz = 32, - .in = nistPt, .out = ct, .sz = sizeof(nistPt), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesEcb(&g_whalCrypto, &enc), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(ct, nistEcbCt, sizeof(nistEcbCt)); -} -#endif /* WHAL_CFG_CRYPTO_AES_ECB */ - -#ifdef WHAL_CFG_CRYPTO_AES_CBC -static void Test_Crypto_AesCbc_Basic(void) -{ - uint8_t ct[32] = {0}; - uint8_t pt[32] = {0}; - - whal_Crypto_AesCbcArgs enc = { - .dir = WHAL_CRYPTO_ENCRYPT, .key = key, .keySz = 32, - .iv = iv, .in = plaintext, .out = ct, .sz = sizeof(plaintext), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesCbc(&g_whalCrypto, &enc), - WHAL_SUCCESS); - - whal_Crypto_AesCbcArgs dec = { - .dir = WHAL_CRYPTO_DECRYPT, .key = key, .keySz = 32, - .iv = iv, .in = ct, .out = pt, .sz = sizeof(ct), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesCbc(&g_whalCrypto, &dec), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(pt, plaintext, sizeof(plaintext)); -} - -static void Test_Crypto_AesCbc_KnownAnswer(void) -{ - uint8_t ct[16] = {0}; - - whal_Crypto_AesCbcArgs enc = { - .dir = WHAL_CRYPTO_ENCRYPT, .key = nistKey, .keySz = 32, - .iv = nistCbcIv, .in = nistPt, .out = ct, .sz = sizeof(nistPt), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesCbc(&g_whalCrypto, &enc), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(ct, nistCbcCt, sizeof(nistCbcCt)); -} -#endif /* WHAL_CFG_CRYPTO_AES_CBC */ - -#ifdef WHAL_CFG_CRYPTO_AES_CTR -static void Test_Crypto_AesCtr_Basic(void) -{ - uint8_t ct[32] = {0}; - uint8_t pt[32] = {0}; - - whal_Crypto_AesCtrArgs enc = { - .dir = WHAL_CRYPTO_ENCRYPT, .key = key, .keySz = 32, - .iv = iv, .in = plaintext, .out = ct, .sz = sizeof(plaintext), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesCtr(&g_whalCrypto, &enc), - WHAL_SUCCESS); - - whal_Crypto_AesCtrArgs dec = { - .dir = WHAL_CRYPTO_DECRYPT, .key = key, .keySz = 32, - .iv = iv, .in = ct, .out = pt, .sz = sizeof(ct), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesCtr(&g_whalCrypto, &dec), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(pt, plaintext, sizeof(plaintext)); -} - -static void Test_Crypto_AesCtr_KnownAnswer(void) -{ - uint8_t ct[16] = {0}; - - whal_Crypto_AesCtrArgs enc = { - .dir = WHAL_CRYPTO_ENCRYPT, .key = nistKey, .keySz = 32, - .iv = nistCtrIv, .in = nistPt, .out = ct, .sz = sizeof(nistPt), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesCtr(&g_whalCrypto, &enc), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(ct, nistCtrCt, sizeof(nistCtrCt)); -} -#endif /* WHAL_CFG_CRYPTO_AES_CTR */ - -#ifdef WHAL_CFG_CRYPTO_AES_GCM -static void Test_Crypto_AesGcm_Basic(void) -{ - uint8_t ct[32] = {0}; - uint8_t pt[32] = {0}; - uint8_t encTag[16] = {0}; - uint8_t decTag[16] = {0}; - - whal_Crypto_AesGcmArgs enc = { - .dir = WHAL_CRYPTO_ENCRYPT, .key = key, .keySz = 32, - .iv = nonce, .ivSz = sizeof(nonce), - .in = plaintext, .out = ct, .sz = sizeof(plaintext), - .aad = aad, .aadSz = sizeof(aad), - .tag = encTag, .tagSz = sizeof(encTag), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesGcm(&g_whalCrypto, &enc), - WHAL_SUCCESS); - - whal_Crypto_AesGcmArgs dec = { - .dir = WHAL_CRYPTO_DECRYPT, .key = key, .keySz = 32, - .iv = nonce, .ivSz = sizeof(nonce), - .in = ct, .out = pt, .sz = sizeof(ct), - .aad = aad, .aadSz = sizeof(aad), - .tag = decTag, .tagSz = sizeof(decTag), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesGcm(&g_whalCrypto, &dec), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(pt, plaintext, sizeof(plaintext)); - WHAL_ASSERT_MEM_EQ(decTag, encTag, sizeof(encTag)); -} - -static void Test_Crypto_AesGcm_KnownAnswer(void) -{ - uint8_t ct[64] = {0}; - uint8_t tag[16] = {0}; - - whal_Crypto_AesGcmArgs enc = { - .dir = WHAL_CRYPTO_ENCRYPT, .key = gcmKey, .keySz = 32, - .iv = gcmIv, .ivSz = sizeof(gcmIv), - .in = gcmPt, .out = ct, .sz = sizeof(gcmPt), - .aad = NULL, .aadSz = 0, - .tag = tag, .tagSz = sizeof(tag), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesGcm(&g_whalCrypto, &enc), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(ct, gcmCt, sizeof(gcmCt)); - WHAL_ASSERT_MEM_EQ(tag, gcmTag, sizeof(gcmTag)); -} - -static void Test_Crypto_AesGcm_KnownAnswer_PartialBlocks(void) -{ - uint8_t ct[sizeof(gcm16Pt)] = {0}; - uint8_t tag[16] = {0}; - - whal_Crypto_AesGcmArgs enc = { - .dir = WHAL_CRYPTO_ENCRYPT, .key = gcmKey, .keySz = 32, - .iv = gcmIv, .ivSz = sizeof(gcmIv), - .in = gcm16Pt, .out = ct, .sz = sizeof(gcm16Pt), - .aad = gcm16Aad, .aadSz = sizeof(gcm16Aad), - .tag = tag, .tagSz = sizeof(tag), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesGcm(&g_whalCrypto, &enc), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(ct, gcm16Ct, sizeof(gcm16Ct)); - WHAL_ASSERT_MEM_EQ(tag, gcm16Tag, sizeof(gcm16Tag)); -} -#endif /* WHAL_CFG_CRYPTO_AES_GCM */ - -#ifdef WHAL_CFG_CRYPTO_AES_GMAC -static void Test_Crypto_AesGmac_Basic(void) -{ - uint8_t tag1[16] = {0}; - uint8_t tag2[16] = {0}; - - whal_Crypto_AesGmacArgs args1 = { - .key = key, .keySz = 32, - .iv = nonce, .ivSz = sizeof(nonce), - .aad = aad, .aadSz = sizeof(aad), - .tag = tag1, .tagSz = sizeof(tag1), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesGmac(&g_whalCrypto, &args1), - WHAL_SUCCESS); - - whal_Crypto_AesGmacArgs args2 = { - .key = key, .keySz = 32, - .iv = nonce, .ivSz = sizeof(nonce), - .aad = aad, .aadSz = sizeof(aad), - .tag = tag2, .tagSz = sizeof(tag2), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesGmac(&g_whalCrypto, &args2), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(tag1, tag2, sizeof(tag1)); -} - -static void Test_Crypto_AesGmac_KnownAnswer(void) -{ - uint8_t tag[16] = {0}; - - whal_Crypto_AesGmacArgs args = { - .key = gmacKey, .keySz = 32, - .iv = gmacIv, .ivSz = sizeof(gmacIv), - .aad = gmacAad, .aadSz = sizeof(gmacAad), - .tag = tag, .tagSz = sizeof(tag), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesGmac(&g_whalCrypto, &args), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(tag, gmacTag, sizeof(gmacTag)); -} -#endif /* WHAL_CFG_CRYPTO_AES_GMAC */ - -#ifdef WHAL_CFG_CRYPTO_AES_CCM -static void Test_Crypto_AesCcm_Basic(void) -{ - uint8_t ct[32] = {0}; - uint8_t pt[32] = {0}; - uint8_t encTag[16] = {0}; - uint8_t decTag[16] = {0}; - - whal_Crypto_AesCcmArgs enc = { - .dir = WHAL_CRYPTO_ENCRYPT, .key = key, .keySz = 32, - .nonce = nonce, .nonceSz = sizeof(nonce), - .in = plaintext, .out = ct, .sz = sizeof(plaintext), - .aad = aad, .aadSz = sizeof(aad), - .tag = encTag, .tagSz = sizeof(encTag), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesCcm(&g_whalCrypto, &enc), - WHAL_SUCCESS); - - whal_Crypto_AesCcmArgs dec = { - .dir = WHAL_CRYPTO_DECRYPT, .key = key, .keySz = 32, - .nonce = nonce, .nonceSz = sizeof(nonce), - .in = ct, .out = pt, .sz = sizeof(ct), - .aad = aad, .aadSz = sizeof(aad), - .tag = decTag, .tagSz = sizeof(decTag), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesCcm(&g_whalCrypto, &dec), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(pt, plaintext, sizeof(plaintext)); - WHAL_ASSERT_MEM_EQ(decTag, encTag, sizeof(encTag)); -} - -static void Test_Crypto_AesCcm_KnownAnswer(void) -{ - uint8_t ct[24] = {0}; - uint8_t tag[16] = {0}; - - whal_Crypto_AesCcmArgs enc = { - .dir = WHAL_CRYPTO_ENCRYPT, .key = ccmKey, .keySz = 32, - .nonce = ccmNonce, .nonceSz = sizeof(ccmNonce), - .in = ccmPt, .out = ct, .sz = sizeof(ccmPt), - .aad = ccmAad, .aadSz = sizeof(ccmAad), - .tag = tag, .tagSz = sizeof(tag), - }; - WHAL_ASSERT_EQ(whal_Crypto_AesCcm(&g_whalCrypto, &enc), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(ct, ccmCt, sizeof(ccmCt)); - WHAL_ASSERT_MEM_EQ(tag, ccmTag, sizeof(ccmTag)); -} -#endif /* WHAL_CFG_CRYPTO_AES_CCM */ - -/* --- Hash / HMAC known-answer vectors --- */ - -#if defined(WHAL_CFG_CRYPTO_SHA1) || defined(WHAL_CFG_CRYPTO_SHA224) || \ - defined(WHAL_CFG_CRYPTO_SHA256) -static const uint8_t hashInput[] = { 'a', 'b', 'c' }; -#endif - -#ifdef WHAL_CFG_CRYPTO_SHA1 -/* NIST FIPS 180-4: SHA-1("abc") */ -static const uint8_t sha1Digest[20] = { - 0xA9, 0x99, 0x3E, 0x36, 0x47, 0x06, 0x81, 0x6A, - 0xBA, 0x3E, 0x25, 0x71, 0x78, 0x50, 0xC2, 0x6C, - 0x9C, 0xD0, 0xD8, 0x9D, -}; - -static void Test_Crypto_Sha1_KnownAnswer(void) -{ - uint8_t digest[20] = {0}; - - whal_Crypto_HashArgs args = { - .in = hashInput, .inSz = sizeof(hashInput), - .digest = digest, .digestSz = sizeof(digest), - }; - WHAL_ASSERT_EQ(whal_Crypto_Sha1(&g_whalHash, &args), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(digest, sha1Digest, sizeof(sha1Digest)); -} -#endif /* WHAL_CFG_CRYPTO_SHA1 */ - -#ifdef WHAL_CFG_CRYPTO_SHA224 -/* NIST FIPS 180-4: SHA-224("abc") */ -static const uint8_t sha224Digest[28] = { - 0x23, 0x09, 0x7D, 0x22, 0x34, 0x05, 0xD8, 0x22, - 0x86, 0x42, 0xA4, 0x77, 0xBD, 0xA2, 0x55, 0xB3, - 0x2A, 0xAD, 0xBC, 0xE4, 0xBD, 0xA0, 0xB3, 0xF7, - 0xE3, 0x6C, 0x9D, 0xA7, -}; - -static void Test_Crypto_Sha224_KnownAnswer(void) -{ - uint8_t digest[28] = {0}; - - whal_Crypto_HashArgs args = { - .in = hashInput, .inSz = sizeof(hashInput), - .digest = digest, .digestSz = sizeof(digest), - }; - WHAL_ASSERT_EQ(whal_Crypto_Sha224(&g_whalHash, &args), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(digest, sha224Digest, sizeof(sha224Digest)); -} -#endif /* WHAL_CFG_CRYPTO_SHA224 */ - -#ifdef WHAL_CFG_CRYPTO_SHA256 -/* NIST FIPS 180-4: SHA-256("abc") */ -static const uint8_t sha256Digest[32] = { - 0xBA, 0x78, 0x16, 0xBF, 0x8F, 0x01, 0xCF, 0xEA, - 0x41, 0x41, 0x40, 0xDE, 0x5D, 0xAE, 0x22, 0x23, - 0xB0, 0x03, 0x61, 0xA3, 0x96, 0x17, 0x7A, 0x9C, - 0xB4, 0x10, 0xFF, 0x61, 0xF2, 0x00, 0x15, 0xAD, -}; - -static void Test_Crypto_Sha256_KnownAnswer(void) -{ - uint8_t digest[32] = {0}; - - whal_Crypto_HashArgs args = { - .in = hashInput, .inSz = sizeof(hashInput), - .digest = digest, .digestSz = sizeof(digest), - }; - WHAL_ASSERT_EQ(whal_Crypto_Sha256(&g_whalHash, &args), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(digest, sha256Digest, sizeof(sha256Digest)); -} -#endif /* WHAL_CFG_CRYPTO_SHA256 */ - -#if defined(WHAL_CFG_CRYPTO_HMAC_SHA1) || defined(WHAL_CFG_CRYPTO_HMAC_SHA224) || \ - defined(WHAL_CFG_CRYPTO_HMAC_SHA256) -/* RFC 2202 / RFC 4231 Test Case 1: HMAC with 20-byte 0x0b key, "Hi There" */ -static const uint8_t hmacKey[20] = { - 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, - 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, - 0x0B, 0x0B, 0x0B, 0x0B, -}; - -static const uint8_t hmacInput[] = { - 'H', 'i', ' ', 'T', 'h', 'e', 'r', 'e', -}; -#endif - -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA1 -/* RFC 2202 section 3, Test Case 1 */ -static const uint8_t hmacSha1Digest[20] = { - 0xB6, 0x17, 0x31, 0x86, 0x55, 0x05, 0x72, 0x64, - 0xE2, 0x8B, 0xC0, 0xB6, 0xFB, 0x37, 0x8C, 0x8E, - 0xF1, 0x46, 0xBE, 0x00, -}; - -static void Test_Crypto_HmacSha1_KnownAnswer(void) -{ - uint8_t digest[20] = {0}; - - whal_Crypto_HmacArgs args = { - .key = hmacKey, .keySz = sizeof(hmacKey), - .in = hmacInput, .inSz = sizeof(hmacInput), - .digest = digest, .digestSz = sizeof(digest), - }; - WHAL_ASSERT_EQ(whal_Crypto_HmacSha1(&g_whalHash, &args), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(digest, hmacSha1Digest, sizeof(hmacSha1Digest)); -} -#endif /* WHAL_CFG_CRYPTO_HMAC_SHA1 */ - -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA224 -/* RFC 4231 section 4, Test Case 1 */ -static const uint8_t hmacSha224Digest[28] = { - 0x89, 0x6F, 0xB1, 0x12, 0x8A, 0xBB, 0xDF, 0x19, - 0x68, 0x32, 0x10, 0x7C, 0xD4, 0x9D, 0xF3, 0x3F, - 0x47, 0xB4, 0xB1, 0x16, 0x99, 0x12, 0xBA, 0x4F, - 0x53, 0x68, 0x4B, 0x22, -}; - -static void Test_Crypto_HmacSha224_KnownAnswer(void) -{ - uint8_t digest[28] = {0}; - - whal_Crypto_HmacArgs args = { - .key = hmacKey, .keySz = sizeof(hmacKey), - .in = hmacInput, .inSz = sizeof(hmacInput), - .digest = digest, .digestSz = sizeof(digest), - }; - WHAL_ASSERT_EQ(whal_Crypto_HmacSha224(&g_whalHash, &args), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(digest, hmacSha224Digest, sizeof(hmacSha224Digest)); -} -#endif /* WHAL_CFG_CRYPTO_HMAC_SHA224 */ - -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA256 -/* RFC 4231 section 4, Test Case 1 */ -static const uint8_t hmacSha256Digest[32] = { - 0xB0, 0x34, 0x4C, 0x61, 0xD8, 0xDB, 0x38, 0x53, - 0x5C, 0xA8, 0xAF, 0xCE, 0xAF, 0x0B, 0xF1, 0x2B, - 0x88, 0x1D, 0xC2, 0x00, 0xC9, 0x83, 0x3D, 0xA7, - 0x26, 0xE9, 0x37, 0x6C, 0x2E, 0x32, 0xCF, 0xF7, -}; - -static void Test_Crypto_HmacSha256_KnownAnswer(void) -{ - uint8_t digest[32] = {0}; - - whal_Crypto_HmacArgs args = { - .key = hmacKey, .keySz = sizeof(hmacKey), - .in = hmacInput, .inSz = sizeof(hmacInput), - .digest = digest, .digestSz = sizeof(digest), - }; - WHAL_ASSERT_EQ(whal_Crypto_HmacSha256(&g_whalHash, &args), - WHAL_SUCCESS); - - WHAL_ASSERT_MEM_EQ(digest, hmacSha256Digest, sizeof(hmacSha256Digest)); -} -#endif /* WHAL_CFG_CRYPTO_HMAC_SHA256 */ - static void Test_Crypto_Api(void) { - whal_Crypto_AesEcbArgs args = {0}; - - WHAL_ASSERT_EQ(whal_Crypto_Init(NULL), WHAL_EINVAL); WHAL_ASSERT_EQ(whal_Crypto_Deinit(NULL), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Crypto_StartOp(NULL, 0, &args), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Crypto_Process(NULL, 0, &args), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Crypto_EndOp(NULL, 0, &args), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Crypto_StartOp(&g_whalCrypto, 0, NULL), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Crypto_Process(&g_whalCrypto, 0, NULL), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Crypto_EndOp(&g_whalCrypto, 0, NULL), WHAL_EINVAL); + WHAL_ASSERT_EQ(whal_Crypto_Init(NULL), WHAL_EINVAL); } void whal_Test_Crypto(void) { WHAL_TEST_SUITE_START("crypto"); WHAL_TEST(Test_Crypto_Api); -#ifdef WHAL_CFG_CRYPTO_AES_ECB - WHAL_TEST(Test_Crypto_AesEcb_Basic); - WHAL_TEST(Test_Crypto_AesEcb_KnownAnswer); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CBC - WHAL_TEST(Test_Crypto_AesCbc_Basic); - WHAL_TEST(Test_Crypto_AesCbc_KnownAnswer); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CTR - WHAL_TEST(Test_Crypto_AesCtr_Basic); - WHAL_TEST(Test_Crypto_AesCtr_KnownAnswer); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_GCM - WHAL_TEST(Test_Crypto_AesGcm_Basic); - WHAL_TEST(Test_Crypto_AesGcm_KnownAnswer); - WHAL_TEST(Test_Crypto_AesGcm_KnownAnswer_PartialBlocks); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_GMAC - WHAL_TEST(Test_Crypto_AesGmac_Basic); - WHAL_TEST(Test_Crypto_AesGmac_KnownAnswer); -#endif -#ifdef WHAL_CFG_CRYPTO_AES_CCM - WHAL_TEST(Test_Crypto_AesCcm_Basic); - WHAL_TEST(Test_Crypto_AesCcm_KnownAnswer); -#endif -#ifdef WHAL_CFG_CRYPTO_SHA1 - WHAL_TEST(Test_Crypto_Sha1_KnownAnswer); -#endif -#ifdef WHAL_CFG_CRYPTO_SHA224 - WHAL_TEST(Test_Crypto_Sha224_KnownAnswer); -#endif -#ifdef WHAL_CFG_CRYPTO_SHA256 - WHAL_TEST(Test_Crypto_Sha256_KnownAnswer); -#endif -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA1 - WHAL_TEST(Test_Crypto_HmacSha1_KnownAnswer); -#endif -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA224 - WHAL_TEST(Test_Crypto_HmacSha224_KnownAnswer); -#endif -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA256 - WHAL_TEST(Test_Crypto_HmacSha256_KnownAnswer); -#endif WHAL_TEST_SUITE_END(); } diff --git a/tests/crypto/test_hmac_sha1.c b/tests/crypto/test_hmac_sha1.c new file mode 100644 index 0000000..96656a5 --- /dev/null +++ b/tests/crypto/test_hmac_sha1.c @@ -0,0 +1,89 @@ +#include +#include +#include "board.h" +#include "test.h" + +/* RFC 2202 / RFC 4231 Test Case 1: HMAC with 20-byte 0x0b key, "Hi There" */ +static const uint8_t hmacKey[20] = { + 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, + 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, + 0x0B, 0x0B, 0x0B, 0x0B, +}; + +static const uint8_t hmacInput[] = { + 'H', 'i', ' ', 'T', 'h', 'e', 'r', 'e', +}; + +/* RFC 2202 section 3, Test Case 1 */ +static const uint8_t hmacSha1Digest[20] = { + 0xB6, 0x17, 0x31, 0x86, 0x55, 0x05, 0x72, 0x64, + 0xE2, 0x8B, 0xC0, 0xB6, 0xFB, 0x37, 0x8C, 0x8E, + 0xF1, 0x46, 0xBE, 0x00, +}; + +static void Test_HmacSha1_KnownAnswer(void) +{ + uint8_t digest[20] = {0}; + + WHAL_ASSERT_EQ(whal_HmacSha1_Oneshot(&g_whalHmacSha1, + hmacKey, sizeof(hmacKey), + hmacInput, sizeof(hmacInput), + digest, sizeof(digest)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(digest, hmacSha1Digest, sizeof(hmacSha1Digest)); +} + +/* Streaming KAT: 100-byte message split mid-block, same hmacKey as above. + * Vectors generated by tests/crypto/gen_test_vectors.py. */ +static const uint8_t hmacStreamMsg[100] = { + 0x03, 0x0A, 0x11, 0x18, 0x1F, 0x26, 0x2D, 0x34, + 0x3B, 0x42, 0x49, 0x50, 0x57, 0x5E, 0x65, 0x6C, + 0x73, 0x7A, 0x81, 0x88, 0x8F, 0x96, 0x9D, 0xA4, + 0xAB, 0xB2, 0xB9, 0xC0, 0xC7, 0xCE, 0xD5, 0xDC, + 0xE3, 0xEA, 0xF1, 0xF8, 0xFF, 0x06, 0x0D, 0x14, + 0x1B, 0x22, 0x29, 0x30, 0x37, 0x3E, 0x45, 0x4C, + 0x53, 0x5A, 0x61, 0x68, 0x6F, 0x76, 0x7D, 0x84, + 0x8B, 0x92, 0x99, 0xA0, 0xA7, 0xAE, 0xB5, 0xBC, + 0xC3, 0xCA, 0xD1, 0xD8, 0xDF, 0xE6, 0xED, 0xF4, + 0xFB, 0x02, 0x09, 0x10, 0x17, 0x1E, 0x25, 0x2C, + 0x33, 0x3A, 0x41, 0x48, 0x4F, 0x56, 0x5D, 0x64, + 0x6B, 0x72, 0x79, 0x80, 0x87, 0x8E, 0x95, 0x9C, + 0xA3, 0xAA, 0xB1, 0xB8, +}; + +static const uint8_t hmacSha1StreamMac[20] = { + 0xCE, 0xB9, 0x83, 0xD3, 0xE8, 0xAC, 0x5C, 0x88, + 0x99, 0xBF, 0xE9, 0xB0, 0x2F, 0x43, 0xBF, 0xB5, + 0xF9, 0x45, 0xFE, 0x44, +}; + +static void Test_HmacSha1_Streaming(void) +{ + uint8_t digest[20] = {0}; + const size_t split = 50; + + WHAL_ASSERT_EQ(whal_HmacSha1_Start(&g_whalHmacSha1, + hmacKey, sizeof(hmacKey)), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_HmacSha1_Process(&g_whalHmacSha1, + hmacStreamMsg, split), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_HmacSha1_Process(&g_whalHmacSha1, + hmacStreamMsg + split, + sizeof(hmacStreamMsg) - split), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_HmacSha1_Finalize(&g_whalHmacSha1, + digest, sizeof(digest)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(digest, hmacSha1StreamMac, sizeof(hmacSha1StreamMac)); +} + +void whal_Test_HmacSha1(void) +{ + WHAL_TEST_SUITE_START("hmac_sha1"); + WHAL_TEST(Test_HmacSha1_KnownAnswer); + WHAL_TEST(Test_HmacSha1_Streaming); + WHAL_TEST_SUITE_END(); +} diff --git a/tests/crypto/test_hmac_sha224.c b/tests/crypto/test_hmac_sha224.c new file mode 100644 index 0000000..02ba8fb --- /dev/null +++ b/tests/crypto/test_hmac_sha224.c @@ -0,0 +1,91 @@ +#include +#include +#include "board.h" +#include "test.h" + +/* RFC 2202 / RFC 4231 Test Case 1: HMAC with 20-byte 0x0b key, "Hi There" */ +static const uint8_t hmacKey[20] = { + 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, + 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, + 0x0B, 0x0B, 0x0B, 0x0B, +}; + +static const uint8_t hmacInput[] = { + 'H', 'i', ' ', 'T', 'h', 'e', 'r', 'e', +}; + +/* RFC 4231 section 4, Test Case 1 */ +static const uint8_t hmacSha224Digest[28] = { + 0x89, 0x6F, 0xB1, 0x12, 0x8A, 0xBB, 0xDF, 0x19, + 0x68, 0x32, 0x10, 0x7C, 0xD4, 0x9D, 0xF3, 0x3F, + 0x47, 0xB4, 0xB1, 0x16, 0x99, 0x12, 0xBA, 0x4F, + 0x53, 0x68, 0x4B, 0x22, +}; + +static void Test_HmacSha224_KnownAnswer(void) +{ + uint8_t digest[28] = {0}; + + WHAL_ASSERT_EQ(whal_HmacSha224_Oneshot(&g_whalHmacSha224, + hmacKey, sizeof(hmacKey), + hmacInput, sizeof(hmacInput), + digest, sizeof(digest)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(digest, hmacSha224Digest, sizeof(hmacSha224Digest)); +} + +/* Streaming KAT: 100-byte message split mid-block, same hmacKey as above. + * Vectors generated by tests/crypto/gen_test_vectors.py. */ +static const uint8_t hmacStreamMsg[100] = { + 0x03, 0x0A, 0x11, 0x18, 0x1F, 0x26, 0x2D, 0x34, + 0x3B, 0x42, 0x49, 0x50, 0x57, 0x5E, 0x65, 0x6C, + 0x73, 0x7A, 0x81, 0x88, 0x8F, 0x96, 0x9D, 0xA4, + 0xAB, 0xB2, 0xB9, 0xC0, 0xC7, 0xCE, 0xD5, 0xDC, + 0xE3, 0xEA, 0xF1, 0xF8, 0xFF, 0x06, 0x0D, 0x14, + 0x1B, 0x22, 0x29, 0x30, 0x37, 0x3E, 0x45, 0x4C, + 0x53, 0x5A, 0x61, 0x68, 0x6F, 0x76, 0x7D, 0x84, + 0x8B, 0x92, 0x99, 0xA0, 0xA7, 0xAE, 0xB5, 0xBC, + 0xC3, 0xCA, 0xD1, 0xD8, 0xDF, 0xE6, 0xED, 0xF4, + 0xFB, 0x02, 0x09, 0x10, 0x17, 0x1E, 0x25, 0x2C, + 0x33, 0x3A, 0x41, 0x48, 0x4F, 0x56, 0x5D, 0x64, + 0x6B, 0x72, 0x79, 0x80, 0x87, 0x8E, 0x95, 0x9C, + 0xA3, 0xAA, 0xB1, 0xB8, +}; + +static const uint8_t hmacSha224StreamMac[28] = { + 0x15, 0xED, 0x14, 0xD1, 0x5C, 0x32, 0x35, 0x44, + 0x0A, 0x42, 0x10, 0x73, 0x17, 0x2B, 0x42, 0x93, + 0xD8, 0xFF, 0x04, 0x4F, 0x5F, 0x08, 0x33, 0x14, + 0xB0, 0x34, 0x5A, 0x95, +}; + +static void Test_HmacSha224_Streaming(void) +{ + uint8_t digest[28] = {0}; + const size_t split = 50; + + WHAL_ASSERT_EQ(whal_HmacSha224_Start(&g_whalHmacSha224, + hmacKey, sizeof(hmacKey)), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_HmacSha224_Process(&g_whalHmacSha224, + hmacStreamMsg, split), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_HmacSha224_Process(&g_whalHmacSha224, + hmacStreamMsg + split, + sizeof(hmacStreamMsg) - split), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_HmacSha224_Finalize(&g_whalHmacSha224, + digest, sizeof(digest)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(digest, hmacSha224StreamMac, sizeof(hmacSha224StreamMac)); +} + +void whal_Test_HmacSha224(void) +{ + WHAL_TEST_SUITE_START("hmac_sha224"); + WHAL_TEST(Test_HmacSha224_KnownAnswer); + WHAL_TEST(Test_HmacSha224_Streaming); + WHAL_TEST_SUITE_END(); +} diff --git a/tests/crypto/test_hmac_sha256.c b/tests/crypto/test_hmac_sha256.c new file mode 100644 index 0000000..ebd09ad --- /dev/null +++ b/tests/crypto/test_hmac_sha256.c @@ -0,0 +1,91 @@ +#include +#include +#include "board.h" +#include "test.h" + +/* RFC 2202 / RFC 4231 Test Case 1: HMAC with 20-byte 0x0b key, "Hi There" */ +static const uint8_t hmacKey[20] = { + 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, + 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B, + 0x0B, 0x0B, 0x0B, 0x0B, +}; + +static const uint8_t hmacInput[] = { + 'H', 'i', ' ', 'T', 'h', 'e', 'r', 'e', +}; + +/* RFC 4231 section 4, Test Case 1 */ +static const uint8_t hmacSha256Digest[32] = { + 0xB0, 0x34, 0x4C, 0x61, 0xD8, 0xDB, 0x38, 0x53, + 0x5C, 0xA8, 0xAF, 0xCE, 0xAF, 0x0B, 0xF1, 0x2B, + 0x88, 0x1D, 0xC2, 0x00, 0xC9, 0x83, 0x3D, 0xA7, + 0x26, 0xE9, 0x37, 0x6C, 0x2E, 0x32, 0xCF, 0xF7, +}; + +static void Test_HmacSha256_KnownAnswer(void) +{ + uint8_t digest[32] = {0}; + + WHAL_ASSERT_EQ(whal_HmacSha256_Oneshot(&g_whalHmacSha256, + hmacKey, sizeof(hmacKey), + hmacInput, sizeof(hmacInput), + digest, sizeof(digest)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(digest, hmacSha256Digest, sizeof(hmacSha256Digest)); +} + +/* Streaming KAT: 100-byte message split mid-block, same hmacKey as above. + * Vectors generated by tests/crypto/gen_test_vectors.py. */ +static const uint8_t hmacStreamMsg[100] = { + 0x03, 0x0A, 0x11, 0x18, 0x1F, 0x26, 0x2D, 0x34, + 0x3B, 0x42, 0x49, 0x50, 0x57, 0x5E, 0x65, 0x6C, + 0x73, 0x7A, 0x81, 0x88, 0x8F, 0x96, 0x9D, 0xA4, + 0xAB, 0xB2, 0xB9, 0xC0, 0xC7, 0xCE, 0xD5, 0xDC, + 0xE3, 0xEA, 0xF1, 0xF8, 0xFF, 0x06, 0x0D, 0x14, + 0x1B, 0x22, 0x29, 0x30, 0x37, 0x3E, 0x45, 0x4C, + 0x53, 0x5A, 0x61, 0x68, 0x6F, 0x76, 0x7D, 0x84, + 0x8B, 0x92, 0x99, 0xA0, 0xA7, 0xAE, 0xB5, 0xBC, + 0xC3, 0xCA, 0xD1, 0xD8, 0xDF, 0xE6, 0xED, 0xF4, + 0xFB, 0x02, 0x09, 0x10, 0x17, 0x1E, 0x25, 0x2C, + 0x33, 0x3A, 0x41, 0x48, 0x4F, 0x56, 0x5D, 0x64, + 0x6B, 0x72, 0x79, 0x80, 0x87, 0x8E, 0x95, 0x9C, + 0xA3, 0xAA, 0xB1, 0xB8, +}; + +static const uint8_t hmacSha256StreamMac[32] = { + 0x42, 0x2F, 0x96, 0x3C, 0x39, 0x2F, 0xDA, 0x07, + 0x48, 0x35, 0x81, 0xE3, 0x04, 0x23, 0xCA, 0x70, + 0x65, 0xC8, 0x58, 0x84, 0x24, 0xED, 0x9A, 0x61, + 0x37, 0x9B, 0x5E, 0xC3, 0x4D, 0x02, 0xF1, 0xBD, +}; + +static void Test_HmacSha256_Streaming(void) +{ + uint8_t digest[32] = {0}; + const size_t split = 50; + + WHAL_ASSERT_EQ(whal_HmacSha256_Start(&g_whalHmacSha256, + hmacKey, sizeof(hmacKey)), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_HmacSha256_Process(&g_whalHmacSha256, + hmacStreamMsg, split), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_HmacSha256_Process(&g_whalHmacSha256, + hmacStreamMsg + split, + sizeof(hmacStreamMsg) - split), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_HmacSha256_Finalize(&g_whalHmacSha256, + digest, sizeof(digest)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(digest, hmacSha256StreamMac, sizeof(hmacSha256StreamMac)); +} + +void whal_Test_HmacSha256(void) +{ + WHAL_TEST_SUITE_START("hmac_sha256"); + WHAL_TEST(Test_HmacSha256_KnownAnswer); + WHAL_TEST(Test_HmacSha256_Streaming); + WHAL_TEST_SUITE_END(); +} diff --git a/tests/crypto/test_sha1.c b/tests/crypto/test_sha1.c new file mode 100644 index 0000000..5e90c3c --- /dev/null +++ b/tests/crypto/test_sha1.c @@ -0,0 +1,75 @@ +#include +#include +#include "board.h" +#include "test.h" + +static const uint8_t hashInput[] = { 'a', 'b', 'c' }; + +/* NIST FIPS 180-4: SHA-1("abc") */ +static const uint8_t sha1Digest[20] = { + 0xA9, 0x99, 0x3E, 0x36, 0x47, 0x06, 0x81, 0x6A, + 0xBA, 0x3E, 0x25, 0x71, 0x78, 0x50, 0xC2, 0x6C, + 0x9C, 0xD0, 0xD8, 0x9D, +}; + +static void Test_Sha1_KnownAnswer(void) +{ + uint8_t digest[20] = {0}; + + WHAL_ASSERT_EQ(whal_Sha1_Oneshot(&g_whalSha1, + hashInput, sizeof(hashInput), + digest, sizeof(digest)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(digest, sha1Digest, sizeof(sha1Digest)); +} + +/* Streaming KAT: 100-byte deterministic message, split mid-block. + * Vectors generated by tests/crypto/gen_test_vectors.py. */ +static const uint8_t streamMsg[100] = { + 0x03, 0x0A, 0x11, 0x18, 0x1F, 0x26, 0x2D, 0x34, + 0x3B, 0x42, 0x49, 0x50, 0x57, 0x5E, 0x65, 0x6C, + 0x73, 0x7A, 0x81, 0x88, 0x8F, 0x96, 0x9D, 0xA4, + 0xAB, 0xB2, 0xB9, 0xC0, 0xC7, 0xCE, 0xD5, 0xDC, + 0xE3, 0xEA, 0xF1, 0xF8, 0xFF, 0x06, 0x0D, 0x14, + 0x1B, 0x22, 0x29, 0x30, 0x37, 0x3E, 0x45, 0x4C, + 0x53, 0x5A, 0x61, 0x68, 0x6F, 0x76, 0x7D, 0x84, + 0x8B, 0x92, 0x99, 0xA0, 0xA7, 0xAE, 0xB5, 0xBC, + 0xC3, 0xCA, 0xD1, 0xD8, 0xDF, 0xE6, 0xED, 0xF4, + 0xFB, 0x02, 0x09, 0x10, 0x17, 0x1E, 0x25, 0x2C, + 0x33, 0x3A, 0x41, 0x48, 0x4F, 0x56, 0x5D, 0x64, + 0x6B, 0x72, 0x79, 0x80, 0x87, 0x8E, 0x95, 0x9C, + 0xA3, 0xAA, 0xB1, 0xB8, +}; + +static const uint8_t sha1StreamDigest[20] = { + 0xBE, 0x7F, 0xD4, 0x15, 0x86, 0xF4, 0x15, 0x66, + 0x5D, 0x26, 0x1A, 0xF1, 0x96, 0x13, 0xA4, 0xBA, + 0x6F, 0x43, 0x46, 0xBB, +}; + +static void Test_Sha1_Streaming(void) +{ + uint8_t digest[20] = {0}; + const size_t split = 50; + + WHAL_ASSERT_EQ(whal_Sha1_Start(&g_whalSha1), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Sha1_Process(&g_whalSha1, streamMsg, split), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Sha1_Process(&g_whalSha1, + streamMsg + split, + sizeof(streamMsg) - split), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Sha1_Finalize(&g_whalSha1, digest, sizeof(digest)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(digest, sha1StreamDigest, sizeof(sha1StreamDigest)); +} + +void whal_Test_Sha1(void) +{ + WHAL_TEST_SUITE_START("sha1"); + WHAL_TEST(Test_Sha1_KnownAnswer); + WHAL_TEST(Test_Sha1_Streaming); + WHAL_TEST_SUITE_END(); +} diff --git a/tests/crypto/test_sha224.c b/tests/crypto/test_sha224.c new file mode 100644 index 0000000..f46ec0f --- /dev/null +++ b/tests/crypto/test_sha224.c @@ -0,0 +1,78 @@ +#include +#include +#include "board.h" +#include "test.h" + +static const uint8_t hashInput[] = { 'a', 'b', 'c' }; + +/* NIST FIPS 180-4: SHA-224("abc") */ +static const uint8_t sha224Digest[28] = { + 0x23, 0x09, 0x7D, 0x22, 0x34, 0x05, 0xD8, 0x22, + 0x86, 0x42, 0xA4, 0x77, 0xBD, 0xA2, 0x55, 0xB3, + 0x2A, 0xAD, 0xBC, 0xE4, 0xBD, 0xA0, 0xB3, 0xF7, + 0xE3, 0x6C, 0x9D, 0xA7, +}; + +static void Test_Sha224_KnownAnswer(void) +{ + uint8_t digest[28] = {0}; + + WHAL_ASSERT_EQ(whal_Sha224_Oneshot(&g_whalSha224, + hashInput, sizeof(hashInput), + digest, sizeof(digest)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(digest, sha224Digest, sizeof(sha224Digest)); +} + +/* Streaming KAT: 100-byte deterministic message, split mid-block. + * Vectors generated by tests/crypto/gen_test_vectors.py. */ +static const uint8_t streamMsg[100] = { + 0x03, 0x0A, 0x11, 0x18, 0x1F, 0x26, 0x2D, 0x34, + 0x3B, 0x42, 0x49, 0x50, 0x57, 0x5E, 0x65, 0x6C, + 0x73, 0x7A, 0x81, 0x88, 0x8F, 0x96, 0x9D, 0xA4, + 0xAB, 0xB2, 0xB9, 0xC0, 0xC7, 0xCE, 0xD5, 0xDC, + 0xE3, 0xEA, 0xF1, 0xF8, 0xFF, 0x06, 0x0D, 0x14, + 0x1B, 0x22, 0x29, 0x30, 0x37, 0x3E, 0x45, 0x4C, + 0x53, 0x5A, 0x61, 0x68, 0x6F, 0x76, 0x7D, 0x84, + 0x8B, 0x92, 0x99, 0xA0, 0xA7, 0xAE, 0xB5, 0xBC, + 0xC3, 0xCA, 0xD1, 0xD8, 0xDF, 0xE6, 0xED, 0xF4, + 0xFB, 0x02, 0x09, 0x10, 0x17, 0x1E, 0x25, 0x2C, + 0x33, 0x3A, 0x41, 0x48, 0x4F, 0x56, 0x5D, 0x64, + 0x6B, 0x72, 0x79, 0x80, 0x87, 0x8E, 0x95, 0x9C, + 0xA3, 0xAA, 0xB1, 0xB8, +}; + +static const uint8_t sha224StreamDigest[28] = { + 0x59, 0xE3, 0xED, 0x2A, 0xB7, 0x90, 0xB3, 0x91, + 0x25, 0x03, 0x5F, 0x7F, 0xCB, 0x4A, 0x72, 0x3F, + 0x59, 0x58, 0xA9, 0xB7, 0xC2, 0x76, 0x09, 0xF8, + 0x8A, 0x53, 0xB1, 0xBB, +}; + +static void Test_Sha224_Streaming(void) +{ + uint8_t digest[28] = {0}; + const size_t split = 50; + + WHAL_ASSERT_EQ(whal_Sha224_Start(&g_whalSha224), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Sha224_Process(&g_whalSha224, streamMsg, split), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Sha224_Process(&g_whalSha224, + streamMsg + split, + sizeof(streamMsg) - split), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Sha224_Finalize(&g_whalSha224, + digest, sizeof(digest)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(digest, sha224StreamDigest, sizeof(sha224StreamDigest)); +} + +void whal_Test_Sha224(void) +{ + WHAL_TEST_SUITE_START("sha224"); + WHAL_TEST(Test_Sha224_KnownAnswer); + WHAL_TEST(Test_Sha224_Streaming); + WHAL_TEST_SUITE_END(); +} diff --git a/tests/crypto/test_sha256.c b/tests/crypto/test_sha256.c new file mode 100644 index 0000000..ee4a9fe --- /dev/null +++ b/tests/crypto/test_sha256.c @@ -0,0 +1,78 @@ +#include +#include +#include "board.h" +#include "test.h" + +static const uint8_t hashInput[] = { 'a', 'b', 'c' }; + +/* NIST FIPS 180-4: SHA-256("abc") */ +static const uint8_t sha256Digest[32] = { + 0xBA, 0x78, 0x16, 0xBF, 0x8F, 0x01, 0xCF, 0xEA, + 0x41, 0x41, 0x40, 0xDE, 0x5D, 0xAE, 0x22, 0x23, + 0xB0, 0x03, 0x61, 0xA3, 0x96, 0x17, 0x7A, 0x9C, + 0xB4, 0x10, 0xFF, 0x61, 0xF2, 0x00, 0x15, 0xAD, +}; + +static void Test_Sha256_KnownAnswer(void) +{ + uint8_t digest[32] = {0}; + + WHAL_ASSERT_EQ(whal_Sha256_Oneshot(&g_whalSha256, + hashInput, sizeof(hashInput), + digest, sizeof(digest)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(digest, sha256Digest, sizeof(sha256Digest)); +} + +/* Streaming KAT: 100-byte deterministic message, split mid-block. + * Vectors generated by tests/crypto/gen_test_vectors.py. */ +static const uint8_t streamMsg[100] = { + 0x03, 0x0A, 0x11, 0x18, 0x1F, 0x26, 0x2D, 0x34, + 0x3B, 0x42, 0x49, 0x50, 0x57, 0x5E, 0x65, 0x6C, + 0x73, 0x7A, 0x81, 0x88, 0x8F, 0x96, 0x9D, 0xA4, + 0xAB, 0xB2, 0xB9, 0xC0, 0xC7, 0xCE, 0xD5, 0xDC, + 0xE3, 0xEA, 0xF1, 0xF8, 0xFF, 0x06, 0x0D, 0x14, + 0x1B, 0x22, 0x29, 0x30, 0x37, 0x3E, 0x45, 0x4C, + 0x53, 0x5A, 0x61, 0x68, 0x6F, 0x76, 0x7D, 0x84, + 0x8B, 0x92, 0x99, 0xA0, 0xA7, 0xAE, 0xB5, 0xBC, + 0xC3, 0xCA, 0xD1, 0xD8, 0xDF, 0xE6, 0xED, 0xF4, + 0xFB, 0x02, 0x09, 0x10, 0x17, 0x1E, 0x25, 0x2C, + 0x33, 0x3A, 0x41, 0x48, 0x4F, 0x56, 0x5D, 0x64, + 0x6B, 0x72, 0x79, 0x80, 0x87, 0x8E, 0x95, 0x9C, + 0xA3, 0xAA, 0xB1, 0xB8, +}; + +static const uint8_t sha256StreamDigest[32] = { + 0x5A, 0x2C, 0xDA, 0x23, 0x51, 0xD1, 0xCD, 0xD9, + 0xDD, 0x79, 0x57, 0xE5, 0x7C, 0x0B, 0x3C, 0x85, + 0x22, 0x45, 0x1F, 0x25, 0xB6, 0x49, 0x45, 0x69, + 0xB7, 0xE9, 0x43, 0x88, 0xC4, 0x6F, 0x09, 0x80, +}; + +static void Test_Sha256_Streaming(void) +{ + uint8_t digest[32] = {0}; + const size_t split = 50; + + WHAL_ASSERT_EQ(whal_Sha256_Start(&g_whalSha256), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Sha256_Process(&g_whalSha256, streamMsg, split), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Sha256_Process(&g_whalSha256, + streamMsg + split, + sizeof(streamMsg) - split), + WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Sha256_Finalize(&g_whalSha256, + digest, sizeof(digest)), + WHAL_SUCCESS); + + WHAL_ASSERT_MEM_EQ(digest, sha256StreamDigest, sizeof(sha256StreamDigest)); +} + +void whal_Test_Sha256(void) +{ + WHAL_TEST_SUITE_START("sha256"); + WHAL_TEST(Test_Sha256_KnownAnswer); + WHAL_TEST(Test_Sha256_Streaming); + WHAL_TEST_SUITE_END(); +} diff --git a/tests/main.c b/tests/main.c index dc832c7..c55314b 100644 --- a/tests/main.c +++ b/tests/main.c @@ -59,6 +59,54 @@ void whal_Test_Crypto_Platform(void); #endif #endif +#ifdef WHAL_TEST_ENABLE_AES_ECB +void whal_Test_AesEcb(void); +#endif + +#ifdef WHAL_TEST_ENABLE_AES_CBC +void whal_Test_AesCbc(void); +#endif + +#ifdef WHAL_TEST_ENABLE_AES_CTR +void whal_Test_AesCtr(void); +#endif + +#ifdef WHAL_TEST_ENABLE_AES_GCM +void whal_Test_AesGcm(void); +#endif + +#ifdef WHAL_TEST_ENABLE_AES_GMAC +void whal_Test_AesGmac(void); +#endif + +#ifdef WHAL_TEST_ENABLE_AES_CCM +void whal_Test_AesCcm(void); +#endif + +#ifdef WHAL_TEST_ENABLE_SHA1 +void whal_Test_Sha1(void); +#endif + +#ifdef WHAL_TEST_ENABLE_SHA224 +void whal_Test_Sha224(void); +#endif + +#ifdef WHAL_TEST_ENABLE_SHA256 +void whal_Test_Sha256(void); +#endif + +#ifdef WHAL_TEST_ENABLE_HMAC_SHA1 +void whal_Test_HmacSha1(void); +#endif + +#ifdef WHAL_TEST_ENABLE_HMAC_SHA224 +void whal_Test_HmacSha224(void); +#endif + +#ifdef WHAL_TEST_ENABLE_HMAC_SHA256 +void whal_Test_HmacSha256(void); +#endif + #ifdef WHAL_TEST_ENABLE_BLOCK void whal_Test_Block(void); #endif @@ -204,6 +252,54 @@ void main(void) #endif #endif +#ifdef WHAL_TEST_ENABLE_AES_ECB + whal_Test_AesEcb(); +#endif + +#ifdef WHAL_TEST_ENABLE_AES_CBC + whal_Test_AesCbc(); +#endif + +#ifdef WHAL_TEST_ENABLE_AES_CTR + whal_Test_AesCtr(); +#endif + +#ifdef WHAL_TEST_ENABLE_AES_GCM + whal_Test_AesGcm(); +#endif + +#ifdef WHAL_TEST_ENABLE_AES_GMAC + whal_Test_AesGmac(); +#endif + +#ifdef WHAL_TEST_ENABLE_AES_CCM + whal_Test_AesCcm(); +#endif + +#ifdef WHAL_TEST_ENABLE_SHA1 + whal_Test_Sha1(); +#endif + +#ifdef WHAL_TEST_ENABLE_SHA224 + whal_Test_Sha224(); +#endif + +#ifdef WHAL_TEST_ENABLE_SHA256 + whal_Test_Sha256(); +#endif + +#ifdef WHAL_TEST_ENABLE_HMAC_SHA1 + whal_Test_HmacSha1(); +#endif + +#ifdef WHAL_TEST_ENABLE_HMAC_SHA224 + whal_Test_HmacSha224(); +#endif + +#ifdef WHAL_TEST_ENABLE_HMAC_SHA256 + whal_Test_HmacSha256(); +#endif + #ifdef WHAL_TEST_ENABLE_BLOCK whal_Test_Block(); #endif diff --git a/wolfHAL/crypto/crypto.h b/wolfHAL/crypto/crypto.h index f4ff670..34e0de1 100644 --- a/wolfHAL/crypto/crypto.h +++ b/wolfHAL/crypto/crypto.h @@ -5,9 +5,14 @@ #include #include -/* +/** * @file crypto.h - * @brief Generic crypto accelerator abstraction and driver interface. + * @brief Crypto accelerator device handle and per-algorithm API. + * + * whal_Crypto is a platform driver representing a crypto hardware peripheral. + * It provides Init/Deinit for hardware lifecycle. Each algorithm gets its own + * typed device struct (whal_AesGcm, whal_AesEcb, etc.) that references the + * underlying whal_Crypto device and a per-algorithm driver vtable. */ /* ---- Common enums ---- */ @@ -17,155 +22,20 @@ typedef enum { WHAL_CRYPTO_DECRYPT, } whal_Crypto_Dir; -enum { - WHAL_CRYPTO_AES_ECB, - WHAL_CRYPTO_AES_CBC, - WHAL_CRYPTO_AES_CTR, - WHAL_CRYPTO_AES_GCM, - WHAL_CRYPTO_AES_GMAC, - WHAL_CRYPTO_AES_CCM, - WHAL_CRYPTO_SHA1, - WHAL_CRYPTO_SHA224, - WHAL_CRYPTO_SHA256, - WHAL_CRYPTO_HMAC_SHA1, - WHAL_CRYPTO_HMAC_SHA224, - WHAL_CRYPTO_HMAC_SHA256, -}; - -/* ---- Per-algorithm argument structs ---- */ - -/* - * @brief Arguments for AES-ECB. - */ -typedef struct { - whal_Crypto_Dir dir; - const void *key; - size_t keySz; /* 16, 24, or 32 */ - const void *in; - void *out; - size_t sz; /* Must be a multiple of 16 */ -} whal_Crypto_AesEcbArgs; - -/* - * @brief Arguments for AES-CBC. - */ -typedef struct { - whal_Crypto_Dir dir; - const void *key; - size_t keySz; /* 16, 24, or 32 */ - const void *iv; /* 16 bytes */ - const void *in; - void *out; - size_t sz; /* Must be a multiple of 16 */ -} whal_Crypto_AesCbcArgs; - -/* - * @brief Arguments for AES-CTR. - */ -typedef struct { - whal_Crypto_Dir dir; - const void *key; - size_t keySz; /* 16, 24, or 32 */ - const void *iv; /* 16 bytes (initial counter block) */ - const void *in; - void *out; - size_t sz; -} whal_Crypto_AesCtrArgs; - -/* - * @brief Arguments for AES-GCM. - */ -typedef struct { - whal_Crypto_Dir dir; - const void *key; - size_t keySz; /* 16, 24, or 32 */ - const void *iv; - size_t ivSz; /* Typically 12 */ - const void *in; - void *out; - size_t sz; - const void *aad; - size_t aadSz; - void *tag; - size_t tagSz; /* Up to 16 */ -} whal_Crypto_AesGcmArgs; - -/* - * @brief Arguments for AES-CCM. - */ -typedef struct { - whal_Crypto_Dir dir; - const void *key; - size_t keySz; /* 16, 24, or 32 */ - const void *nonce; - size_t nonceSz; /* 7-13 */ - const void *in; - void *out; - size_t sz; - const void *aad; - size_t aadSz; - void *tag; - size_t tagSz; /* 4, 6, 8, 10, 12, 14, or 16 */ -} whal_Crypto_AesCcmArgs; - -/* - * @brief Arguments for AES-GMAC (authentication only, no payload). - */ -typedef struct { - const void *key; - size_t keySz; /* 16, 24, or 32 */ - const void *iv; - size_t ivSz; /* Typically 12 */ - const void *aad; - size_t aadSz; - void *tag; - size_t tagSz; /* Up to 16 */ -} whal_Crypto_AesGmacArgs; - -/* - * @brief Arguments for one-shot hash (SHA-1/224/256/...). - */ -typedef struct { - const void *in; - size_t inSz; - void *digest; - size_t digestSz; /* Algorithm-specific (20/28/32/48/64) */ -} whal_Crypto_HashArgs; - -/* - * @brief Arguments for one-shot HMAC (HMAC-SHA-1/224/256/...). - */ -typedef struct { - const void *key; - size_t keySz; - const void *in; - size_t inSz; - void *digest; - size_t digestSz; /* Algorithm-specific (20/28/32/48/64) */ -} whal_Crypto_HmacArgs; - -/* ---- Device and driver ---- */ +/* ---- Hardware device (platform driver) ---- */ typedef struct whal_Crypto whal_Crypto; -/* - * @brief Driver vtable for crypto devices. +/** + * @brief Crypto hardware driver vtable (Init/Deinit only). */ typedef struct { - /* Initialize the crypto hardware. */ - whal_Error (*Init)(whal_Crypto *cryptoDev); - /* Deinitialize the crypto hardware. */ - whal_Error (*Deinit)(whal_Crypto *cryptoDev); - /* Start a crypto operation: configure hardware, load key/IV, process AAD. */ - whal_Error (*StartOp)(whal_Crypto *cryptoDev, size_t opId, void *opArgs); - /* Process data through the crypto engine. */ - whal_Error (*Process)(whal_Crypto *cryptoDev, size_t opId, void *opArgs); - /* End a crypto operation: finalize, release hardware. */ - whal_Error (*EndOp)(whal_Crypto *cryptoDev, size_t opId, void *opArgs); + whal_Error (*Init)(whal_Crypto *dev); + whal_Error (*Deinit)(whal_Crypto *dev); } whal_CryptoDriver; -/* - * @brief Crypto device instance tying a register map, driver, and configuration. +/** + * @brief Crypto hardware device instance. */ struct whal_Crypto { const size_t base; @@ -173,749 +43,397 @@ struct whal_Crypto { const void *cfg; }; -/* - * @brief Initialize a crypto device and its driver. - * - * @param cryptoDev Pointer to the crypto instance to initialize. - * - * @retval WHAL_SUCCESS Driver-specific init completed. - * @retval WHAL_EINVAL Null pointer. - * @retval WHAL_ENOTSUP Operation not implemented by this driver. - */ -whal_Error whal_Crypto_Init(whal_Crypto *cryptoDev); - -/* - * @brief Deinitialize a crypto device and release resources. - * - * @param cryptoDev Pointer to the crypto instance to deinitialize. - * - * @retval WHAL_SUCCESS Driver-specific deinit completed. - * @retval WHAL_EINVAL Null pointer. - * @retval WHAL_ENOTSUP Operation not implemented by this driver. - */ -whal_Error whal_Crypto_Deinit(whal_Crypto *cryptoDev); - -/* - * @brief Start a crypto operation. - * - * Configures the hardware for the requested algorithm, loads keys and - * parameters, and performs any setup (e.g. AAD processing for AEAD modes). - * - * @param cryptoDev Pointer to the crypto instance. - * @param opId Operation identifier (e.g. WHAL_CRYPTO_AES_GCM). - * @param opArgs Pointer to the algorithm-specific arguments struct. - * - * @retval WHAL_SUCCESS Operation started. - * @retval WHAL_EINVAL Invalid arguments. - * @retval WHAL_ENOTSUP Operation not implemented by this driver. - * @retval WHAL_EHARDWARE Hardware error during setup. - */ -whal_Error whal_Crypto_StartOp(whal_Crypto *cryptoDev, size_t opId, - void *opArgs); - -/* - * @brief Process data through an active crypto operation. - * - * Feeds data through the hardware. May be called multiple times for - * streaming. Optional for single-shot operations. +/** + * @brief Initialize a crypto hardware device. * - * @param cryptoDev Pointer to the crypto instance. - * @param opId Operation identifier. - * @param opArgs Pointer to the algorithm-specific arguments struct. - * - * @retval WHAL_SUCCESS Data processed. - * @retval WHAL_EINVAL Invalid arguments. - * @retval WHAL_ENOTSUP Operation not implemented by this driver. - * @retval WHAL_EHARDWARE Hardware error during processing. + * @param dev Crypto device instance. */ -whal_Error whal_Crypto_Process(whal_Crypto *cryptoDev, size_t opId, - void *opArgs); +whal_Error whal_Crypto_Init(whal_Crypto *dev); -/* - * @brief End a crypto operation. - * - * Finalizes the operation, reads output (tag, digest, signature), and - * releases the hardware. - * - * @param cryptoDev Pointer to the crypto instance. - * @param opId Operation identifier. - * @param opArgs Pointer to the algorithm-specific arguments struct. +/** + * @brief Deinitialize a crypto hardware device. * - * @retval WHAL_SUCCESS Operation finalized. - * @retval WHAL_EINVAL Invalid arguments. - * @retval WHAL_ENOTSUP Operation not implemented by this driver. - * @retval WHAL_EHARDWARE Hardware error during finalization. + * @param dev Crypto device instance. */ -whal_Error whal_Crypto_EndOp(whal_Crypto *cryptoDev, size_t opId, - void *opArgs); +whal_Error whal_Crypto_Deinit(whal_Crypto *dev); -/* ---- Per-algorithm inline wrappers ---- */ -#ifdef WHAL_CFG_CRYPTO_AES_ECB +/* ---- Per-algorithm device structs and vtables ---- */ /* AES-ECB */ -static inline whal_Error whal_Crypto_AesEcb(whal_Crypto *dev, - whal_Crypto_AesEcbArgs *args) -{ - whal_Error err; - - err = whal_Crypto_StartOp(dev, WHAL_CRYPTO_AES_ECB, args); - if (err) - return err; - - err = whal_Crypto_Process(dev, WHAL_CRYPTO_AES_ECB, args); - if (err) - return err; +typedef struct whal_AesEcb whal_AesEcb; - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_AES_ECB, args); -} - -static inline whal_Error whal_Crypto_AesEcb_Start(whal_Crypto *dev, - whal_Crypto_Dir dir, - const void *key, size_t keySz) -{ - whal_Crypto_AesEcbArgs args = {0}; - - args.dir = dir; - args.key = key; - args.keySz = keySz; - - return whal_Crypto_StartOp(dev, WHAL_CRYPTO_AES_ECB, &args); -} - -static inline whal_Error whal_Crypto_AesEcb_Update(whal_Crypto *dev, - const void *in, void *out, - size_t sz) -{ - whal_Crypto_AesEcbArgs args = {0}; - - args.in = in; - args.out = out; - args.sz = sz; - - return whal_Crypto_Process(dev, WHAL_CRYPTO_AES_ECB, &args); -} - -static inline whal_Error whal_Crypto_AesEcb_Finalize(whal_Crypto *dev) -{ - whal_Crypto_AesEcbArgs args = {0}; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_AES_ECB, &args); -} -#endif /* WHAL_CFG_CRYPTO_AES_ECB */ +typedef struct { + whal_Error (*Oneshot)(whal_AesEcb *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *in, void *out, size_t sz); + whal_Error (*Start)(whal_AesEcb *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz); + whal_Error (*Process)(whal_AesEcb *dev, + const void *in, void *out, size_t sz); +} whal_AesEcbDriver; + +struct whal_AesEcb { + whal_Crypto *crypto; + const whal_AesEcbDriver *driver; +}; -#ifdef WHAL_CFG_CRYPTO_AES_CBC +whal_Error whal_AesEcb_Oneshot(whal_AesEcb *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *in, void *out, size_t sz); +whal_Error whal_AesEcb_Start(whal_AesEcb *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz); +whal_Error whal_AesEcb_Process(whal_AesEcb *dev, + const void *in, void *out, size_t sz); /* AES-CBC */ -static inline whal_Error whal_Crypto_AesCbc(whal_Crypto *dev, - whal_Crypto_AesCbcArgs *args) -{ - whal_Error err; - - err = whal_Crypto_StartOp(dev, WHAL_CRYPTO_AES_CBC, args); - if (err) - return err; - - err = whal_Crypto_Process(dev, WHAL_CRYPTO_AES_CBC, args); - if (err) - return err; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_AES_CBC, args); -} - -static inline whal_Error whal_Crypto_AesCbc_Start(whal_Crypto *dev, - whal_Crypto_Dir dir, - const void *key, size_t keySz, - const void *iv) -{ - whal_Crypto_AesCbcArgs args = {0}; - - args.dir = dir; - args.key = key; - args.keySz = keySz; - args.iv = iv; - - return whal_Crypto_StartOp(dev, WHAL_CRYPTO_AES_CBC, &args); -} - -static inline whal_Error whal_Crypto_AesCbc_Update(whal_Crypto *dev, - const void *in, void *out, - size_t sz) -{ - whal_Crypto_AesCbcArgs args = {0}; - - args.in = in; - args.out = out; - args.sz = sz; - - return whal_Crypto_Process(dev, WHAL_CRYPTO_AES_CBC, &args); -} - -static inline whal_Error whal_Crypto_AesCbc_Finalize(whal_Crypto *dev) -{ - whal_Crypto_AesCbcArgs args = {0}; +typedef struct whal_AesCbc whal_AesCbc; - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_AES_CBC, &args); -} -#endif /* WHAL_CFG_CRYPTO_AES_CBC */ +typedef struct { + whal_Error (*Oneshot)(whal_AesCbc *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, + const void *in, void *out, size_t sz); + whal_Error (*Start)(whal_AesCbc *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv); + whal_Error (*Process)(whal_AesCbc *dev, + const void *in, void *out, size_t sz); +} whal_AesCbcDriver; + +struct whal_AesCbc { + whal_Crypto *crypto; + const whal_AesCbcDriver *driver; +}; -#ifdef WHAL_CFG_CRYPTO_AES_CTR +whal_Error whal_AesCbc_Oneshot(whal_AesCbc *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, + const void *in, void *out, size_t sz); +whal_Error whal_AesCbc_Start(whal_AesCbc *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv); +whal_Error whal_AesCbc_Process(whal_AesCbc *dev, + const void *in, void *out, size_t sz); /* AES-CTR */ -static inline whal_Error whal_Crypto_AesCtr(whal_Crypto *dev, - whal_Crypto_AesCtrArgs *args) -{ - whal_Error err; - - err = whal_Crypto_StartOp(dev, WHAL_CRYPTO_AES_CTR, args); - if (err) - return err; - - err = whal_Crypto_Process(dev, WHAL_CRYPTO_AES_CTR, args); - if (err) - return err; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_AES_CTR, args); -} - -static inline whal_Error whal_Crypto_AesCtr_Start(whal_Crypto *dev, - whal_Crypto_Dir dir, - const void *key, size_t keySz, - const void *iv) -{ - whal_Crypto_AesCtrArgs args = {0}; - - args.dir = dir; - args.key = key; - args.keySz = keySz; - args.iv = iv; - - return whal_Crypto_StartOp(dev, WHAL_CRYPTO_AES_CTR, &args); -} - -static inline whal_Error whal_Crypto_AesCtr_Update(whal_Crypto *dev, - const void *in, void *out, - size_t sz) -{ - whal_Crypto_AesCtrArgs args = {0}; - - args.in = in; - args.out = out; - args.sz = sz; +typedef struct whal_AesCtr whal_AesCtr; - return whal_Crypto_Process(dev, WHAL_CRYPTO_AES_CTR, &args); -} - -static inline whal_Error whal_Crypto_AesCtr_Finalize(whal_Crypto *dev) -{ - whal_Crypto_AesCtrArgs args = {0}; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_AES_CTR, &args); -} -#endif /* WHAL_CFG_CRYPTO_AES_CTR */ +typedef struct { + whal_Error (*Oneshot)(whal_AesCtr *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, + const void *in, void *out, size_t sz); + whal_Error (*Start)(whal_AesCtr *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv); + whal_Error (*Process)(whal_AesCtr *dev, + const void *in, void *out, size_t sz); +} whal_AesCtrDriver; + +struct whal_AesCtr { + whal_Crypto *crypto; + const whal_AesCtrDriver *driver; +}; -#ifdef WHAL_CFG_CRYPTO_AES_GCM +whal_Error whal_AesCtr_Oneshot(whal_AesCtr *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, + const void *in, void *out, size_t sz); +whal_Error whal_AesCtr_Start(whal_AesCtr *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv); +whal_Error whal_AesCtr_Process(whal_AesCtr *dev, + const void *in, void *out, size_t sz); /* AES-GCM */ -static inline whal_Error whal_Crypto_AesGcm(whal_Crypto *dev, - whal_Crypto_AesGcmArgs *args) -{ - whal_Error err; - - err = whal_Crypto_StartOp(dev, WHAL_CRYPTO_AES_GCM, args); - if (err) - return err; - - err = whal_Crypto_Process(dev, WHAL_CRYPTO_AES_GCM, args); - if (err) - return err; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_AES_GCM, args); -} - -static inline whal_Error whal_Crypto_AesGcm_Start(whal_Crypto *dev, - whal_Crypto_Dir dir, - const void *key, size_t keySz, - const void *iv, size_t ivSz, - const void *aad, size_t aadSz) -{ - whal_Crypto_AesGcmArgs args = {0}; - - args.dir = dir; - args.key = key; - args.keySz = keySz; - args.iv = iv; - args.ivSz = ivSz; - args.aad = aad; - args.aadSz = aadSz; - - return whal_Crypto_StartOp(dev, WHAL_CRYPTO_AES_GCM, &args); -} - -static inline whal_Error whal_Crypto_AesGcm_Update(whal_Crypto *dev, - whal_Crypto_Dir dir, - const void *in, void *out, - size_t sz, size_t aadSz) -{ - whal_Crypto_AesGcmArgs args = {0}; - - args.dir = dir; - args.in = in; - args.out = out; - args.sz = sz; - args.aadSz = aadSz; - - return whal_Crypto_Process(dev, WHAL_CRYPTO_AES_GCM, &args); -} - -static inline whal_Error whal_Crypto_AesGcm_Finalize(whal_Crypto *dev, - void *tag, size_t tagSz, - size_t aadSz, size_t sz) -{ - whal_Crypto_AesGcmArgs args = {0}; - - args.tag = tag; - args.tagSz = tagSz; - args.aadSz = aadSz; - args.sz = sz; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_AES_GCM, &args); -} -#endif /* WHAL_CFG_CRYPTO_AES_GCM */ - -#ifdef WHAL_CFG_CRYPTO_AES_GMAC +typedef struct whal_AesGcm whal_AesGcm; -/* AES-GMAC */ +typedef struct { + whal_Error (*Oneshot)(whal_AesGcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz, + const void *in, void *out, size_t sz, + void *tag, size_t tagSz); + whal_Error (*Start)(whal_AesGcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz); + whal_Error (*Process)(whal_AesGcm *dev, + const void *in, void *out, size_t sz); + whal_Error (*Finalize)(whal_AesGcm *dev, + void *tag, size_t tagSz); +} whal_AesGcmDriver; + +struct whal_AesGcm { + whal_Crypto *crypto; + const whal_AesGcmDriver *driver; + void *state; +}; -static inline whal_Error whal_Crypto_AesGmac(whal_Crypto *dev, - whal_Crypto_AesGmacArgs *args) -{ - whal_Error err; +whal_Error whal_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz, + const void *in, void *out, size_t sz, + void *tag, size_t tagSz); +whal_Error whal_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz); +whal_Error whal_AesGcm_Process(whal_AesGcm *dev, + const void *in, void *out, size_t sz); +whal_Error whal_AesGcm_Finalize(whal_AesGcm *dev, + void *tag, size_t tagSz); - err = whal_Crypto_StartOp(dev, WHAL_CRYPTO_AES_GMAC, args); - if (err) - return err; +/* AES-GMAC */ - err = whal_Crypto_Process(dev, WHAL_CRYPTO_AES_GMAC, args); - if (err) - return err; +typedef struct whal_AesGmac whal_AesGmac; - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_AES_GMAC, args); -} -#endif /* WHAL_CFG_CRYPTO_AES_GMAC */ +typedef struct { + whal_Error (*Oneshot)(whal_AesGmac *dev, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz, + void *tag, size_t tagSz); +} whal_AesGmacDriver; + +struct whal_AesGmac { + whal_Crypto *crypto; + const whal_AesGmacDriver *driver; +}; -#ifdef WHAL_CFG_CRYPTO_AES_CCM +whal_Error whal_AesGmac_Oneshot(whal_AesGmac *dev, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz, + void *tag, size_t tagSz); /* AES-CCM */ -static inline whal_Error whal_Crypto_AesCcm(whal_Crypto *dev, - whal_Crypto_AesCcmArgs *args) -{ - whal_Error err; - - err = whal_Crypto_StartOp(dev, WHAL_CRYPTO_AES_CCM, args); - if (err) - return err; - - err = whal_Crypto_Process(dev, WHAL_CRYPTO_AES_CCM, args); - if (err) - return err; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_AES_CCM, args); -} - -static inline whal_Error whal_Crypto_AesCcm_Start(whal_Crypto *dev, - whal_Crypto_Dir dir, - const void *key, size_t keySz, - const void *nonce, - size_t nonceSz, - const void *aad, size_t aadSz, - size_t tagSz, size_t sz) -{ - whal_Crypto_AesCcmArgs args = {0}; - - args.dir = dir; - args.key = key; - args.keySz = keySz; - args.nonce = nonce; - args.nonceSz = nonceSz; - args.aad = aad; - args.aadSz = aadSz; - args.tagSz = tagSz; - args.sz = sz; - - return whal_Crypto_StartOp(dev, WHAL_CRYPTO_AES_CCM, &args); -} - -static inline whal_Error whal_Crypto_AesCcm_Update(whal_Crypto *dev, - whal_Crypto_Dir dir, - const void *in, void *out, - size_t sz, size_t aadSz) -{ - whal_Crypto_AesCcmArgs args = {0}; - - args.dir = dir; - args.in = in; - args.out = out; - args.sz = sz; - args.aadSz = aadSz; - - return whal_Crypto_Process(dev, WHAL_CRYPTO_AES_CCM, &args); -} - -static inline whal_Error whal_Crypto_AesCcm_Finalize(whal_Crypto *dev, - void *tag, size_t tagSz, - size_t aadSz, size_t sz) -{ - whal_Crypto_AesCcmArgs args = {0}; - - args.tag = tag; - args.tagSz = tagSz; - args.aadSz = aadSz; - args.sz = sz; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_AES_CCM, &args); -} -#endif /* WHAL_CFG_CRYPTO_AES_CCM */ - -#ifdef WHAL_CFG_CRYPTO_SHA1 - -/* SHA-1 */ - -static inline whal_Error whal_Crypto_Sha1(whal_Crypto *dev, - whal_Crypto_HashArgs *args) -{ - whal_Error err; - - err = whal_Crypto_StartOp(dev, WHAL_CRYPTO_SHA1, args); - if (err) - return err; - - err = whal_Crypto_Process(dev, WHAL_CRYPTO_SHA1, args); - if (err) - return err; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_SHA1, args); -} - -static inline whal_Error whal_Crypto_Sha1_Start(whal_Crypto *dev) -{ - whal_Crypto_HashArgs args = {0}; - - return whal_Crypto_StartOp(dev, WHAL_CRYPTO_SHA1, &args); -} - -static inline whal_Error whal_Crypto_Sha1_Update(whal_Crypto *dev, - const void *in, size_t inSz) -{ - whal_Crypto_HashArgs args = {0}; +typedef struct whal_AesCcm whal_AesCcm; - args.in = in; - args.inSz = inSz; +typedef struct { + whal_Error (*Oneshot)(whal_AesCcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *nonce, size_t nonceSz, + const void *aad, size_t aadSz, + const void *in, void *out, size_t sz, + void *tag, size_t tagSz); + whal_Error (*Start)(whal_AesCcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *nonce, size_t nonceSz, + const void *aad, size_t aadSz, + size_t tagSz, size_t sz); + whal_Error (*Process)(whal_AesCcm *dev, + const void *in, void *out, size_t sz); + whal_Error (*Finalize)(whal_AesCcm *dev, + void *tag, size_t tagSz); +} whal_AesCcmDriver; + +struct whal_AesCcm { + whal_Crypto *crypto; + const whal_AesCcmDriver *driver; + void *state; +}; - return whal_Crypto_Process(dev, WHAL_CRYPTO_SHA1, &args); -} +whal_Error whal_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *nonce, size_t nonceSz, + const void *aad, size_t aadSz, + const void *in, void *out, size_t sz, + void *tag, size_t tagSz); +whal_Error whal_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *nonce, size_t nonceSz, + const void *aad, size_t aadSz, + size_t tagSz, size_t sz); +whal_Error whal_AesCcm_Process(whal_AesCcm *dev, + const void *in, void *out, size_t sz); +whal_Error whal_AesCcm_Finalize(whal_AesCcm *dev, + void *tag, size_t tagSz); -static inline whal_Error whal_Crypto_Sha1_Finalize(whal_Crypto *dev, - void *digest, - size_t digestSz) -{ - whal_Crypto_HashArgs args = {0}; +/* SHA-1 */ - args.digest = digest; - args.digestSz = digestSz; +typedef struct whal_Sha1 whal_Sha1; - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_SHA1, &args); -} -#endif /* WHAL_CFG_CRYPTO_SHA1 */ +typedef struct { + whal_Error (*Oneshot)(whal_Sha1 *dev, + const void *in, size_t inSz, + void *digest, size_t digestSz); + whal_Error (*Start)(whal_Sha1 *dev); + whal_Error (*Process)(whal_Sha1 *dev, const void *in, size_t inSz); + whal_Error (*Finalize)(whal_Sha1 *dev, void *digest, size_t digestSz); +} whal_Sha1Driver; + +struct whal_Sha1 { + whal_Crypto *crypto; + const whal_Sha1Driver *driver; +}; -#ifdef WHAL_CFG_CRYPTO_SHA224 +whal_Error whal_Sha1_Oneshot(whal_Sha1 *dev, + const void *in, size_t inSz, + void *digest, size_t digestSz); +whal_Error whal_Sha1_Start(whal_Sha1 *dev); +whal_Error whal_Sha1_Process(whal_Sha1 *dev, const void *in, size_t inSz); +whal_Error whal_Sha1_Finalize(whal_Sha1 *dev, void *digest, size_t digestSz); /* SHA-224 */ -static inline whal_Error whal_Crypto_Sha224(whal_Crypto *dev, - whal_Crypto_HashArgs *args) -{ - whal_Error err; - - err = whal_Crypto_StartOp(dev, WHAL_CRYPTO_SHA224, args); - if (err) - return err; - - err = whal_Crypto_Process(dev, WHAL_CRYPTO_SHA224, args); - if (err) - return err; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_SHA224, args); -} - -static inline whal_Error whal_Crypto_Sha224_Start(whal_Crypto *dev) -{ - whal_Crypto_HashArgs args = {0}; - - return whal_Crypto_StartOp(dev, WHAL_CRYPTO_SHA224, &args); -} +typedef struct whal_Sha224 whal_Sha224; -static inline whal_Error whal_Crypto_Sha224_Update(whal_Crypto *dev, - const void *in, size_t inSz) -{ - whal_Crypto_HashArgs args = {0}; - - args.in = in; - args.inSz = inSz; - - return whal_Crypto_Process(dev, WHAL_CRYPTO_SHA224, &args); -} - -static inline whal_Error whal_Crypto_Sha224_Finalize(whal_Crypto *dev, - void *digest, - size_t digestSz) -{ - whal_Crypto_HashArgs args = {0}; - - args.digest = digest; - args.digestSz = digestSz; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_SHA224, &args); -} -#endif /* WHAL_CFG_CRYPTO_SHA224 */ +typedef struct { + whal_Error (*Oneshot)(whal_Sha224 *dev, + const void *in, size_t inSz, + void *digest, size_t digestSz); + whal_Error (*Start)(whal_Sha224 *dev); + whal_Error (*Process)(whal_Sha224 *dev, const void *in, size_t inSz); + whal_Error (*Finalize)(whal_Sha224 *dev, void *digest, size_t digestSz); +} whal_Sha224Driver; + +struct whal_Sha224 { + whal_Crypto *crypto; + const whal_Sha224Driver *driver; +}; -#ifdef WHAL_CFG_CRYPTO_SHA256 +whal_Error whal_Sha224_Oneshot(whal_Sha224 *dev, + const void *in, size_t inSz, + void *digest, size_t digestSz); +whal_Error whal_Sha224_Start(whal_Sha224 *dev); +whal_Error whal_Sha224_Process(whal_Sha224 *dev, const void *in, size_t inSz); +whal_Error whal_Sha224_Finalize(whal_Sha224 *dev, + void *digest, size_t digestSz); /* SHA-256 */ -static inline whal_Error whal_Crypto_Sha256(whal_Crypto *dev, - whal_Crypto_HashArgs *args) -{ - whal_Error err; - - err = whal_Crypto_StartOp(dev, WHAL_CRYPTO_SHA256, args); - if (err) - return err; - - err = whal_Crypto_Process(dev, WHAL_CRYPTO_SHA256, args); - if (err) - return err; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_SHA256, args); -} +typedef struct whal_Sha256 whal_Sha256; -static inline whal_Error whal_Crypto_Sha256_Start(whal_Crypto *dev) -{ - whal_Crypto_HashArgs args = {0}; - - return whal_Crypto_StartOp(dev, WHAL_CRYPTO_SHA256, &args); -} - -static inline whal_Error whal_Crypto_Sha256_Update(whal_Crypto *dev, - const void *in, size_t inSz) -{ - whal_Crypto_HashArgs args = {0}; - - args.in = in; - args.inSz = inSz; - - return whal_Crypto_Process(dev, WHAL_CRYPTO_SHA256, &args); -} - -static inline whal_Error whal_Crypto_Sha256_Finalize(whal_Crypto *dev, - void *digest, - size_t digestSz) -{ - whal_Crypto_HashArgs args = {0}; - - args.digest = digest; - args.digestSz = digestSz; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_SHA256, &args); -} -#endif /* WHAL_CFG_CRYPTO_SHA256 */ +typedef struct { + whal_Error (*Oneshot)(whal_Sha256 *dev, + const void *in, size_t inSz, + void *digest, size_t digestSz); + whal_Error (*Start)(whal_Sha256 *dev); + whal_Error (*Process)(whal_Sha256 *dev, const void *in, size_t inSz); + whal_Error (*Finalize)(whal_Sha256 *dev, void *digest, size_t digestSz); +} whal_Sha256Driver; + +struct whal_Sha256 { + whal_Crypto *crypto; + const whal_Sha256Driver *driver; +}; -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA1 +whal_Error whal_Sha256_Oneshot(whal_Sha256 *dev, + const void *in, size_t inSz, + void *digest, size_t digestSz); +whal_Error whal_Sha256_Start(whal_Sha256 *dev); +whal_Error whal_Sha256_Process(whal_Sha256 *dev, const void *in, size_t inSz); +whal_Error whal_Sha256_Finalize(whal_Sha256 *dev, + void *digest, size_t digestSz); /* HMAC-SHA-1 */ -static inline whal_Error whal_Crypto_HmacSha1(whal_Crypto *dev, - whal_Crypto_HmacArgs *args) -{ - whal_Error err; +typedef struct whal_HmacSha1 whal_HmacSha1; - err = whal_Crypto_StartOp(dev, WHAL_CRYPTO_HMAC_SHA1, args); - if (err) - return err; - - err = whal_Crypto_Process(dev, WHAL_CRYPTO_HMAC_SHA1, args); - if (err) - return err; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_HMAC_SHA1, args); -} - -static inline whal_Error whal_Crypto_HmacSha1_Start(whal_Crypto *dev, - const void *key, - size_t keySz) -{ - whal_Crypto_HmacArgs args = {0}; - - args.key = key; - args.keySz = keySz; - - return whal_Crypto_StartOp(dev, WHAL_CRYPTO_HMAC_SHA1, &args); -} - -static inline whal_Error whal_Crypto_HmacSha1_Update(whal_Crypto *dev, - const void *in, - size_t inSz) -{ - whal_Crypto_HmacArgs args = {0}; - - args.in = in; - args.inSz = inSz; - - return whal_Crypto_Process(dev, WHAL_CRYPTO_HMAC_SHA1, &args); -} - -static inline whal_Error whal_Crypto_HmacSha1_Finalize(whal_Crypto *dev, - const void *key, - size_t keySz, - void *digest, - size_t digestSz) -{ - whal_Crypto_HmacArgs args = {0}; - - args.key = key; - args.keySz = keySz; - args.digest = digest; - args.digestSz = digestSz; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_HMAC_SHA1, &args); -} -#endif /* WHAL_CFG_CRYPTO_HMAC_SHA1 */ +typedef struct { + whal_Error (*Oneshot)(whal_HmacSha1 *dev, + const void *key, size_t keySz, + const void *in, size_t inSz, + void *digest, size_t digestSz); + whal_Error (*Start)(whal_HmacSha1 *dev, + const void *key, size_t keySz); + whal_Error (*Process)(whal_HmacSha1 *dev, + const void *in, size_t inSz); + whal_Error (*Finalize)(whal_HmacSha1 *dev, + void *digest, size_t digestSz); +} whal_HmacSha1Driver; + +struct whal_HmacSha1 { + whal_Crypto *crypto; + const whal_HmacSha1Driver *driver; + void *state; +}; -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA224 +whal_Error whal_HmacSha1_Oneshot(whal_HmacSha1 *dev, + const void *key, size_t keySz, + const void *in, size_t inSz, + void *digest, size_t digestSz); +whal_Error whal_HmacSha1_Start(whal_HmacSha1 *dev, + const void *key, size_t keySz); +whal_Error whal_HmacSha1_Process(whal_HmacSha1 *dev, + const void *in, size_t inSz); +whal_Error whal_HmacSha1_Finalize(whal_HmacSha1 *dev, + void *digest, size_t digestSz); /* HMAC-SHA-224 */ -static inline whal_Error whal_Crypto_HmacSha224(whal_Crypto *dev, - whal_Crypto_HmacArgs *args) -{ - whal_Error err; - - err = whal_Crypto_StartOp(dev, WHAL_CRYPTO_HMAC_SHA224, args); - if (err) - return err; - - err = whal_Crypto_Process(dev, WHAL_CRYPTO_HMAC_SHA224, args); - if (err) - return err; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_HMAC_SHA224, args); -} - -static inline whal_Error whal_Crypto_HmacSha224_Start(whal_Crypto *dev, - const void *key, - size_t keySz) -{ - whal_Crypto_HmacArgs args = {0}; - - args.key = key; - args.keySz = keySz; - - return whal_Crypto_StartOp(dev, WHAL_CRYPTO_HMAC_SHA224, &args); -} - -static inline whal_Error whal_Crypto_HmacSha224_Update(whal_Crypto *dev, - const void *in, - size_t inSz) -{ - whal_Crypto_HmacArgs args = {0}; +typedef struct whal_HmacSha224 whal_HmacSha224; - args.in = in; - args.inSz = inSz; - - return whal_Crypto_Process(dev, WHAL_CRYPTO_HMAC_SHA224, &args); -} - -static inline whal_Error whal_Crypto_HmacSha224_Finalize(whal_Crypto *dev, - const void *key, - size_t keySz, - void *digest, - size_t digestSz) -{ - whal_Crypto_HmacArgs args = {0}; - - args.key = key; - args.keySz = keySz; - args.digest = digest; - args.digestSz = digestSz; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_HMAC_SHA224, &args); -} -#endif /* WHAL_CFG_CRYPTO_HMAC_SHA224 */ +typedef struct { + whal_Error (*Oneshot)(whal_HmacSha224 *dev, + const void *key, size_t keySz, + const void *in, size_t inSz, + void *digest, size_t digestSz); + whal_Error (*Start)(whal_HmacSha224 *dev, + const void *key, size_t keySz); + whal_Error (*Process)(whal_HmacSha224 *dev, + const void *in, size_t inSz); + whal_Error (*Finalize)(whal_HmacSha224 *dev, + void *digest, size_t digestSz); +} whal_HmacSha224Driver; + +struct whal_HmacSha224 { + whal_Crypto *crypto; + const whal_HmacSha224Driver *driver; + void *state; +}; -#ifdef WHAL_CFG_CRYPTO_HMAC_SHA256 +whal_Error whal_HmacSha224_Oneshot(whal_HmacSha224 *dev, + const void *key, size_t keySz, + const void *in, size_t inSz, + void *digest, size_t digestSz); +whal_Error whal_HmacSha224_Start(whal_HmacSha224 *dev, + const void *key, size_t keySz); +whal_Error whal_HmacSha224_Process(whal_HmacSha224 *dev, + const void *in, size_t inSz); +whal_Error whal_HmacSha224_Finalize(whal_HmacSha224 *dev, + void *digest, size_t digestSz); /* HMAC-SHA-256 */ -static inline whal_Error whal_Crypto_HmacSha256(whal_Crypto *dev, - whal_Crypto_HmacArgs *args) -{ - whal_Error err; - - err = whal_Crypto_StartOp(dev, WHAL_CRYPTO_HMAC_SHA256, args); - if (err) - return err; - - err = whal_Crypto_Process(dev, WHAL_CRYPTO_HMAC_SHA256, args); - if (err) - return err; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_HMAC_SHA256, args); -} - -static inline whal_Error whal_Crypto_HmacSha256_Start(whal_Crypto *dev, - const void *key, - size_t keySz) -{ - whal_Crypto_HmacArgs args = {0}; +typedef struct whal_HmacSha256 whal_HmacSha256; - args.key = key; - args.keySz = keySz; - - return whal_Crypto_StartOp(dev, WHAL_CRYPTO_HMAC_SHA256, &args); -} - -static inline whal_Error whal_Crypto_HmacSha256_Update(whal_Crypto *dev, - const void *in, - size_t inSz) -{ - whal_Crypto_HmacArgs args = {0}; - - args.in = in; - args.inSz = inSz; - - return whal_Crypto_Process(dev, WHAL_CRYPTO_HMAC_SHA256, &args); -} - -static inline whal_Error whal_Crypto_HmacSha256_Finalize(whal_Crypto *dev, - const void *key, - size_t keySz, - void *digest, - size_t digestSz) -{ - whal_Crypto_HmacArgs args = {0}; - - args.key = key; - args.keySz = keySz; - args.digest = digest; - args.digestSz = digestSz; - - return whal_Crypto_EndOp(dev, WHAL_CRYPTO_HMAC_SHA256, &args); -} +typedef struct { + whal_Error (*Oneshot)(whal_HmacSha256 *dev, + const void *key, size_t keySz, + const void *in, size_t inSz, + void *digest, size_t digestSz); + whal_Error (*Start)(whal_HmacSha256 *dev, + const void *key, size_t keySz); + whal_Error (*Process)(whal_HmacSha256 *dev, + const void *in, size_t inSz); + whal_Error (*Finalize)(whal_HmacSha256 *dev, + void *digest, size_t digestSz); +} whal_HmacSha256Driver; + +struct whal_HmacSha256 { + whal_Crypto *crypto; + const whal_HmacSha256Driver *driver; + void *state; +}; -#endif /* WHAL_CFG_CRYPTO_HMAC_SHA256 */ +whal_Error whal_HmacSha256_Oneshot(whal_HmacSha256 *dev, + const void *key, size_t keySz, + const void *in, size_t inSz, + void *digest, size_t digestSz); +whal_Error whal_HmacSha256_Start(whal_HmacSha256 *dev, + const void *key, size_t keySz); +whal_Error whal_HmacSha256_Process(whal_HmacSha256 *dev, + const void *in, size_t inSz); +whal_Error whal_HmacSha256_Finalize(whal_HmacSha256 *dev, + void *digest, size_t digestSz); #endif /* WHAL_CRYPTO_H */ diff --git a/wolfHAL/crypto/stm32n6_cryp.h b/wolfHAL/crypto/stm32n6_cryp.h index b579b3d..79f15da 100644 --- a/wolfHAL/crypto/stm32n6_cryp.h +++ b/wolfHAL/crypto/stm32n6_cryp.h @@ -1,7 +1,6 @@ #ifndef WHAL_STM32N6_CRYP_H #define WHAL_STM32N6_CRYP_H -#include #include #include @@ -10,9 +9,8 @@ * @brief STM32N6 CRYP (cryptographic processor) driver. * * The CRYP peripheral on the STM32N6 supports AES-128/192/256 in ECB, CBC, - * CTR, GCM, GMAC, and CCM chaining modes. It uses banked key registers - * (K0LR/K0RR..K3LR/K3RR) and a four-word FIFO interface (DINR/DOUTR) — a - * different programming model from the SAES peripheral. + * CTR, GCM, GMAC, and CCM chaining modes. Each algorithm is exposed through + * a per-algorithm vtable with Oneshot/Start/Process/Finalize operations. */ /** @@ -20,81 +18,409 @@ */ typedef struct { whal_Timeout *timeout; - - /* Driver-internal state, not initialized by user. */ - uint8_t ccmCtr0[16]; } whal_Stm32n6_Cryp_Cfg; -#ifndef WHAL_CFG_STM32N6_CRYP_DIRECT_API_MAPPING +/* ---- Streaming state ---- */ + +/** + * @brief AES-GCM streaming state (aadSz/dataSz for final-phase GHASH). + */ +typedef struct { + size_t aadSz; + size_t dataSz; +} whal_Stm32n6_AesGcm_State; + +/** + * @brief AES-CCM streaming state. + * + * @c ccmCtr0 is computed from the nonce in Start and replayed by Finalize for + * the tag's final-phase counter. @c aadSz / @c dataSz feed the final-phase + * length encoding. + */ +typedef struct { + size_t aadSz; + size_t dataSz; + uint8_t ccmCtr0[16]; +} whal_Stm32n6_AesCcm_State; + +/* ---- Direct API mapping ---- */ + +#ifdef WHAL_CFG_STM32N6_CRYP_INIT_DIRECT_API_MAPPING +#define whal_Stm32n6_Cryp_Init whal_Crypto_Init +#define whal_Stm32n6_Cryp_Deinit whal_Crypto_Deinit +#endif + +#ifdef WHAL_CFG_STM32N6_CRYP_ECB_DIRECT_API_MAPPING +#define whal_Stm32n6_CrypAesEcb_Oneshot whal_AesEcb_Oneshot +#define whal_Stm32n6_CrypAesEcb_Start whal_AesEcb_Start +#define whal_Stm32n6_CrypAesEcb_Process whal_AesEcb_Process +#endif + +#ifdef WHAL_CFG_STM32N6_CRYP_CBC_DIRECT_API_MAPPING +#define whal_Stm32n6_CrypAesCbc_Oneshot whal_AesCbc_Oneshot +#define whal_Stm32n6_CrypAesCbc_Start whal_AesCbc_Start +#define whal_Stm32n6_CrypAesCbc_Process whal_AesCbc_Process +#endif + +#ifdef WHAL_CFG_STM32N6_CRYP_CTR_DIRECT_API_MAPPING +#define whal_Stm32n6_CrypAesCtr_Oneshot whal_AesCtr_Oneshot +#define whal_Stm32n6_CrypAesCtr_Start whal_AesCtr_Start +#define whal_Stm32n6_CrypAesCtr_Process whal_AesCtr_Process +#endif + +#ifdef WHAL_CFG_STM32N6_CRYP_GCM_DIRECT_API_MAPPING +#define whal_Stm32n6_CrypAesGcm_Oneshot whal_AesGcm_Oneshot +#define whal_Stm32n6_CrypAesGcm_Start whal_AesGcm_Start +#define whal_Stm32n6_CrypAesGcm_Process whal_AesGcm_Process +#define whal_Stm32n6_CrypAesGcm_Finalize whal_AesGcm_Finalize +#endif + +#ifdef WHAL_CFG_STM32N6_CRYP_GMAC_DIRECT_API_MAPPING +#define whal_Stm32n6_CrypAesGmac_Oneshot whal_AesGmac_Oneshot +#endif + +#ifdef WHAL_CFG_STM32N6_CRYP_CCM_DIRECT_API_MAPPING +#define whal_Stm32n6_CrypAesCcm_Oneshot whal_AesCcm_Oneshot +#define whal_Stm32n6_CrypAesCcm_Start whal_AesCcm_Start +#define whal_Stm32n6_CrypAesCcm_Process whal_AesCcm_Process +#define whal_Stm32n6_CrypAesCcm_Finalize whal_AesCcm_Finalize +#endif + +/* ---- Init / Deinit ---- */ + +/** + * @brief Initialize the STM32N6 CRYP peripheral. + * + * @param dev Crypto device instance. + */ +whal_Error whal_Stm32n6_Cryp_Init(whal_Crypto *dev); + +/** + * @brief Deinitialize the STM32N6 CRYP peripheral. + * + * @param dev Crypto device instance. + */ +whal_Error whal_Stm32n6_Cryp_Deinit(whal_Crypto *dev); + +/* ---- AES-ECB ---- */ + +/** + * @brief AES-ECB one-shot encrypt or decrypt. + * + * @param dev AES-ECB device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16, 24, or 32). + * @param in Input data (multiple of 16 bytes). + * @param out Output buffer. + * @param sz Data size in bytes. + */ +whal_Error whal_Stm32n6_CrypAesEcb_Oneshot(whal_AesEcb *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *in, void *out, + size_t sz); + +/** + * @brief Start an AES-ECB streaming session (load key). + * + * @param dev AES-ECB device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16, 24, or 32). + */ +whal_Error whal_Stm32n6_CrypAesEcb_Start(whal_AesEcb *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz); + +/** + * @brief Process data through an active AES-ECB session. + * + * @param dev AES-ECB device instance. + * @param in Input data (multiple of 16 bytes). + * @param out Output buffer. + * @param sz Data size in bytes. + */ +whal_Error whal_Stm32n6_CrypAesEcb_Process(whal_AesEcb *dev, + const void *in, void *out, + size_t sz); + +/* ---- AES-CBC ---- */ + +/** + * @brief AES-CBC one-shot encrypt or decrypt. + * + * @param dev AES-CBC device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16, 24, or 32). + * @param iv Initialization vector (16 bytes). + * @param in Input data (multiple of 16 bytes). + * @param out Output buffer. + * @param sz Data size in bytes. + */ +whal_Error whal_Stm32n6_CrypAesCbc_Oneshot(whal_AesCbc *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, + const void *in, void *out, + size_t sz); + +/** + * @brief Start an AES-CBC streaming session (load key and IV). + * + * @param dev AES-CBC device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16, 24, or 32). + * @param iv Initialization vector (16 bytes). + */ +whal_Error whal_Stm32n6_CrypAesCbc_Start(whal_AesCbc *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv); + /** - * @brief Driver instance for the STM32N6 CRYP peripheral. + * @brief Process data through an active AES-CBC session. + * + * @param dev AES-CBC device instance. + * @param in Input data (multiple of 16 bytes). + * @param out Output buffer. + * @param sz Data size in bytes. + */ +whal_Error whal_Stm32n6_CrypAesCbc_Process(whal_AesCbc *dev, + const void *in, void *out, + size_t sz); + +/* ---- AES-CTR ---- */ + +/** + * @brief AES-CTR one-shot encrypt or decrypt. + * + * @param dev AES-CTR device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16, 24, or 32). + * @param iv Initial counter block (16 bytes). + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. + */ +whal_Error whal_Stm32n6_CrypAesCtr_Oneshot(whal_AesCtr *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, + const void *in, void *out, + size_t sz); + +/** + * @brief Start an AES-CTR streaming session (load key and counter). + * + * @param dev AES-CTR device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16, 24, or 32). + * @param iv Initial counter block (16 bytes). */ -extern const whal_CryptoDriver whal_Stm32n6_Cryp_Driver; +whal_Error whal_Stm32n6_CrypAesCtr_Start(whal_AesCtr *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv); /** - * @brief Initialize the CRYP peripheral. + * @brief Process data through an active AES-CTR session. * - * @param cryptoDev Crypto device instance. + * @param dev AES-CTR device instance. + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. + */ +whal_Error whal_Stm32n6_CrypAesCtr_Process(whal_AesCtr *dev, + const void *in, void *out, + size_t sz); + +/* ---- AES-GCM ---- */ + +/** + * @brief AES-GCM one-shot authenticated encrypt or decrypt. * - * @retval WHAL_SUCCESS Initialization completed. - * @retval WHAL_EINVAL Invalid arguments. + * @param dev AES-GCM device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16, 24, or 32). + * @param iv Initialization vector. + * @param ivSz IV size in bytes (must be 12). + * @param aad Additional authenticated data. + * @param aadSz AAD size in bytes. + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. + * @param tag Authentication tag output. + * @param tagSz Tag size in bytes (up to 16). */ -whal_Error whal_Stm32n6_Cryp_Init(whal_Crypto *cryptoDev); +whal_Error whal_Stm32n6_CrypAesGcm_Oneshot(whal_AesGcm *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz, + const void *in, void *out, + size_t sz, + void *tag, size_t tagSz); /** - * @brief Deinitialize the CRYP peripheral. + * @brief Start an AES-GCM streaming session (init + header phases). * - * @param cryptoDev Crypto device instance. + * @param dev AES-GCM device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16, 24, or 32). + * @param iv Initialization vector. + * @param ivSz IV size in bytes (must be 12). + * @param aad Additional authenticated data. + * @param aadSz AAD size in bytes. + */ +whal_Error whal_Stm32n6_CrypAesGcm_Start(whal_AesGcm *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz); + +/** + * @brief Process payload data through an active AES-GCM session. * - * @retval WHAL_SUCCESS Deinit completed. - * @retval WHAL_EINVAL Invalid arguments. + * @param dev AES-GCM device instance. + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. */ -whal_Error whal_Stm32n6_Cryp_Deinit(whal_Crypto *cryptoDev); +whal_Error whal_Stm32n6_CrypAesGcm_Process(whal_AesGcm *dev, + const void *in, void *out, + size_t sz); /** - * @brief Start an AES operation: configure CR, load key/IV, process AAD. + * @brief Finalize an AES-GCM session and produce the authentication tag. * - * @param cryptoDev Crypto device instance. - * @param opId Operation identifier (e.g. WHAL_CRYPTO_AES_GCM). - * @param opArgs Pointer to the algorithm-specific arguments struct. + * @param dev AES-GCM device instance. + * @param tag Authentication tag output. + * @param tagSz Tag size in bytes (up to 16). + */ +whal_Error whal_Stm32n6_CrypAesGcm_Finalize(whal_AesGcm *dev, + void *tag, size_t tagSz); + +/* ---- AES-GMAC ---- */ + +/** + * @brief AES-GMAC one-shot authentication (no payload). * - * @retval WHAL_SUCCESS Operation started. - * @retval WHAL_EINVAL Invalid arguments. - * @retval WHAL_ENOTSUP Unsupported opId or parameter. - * @retval WHAL_EHARDWARE Hardware error during setup. + * @param dev AES-GMAC device instance. + * @param key Key buffer. + * @param keySz Key size in bytes (16, 24, or 32). + * @param iv Initialization vector. + * @param ivSz IV size in bytes (must be 12). + * @param aad Authenticated data. + * @param aadSz Data size in bytes. + * @param tag Authentication tag output. + * @param tagSz Tag size in bytes (up to 16). */ -whal_Error whal_Stm32n6_Cryp_StartOp(whal_Crypto *cryptoDev, size_t opId, - void *opArgs); +whal_Error whal_Stm32n6_CrypAesGmac_Oneshot(whal_AesGmac *dev, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz, + void *tag, size_t tagSz); + +/* ---- AES-CCM ---- */ /** - * @brief Process payload data through an active AES operation. + * @brief AES-CCM one-shot authenticated encrypt or decrypt. * - * @param cryptoDev Crypto device instance. - * @param opId Operation identifier. - * @param opArgs Pointer to the algorithm-specific arguments struct. + * @param dev AES-CCM device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16, 24, or 32). + * @param nonce Nonce buffer. + * @param nonceSz Nonce size in bytes (7-13). + * @param aad Additional authenticated data. + * @param aadSz AAD size in bytes. + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. + * @param tag Authentication tag output. + * @param tagSz Tag size in bytes (4, 6, 8, 10, 12, 14, or 16). + */ +whal_Error whal_Stm32n6_CrypAesCcm_Oneshot(whal_AesCcm *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *nonce, size_t nonceSz, + const void *aad, size_t aadSz, + const void *in, void *out, + size_t sz, + void *tag, size_t tagSz); + +/** + * @brief Start an AES-CCM streaming session (init + header phases). * - * @retval WHAL_SUCCESS Data processed. - * @retval WHAL_EINVAL Invalid arguments. - * @retval WHAL_ENOTSUP Unsupported opId. - * @retval WHAL_EHARDWARE Hardware error during processing. + * @param dev AES-CCM device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16, 24, or 32). + * @param nonce Nonce buffer. + * @param nonceSz Nonce size in bytes (7-13). + * @param aad Additional authenticated data. + * @param aadSz AAD size in bytes. + * @param tagSz Tag size (needed for B0 block construction). + * @param sz Total payload size (needed for B0 block construction). */ -whal_Error whal_Stm32n6_Cryp_Process(whal_Crypto *cryptoDev, size_t opId, - void *opArgs); +whal_Error whal_Stm32n6_CrypAesCcm_Start(whal_AesCcm *dev, + whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *nonce, size_t nonceSz, + const void *aad, size_t aadSz, + size_t tagSz, size_t sz); /** - * @brief End an AES operation: finalize, read tag, release hardware. + * @brief Process payload data through an active AES-CCM session. * - * @param cryptoDev Crypto device instance. - * @param opId Operation identifier. - * @param opArgs Pointer to the algorithm-specific arguments struct. + * @param dev AES-CCM device instance. + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. + */ +whal_Error whal_Stm32n6_CrypAesCcm_Process(whal_AesCcm *dev, + const void *in, void *out, + size_t sz); + +/** + * @brief Finalize an AES-CCM session and produce the authentication tag. * - * @retval WHAL_SUCCESS Operation finalized. - * @retval WHAL_EINVAL Invalid arguments. - * @retval WHAL_ENOTSUP Unsupported opId. - * @retval WHAL_EHARDWARE Hardware error during finalization. + * @param dev AES-CCM device instance. + * @param tag Authentication tag output. + * @param tagSz Tag size in bytes. */ -whal_Error whal_Stm32n6_Cryp_EndOp(whal_Crypto *cryptoDev, size_t opId, - void *opArgs); -#endif /* !WHAL_CFG_STM32N6_CRYP_DIRECT_API_MAPPING */ +whal_Error whal_Stm32n6_CrypAesCcm_Finalize(whal_AesCcm *dev, + void *tag, size_t tagSz); + +/* ---- Vtable externs ---- */ + +#ifndef WHAL_CFG_STM32N6_CRYP_INIT_DIRECT_API_MAPPING +extern const whal_CryptoDriver whal_Stm32n6_Cryp_CryptoDriver; +#endif +#ifndef WHAL_CFG_STM32N6_CRYP_ECB_DIRECT_API_MAPPING +extern const whal_AesEcbDriver whal_Stm32n6_Cryp_EcbDriver; +#endif +#ifndef WHAL_CFG_STM32N6_CRYP_CBC_DIRECT_API_MAPPING +extern const whal_AesCbcDriver whal_Stm32n6_Cryp_CbcDriver; +#endif +#ifndef WHAL_CFG_STM32N6_CRYP_CTR_DIRECT_API_MAPPING +extern const whal_AesCtrDriver whal_Stm32n6_Cryp_CtrDriver; +#endif +#ifndef WHAL_CFG_STM32N6_CRYP_GCM_DIRECT_API_MAPPING +extern const whal_AesGcmDriver whal_Stm32n6_Cryp_GcmDriver; +#endif +#ifndef WHAL_CFG_STM32N6_CRYP_GMAC_DIRECT_API_MAPPING +extern const whal_AesGmacDriver whal_Stm32n6_Cryp_GmacDriver; +#endif +#ifndef WHAL_CFG_STM32N6_CRYP_CCM_DIRECT_API_MAPPING +extern const whal_AesCcmDriver whal_Stm32n6_Cryp_CcmDriver; +#endif #endif /* WHAL_STM32N6_CRYP_H */ diff --git a/wolfHAL/crypto/stm32n6_hash.h b/wolfHAL/crypto/stm32n6_hash.h index 7c864ec..4f4dc05 100644 --- a/wolfHAL/crypto/stm32n6_hash.h +++ b/wolfHAL/crypto/stm32n6_hash.h @@ -14,13 +14,17 @@ typedef whal_Stm32wba_Hash_Cfg whal_Stm32n6_Hash_Cfg; -#ifndef WHAL_CFG_STM32N6_HASH_DIRECT_API_MAPPING -#define whal_Stm32n6_Hash_Driver whal_Stm32wba_Hash_Driver -#define whal_Stm32n6_Hash_Init whal_Stm32wba_Hash_Init -#define whal_Stm32n6_Hash_Deinit whal_Stm32wba_Hash_Deinit -#define whal_Stm32n6_Hash_StartOp whal_Stm32wba_Hash_StartOp -#define whal_Stm32n6_Hash_Process whal_Stm32wba_Hash_Process -#define whal_Stm32n6_Hash_EndOp whal_Stm32wba_Hash_EndOp -#endif /* !WHAL_CFG_STM32N6_HASH_DIRECT_API_MAPPING */ +typedef whal_Stm32wba_HmacSha1_State whal_Stm32n6_HmacSha1_State; +typedef whal_Stm32wba_HmacSha224_State whal_Stm32n6_HmacSha224_State; +typedef whal_Stm32wba_HmacSha256_State whal_Stm32n6_HmacSha256_State; + +#define whal_Stm32n6_Hash_CryptoDriver whal_Stm32wba_Hash_CryptoDriver + +#define whal_Stm32n6_Hash_Sha1Driver whal_Stm32wba_Hash_Sha1Driver +#define whal_Stm32n6_Hash_Sha224Driver whal_Stm32wba_Hash_Sha224Driver +#define whal_Stm32n6_Hash_Sha256Driver whal_Stm32wba_Hash_Sha256Driver +#define whal_Stm32n6_Hash_HmacSha1Driver whal_Stm32wba_Hash_HmacSha1Driver +#define whal_Stm32n6_Hash_HmacSha224Driver whal_Stm32wba_Hash_HmacSha224Driver +#define whal_Stm32n6_Hash_HmacSha256Driver whal_Stm32wba_Hash_HmacSha256Driver #endif /* WHAL_STM32N6_HASH_H */ diff --git a/wolfHAL/crypto/stm32wb_aes.h b/wolfHAL/crypto/stm32wb_aes.h index ff54779..91ca548 100644 --- a/wolfHAL/crypto/stm32wb_aes.h +++ b/wolfHAL/crypto/stm32wb_aes.h @@ -1,96 +1,401 @@ #ifndef WHAL_STM32WB_AES_H #define WHAL_STM32WB_AES_H -#include #include #include -/* +/** * @file stm32wb_aes.h * @brief STM32WB AES hardware accelerator driver. * * The STM32WB AES1 peripheral supports 128/256-bit keys in ECB, CBC, - * CTR, GCM, GMAC, and CCM modes. This driver exposes those modes through the - * generic whal_Crypto interface using the StartOp/Process/EndOp pattern. + * CTR, GCM, GMAC, and CCM modes. Each algorithm is exposed through + * a per-algorithm vtable with Oneshot/Start/Process/Finalize operations. */ -/* +/** * @brief AES device configuration. */ typedef struct { whal_Timeout *timeout; } whal_Stm32wb_Aes_Cfg; -#ifndef WHAL_CFG_STM32WB_AES_DIRECT_API_MAPPING -/* - * @brief Driver instance for STM32WB AES peripheral. +/* ---- Streaming state ---- */ + +/** + * @brief AES-GCM streaming state (aadSz/dataSz for final-phase GHASH). + */ +typedef struct { + size_t aadSz; + size_t dataSz; +} whal_Stm32wb_AesGcm_State; + +/** + * @brief AES-CCM streaming state (aadSz/dataSz for final-phase tag). */ -extern const whal_CryptoDriver whal_Stm32wb_Aes_Driver; +typedef struct { + size_t aadSz; + size_t dataSz; +} whal_Stm32wb_AesCcm_State; + +/* ---- Direct API mapping ---- */ + +#ifdef WHAL_CFG_STM32WB_AES_INIT_DIRECT_API_MAPPING +#define whal_Stm32wb_Aes_Init whal_Crypto_Init +#define whal_Stm32wb_Aes_Deinit whal_Crypto_Deinit +#endif + +#ifdef WHAL_CFG_STM32WB_AES_ECB_DIRECT_API_MAPPING +#define whal_Stm32wb_AesEcb_Oneshot whal_AesEcb_Oneshot +#define whal_Stm32wb_AesEcb_Start whal_AesEcb_Start +#define whal_Stm32wb_AesEcb_Process whal_AesEcb_Process +#endif -/* +#ifdef WHAL_CFG_STM32WB_AES_CBC_DIRECT_API_MAPPING +#define whal_Stm32wb_AesCbc_Oneshot whal_AesCbc_Oneshot +#define whal_Stm32wb_AesCbc_Start whal_AesCbc_Start +#define whal_Stm32wb_AesCbc_Process whal_AesCbc_Process +#endif + +#ifdef WHAL_CFG_STM32WB_AES_CTR_DIRECT_API_MAPPING +#define whal_Stm32wb_AesCtr_Oneshot whal_AesCtr_Oneshot +#define whal_Stm32wb_AesCtr_Start whal_AesCtr_Start +#define whal_Stm32wb_AesCtr_Process whal_AesCtr_Process +#endif + +#ifdef WHAL_CFG_STM32WB_AES_GCM_DIRECT_API_MAPPING +#define whal_Stm32wb_AesGcm_Oneshot whal_AesGcm_Oneshot +#define whal_Stm32wb_AesGcm_Start whal_AesGcm_Start +#define whal_Stm32wb_AesGcm_Process whal_AesGcm_Process +#define whal_Stm32wb_AesGcm_Finalize whal_AesGcm_Finalize +#endif + +#ifdef WHAL_CFG_STM32WB_AES_GMAC_DIRECT_API_MAPPING +#define whal_Stm32wb_AesGmac_Oneshot whal_AesGmac_Oneshot +#endif + +#ifdef WHAL_CFG_STM32WB_AES_CCM_DIRECT_API_MAPPING +#define whal_Stm32wb_AesCcm_Oneshot whal_AesCcm_Oneshot +#define whal_Stm32wb_AesCcm_Start whal_AesCcm_Start +#define whal_Stm32wb_AesCcm_Process whal_AesCcm_Process +#define whal_Stm32wb_AesCcm_Finalize whal_AesCcm_Finalize +#endif + +/* ---- Init / Deinit ---- */ + +/** * @brief Initialize the STM32WB AES peripheral. * - * @param cryptoDev Cipher device instance. - * - * @retval WHAL_SUCCESS Initialization completed. - * @retval WHAL_EINVAL Invalid arguments. + * @param dev Crypto device instance. */ -whal_Error whal_Stm32wb_Aes_Init(whal_Crypto *cryptoDev); +whal_Error whal_Stm32wb_Aes_Init(whal_Crypto *dev); -/* +/** * @brief Deinitialize the STM32WB AES peripheral. * - * @param cryptoDev Cipher device instance. + * @param dev Crypto device instance. + */ +whal_Error whal_Stm32wb_Aes_Deinit(whal_Crypto *dev); + +/* ---- AES-ECB ---- */ + +/** + * @brief AES-ECB one-shot encrypt or decrypt. + * + * @param dev AES-ECB device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16 or 32). + * @param in Input data (multiple of 16 bytes). + * @param out Output buffer. + * @param sz Data size in bytes. + */ +whal_Error whal_Stm32wb_AesEcb_Oneshot(whal_AesEcb *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *in, void *out, size_t sz); + +/** + * @brief Start an AES-ECB streaming session (load key). + * + * @param dev AES-ECB device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16 or 32). + */ +whal_Error whal_Stm32wb_AesEcb_Start(whal_AesEcb *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz); + +/** + * @brief Process data through an active AES-ECB session. + * + * @param dev AES-ECB device instance. + * @param in Input data (multiple of 16 bytes). + * @param out Output buffer. + * @param sz Data size in bytes. + */ +whal_Error whal_Stm32wb_AesEcb_Process(whal_AesEcb *dev, + const void *in, void *out, size_t sz); + +/* ---- AES-CBC ---- */ + +/** + * @brief AES-CBC one-shot encrypt or decrypt. + * + * @param dev AES-CBC device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16 or 32). + * @param iv Initialization vector (16 bytes). + * @param in Input data (multiple of 16 bytes). + * @param out Output buffer. + * @param sz Data size in bytes. + */ +whal_Error whal_Stm32wb_AesCbc_Oneshot(whal_AesCbc *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, + const void *in, void *out, size_t sz); + +/** + * @brief Start an AES-CBC streaming session (load key and IV). + * + * @param dev AES-CBC device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16 or 32). + * @param iv Initialization vector (16 bytes). + */ +whal_Error whal_Stm32wb_AesCbc_Start(whal_AesCbc *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv); + +/** + * @brief Process data through an active AES-CBC session. + * + * @param dev AES-CBC device instance. + * @param in Input data (multiple of 16 bytes). + * @param out Output buffer. + * @param sz Data size in bytes. + */ +whal_Error whal_Stm32wb_AesCbc_Process(whal_AesCbc *dev, + const void *in, void *out, size_t sz); + +/* ---- AES-CTR ---- */ + +/** + * @brief AES-CTR one-shot encrypt or decrypt. + * + * @param dev AES-CTR device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16 or 32). + * @param iv Initial counter block (16 bytes). + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. + */ +whal_Error whal_Stm32wb_AesCtr_Oneshot(whal_AesCtr *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, + const void *in, void *out, size_t sz); + +/** + * @brief Start an AES-CTR streaming session (load key and counter). + * + * @param dev AES-CTR device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16 or 32). + * @param iv Initial counter block (16 bytes). + */ +whal_Error whal_Stm32wb_AesCtr_Start(whal_AesCtr *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv); + +/** + * @brief Process data through an active AES-CTR session. + * + * @param dev AES-CTR device instance. + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. + */ +whal_Error whal_Stm32wb_AesCtr_Process(whal_AesCtr *dev, + const void *in, void *out, size_t sz); + +/* ---- AES-GCM ---- */ + +/** + * @brief AES-GCM one-shot authenticated encrypt or decrypt. * - * @retval WHAL_SUCCESS Deinit completed. - * @retval WHAL_EINVAL Invalid arguments. + * @param dev AES-GCM device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16 or 32). + * @param iv Initialization vector. + * @param ivSz IV size in bytes (typically 12). + * @param aad Additional authenticated data. + * @param aadSz AAD size in bytes. + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. + * @param tag Authentication tag output. + * @param tagSz Tag size in bytes (up to 16). */ -whal_Error whal_Stm32wb_Aes_Deinit(whal_Crypto *cryptoDev); +whal_Error whal_Stm32wb_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz, + const void *in, void *out, size_t sz, + void *tag, size_t tagSz); -/* - * @brief Start an AES cipher operation. +/** + * @brief Start an AES-GCM streaming session (init + header phases). * - * @param cryptoDev Cipher device instance. - * @param opId Cipher algorithm identifier. - * @param opArgs Pointer to the algorithm-specific arguments struct. + * @param dev AES-GCM device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16 or 32). + * @param iv Initialization vector. + * @param ivSz IV size in bytes (typically 12). + * @param aad Additional authenticated data. + * @param aadSz AAD size in bytes. + */ +whal_Error whal_Stm32wb_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz); + +/** + * @brief Process payload data through an active AES-GCM session. + * + * @param dev AES-GCM device instance. + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. + */ +whal_Error whal_Stm32wb_AesGcm_Process(whal_AesGcm *dev, + const void *in, void *out, size_t sz); + +/** + * @brief Finalize an AES-GCM session and produce the authentication tag. + * + * @param dev AES-GCM device instance. + * @param tag Authentication tag output. + * @param tagSz Tag size in bytes (up to 16). + */ +whal_Error whal_Stm32wb_AesGcm_Finalize(whal_AesGcm *dev, + void *tag, size_t tagSz); + +/* ---- AES-GMAC ---- */ + +/** + * @brief AES-GMAC one-shot authentication (no payload). * - * @retval WHAL_SUCCESS Operation started. - * @retval WHAL_EINVAL Invalid arguments. - * @retval WHAL_ENOTSUP Unsupported opId or parameter (e.g. key size). - * @retval WHAL_EHARDWARE Hardware error during setup. + * @param dev AES-GMAC device instance. + * @param key Key buffer. + * @param keySz Key size in bytes (16 or 32). + * @param iv Initialization vector. + * @param ivSz IV size in bytes (typically 12). + * @param aad Authenticated data. + * @param aadSz Data size in bytes. + * @param tag Authentication tag output. + * @param tagSz Tag size in bytes (up to 16). */ -whal_Error whal_Stm32wb_Aes_StartOp(whal_Crypto *cryptoDev, size_t opId, - void *opArgs); +whal_Error whal_Stm32wb_AesGmac_Oneshot(whal_AesGmac *dev, + const void *key, size_t keySz, + const void *iv, size_t ivSz, + const void *aad, size_t aadSz, + void *tag, size_t tagSz); + +/* ---- AES-CCM ---- */ -/* - * @brief Process data through an active AES operation. +/** + * @brief AES-CCM one-shot authenticated encrypt or decrypt. * - * @param cryptoDev Cipher device instance. - * @param opId Cipher algorithm identifier. - * @param opArgs Pointer to the algorithm-specific arguments struct. + * @param dev AES-CCM device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16 or 32). + * @param nonce Nonce buffer. + * @param nonceSz Nonce size in bytes (7-13). + * @param aad Additional authenticated data. + * @param aadSz AAD size in bytes. + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. + * @param tag Authentication tag output. + * @param tagSz Tag size in bytes (4, 6, 8, 10, 12, 14, or 16). + */ +whal_Error whal_Stm32wb_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *nonce, size_t nonceSz, + const void *aad, size_t aadSz, + const void *in, void *out, size_t sz, + void *tag, size_t tagSz); + +/** + * @brief Start an AES-CCM streaming session (init + header phases). * - * @retval WHAL_SUCCESS Data processed. - * @retval WHAL_EINVAL Invalid arguments. - * @retval WHAL_ENOTSUP Unsupported opId. - * @retval WHAL_EHARDWARE Hardware error during processing. + * @param dev AES-CCM device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes (16 or 32). + * @param nonce Nonce buffer. + * @param nonceSz Nonce size in bytes (7-13). + * @param aad Additional authenticated data. + * @param aadSz AAD size in bytes. + * @param tagSz Tag size (needed for B0 block construction). + * @param sz Total payload size (needed for B0 block construction). */ -whal_Error whal_Stm32wb_Aes_Process(whal_Crypto *cryptoDev, size_t opId, - void *opArgs); +whal_Error whal_Stm32wb_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, + const void *key, size_t keySz, + const void *nonce, size_t nonceSz, + const void *aad, size_t aadSz, + size_t tagSz, size_t sz); -/* - * @brief End an AES cipher operation. +/** + * @brief Process payload data through an active AES-CCM session. * - * @param cryptoDev Cipher device instance. - * @param opId Cipher algorithm identifier. - * @param opArgs Pointer to the algorithm-specific arguments struct. + * @param dev AES-CCM device instance. + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. + */ +whal_Error whal_Stm32wb_AesCcm_Process(whal_AesCcm *dev, + const void *in, void *out, size_t sz); + +/** + * @brief Finalize an AES-CCM session and produce the authentication tag. * - * @retval WHAL_SUCCESS Operation finalized. - * @retval WHAL_EINVAL Invalid arguments. - * @retval WHAL_ENOTSUP Unsupported opId. - * @retval WHAL_EHARDWARE Hardware error during finalization. + * @param dev AES-CCM device instance. + * @param tag Authentication tag output. + * @param tagSz Tag size in bytes. */ -whal_Error whal_Stm32wb_Aes_EndOp(whal_Crypto *cryptoDev, size_t opId, - void *opArgs); -#endif /* !WHAL_CFG_STM32WB_AES_DIRECT_API_MAPPING */ +whal_Error whal_Stm32wb_AesCcm_Finalize(whal_AesCcm *dev, + void *tag, size_t tagSz); + +/* ---- Vtable externs ---- */ + +#ifndef WHAL_CFG_STM32WB_AES_INIT_DIRECT_API_MAPPING +extern const whal_CryptoDriver whal_Stm32wb_Aes_CryptoDriver; +#endif +#ifndef WHAL_CFG_STM32WB_AES_ECB_DIRECT_API_MAPPING +extern const whal_AesEcbDriver whal_Stm32wb_Aes_EcbDriver; +#endif +#ifndef WHAL_CFG_STM32WB_AES_CBC_DIRECT_API_MAPPING +extern const whal_AesCbcDriver whal_Stm32wb_Aes_CbcDriver; +#endif +#ifndef WHAL_CFG_STM32WB_AES_CTR_DIRECT_API_MAPPING +extern const whal_AesCtrDriver whal_Stm32wb_Aes_CtrDriver; +#endif +#ifndef WHAL_CFG_STM32WB_AES_GCM_DIRECT_API_MAPPING +extern const whal_AesGcmDriver whal_Stm32wb_Aes_GcmDriver; +#endif +#ifndef WHAL_CFG_STM32WB_AES_GMAC_DIRECT_API_MAPPING +extern const whal_AesGmacDriver whal_Stm32wb_Aes_GmacDriver; +#endif +#ifndef WHAL_CFG_STM32WB_AES_CCM_DIRECT_API_MAPPING +extern const whal_AesCcmDriver whal_Stm32wb_Aes_CcmDriver; +#endif #endif /* WHAL_STM32WB_AES_H */ diff --git a/wolfHAL/crypto/stm32wba_aes.h b/wolfHAL/crypto/stm32wba_aes.h index 75b7bf6..a0a78aa 100644 --- a/wolfHAL/crypto/stm32wba_aes.h +++ b/wolfHAL/crypto/stm32wba_aes.h @@ -1,7 +1,7 @@ #ifndef WHAL_STM32WBA_AES_H #define WHAL_STM32WBA_AES_H -/* +/** * @file stm32wba_aes.h * @brief STM32WBA AES driver (alias for STM32WB AES). * @@ -14,13 +14,17 @@ typedef whal_Stm32wb_Aes_Cfg whal_Stm32wba_Aes_Cfg; -#ifndef WHAL_CFG_STM32WBA_AES_DIRECT_API_MAPPING -#define whal_Stm32wba_Aes_Driver whal_Stm32wb_Aes_Driver -#define whal_Stm32wba_Aes_Init whal_Stm32wb_Aes_Init -#define whal_Stm32wba_Aes_Deinit whal_Stm32wb_Aes_Deinit -#define whal_Stm32wba_Aes_StartOp whal_Stm32wb_Aes_StartOp -#define whal_Stm32wba_Aes_Process whal_Stm32wb_Aes_Process -#define whal_Stm32wba_Aes_EndOp whal_Stm32wb_Aes_EndOp -#endif /* !WHAL_CFG_STM32WBA_AES_DIRECT_API_MAPPING */ +typedef whal_Stm32wb_AesGcm_State whal_Stm32wba_AesGcm_State; +typedef whal_Stm32wb_AesCcm_State whal_Stm32wba_AesCcm_State; + +#define whal_Stm32wba_Aes_CryptoDriver whal_Stm32wb_Aes_CryptoDriver + +#define whal_Stm32wba_Aes_EcbDriver whal_Stm32wb_Aes_EcbDriver +#define whal_Stm32wba_Aes_CbcDriver whal_Stm32wb_Aes_CbcDriver +#define whal_Stm32wba_Aes_CtrDriver whal_Stm32wb_Aes_CtrDriver +#define whal_Stm32wba_Aes_GcmDriver whal_Stm32wb_Aes_GcmDriver +#define whal_Stm32wba_Aes_GmacDriver whal_Stm32wb_Aes_GmacDriver +#define whal_Stm32wba_Aes_CcmDriver whal_Stm32wb_Aes_CcmDriver + #endif /* WHAL_STM32WBA_AES_H */ diff --git a/wolfHAL/crypto/stm32wba_hash.h b/wolfHAL/crypto/stm32wba_hash.h index 3d437b6..e47a54d 100644 --- a/wolfHAL/crypto/stm32wba_hash.h +++ b/wolfHAL/crypto/stm32wba_hash.h @@ -1,93 +1,395 @@ #ifndef WHAL_STM32WBA_HASH_H #define WHAL_STM32WBA_HASH_H -#include #include #include -/* +/** * @file stm32wba_hash.h * @brief STM32WBA HASH hardware accelerator driver. * * The STM32WBA HASH peripheral supports SHA-1, SHA-224, SHA-256 and HMAC - * variants. This driver exposes those algorithms through the generic - * whal_Crypto interface using the StartOp/Process/EndOp pattern. + * variants. Each algorithm is exposed through a per-algorithm vtable with + * Oneshot/Start/Process/Finalize operations. */ -/* +/** * @brief HASH device configuration. */ typedef struct { whal_Timeout *timeout; } whal_Stm32wba_Hash_Cfg; -#ifndef WHAL_CFG_STM32WBA_HASH_DIRECT_API_MAPPING -/* - * @brief Driver instance for STM32WBA HASH peripheral. +/* ---- Streaming state ---- */ + +/** + * @brief HMAC streaming state (key pointer retained for outer-key phase). */ -extern const whal_CryptoDriver whal_Stm32wba_Hash_Driver; +typedef struct { + const void *key; + size_t keySz; +} whal_Stm32wba_HmacSha1_State; + +typedef whal_Stm32wba_HmacSha1_State whal_Stm32wba_HmacSha224_State; +typedef whal_Stm32wba_HmacSha1_State whal_Stm32wba_HmacSha256_State; + +/* ---- Direct API mapping ---- */ + +#ifdef WHAL_CFG_STM32WBA_HASH_INIT_DIRECT_API_MAPPING +#define whal_Stm32wba_Hash_Init whal_Crypto_Init +#define whal_Stm32wba_Hash_Deinit whal_Crypto_Deinit +#endif + +#ifdef WHAL_CFG_STM32WBA_HASH_SHA1_DIRECT_API_MAPPING +#define whal_Stm32wba_Sha1_Oneshot whal_Sha1_Oneshot +#define whal_Stm32wba_Sha1_Start whal_Sha1_Start +#define whal_Stm32wba_Sha1_Process whal_Sha1_Process +#define whal_Stm32wba_Sha1_Finalize whal_Sha1_Finalize +#endif + +#ifdef WHAL_CFG_STM32WBA_HASH_SHA224_DIRECT_API_MAPPING +#define whal_Stm32wba_Sha224_Oneshot whal_Sha224_Oneshot +#define whal_Stm32wba_Sha224_Start whal_Sha224_Start +#define whal_Stm32wba_Sha224_Process whal_Sha224_Process +#define whal_Stm32wba_Sha224_Finalize whal_Sha224_Finalize +#endif + +#ifdef WHAL_CFG_STM32WBA_HASH_SHA256_DIRECT_API_MAPPING +#define whal_Stm32wba_Sha256_Oneshot whal_Sha256_Oneshot +#define whal_Stm32wba_Sha256_Start whal_Sha256_Start +#define whal_Stm32wba_Sha256_Process whal_Sha256_Process +#define whal_Stm32wba_Sha256_Finalize whal_Sha256_Finalize +#endif + +#ifdef WHAL_CFG_STM32WBA_HASH_HMAC_SHA1_DIRECT_API_MAPPING +#define whal_Stm32wba_HmacSha1_Oneshot whal_HmacSha1_Oneshot +#define whal_Stm32wba_HmacSha1_Start whal_HmacSha1_Start +#define whal_Stm32wba_HmacSha1_Process whal_HmacSha1_Process +#define whal_Stm32wba_HmacSha1_Finalize whal_HmacSha1_Finalize +#endif + +#ifdef WHAL_CFG_STM32WBA_HASH_HMAC_SHA224_DIRECT_API_MAPPING +#define whal_Stm32wba_HmacSha224_Oneshot whal_HmacSha224_Oneshot +#define whal_Stm32wba_HmacSha224_Start whal_HmacSha224_Start +#define whal_Stm32wba_HmacSha224_Process whal_HmacSha224_Process +#define whal_Stm32wba_HmacSha224_Finalize whal_HmacSha224_Finalize +#endif -/* +#ifdef WHAL_CFG_STM32WBA_HASH_HMAC_SHA256_DIRECT_API_MAPPING +#define whal_Stm32wba_HmacSha256_Oneshot whal_HmacSha256_Oneshot +#define whal_Stm32wba_HmacSha256_Start whal_HmacSha256_Start +#define whal_Stm32wba_HmacSha256_Process whal_HmacSha256_Process +#define whal_Stm32wba_HmacSha256_Finalize whal_HmacSha256_Finalize +#endif + +/* ---- Init / Deinit ---- */ + +/** * @brief Initialize the STM32WBA HASH peripheral. * - * @param cryptoDev Crypto device instance. - * - * @retval WHAL_SUCCESS Initialization completed. - * @retval WHAL_EINVAL Invalid arguments. + * @param dev Crypto device instance. */ -whal_Error whal_Stm32wba_Hash_Init(whal_Crypto *cryptoDev); +whal_Error whal_Stm32wba_Hash_Init(whal_Crypto *dev); -/* +/** * @brief Deinitialize the STM32WBA HASH peripheral. * - * @param cryptoDev Crypto device instance. + * @param dev Crypto device instance. + */ +whal_Error whal_Stm32wba_Hash_Deinit(whal_Crypto *dev); + +/* ---- SHA-1 ---- */ + +/** + * @brief SHA-1 one-shot hash. + * + * @param dev SHA-1 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + * @param digest Output digest buffer. + * @param digestSz Digest size in bytes (must be 20). + */ +whal_Error whal_Stm32wba_Sha1_Oneshot(whal_Sha1 *dev, + const void *in, size_t inSz, + void *digest, size_t digestSz); + +/** + * @brief Start a SHA-1 streaming session. + * + * @param dev SHA-1 device instance. + */ +whal_Error whal_Stm32wba_Sha1_Start(whal_Sha1 *dev); + +/** + * @brief Process data through an active SHA-1 session. + * + * @param dev SHA-1 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + */ +whal_Error whal_Stm32wba_Sha1_Process(whal_Sha1 *dev, + const void *in, size_t inSz); + +/** + * @brief Finalize a SHA-1 session and produce the digest. + * + * @param dev SHA-1 device instance. + * @param digest Output digest buffer. + * @param digestSz Digest size in bytes (must be 20). + */ +whal_Error whal_Stm32wba_Sha1_Finalize(whal_Sha1 *dev, + void *digest, size_t digestSz); + +/* ---- SHA-224 ---- */ + +/** + * @brief SHA-224 one-shot hash. + * + * @param dev SHA-224 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + * @param digest Output digest buffer. + * @param digestSz Digest size in bytes (must be 28). + */ +whal_Error whal_Stm32wba_Sha224_Oneshot(whal_Sha224 *dev, + const void *in, size_t inSz, + void *digest, size_t digestSz); + +/** + * @brief Start a SHA-224 streaming session. + * + * @param dev SHA-224 device instance. + */ +whal_Error whal_Stm32wba_Sha224_Start(whal_Sha224 *dev); + +/** + * @brief Process data through an active SHA-224 session. + * + * @param dev SHA-224 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + */ +whal_Error whal_Stm32wba_Sha224_Process(whal_Sha224 *dev, + const void *in, size_t inSz); + +/** + * @brief Finalize a SHA-224 session and produce the digest. + * + * @param dev SHA-224 device instance. + * @param digest Output digest buffer. + * @param digestSz Digest size in bytes (must be 28). + */ +whal_Error whal_Stm32wba_Sha224_Finalize(whal_Sha224 *dev, + void *digest, size_t digestSz); + +/* ---- SHA-256 ---- */ + +/** + * @brief SHA-256 one-shot hash. + * + * @param dev SHA-256 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + * @param digest Output digest buffer. + * @param digestSz Digest size in bytes (must be 32). + */ +whal_Error whal_Stm32wba_Sha256_Oneshot(whal_Sha256 *dev, + const void *in, size_t inSz, + void *digest, size_t digestSz); + +/** + * @brief Start a SHA-256 streaming session. + * + * @param dev SHA-256 device instance. + */ +whal_Error whal_Stm32wba_Sha256_Start(whal_Sha256 *dev); + +/** + * @brief Process data through an active SHA-256 session. + * + * @param dev SHA-256 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + */ +whal_Error whal_Stm32wba_Sha256_Process(whal_Sha256 *dev, + const void *in, size_t inSz); + +/** + * @brief Finalize a SHA-256 session and produce the digest. + * + * @param dev SHA-256 device instance. + * @param digest Output digest buffer. + * @param digestSz Digest size in bytes (must be 32). + */ +whal_Error whal_Stm32wba_Sha256_Finalize(whal_Sha256 *dev, + void *digest, size_t digestSz); + +/* ---- HMAC-SHA-1 ---- */ + +/** + * @brief HMAC-SHA-1 one-shot. + * + * @param dev HMAC-SHA-1 device instance. + * @param key Key buffer. + * @param keySz Key size in bytes. + * @param in Input data. + * @param inSz Input size in bytes. + * @param digest Output digest buffer. + * @param digestSz Digest size in bytes (must be 20). + */ +whal_Error whal_Stm32wba_HmacSha1_Oneshot(whal_HmacSha1 *dev, + const void *key, size_t keySz, + const void *in, size_t inSz, + void *digest, size_t digestSz); + +/** + * @brief Start an HMAC-SHA-1 streaming session. + * + * @param dev HMAC-SHA-1 device instance. + * @param key Key buffer. + * @param keySz Key size in bytes. + */ +whal_Error whal_Stm32wba_HmacSha1_Start(whal_HmacSha1 *dev, + const void *key, size_t keySz); + +/** + * @brief Process data through an active HMAC-SHA-1 session. + * + * @param dev HMAC-SHA-1 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + */ +whal_Error whal_Stm32wba_HmacSha1_Process(whal_HmacSha1 *dev, + const void *in, size_t inSz); + +/** + * @brief Finalize an HMAC-SHA-1 session and produce the digest. + * + * @param dev HMAC-SHA-1 device instance. + * @param digest Output digest buffer. + * @param digestSz Digest size in bytes (must be 20). + */ +whal_Error whal_Stm32wba_HmacSha1_Finalize(whal_HmacSha1 *dev, + void *digest, size_t digestSz); + +/* ---- HMAC-SHA-224 ---- */ + +/** + * @brief HMAC-SHA-224 one-shot. + * + * @param dev HMAC-SHA-224 device instance. + * @param key Key buffer. + * @param keySz Key size in bytes. + * @param in Input data. + * @param inSz Input size in bytes. + * @param digest Output digest buffer. + * @param digestSz Digest size in bytes (must be 28). + */ +whal_Error whal_Stm32wba_HmacSha224_Oneshot(whal_HmacSha224 *dev, + const void *key, size_t keySz, + const void *in, size_t inSz, + void *digest, size_t digestSz); + +/** + * @brief Start an HMAC-SHA-224 streaming session. * - * @retval WHAL_SUCCESS Deinit completed. - * @retval WHAL_EINVAL Invalid arguments. + * @param dev HMAC-SHA-224 device instance. + * @param key Key buffer. + * @param keySz Key size in bytes. */ -whal_Error whal_Stm32wba_Hash_Deinit(whal_Crypto *cryptoDev); +whal_Error whal_Stm32wba_HmacSha224_Start(whal_HmacSha224 *dev, + const void *key, size_t keySz); -/* - * @brief Start a hash/HMAC operation. +/** + * @brief Process data through an active HMAC-SHA-224 session. * - * @param cryptoDev Crypto device instance. - * @param opId Algorithm identifier (WHAL_CRYPTO_SHA* / WHAL_CRYPTO_HMAC_SHA*). - * @param opArgs Pointer to whal_Crypto_HashArgs or whal_Crypto_HmacArgs. + * @param dev HMAC-SHA-224 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + */ +whal_Error whal_Stm32wba_HmacSha224_Process(whal_HmacSha224 *dev, + const void *in, size_t inSz); + +/** + * @brief Finalize an HMAC-SHA-224 session and produce the digest. * - * @retval WHAL_SUCCESS Operation started. - * @retval WHAL_EINVAL Invalid arguments. - * @retval WHAL_EHARDWARE Hardware error during setup. + * @param dev HMAC-SHA-224 device instance. + * @param digest Output digest buffer. + * @param digestSz Digest size in bytes (must be 28). */ -whal_Error whal_Stm32wba_Hash_StartOp(whal_Crypto *cryptoDev, size_t opId, - void *opArgs); +whal_Error whal_Stm32wba_HmacSha224_Finalize(whal_HmacSha224 *dev, + void *digest, size_t digestSz); -/* - * @brief Feed data into an active hash/HMAC operation. +/* ---- HMAC-SHA-256 ---- */ + +/** + * @brief HMAC-SHA-256 one-shot. * - * @param cryptoDev Crypto device instance. - * @param opId Algorithm identifier. - * @param opArgs Pointer to whal_Crypto_HashArgs or whal_Crypto_HmacArgs. + * @param dev HMAC-SHA-256 device instance. + * @param key Key buffer. + * @param keySz Key size in bytes. + * @param in Input data. + * @param inSz Input size in bytes. + * @param digest Output digest buffer. + * @param digestSz Digest size in bytes (must be 32). + */ +whal_Error whal_Stm32wba_HmacSha256_Oneshot(whal_HmacSha256 *dev, + const void *key, size_t keySz, + const void *in, size_t inSz, + void *digest, size_t digestSz); + +/** + * @brief Start an HMAC-SHA-256 streaming session. * - * @retval WHAL_SUCCESS Data processed. - * @retval WHAL_EINVAL Invalid arguments. - * @retval WHAL_EHARDWARE Hardware error during processing. + * @param dev HMAC-SHA-256 device instance. + * @param key Key buffer. + * @param keySz Key size in bytes. */ -whal_Error whal_Stm32wba_Hash_Process(whal_Crypto *cryptoDev, size_t opId, - void *opArgs); +whal_Error whal_Stm32wba_HmacSha256_Start(whal_HmacSha256 *dev, + const void *key, size_t keySz); -/* - * @brief End a hash/HMAC operation and read the digest. +/** + * @brief Process data through an active HMAC-SHA-256 session. * - * @param cryptoDev Crypto device instance. - * @param opId Algorithm identifier. - * @param opArgs Pointer to whal_Crypto_HashArgs or whal_Crypto_HmacArgs. + * @param dev HMAC-SHA-256 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + */ +whal_Error whal_Stm32wba_HmacSha256_Process(whal_HmacSha256 *dev, + const void *in, size_t inSz); + +/** + * @brief Finalize an HMAC-SHA-256 session and produce the digest. * - * @retval WHAL_SUCCESS Operation finalized. - * @retval WHAL_EINVAL Invalid arguments. - * @retval WHAL_EHARDWARE Hardware error during finalization. + * @param dev HMAC-SHA-256 device instance. + * @param digest Output digest buffer. + * @param digestSz Digest size in bytes (must be 32). */ -whal_Error whal_Stm32wba_Hash_EndOp(whal_Crypto *cryptoDev, size_t opId, - void *opArgs); -#endif /* !WHAL_CFG_STM32WBA_HASH_DIRECT_API_MAPPING */ +whal_Error whal_Stm32wba_HmacSha256_Finalize(whal_HmacSha256 *dev, + void *digest, size_t digestSz); + +/* ---- Vtable externs ---- */ + +#ifndef WHAL_CFG_STM32WBA_HASH_INIT_DIRECT_API_MAPPING +extern const whal_CryptoDriver whal_Stm32wba_Hash_CryptoDriver; +#endif +#ifndef WHAL_CFG_STM32WBA_HASH_SHA1_DIRECT_API_MAPPING +extern const whal_Sha1Driver whal_Stm32wba_Hash_Sha1Driver; +#endif +#ifndef WHAL_CFG_STM32WBA_HASH_SHA224_DIRECT_API_MAPPING +extern const whal_Sha224Driver whal_Stm32wba_Hash_Sha224Driver; +#endif +#ifndef WHAL_CFG_STM32WBA_HASH_SHA256_DIRECT_API_MAPPING +extern const whal_Sha256Driver whal_Stm32wba_Hash_Sha256Driver; +#endif +#ifndef WHAL_CFG_STM32WBA_HASH_HMAC_SHA1_DIRECT_API_MAPPING +extern const whal_HmacSha1Driver whal_Stm32wba_Hash_HmacSha1Driver; +#endif +#ifndef WHAL_CFG_STM32WBA_HASH_HMAC_SHA224_DIRECT_API_MAPPING +extern const whal_HmacSha224Driver whal_Stm32wba_Hash_HmacSha224Driver; +#endif +#ifndef WHAL_CFG_STM32WBA_HASH_HMAC_SHA256_DIRECT_API_MAPPING +extern const whal_HmacSha256Driver whal_Stm32wba_Hash_HmacSha256Driver; +#endif #endif /* WHAL_STM32WBA_HASH_H */ diff --git a/wolfHAL/platform/st/stm32n657a0.h b/wolfHAL/platform/st/stm32n657a0.h index 42ce45c..1454c77 100644 --- a/wolfHAL/platform/st/stm32n657a0.h +++ b/wolfHAL/platform/st/stm32n657a0.h @@ -68,10 +68,8 @@ #define WHAL_STM32N657_RNG_DRIVER &whal_Stm32n6_Rng_Driver #define WHAL_STM32N657_CRYP_BASE 0x44020800 -#define WHAL_STM32N657_CRYP_DRIVER &whal_Stm32n6_Cryp_Driver #define WHAL_STM32N657_HASH_BASE 0x44020400 -#define WHAL_STM32N657_HASH_DRIVER &whal_Stm32n6_Hash_Driver #define WHAL_STM32N657_GPDMA1_BASE 0x40021000 #define WHAL_STM32N657_GPDMA1_DRIVER &whal_Stm32n6_Gpdma_Driver diff --git a/wolfHAL/platform/st/stm32wb55xx.h b/wolfHAL/platform/st/stm32wb55xx.h index a8debed..fa88733 100644 --- a/wolfHAL/platform/st/stm32wb55xx.h +++ b/wolfHAL/platform/st/stm32wb55xx.h @@ -39,7 +39,7 @@ #define WHAL_STM32WB55_RNG_DRIVER &whal_Stm32wb_Rng_Driver #define WHAL_STM32WB55_AES1_BASE 0x50060000 -#define WHAL_STM32WB55_AES1_DRIVER &whal_Stm32wb_Aes_Driver +#define WHAL_STM32WB55_AES1_DRIVER &whal_Stm32wb_Aes_CryptoDriver #define WHAL_STM32WB55_I2C1_BASE 0x40005400 #define WHAL_STM32WB55_I2C1_DRIVER &whal_Stm32wb_I2c_Driver diff --git a/wolfHAL/platform/st/stm32wba55cg.h b/wolfHAL/platform/st/stm32wba55cg.h index b7fcc67..d3b93f6 100644 --- a/wolfHAL/platform/st/stm32wba55cg.h +++ b/wolfHAL/platform/st/stm32wba55cg.h @@ -67,10 +67,8 @@ #define WHAL_STM32WBA55_GPDMA1_DRIVER &whal_Stm32wba_Gpdma_Driver #define WHAL_STM32WBA55_AES_BASE 0x420C0000 -#define WHAL_STM32WBA55_AES_DRIVER &whal_Stm32wba_Aes_Driver #define WHAL_STM32WBA55_HASH_BASE 0x420C0400 -#define WHAL_STM32WBA55_HASH_DRIVER &whal_Stm32wba_Hash_Driver #define WHAL_STM32WBA55_IWDG_BASE 0x40003000 #define WHAL_STM32WBA55_IWDG_DRIVER &whal_Stm32wba_Iwdg_Driver From 0e8c2731d5dbd2c195d64d2ea9ca941af98179da Mon Sep 17 00:00:00 2001 From: Alex Lanzano Date: Wed, 13 May 2026 18:04:57 -0400 Subject: [PATCH 6/7] [drivers, stm32wb, stm32h5] Introduce single instance drivers --- boards/peripheral/flash/spi_nor_w25q64.c | 2 +- boards/pic32cz_curiosity_ultra/board.c | 53 +---- boards/pic32cz_curiosity_ultra/board.h | 43 +++- boards/pic32cz_curiosity_ultra/board.mk | 4 +- boards/stm32c031_nucleo/board.c | 65 +------ boards/stm32c031_nucleo/board.h | 55 +++++- boards/stm32c031_nucleo/board.mk | 4 +- boards/stm32f091rc_nucleo/board.c | 79 +------- boards/stm32f091rc_nucleo/board.h | 70 ++++++- boards/stm32f091rc_nucleo/board.mk | 4 +- boards/stm32f302r8_nucleo/board.c | 79 +------- boards/stm32f302r8_nucleo/board.h | 70 ++++++- boards/stm32f302r8_nucleo/board.mk | 4 +- boards/stm32f411_blackpill/board.c | 65 +------ boards/stm32f411_blackpill/board.h | 55 +++++- boards/stm32f411_blackpill/board.mk | 4 +- boards/stm32h563zi_nucleo/board.c | 184 ++---------------- boards/stm32h563zi_nucleo/board.h | 139 ++++++++++++- boards/stm32h563zi_nucleo/board.mk | 4 +- boards/stm32l152re_nucleo/board.c | 79 +------- boards/stm32l152re_nucleo/board.h | 70 ++++++- boards/stm32l152re_nucleo/board.mk | 4 +- boards/stm32n657a0_nucleo/board.c | 195 ++----------------- boards/stm32n657a0_nucleo/board.h | 173 ++++++++++++++++- boards/stm32n657a0_nucleo/board.mk | 6 +- boards/stm32wb55xx_nucleo/board.c | 149 ++------------ boards/stm32wb55xx_nucleo/board.h | 161 ++++++++++++++- boards/stm32wb55xx_nucleo/board.mk | 11 +- boards/stm32wba55cg_nucleo/board.c | 98 ++-------- boards/stm32wba55cg_nucleo/board.h | 78 +++++++- boards/stm32wba55cg_nucleo/board.mk | 6 +- examples/blinky/main.c | 4 +- src/clock/stm32h5_rcc.c | 163 ---------------- src/clock/stm32wb_rcc.c | 167 ---------------- src/crypto/stm32wb_aes.c | 237 ++++++++++------------- src/dma/stm32wb_dma.c | 60 +++++- src/eth/stm32h5_eth.c | 139 ++++++------- src/eth_phy/lan8742a_eth_phy.c | 35 ++-- src/flash/stm32wb_flash.c | 58 ++---- src/gpio/stm32wb_gpio.c | 35 ++-- src/i2c/stm32wb_i2c.c | 67 ++++++- src/irq/cortex_m4_nvic.c | 25 +-- src/rng/stm32h5_rng.c | 30 ++- src/rng/stm32wb_rng.c | 22 +-- src/spi/stm32wb_spi.c | 69 ++++++- src/timer/systick.c | 43 ++-- src/uart/stm32wb_uart.c | 58 +++++- src/uart/stm32wb_uart_dma.c | 62 ++++-- src/watchdog/stm32wb_iwdg.c | 26 +-- src/watchdog/stm32wb_wwdg.c | 30 +-- wolfHAL/clock/stm32h5_rcc.h | 223 ++++++++++++++------- wolfHAL/clock/stm32wb_rcc.h | 236 +++++++++++++--------- wolfHAL/eth/stm32h5_eth.h | 3 - wolfHAL/gpio/stm32c0_gpio.h | 2 + wolfHAL/gpio/stm32f0_gpio.h | 2 + wolfHAL/gpio/stm32f3_gpio.h | 2 + wolfHAL/gpio/stm32f4_gpio.h | 2 + wolfHAL/gpio/stm32h5_gpio.h | 2 + wolfHAL/gpio/stm32l1_gpio.h | 2 + wolfHAL/gpio/stm32n6_gpio.h | 2 + wolfHAL/gpio/stm32wb_gpio.h | 4 +- wolfHAL/gpio/stm32wba_gpio.h | 2 + wolfHAL/uart/stm32c0_uart.h | 2 + wolfHAL/uart/stm32h5_uart.h | 2 + wolfHAL/uart/stm32n6_uart.h | 2 + wolfHAL/uart/stm32wba_uart.h | 2 + wolfHAL/wolfHAL.h | 6 + 67 files changed, 1914 insertions(+), 1925 deletions(-) delete mode 100644 src/clock/stm32h5_rcc.c delete mode 100644 src/clock/stm32wb_rcc.c diff --git a/boards/peripheral/flash/spi_nor_w25q64.c b/boards/peripheral/flash/spi_nor_w25q64.c index f77b3c2..db263d9 100644 --- a/boards/peripheral/flash/spi_nor_w25q64.c +++ b/boards/peripheral/flash/spi_nor_w25q64.c @@ -26,7 +26,7 @@ whal_Flash g_whalSpiNorW25q64 = { .cfg = &(whal_SpiNor_Cfg) { .spiDev = &g_whalSpi, .spiComCfg = &g_w25q64ComCfg, - .gpioDev = &g_whalGpio, + .gpioDev = &whal_Stm32wb_Gpio_Dev, .csPin = SPI_CS_PIN, .timeout = &g_whalTimeout, .pageSz = W25Q64_PAGE_SZ, diff --git a/boards/pic32cz_curiosity_ultra/board.c b/boards/pic32cz_curiosity_ultra/board.c index 645c95e..c943931 100644 --- a/boards/pic32cz_curiosity_ultra/board.c +++ b/boards/pic32cz_curiosity_ultra/board.c @@ -28,35 +28,6 @@ static const whal_Pic32cz_Clock_PeriphClk g_periphClks[] = { }; #define PERIPH_CLK_COUNT (sizeof(g_periphClks) / sizeof(g_periphClks[0])) -/* GPIO */ -whal_Gpio g_whalGpio = { - .base = WHAL_PIC32CZ_GPIO_BASE, - /* .driver: direct API mapping */ - - .cfg = &(whal_Pic32cz_Gpio_Cfg) { - .pinCfgCount = 3, - .pinCfg = (whal_Pic32cz_Gpio_PinCfg[]) { - { /* LED */ - .port = 1, - .pin = 21, - .dir = WHAL_PIC32CZ_DIR_OUTPUT, - .out = 0, - }, - { /* UART TX */ - .port = 2, - .pin = 21, - .pmuxEn = 1, - .pmux = WHAL_PIC32CZ_PMUX_SERCOM_ALT, - }, - { /* UART RX */ - .port = 2, - .pin = 22, - .pmuxEn = 1, - .pmux = WHAL_PIC32CZ_PMUX_SERCOM_ALT, - }, - }, - }, -}; /* UART */ whal_Uart g_whalUart = { @@ -70,18 +41,6 @@ whal_Uart g_whalUart = { }, }; -/* Timer */ -whal_Timer g_whalTimer = { - .base = WHAL_CORTEX_M7_SYSTICK_BASE, - .driver = WHAL_CORTEX_M7_SYSTICK_DRIVER, - - .cfg = &(whal_SysTick_Cfg) { - .cyclesPerTick = 300000000 / 1000, - .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, - .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, - }, -}; - /* Flash */ whal_Flash g_whalFlash = { .base = WHAL_PIC32CZ_FLASH_BASE, @@ -169,7 +128,7 @@ whal_Error Board_Init(void) return err; } - err = whal_Gpio_Init(&g_whalGpio); + err = whal_Gpio_Init(WHAL_SINGLETON); if (err) { return err; } @@ -184,12 +143,12 @@ whal_Error Board_Init(void) return err; } - err = whal_Timer_Init(&g_whalTimer); + err = whal_Timer_Init(WHAL_SINGLETON); if (err) { return err; } - err = whal_Timer_Start(&g_whalTimer); + err = whal_Timer_Start(WHAL_SINGLETON); if (err) { return err; } @@ -211,12 +170,12 @@ whal_Error Board_Deinit(void) return err; } - err = whal_Timer_Stop(&g_whalTimer); + err = whal_Timer_Stop(WHAL_SINGLETON); if (err) { return err; } - err = whal_Timer_Deinit(&g_whalTimer); + err = whal_Timer_Deinit(WHAL_SINGLETON); if (err) { return err; } @@ -231,7 +190,7 @@ whal_Error Board_Deinit(void) return err; } - err = whal_Gpio_Deinit(&g_whalGpio); + err = whal_Gpio_Deinit(WHAL_SINGLETON); if (err) { return err; } diff --git a/boards/pic32cz_curiosity_ultra/board.h b/boards/pic32cz_curiosity_ultra/board.h index 581a125..57bbaa6 100644 --- a/boards/pic32cz_curiosity_ultra/board.h +++ b/boards/pic32cz_curiosity_ultra/board.h @@ -4,10 +4,9 @@ #include #include #include +#include extern whal_Clock g_whalClock; -extern whal_Gpio g_whalGpio; -extern whal_Timer g_whalTimer; extern whal_Uart g_whalUart; extern whal_Flash g_whalFlash; @@ -17,6 +16,46 @@ extern volatile uint32_t g_tick; #define BOARD_FLASH_TEST_ADDR 0x0C000000 #define BOARD_FLASH_SECTOR_SZ 0x1000 +static const whal_Gpio whal_Pic32cz_Gpio_Dev = { + .base = WHAL_PIC32CZ_GPIO_BASE, + + .cfg = (void *)&(const whal_Pic32cz_Gpio_Cfg){ + .pinCfgCount = 3, + .pinCfg = (whal_Pic32cz_Gpio_PinCfg[]) { + { /* LED */ + .port = 1, + .pin = 21, + .dir = WHAL_PIC32CZ_DIR_OUTPUT, + .out = 0, + }, + { /* UART TX */ + .port = 2, + .pin = 21, + .pmuxEn = 1, + .pmux = WHAL_PIC32CZ_PMUX_SERCOM_ALT, + }, + { /* UART RX */ + .port = 2, + .pin = 22, + .pmuxEn = 1, + .pmux = WHAL_PIC32CZ_PMUX_SERCOM_ALT, + }, + }, + }, +}; + +/* SysTick singleton — referenced by systick.c directly. */ +static const whal_Timer whal_SysTick_Dev = { + .base = WHAL_CORTEX_M7_SYSTICK_BASE, + /* .driver: direct API mapping */ + + .cfg = (void *)&(const whal_SysTick_Cfg){ + .cyclesPerTick = 300000000 / 1000, + .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, + .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, + }, +}; + whal_Error Board_Init(void); whal_Error Board_Deinit(void); void Board_WaitMs(size_t ms); diff --git a/boards/pic32cz_curiosity_ultra/board.mk b/boards/pic32cz_curiosity_ultra/board.mk index b28b7b8..be9d216 100644 --- a/boards/pic32cz_curiosity_ultra/board.mk +++ b/boards/pic32cz_curiosity_ultra/board.mk @@ -12,7 +12,8 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -DPLATFORM_PIC32CZ -MMD -MP \ -DWHAL_CFG_PIC32CZ_GPIO_DIRECT_API_MAPPING \ -DWHAL_CFG_PIC32CZ_CLOCK_DIRECT_API_MAPPING \ - -DWHAL_CFG_PIC32CZ_UART_DIRECT_API_MAPPING + -DWHAL_CFG_PIC32CZ_UART_DIRECT_API_MAPPING \ + -DWHAL_CFG_SYSTICK_TIMER_DIRECT_API_MAPPING LDFLAGS = --omagic -static --gc-sections LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld @@ -22,7 +23,6 @@ INCLUDE += -I$(_BOARD_DIR) -I$(WHAL_DIR)/boards/peripheral BOARD_SOURCE = $(_BOARD_DIR)/ivt.c BOARD_SOURCE += $(_BOARD_DIR)/board.c BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*.c) -BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/timer.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/flash.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/rng.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/block.c) diff --git a/boards/stm32c031_nucleo/board.c b/boards/stm32c031_nucleo/board.c index 02fc763..64b2be9 100644 --- a/boards/stm32c031_nucleo/board.c +++ b/boards/stm32c031_nucleo/board.c @@ -44,59 +44,6 @@ static const whal_Stm32c0_Rcc_PeriphClk g_periphClks[] = { }; #define PERIPH_CLK_COUNT (sizeof(g_periphClks) / sizeof(g_periphClks[0])) -/* GPIO */ -whal_Gpio g_whalGpio = { - .base = WHAL_STM32C031_GPIO_BASE, - /* .driver: direct API mapping */ - - .cfg = &(whal_Stm32c0_Gpio_Cfg) { - .pinCfg = (whal_Stm32c0_Gpio_PinCfg[PIN_COUNT]) { - /* LD4 Green LED on PA5 */ - [LED_PIN] = WHAL_STM32C0_GPIO_PIN( - WHAL_STM32C0_GPIO_PORT_A, 5, WHAL_STM32C0_GPIO_MODE_OUT, - WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_LOW, - WHAL_STM32C0_GPIO_PULL_NONE, 0), - /* USART2 TX on PA2, AF1 (ST-Link VCP) */ - [UART_TX_PIN] = WHAL_STM32C0_GPIO_PIN( - WHAL_STM32C0_GPIO_PORT_A, 2, WHAL_STM32C0_GPIO_MODE_ALTFN, - WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_FAST, - WHAL_STM32C0_GPIO_PULL_UP, 1), - /* USART2 RX on PA3, AF1 (ST-Link VCP) */ - [UART_RX_PIN] = WHAL_STM32C0_GPIO_PIN( - WHAL_STM32C0_GPIO_PORT_A, 3, WHAL_STM32C0_GPIO_MODE_ALTFN, - WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_FAST, - WHAL_STM32C0_GPIO_PULL_UP, 1), - /* SPI1 SCK on PA1, AF0 */ - [SPI_SCK_PIN] = WHAL_STM32C0_GPIO_PIN( - WHAL_STM32C0_GPIO_PORT_A, 1, WHAL_STM32C0_GPIO_MODE_ALTFN, - WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_FAST, - WHAL_STM32C0_GPIO_PULL_NONE, 0), - /* SPI1 MISO on PA6, AF0 */ - [SPI_MISO_PIN] = WHAL_STM32C0_GPIO_PIN( - WHAL_STM32C0_GPIO_PORT_A, 6, WHAL_STM32C0_GPIO_MODE_ALTFN, - WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_FAST, - WHAL_STM32C0_GPIO_PULL_NONE, 0), - /* SPI1 MOSI on PA7, AF0 */ - [SPI_MOSI_PIN] = WHAL_STM32C0_GPIO_PIN( - WHAL_STM32C0_GPIO_PORT_A, 7, WHAL_STM32C0_GPIO_MODE_ALTFN, - WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_FAST, - WHAL_STM32C0_GPIO_PULL_NONE, 0), - }, - .pinCount = PIN_COUNT, - }, -}; - -/* Timer */ -whal_Timer g_whalTimer = { - .base = WHAL_CORTEX_M0PLUS_SYSTICK_BASE, - .driver = WHAL_CORTEX_M0PLUS_SYSTICK_DRIVER, - - .cfg = &(whal_SysTick_Cfg) { - .cyclesPerTick = 48000000 / 1000, /* 48 MHz / 1 kHz = 1 ms tick */ - .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, - .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, - }, -}; /* UART */ whal_Uart g_whalUart = { @@ -162,7 +109,7 @@ whal_Error Board_Init(void) return err; } - err = whal_Gpio_Init(&g_whalGpio); + err = whal_Gpio_Init(WHAL_SINGLETON); if (err) return err; @@ -174,11 +121,11 @@ whal_Error Board_Init(void) if (err) return err; - err = whal_Timer_Init(&g_whalTimer); + err = whal_Timer_Init(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Start(&g_whalTimer); + err = whal_Timer_Start(WHAL_SINGLETON); if (err) return err; @@ -197,11 +144,11 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Timer_Stop(&g_whalTimer); + err = whal_Timer_Stop(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Deinit(&g_whalTimer); + err = whal_Timer_Deinit(WHAL_SINGLETON); if (err) return err; @@ -213,7 +160,7 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Gpio_Deinit(&g_whalGpio); + err = whal_Gpio_Deinit(WHAL_SINGLETON); if (err) return err; diff --git a/boards/stm32c031_nucleo/board.h b/boards/stm32c031_nucleo/board.h index d504dc0..6b49cf8 100644 --- a/boards/stm32c031_nucleo/board.h +++ b/boards/stm32c031_nucleo/board.h @@ -4,10 +4,9 @@ #include #include #include +#include extern whal_Clock g_whalClock; -extern whal_Gpio g_whalGpio; -extern whal_Timer g_whalTimer; extern whal_Uart g_whalUart; extern whal_Spi g_whalSpi; extern whal_Flash g_whalFlash; @@ -32,6 +31,58 @@ enum { #define BOARD_FLASH_TEST_ADDR 0x08007800 #define BOARD_FLASH_SECTOR_SZ 0x800 +static const whal_Gpio whal_Stm32c0_Gpio_Dev = { + .base = WHAL_STM32C031_GPIO_BASE, + + .cfg = (void *)&(const whal_Stm32c0_Gpio_Cfg){ + .pinCfg = (const whal_Stm32c0_Gpio_PinCfg[PIN_COUNT]){ + /* LD4 Green LED on PA5 */ + [LED_PIN] = WHAL_STM32C0_GPIO_PIN( + WHAL_STM32C0_GPIO_PORT_A, 5, WHAL_STM32C0_GPIO_MODE_OUT, + WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_LOW, + WHAL_STM32C0_GPIO_PULL_NONE, 0), + /* USART2 TX on PA2, AF1 (ST-Link VCP) */ + [UART_TX_PIN] = WHAL_STM32C0_GPIO_PIN( + WHAL_STM32C0_GPIO_PORT_A, 2, WHAL_STM32C0_GPIO_MODE_ALTFN, + WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_FAST, + WHAL_STM32C0_GPIO_PULL_UP, 1), + /* USART2 RX on PA3, AF1 (ST-Link VCP) */ + [UART_RX_PIN] = WHAL_STM32C0_GPIO_PIN( + WHAL_STM32C0_GPIO_PORT_A, 3, WHAL_STM32C0_GPIO_MODE_ALTFN, + WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_FAST, + WHAL_STM32C0_GPIO_PULL_UP, 1), + /* SPI1 SCK on PA1, AF0 */ + [SPI_SCK_PIN] = WHAL_STM32C0_GPIO_PIN( + WHAL_STM32C0_GPIO_PORT_A, 1, WHAL_STM32C0_GPIO_MODE_ALTFN, + WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_FAST, + WHAL_STM32C0_GPIO_PULL_NONE, 0), + /* SPI1 MISO on PA6, AF0 */ + [SPI_MISO_PIN] = WHAL_STM32C0_GPIO_PIN( + WHAL_STM32C0_GPIO_PORT_A, 6, WHAL_STM32C0_GPIO_MODE_ALTFN, + WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_FAST, + WHAL_STM32C0_GPIO_PULL_NONE, 0), + /* SPI1 MOSI on PA7, AF0 */ + [SPI_MOSI_PIN] = WHAL_STM32C0_GPIO_PIN( + WHAL_STM32C0_GPIO_PORT_A, 7, WHAL_STM32C0_GPIO_MODE_ALTFN, + WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_FAST, + WHAL_STM32C0_GPIO_PULL_NONE, 0), + }, + .pinCount = PIN_COUNT, + }, +}; + +/* SysTick singleton — referenced by systick.c directly. */ +static const whal_Timer whal_SysTick_Dev = { + .base = WHAL_CORTEX_M0PLUS_SYSTICK_BASE, + /* .driver: direct API mapping */ + + .cfg = (void *)&(const whal_SysTick_Cfg){ + .cyclesPerTick = 48000000 / 1000, + .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, + .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, + }, +}; + whal_Error Board_Init(void); whal_Error Board_Deinit(void); void Board_WaitMs(size_t ms); diff --git a/boards/stm32c031_nucleo/board.mk b/boards/stm32c031_nucleo/board.mk index eccdc9b..3985377 100644 --- a/boards/stm32c031_nucleo/board.mk +++ b/boards/stm32c031_nucleo/board.mk @@ -13,7 +13,8 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -DWHAL_CFG_STM32C0_GPIO_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32C0_RCC_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32C0_UART_DIRECT_API_MAPPING \ - -DWHAL_CFG_STM32C0_SPI_DIRECT_API_MAPPING + -DWHAL_CFG_STM32C0_SPI_DIRECT_API_MAPPING \ + -DWHAL_CFG_SYSTICK_TIMER_DIRECT_API_MAPPING LDFLAGS = -mcpu=cortex-m0plus -mthumb -ffreestanding -nostartfiles \ -Wl,--omagic -Wl,--gc-sections -static @@ -24,7 +25,6 @@ INCLUDE += -I$(_BOARD_DIR) -I$(WHAL_DIR)/boards/peripheral BOARD_SOURCE = $(_BOARD_DIR)/ivt.c BOARD_SOURCE += $(_BOARD_DIR)/board.c BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*.c) -BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/timer.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/flash.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/rng.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/crypto.c) diff --git a/boards/stm32f091rc_nucleo/board.c b/boards/stm32f091rc_nucleo/board.c index 06d9dfd..12bd6cb 100644 --- a/boards/stm32f091rc_nucleo/board.c +++ b/boards/stm32f091rc_nucleo/board.c @@ -42,73 +42,6 @@ static const whal_Stm32f0_Rcc_PeriphClk g_periphClks[] = { }; #define PERIPH_CLK_COUNT (sizeof(g_periphClks) / sizeof(g_periphClks[0])) -/* GPIO */ -whal_Gpio g_whalGpio = { - .base = WHAL_STM32F091_GPIO_BASE, - - .cfg = &(whal_Stm32f0_Gpio_Cfg) { - .pinCfg = (whal_Stm32f0_Gpio_PinCfg[PIN_COUNT]) { - /* LD2 Green LED on PA5 */ - [LED_PIN] = WHAL_STM32F0_GPIO_PIN( - WHAL_STM32F0_GPIO_PORT_A, 5, WHAL_STM32F0_GPIO_MODE_OUT, - WHAL_STM32F0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F0_GPIO_SPEED_LOW, - WHAL_STM32F0_GPIO_PULL_NONE, 0), - /* USART2 TX on PA2, AF1 */ - [UART_TX_PIN] = WHAL_STM32F0_GPIO_PIN( - WHAL_STM32F0_GPIO_PORT_A, 2, WHAL_STM32F0_GPIO_MODE_ALTFN, - WHAL_STM32F0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F0_GPIO_SPEED_FAST, - WHAL_STM32F0_GPIO_PULL_UP, 1), - /* USART2 RX on PA3, AF1 */ - [UART_RX_PIN] = WHAL_STM32F0_GPIO_PIN( - WHAL_STM32F0_GPIO_PORT_A, 3, WHAL_STM32F0_GPIO_MODE_ALTFN, - WHAL_STM32F0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F0_GPIO_SPEED_FAST, - WHAL_STM32F0_GPIO_PULL_UP, 1), - /* SPI1 SCK on PB3, AF0 */ - [SPI_SCK_PIN] = WHAL_STM32F0_GPIO_PIN( - WHAL_STM32F0_GPIO_PORT_B, 3, WHAL_STM32F0_GPIO_MODE_ALTFN, - WHAL_STM32F0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F0_GPIO_SPEED_FAST, - WHAL_STM32F0_GPIO_PULL_NONE, 0), - /* SPI1 MISO on PB4, AF0 */ - [SPI_MISO_PIN] = WHAL_STM32F0_GPIO_PIN( - WHAL_STM32F0_GPIO_PORT_B, 4, WHAL_STM32F0_GPIO_MODE_ALTFN, - WHAL_STM32F0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F0_GPIO_SPEED_FAST, - WHAL_STM32F0_GPIO_PULL_NONE, 0), - /* SPI1 MOSI on PB5, AF0 */ - [SPI_MOSI_PIN] = WHAL_STM32F0_GPIO_PIN( - WHAL_STM32F0_GPIO_PORT_B, 5, WHAL_STM32F0_GPIO_MODE_ALTFN, - WHAL_STM32F0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F0_GPIO_SPEED_FAST, - WHAL_STM32F0_GPIO_PULL_NONE, 0), - /* SPI CS on PB6, output, push-pull */ - [SPI_CS_PIN] = WHAL_STM32F0_GPIO_PIN( - WHAL_STM32F0_GPIO_PORT_B, 6, WHAL_STM32F0_GPIO_MODE_OUT, - WHAL_STM32F0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F0_GPIO_SPEED_FAST, - WHAL_STM32F0_GPIO_PULL_UP, 0), - /* I2C1 SCL on PB8, AF1, open-drain */ - [I2C_SCL_PIN] = WHAL_STM32F0_GPIO_PIN( - WHAL_STM32F0_GPIO_PORT_B, 8, WHAL_STM32F0_GPIO_MODE_ALTFN, - WHAL_STM32F0_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32F0_GPIO_SPEED_FAST, - WHAL_STM32F0_GPIO_PULL_UP, 1), - /* I2C1 SDA on PB9, AF1, open-drain */ - [I2C_SDA_PIN] = WHAL_STM32F0_GPIO_PIN( - WHAL_STM32F0_GPIO_PORT_B, 9, WHAL_STM32F0_GPIO_MODE_ALTFN, - WHAL_STM32F0_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32F0_GPIO_SPEED_FAST, - WHAL_STM32F0_GPIO_PULL_UP, 1), - }, - .pinCount = PIN_COUNT, - }, -}; - -/* Timer — SysTick at 1 ms */ -whal_Timer g_whalTimer = { - .base = WHAL_CORTEX_M0_SYSTICK_BASE, - .driver = WHAL_CORTEX_M0_SYSTICK_DRIVER, - - .cfg = &(whal_SysTick_Cfg) { - .cyclesPerTick = 48000000 / 1000, - .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, - .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, - }, -}; /* UART — USART2 at 115200 baud */ whal_Uart g_whalUart = { @@ -204,7 +137,7 @@ whal_Error Board_Init(void) return err; } - err = whal_Gpio_Init(&g_whalGpio); + err = whal_Gpio_Init(WHAL_SINGLETON); if (err) return err; @@ -220,11 +153,11 @@ whal_Error Board_Init(void) if (err) return err; - err = whal_Timer_Init(&g_whalTimer); + err = whal_Timer_Init(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Start(&g_whalTimer); + err = whal_Timer_Start(WHAL_SINGLETON); if (err) return err; @@ -243,11 +176,11 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Timer_Stop(&g_whalTimer); + err = whal_Timer_Stop(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Deinit(&g_whalTimer); + err = whal_Timer_Deinit(WHAL_SINGLETON); if (err) return err; @@ -263,7 +196,7 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Gpio_Deinit(&g_whalGpio); + err = whal_Gpio_Deinit(WHAL_SINGLETON); if (err) return err; diff --git a/boards/stm32f091rc_nucleo/board.h b/boards/stm32f091rc_nucleo/board.h index 9cf108e..e31221f 100644 --- a/boards/stm32f091rc_nucleo/board.h +++ b/boards/stm32f091rc_nucleo/board.h @@ -4,10 +4,9 @@ #include #include #include +#include extern whal_Clock g_whalClock; -extern whal_Gpio g_whalGpio; -extern whal_Timer g_whalTimer; extern whal_Uart g_whalUart; extern whal_Spi g_whalSpi; extern whal_I2c g_whalI2c; @@ -37,6 +36,73 @@ enum { #define BOARD_FLASH_TEST_ADDR 0x0803F800 #define BOARD_FLASH_SECTOR_SZ 0x800 +static const whal_Gpio whal_Stm32f0_Gpio_Dev = { + .base = WHAL_STM32F091_GPIO_BASE, + + .cfg = (void *)&(const whal_Stm32f0_Gpio_Cfg){ + .pinCfg = (const whal_Stm32f0_Gpio_PinCfg[PIN_COUNT]){ + /* LD2 Green LED on PA5 */ + [LED_PIN] = WHAL_STM32F0_GPIO_PIN( + WHAL_STM32F0_GPIO_PORT_A, 5, WHAL_STM32F0_GPIO_MODE_OUT, + WHAL_STM32F0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F0_GPIO_SPEED_LOW, + WHAL_STM32F0_GPIO_PULL_NONE, 0), + /* USART2 TX on PA2, AF1 */ + [UART_TX_PIN] = WHAL_STM32F0_GPIO_PIN( + WHAL_STM32F0_GPIO_PORT_A, 2, WHAL_STM32F0_GPIO_MODE_ALTFN, + WHAL_STM32F0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F0_GPIO_SPEED_FAST, + WHAL_STM32F0_GPIO_PULL_UP, 1), + /* USART2 RX on PA3, AF1 */ + [UART_RX_PIN] = WHAL_STM32F0_GPIO_PIN( + WHAL_STM32F0_GPIO_PORT_A, 3, WHAL_STM32F0_GPIO_MODE_ALTFN, + WHAL_STM32F0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F0_GPIO_SPEED_FAST, + WHAL_STM32F0_GPIO_PULL_UP, 1), + /* SPI1 SCK on PB3, AF0 */ + [SPI_SCK_PIN] = WHAL_STM32F0_GPIO_PIN( + WHAL_STM32F0_GPIO_PORT_B, 3, WHAL_STM32F0_GPIO_MODE_ALTFN, + WHAL_STM32F0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F0_GPIO_SPEED_FAST, + WHAL_STM32F0_GPIO_PULL_NONE, 0), + /* SPI1 MISO on PB4, AF0 */ + [SPI_MISO_PIN] = WHAL_STM32F0_GPIO_PIN( + WHAL_STM32F0_GPIO_PORT_B, 4, WHAL_STM32F0_GPIO_MODE_ALTFN, + WHAL_STM32F0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F0_GPIO_SPEED_FAST, + WHAL_STM32F0_GPIO_PULL_NONE, 0), + /* SPI1 MOSI on PB5, AF0 */ + [SPI_MOSI_PIN] = WHAL_STM32F0_GPIO_PIN( + WHAL_STM32F0_GPIO_PORT_B, 5, WHAL_STM32F0_GPIO_MODE_ALTFN, + WHAL_STM32F0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F0_GPIO_SPEED_FAST, + WHAL_STM32F0_GPIO_PULL_NONE, 0), + /* SPI CS on PB6, output, push-pull */ + [SPI_CS_PIN] = WHAL_STM32F0_GPIO_PIN( + WHAL_STM32F0_GPIO_PORT_B, 6, WHAL_STM32F0_GPIO_MODE_OUT, + WHAL_STM32F0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F0_GPIO_SPEED_FAST, + WHAL_STM32F0_GPIO_PULL_UP, 0), + /* I2C1 SCL on PB8, AF1, open-drain */ + [I2C_SCL_PIN] = WHAL_STM32F0_GPIO_PIN( + WHAL_STM32F0_GPIO_PORT_B, 8, WHAL_STM32F0_GPIO_MODE_ALTFN, + WHAL_STM32F0_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32F0_GPIO_SPEED_FAST, + WHAL_STM32F0_GPIO_PULL_UP, 1), + /* I2C1 SDA on PB9, AF1, open-drain */ + [I2C_SDA_PIN] = WHAL_STM32F0_GPIO_PIN( + WHAL_STM32F0_GPIO_PORT_B, 9, WHAL_STM32F0_GPIO_MODE_ALTFN, + WHAL_STM32F0_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32F0_GPIO_SPEED_FAST, + WHAL_STM32F0_GPIO_PULL_UP, 1), + }, + .pinCount = PIN_COUNT, + }, +}; + +/* SysTick singleton — referenced by systick.c directly. */ +static const whal_Timer whal_SysTick_Dev = { + .base = WHAL_CORTEX_M0_SYSTICK_BASE, + /* .driver: direct API mapping */ + + .cfg = (void *)&(const whal_SysTick_Cfg){ + .cyclesPerTick = 48000000 / 1000, + .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, + .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, + }, +}; + whal_Error Board_Init(void); whal_Error Board_Deinit(void); void Board_WaitMs(size_t ms); diff --git a/boards/stm32f091rc_nucleo/board.mk b/boards/stm32f091rc_nucleo/board.mk index f8d972c..71b7d0d 100644 --- a/boards/stm32f091rc_nucleo/board.mk +++ b/boards/stm32f091rc_nucleo/board.mk @@ -15,7 +15,8 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -DWHAL_CFG_STM32F0_UART_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32F0_SPI_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32F0_I2C_DIRECT_API_MAPPING \ - $(if $(filter iwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_IWDG) + $(if $(filter iwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_IWDG) \ + -DWHAL_CFG_SYSTICK_TIMER_DIRECT_API_MAPPING LDFLAGS = -mcpu=cortex-m0 -mthumb -ffreestanding -nostartfiles \ -Wl,--omagic -Wl,--gc-sections -static @@ -26,7 +27,6 @@ INCLUDE += -I$(_BOARD_DIR) -I$(WHAL_DIR)/boards/peripheral BOARD_SOURCE = $(_BOARD_DIR)/ivt.c BOARD_SOURCE += $(_BOARD_DIR)/board.c BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*.c) -BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/timer.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/flash.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/rng.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/crypto.c) diff --git a/boards/stm32f302r8_nucleo/board.c b/boards/stm32f302r8_nucleo/board.c index 804aad6..072e46d 100644 --- a/boards/stm32f302r8_nucleo/board.c +++ b/boards/stm32f302r8_nucleo/board.c @@ -45,73 +45,6 @@ static const whal_Stm32f3_Rcc_PeriphClk g_periphClks[] = { }; #define PERIPH_CLK_COUNT (sizeof(g_periphClks) / sizeof(g_periphClks[0])) -/* GPIO */ -whal_Gpio g_whalGpio = { - .base = WHAL_STM32F302_GPIO_BASE, - - .cfg = &(whal_Stm32f3_Gpio_Cfg) { - .pinCfg = (whal_Stm32f3_Gpio_PinCfg[PIN_COUNT]) { - /* LD2 Green LED on PB13 (per UM1724 Figure 14, NUCLEO-F302R8) */ - [LED_PIN] = WHAL_STM32F3_GPIO_PIN( - WHAL_STM32F3_GPIO_PORT_B, 13, WHAL_STM32F3_GPIO_MODE_OUT, - WHAL_STM32F3_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F3_GPIO_SPEED_LOW, - WHAL_STM32F3_GPIO_PULL_NONE, 0), - /* USART2 TX on PA2, AF7 */ - [UART_TX_PIN] = WHAL_STM32F3_GPIO_PIN( - WHAL_STM32F3_GPIO_PORT_A, 2, WHAL_STM32F3_GPIO_MODE_ALTFN, - WHAL_STM32F3_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F3_GPIO_SPEED_FAST, - WHAL_STM32F3_GPIO_PULL_UP, 7), - /* USART2 RX on PA3, AF7 */ - [UART_RX_PIN] = WHAL_STM32F3_GPIO_PIN( - WHAL_STM32F3_GPIO_PORT_A, 3, WHAL_STM32F3_GPIO_MODE_ALTFN, - WHAL_STM32F3_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F3_GPIO_SPEED_FAST, - WHAL_STM32F3_GPIO_PULL_UP, 7), - /* SPI3 SCK on PB3, AF6 */ - [SPI_SCK_PIN] = WHAL_STM32F3_GPIO_PIN( - WHAL_STM32F3_GPIO_PORT_B, 3, WHAL_STM32F3_GPIO_MODE_ALTFN, - WHAL_STM32F3_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F3_GPIO_SPEED_FAST, - WHAL_STM32F3_GPIO_PULL_NONE, 6), - /* SPI3 MISO on PB4, AF6 */ - [SPI_MISO_PIN] = WHAL_STM32F3_GPIO_PIN( - WHAL_STM32F3_GPIO_PORT_B, 4, WHAL_STM32F3_GPIO_MODE_ALTFN, - WHAL_STM32F3_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F3_GPIO_SPEED_FAST, - WHAL_STM32F3_GPIO_PULL_NONE, 6), - /* SPI3 MOSI on PB5, AF6 */ - [SPI_MOSI_PIN] = WHAL_STM32F3_GPIO_PIN( - WHAL_STM32F3_GPIO_PORT_B, 5, WHAL_STM32F3_GPIO_MODE_ALTFN, - WHAL_STM32F3_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F3_GPIO_SPEED_FAST, - WHAL_STM32F3_GPIO_PULL_NONE, 6), - /* SPI CS on PB12, output, push-pull */ - [SPI_CS_PIN] = WHAL_STM32F3_GPIO_PIN( - WHAL_STM32F3_GPIO_PORT_B, 12, WHAL_STM32F3_GPIO_MODE_OUT, - WHAL_STM32F3_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F3_GPIO_SPEED_FAST, - WHAL_STM32F3_GPIO_PULL_UP, 0), - /* I2C1 SCL on PB8, AF4, open-drain */ - [I2C_SCL_PIN] = WHAL_STM32F3_GPIO_PIN( - WHAL_STM32F3_GPIO_PORT_B, 8, WHAL_STM32F3_GPIO_MODE_ALTFN, - WHAL_STM32F3_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32F3_GPIO_SPEED_FAST, - WHAL_STM32F3_GPIO_PULL_UP, 4), - /* I2C1 SDA on PB9, AF4, open-drain */ - [I2C_SDA_PIN] = WHAL_STM32F3_GPIO_PIN( - WHAL_STM32F3_GPIO_PORT_B, 9, WHAL_STM32F3_GPIO_MODE_ALTFN, - WHAL_STM32F3_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32F3_GPIO_SPEED_FAST, - WHAL_STM32F3_GPIO_PULL_UP, 4), - }, - .pinCount = PIN_COUNT, - }, -}; - -/* Timer — SysTick at 1 ms */ -whal_Timer g_whalTimer = { - .base = WHAL_CORTEX_M4_SYSTICK_BASE, - .driver = WHAL_CORTEX_M4_SYSTICK_DRIVER, - - .cfg = &(whal_SysTick_Cfg) { - .cyclesPerTick = 48000000 / 1000, - .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, - .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, - }, -}; /* UART — USART2 at 115200 baud */ whal_Uart g_whalUart = { @@ -220,7 +153,7 @@ whal_Error Board_Init(void) return err; } - err = whal_Gpio_Init(&g_whalGpio); + err = whal_Gpio_Init(WHAL_SINGLETON); if (err) return err; @@ -236,11 +169,11 @@ whal_Error Board_Init(void) if (err) return err; - err = whal_Timer_Init(&g_whalTimer); + err = whal_Timer_Init(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Start(&g_whalTimer); + err = whal_Timer_Start(WHAL_SINGLETON); if (err) return err; @@ -259,11 +192,11 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Timer_Stop(&g_whalTimer); + err = whal_Timer_Stop(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Deinit(&g_whalTimer); + err = whal_Timer_Deinit(WHAL_SINGLETON); if (err) return err; @@ -279,7 +212,7 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Gpio_Deinit(&g_whalGpio); + err = whal_Gpio_Deinit(WHAL_SINGLETON); if (err) return err; diff --git a/boards/stm32f302r8_nucleo/board.h b/boards/stm32f302r8_nucleo/board.h index 346ffb3..03c81e0 100644 --- a/boards/stm32f302r8_nucleo/board.h +++ b/boards/stm32f302r8_nucleo/board.h @@ -4,10 +4,9 @@ #include #include #include +#include extern whal_Clock g_whalClock; -extern whal_Gpio g_whalGpio; -extern whal_Timer g_whalTimer; extern whal_Uart g_whalUart; extern whal_Spi g_whalSpi; extern whal_I2c g_whalI2c; @@ -37,6 +36,73 @@ enum { #define BOARD_FLASH_TEST_ADDR 0x0800F800 #define BOARD_FLASH_SECTOR_SZ 0x800 +static const whal_Gpio whal_Stm32f3_Gpio_Dev = { + .base = WHAL_STM32F302_GPIO_BASE, + + .cfg = (void *)&(const whal_Stm32f3_Gpio_Cfg){ + .pinCfg = (const whal_Stm32f3_Gpio_PinCfg[PIN_COUNT]){ + /* LD2 Green LED on PB13 (per UM1724 Figure 14, NUCLEO-F302R8) */ + [LED_PIN] = WHAL_STM32F3_GPIO_PIN( + WHAL_STM32F3_GPIO_PORT_B, 13, WHAL_STM32F3_GPIO_MODE_OUT, + WHAL_STM32F3_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F3_GPIO_SPEED_LOW, + WHAL_STM32F3_GPIO_PULL_NONE, 0), + /* USART2 TX on PA2, AF7 */ + [UART_TX_PIN] = WHAL_STM32F3_GPIO_PIN( + WHAL_STM32F3_GPIO_PORT_A, 2, WHAL_STM32F3_GPIO_MODE_ALTFN, + WHAL_STM32F3_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F3_GPIO_SPEED_FAST, + WHAL_STM32F3_GPIO_PULL_UP, 7), + /* USART2 RX on PA3, AF7 */ + [UART_RX_PIN] = WHAL_STM32F3_GPIO_PIN( + WHAL_STM32F3_GPIO_PORT_A, 3, WHAL_STM32F3_GPIO_MODE_ALTFN, + WHAL_STM32F3_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F3_GPIO_SPEED_FAST, + WHAL_STM32F3_GPIO_PULL_UP, 7), + /* SPI3 SCK on PB3, AF6 */ + [SPI_SCK_PIN] = WHAL_STM32F3_GPIO_PIN( + WHAL_STM32F3_GPIO_PORT_B, 3, WHAL_STM32F3_GPIO_MODE_ALTFN, + WHAL_STM32F3_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F3_GPIO_SPEED_FAST, + WHAL_STM32F3_GPIO_PULL_NONE, 6), + /* SPI3 MISO on PB4, AF6 */ + [SPI_MISO_PIN] = WHAL_STM32F3_GPIO_PIN( + WHAL_STM32F3_GPIO_PORT_B, 4, WHAL_STM32F3_GPIO_MODE_ALTFN, + WHAL_STM32F3_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F3_GPIO_SPEED_FAST, + WHAL_STM32F3_GPIO_PULL_NONE, 6), + /* SPI3 MOSI on PB5, AF6 */ + [SPI_MOSI_PIN] = WHAL_STM32F3_GPIO_PIN( + WHAL_STM32F3_GPIO_PORT_B, 5, WHAL_STM32F3_GPIO_MODE_ALTFN, + WHAL_STM32F3_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F3_GPIO_SPEED_FAST, + WHAL_STM32F3_GPIO_PULL_NONE, 6), + /* SPI CS on PB12, output, push-pull */ + [SPI_CS_PIN] = WHAL_STM32F3_GPIO_PIN( + WHAL_STM32F3_GPIO_PORT_B, 12, WHAL_STM32F3_GPIO_MODE_OUT, + WHAL_STM32F3_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F3_GPIO_SPEED_FAST, + WHAL_STM32F3_GPIO_PULL_UP, 0), + /* I2C1 SCL on PB8, AF4, open-drain */ + [I2C_SCL_PIN] = WHAL_STM32F3_GPIO_PIN( + WHAL_STM32F3_GPIO_PORT_B, 8, WHAL_STM32F3_GPIO_MODE_ALTFN, + WHAL_STM32F3_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32F3_GPIO_SPEED_FAST, + WHAL_STM32F3_GPIO_PULL_UP, 4), + /* I2C1 SDA on PB9, AF4, open-drain */ + [I2C_SDA_PIN] = WHAL_STM32F3_GPIO_PIN( + WHAL_STM32F3_GPIO_PORT_B, 9, WHAL_STM32F3_GPIO_MODE_ALTFN, + WHAL_STM32F3_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32F3_GPIO_SPEED_FAST, + WHAL_STM32F3_GPIO_PULL_UP, 4), + }, + .pinCount = PIN_COUNT, + }, +}; + +/* SysTick singleton — referenced by systick.c directly. */ +static const whal_Timer whal_SysTick_Dev = { + .base = WHAL_CORTEX_M4_SYSTICK_BASE, + /* .driver: direct API mapping */ + + .cfg = (void *)&(const whal_SysTick_Cfg){ + .cyclesPerTick = 48000000 / 1000, + .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, + .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, + }, +}; + whal_Error Board_Init(void); whal_Error Board_Deinit(void); void Board_WaitMs(size_t ms); diff --git a/boards/stm32f302r8_nucleo/board.mk b/boards/stm32f302r8_nucleo/board.mk index 8736e48..d15fd57 100644 --- a/boards/stm32f302r8_nucleo/board.mk +++ b/boards/stm32f302r8_nucleo/board.mk @@ -17,7 +17,8 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -DWHAL_CFG_STM32F3_SPI_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32F3_I2C_DIRECT_API_MAPPING \ $(if $(filter iwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_IWDG) \ - $(if $(filter wwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_WWDG) + $(if $(filter wwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_WWDG) \ + -DWHAL_CFG_SYSTICK_TIMER_DIRECT_API_MAPPING LDFLAGS = -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 \ -ffreestanding -nostartfiles -Wl,--omagic -Wl,--gc-sections -static @@ -28,7 +29,6 @@ INCLUDE += -I$(_BOARD_DIR) -I$(WHAL_DIR)/boards/peripheral BOARD_SOURCE = $(_BOARD_DIR)/ivt.c BOARD_SOURCE += $(_BOARD_DIR)/board.c BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*.c) -BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/timer.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/flash.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/rng.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/crypto.c) diff --git a/boards/stm32f411_blackpill/board.c b/boards/stm32f411_blackpill/board.c index c7a4c81..49b8d4e 100644 --- a/boards/stm32f411_blackpill/board.c +++ b/boards/stm32f411_blackpill/board.c @@ -50,59 +50,6 @@ static const whal_Stm32f4_Rcc_PeriphClk g_periphClks[] = { }; #define PERIPH_CLK_COUNT (sizeof(g_periphClks) / sizeof(g_periphClks[0])) -/* GPIO */ -whal_Gpio g_whalGpio = { - .base = WHAL_STM32F411_GPIO_BASE, - /* .driver: direct API mapping */ - - .cfg = &(whal_Stm32f4_Gpio_Cfg) { - .pinCfg = (whal_Stm32f4_Gpio_PinCfg[PIN_COUNT]) { - /* LED on PC13 (active low) */ - [LED_PIN] = WHAL_STM32F4_GPIO_PIN( - WHAL_STM32F4_GPIO_PORT_C, 13, WHAL_STM32F4_GPIO_MODE_OUT, - WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_LOW, - WHAL_STM32F4_GPIO_PULL_NONE, 0), - /* USART2 TX on PA2 (AF7) */ - [UART_TX_PIN] = WHAL_STM32F4_GPIO_PIN( - WHAL_STM32F4_GPIO_PORT_A, 2, WHAL_STM32F4_GPIO_MODE_ALTFN, - WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_FAST, - WHAL_STM32F4_GPIO_PULL_UP, 7), - /* USART2 RX on PA3 (AF7) */ - [UART_RX_PIN] = WHAL_STM32F4_GPIO_PIN( - WHAL_STM32F4_GPIO_PORT_A, 3, WHAL_STM32F4_GPIO_MODE_ALTFN, - WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_FAST, - WHAL_STM32F4_GPIO_PULL_UP, 7), - /* SPI1 SCK on PA5 (AF5) */ - [SPI_SCK_PIN] = WHAL_STM32F4_GPIO_PIN( - WHAL_STM32F4_GPIO_PORT_A, 5, WHAL_STM32F4_GPIO_MODE_ALTFN, - WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_FAST, - WHAL_STM32F4_GPIO_PULL_NONE, 5), - /* SPI1 MISO on PA6 (AF5) */ - [SPI_MISO_PIN] = WHAL_STM32F4_GPIO_PIN( - WHAL_STM32F4_GPIO_PORT_A, 6, WHAL_STM32F4_GPIO_MODE_ALTFN, - WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_FAST, - WHAL_STM32F4_GPIO_PULL_NONE, 5), - /* SPI1 MOSI on PA7 (AF5) */ - [SPI_MOSI_PIN] = WHAL_STM32F4_GPIO_PIN( - WHAL_STM32F4_GPIO_PORT_A, 7, WHAL_STM32F4_GPIO_MODE_ALTFN, - WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_FAST, - WHAL_STM32F4_GPIO_PULL_NONE, 5), - }, - .pinCount = PIN_COUNT, - }, -}; - -/* Timer */ -whal_Timer g_whalTimer = { - .base = WHAL_CORTEX_M4_SYSTICK_BASE, - .driver = WHAL_CORTEX_M4_SYSTICK_DRIVER, - - .cfg = &(whal_SysTick_Cfg) { - .cyclesPerTick = 100000000 / 1000, /* 100 MHz / 1 kHz = 1 ms tick */ - .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, - .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, - }, -}; /* UART */ whal_Uart g_whalUart = { @@ -192,7 +139,7 @@ whal_Error Board_Init(void) return err; } - err = whal_Gpio_Init(&g_whalGpio); + err = whal_Gpio_Init(WHAL_SINGLETON); if (err) return err; @@ -204,11 +151,11 @@ whal_Error Board_Init(void) if (err) return err; - err = whal_Timer_Init(&g_whalTimer); + err = whal_Timer_Init(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Start(&g_whalTimer); + err = whal_Timer_Start(WHAL_SINGLETON); if (err) return err; @@ -227,11 +174,11 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Timer_Stop(&g_whalTimer); + err = whal_Timer_Stop(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Deinit(&g_whalTimer); + err = whal_Timer_Deinit(WHAL_SINGLETON); if (err) return err; @@ -243,7 +190,7 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Gpio_Deinit(&g_whalGpio); + err = whal_Gpio_Deinit(WHAL_SINGLETON); if (err) return err; diff --git a/boards/stm32f411_blackpill/board.h b/boards/stm32f411_blackpill/board.h index 98f2da3..f5fad4d 100644 --- a/boards/stm32f411_blackpill/board.h +++ b/boards/stm32f411_blackpill/board.h @@ -4,10 +4,9 @@ #include #include #include +#include extern whal_Clock g_whalClock; -extern whal_Gpio g_whalGpio; -extern whal_Timer g_whalTimer; extern whal_Uart g_whalUart; extern whal_Spi g_whalSpi; extern whal_Flash g_whalFlash; @@ -32,6 +31,58 @@ enum { #define BOARD_FLASH_SECTOR_SZ 0x20000 #define BOARD_FLASH_WRITE_SZ 4 +static const whal_Gpio whal_Stm32f4_Gpio_Dev = { + .base = WHAL_STM32F411_GPIO_BASE, + + .cfg = (void *)&(const whal_Stm32f4_Gpio_Cfg){ + .pinCfg = (const whal_Stm32f4_Gpio_PinCfg[PIN_COUNT]){ + /* LED on PC13 (active low) */ + [LED_PIN] = WHAL_STM32F4_GPIO_PIN( + WHAL_STM32F4_GPIO_PORT_C, 13, WHAL_STM32F4_GPIO_MODE_OUT, + WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_LOW, + WHAL_STM32F4_GPIO_PULL_NONE, 0), + /* USART2 TX on PA2 (AF7) */ + [UART_TX_PIN] = WHAL_STM32F4_GPIO_PIN( + WHAL_STM32F4_GPIO_PORT_A, 2, WHAL_STM32F4_GPIO_MODE_ALTFN, + WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_FAST, + WHAL_STM32F4_GPIO_PULL_UP, 7), + /* USART2 RX on PA3 (AF7) */ + [UART_RX_PIN] = WHAL_STM32F4_GPIO_PIN( + WHAL_STM32F4_GPIO_PORT_A, 3, WHAL_STM32F4_GPIO_MODE_ALTFN, + WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_FAST, + WHAL_STM32F4_GPIO_PULL_UP, 7), + /* SPI1 SCK on PA5 (AF5) */ + [SPI_SCK_PIN] = WHAL_STM32F4_GPIO_PIN( + WHAL_STM32F4_GPIO_PORT_A, 5, WHAL_STM32F4_GPIO_MODE_ALTFN, + WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_FAST, + WHAL_STM32F4_GPIO_PULL_NONE, 5), + /* SPI1 MISO on PA6 (AF5) */ + [SPI_MISO_PIN] = WHAL_STM32F4_GPIO_PIN( + WHAL_STM32F4_GPIO_PORT_A, 6, WHAL_STM32F4_GPIO_MODE_ALTFN, + WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_FAST, + WHAL_STM32F4_GPIO_PULL_NONE, 5), + /* SPI1 MOSI on PA7 (AF5) */ + [SPI_MOSI_PIN] = WHAL_STM32F4_GPIO_PIN( + WHAL_STM32F4_GPIO_PORT_A, 7, WHAL_STM32F4_GPIO_MODE_ALTFN, + WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_FAST, + WHAL_STM32F4_GPIO_PULL_NONE, 5), + }, + .pinCount = PIN_COUNT, + }, +}; + +/* SysTick singleton — referenced by systick.c directly. */ +static const whal_Timer whal_SysTick_Dev = { + .base = WHAL_CORTEX_M4_SYSTICK_BASE, + /* .driver: direct API mapping */ + + .cfg = (void *)&(const whal_SysTick_Cfg){ + .cyclesPerTick = 100000000 / 1000, + .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, + .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, + }, +}; + whal_Error Board_Init(void); whal_Error Board_Deinit(void); void Board_WaitMs(size_t ms); diff --git a/boards/stm32f411_blackpill/board.mk b/boards/stm32f411_blackpill/board.mk index e9f49b4..a12eaa5 100644 --- a/boards/stm32f411_blackpill/board.mk +++ b/boards/stm32f411_blackpill/board.mk @@ -14,7 +14,8 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -DWHAL_CFG_STM32F4_GPIO_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32F4_RCC_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32F4_UART_DIRECT_API_MAPPING \ - -DWHAL_CFG_STM32F4_SPI_DIRECT_API_MAPPING + -DWHAL_CFG_STM32F4_SPI_DIRECT_API_MAPPING \ + -DWHAL_CFG_SYSTICK_TIMER_DIRECT_API_MAPPING LDFLAGS = --omagic -static --gc-sections LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld @@ -24,7 +25,6 @@ INCLUDE += -I$(_BOARD_DIR) -I$(WHAL_DIR)/boards/peripheral BOARD_SOURCE = $(_BOARD_DIR)/ivt.c BOARD_SOURCE += $(_BOARD_DIR)/board.c BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*.c) -BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/timer.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/flash.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/rng.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/crypto.c) diff --git a/boards/stm32h563zi_nucleo/board.c b/boards/stm32h563zi_nucleo/board.c index a451e2d..73302bd 100644 --- a/boards/stm32h563zi_nucleo/board.c +++ b/boards/stm32h563zi_nucleo/board.c @@ -50,109 +50,7 @@ static const whal_Stm32h5_Rcc_PeriphClk g_ethClocks[] = { }; #define ETH_CLOCK_COUNT (sizeof(g_ethClocks) / sizeof(g_ethClocks[0])) -/* GPIO */ -whal_Gpio g_whalGpio = { - .base = WHAL_STM32H563_GPIO_BASE, - /* .driver: direct API mapping */ - - .cfg = &(whal_Stm32h5_Gpio_Cfg) { - .pinCfg = (whal_Stm32h5_Gpio_PinCfg[PIN_COUNT]) { - /* LD1 Green LED on PB0 */ - [LED_PIN] = WHAL_STM32H5_GPIO_PIN( - WHAL_STM32H5_GPIO_PORT_B, 0, WHAL_STM32H5_GPIO_MODE_OUT, - WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_LOW, - WHAL_STM32H5_GPIO_PULL_NONE, 0), - /* USART3 TX on PD8, AF7 (ST-Link VCP) */ - [UART_TX_PIN] = WHAL_STM32H5_GPIO_PIN( - WHAL_STM32H5_GPIO_PORT_D, 8, WHAL_STM32H5_GPIO_MODE_ALTFN, - WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, - WHAL_STM32H5_GPIO_PULL_UP, 7), - /* USART3 RX on PD9, AF7 (ST-Link VCP) */ - [UART_RX_PIN] = WHAL_STM32H5_GPIO_PIN( - WHAL_STM32H5_GPIO_PORT_D, 9, WHAL_STM32H5_GPIO_MODE_ALTFN, - WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, - WHAL_STM32H5_GPIO_PULL_UP, 7), - /* SPI1 SCK on PA5 */ - [SPI_SCK_PIN] = WHAL_STM32H5_GPIO_PIN( - WHAL_STM32H5_GPIO_PORT_A, 5, WHAL_STM32H5_GPIO_MODE_ALTFN, - WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, - WHAL_STM32H5_GPIO_PULL_NONE, 5), - /* SPI1 MISO on PG9 */ - [SPI_MISO_PIN] = WHAL_STM32H5_GPIO_PIN( - WHAL_STM32H5_GPIO_PORT_G, 9, WHAL_STM32H5_GPIO_MODE_ALTFN, - WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, - WHAL_STM32H5_GPIO_PULL_NONE, 5), - /* SPI1 MOSI on PB5 */ - [SPI_MOSI_PIN] = WHAL_STM32H5_GPIO_PIN( - WHAL_STM32H5_GPIO_PORT_B, 5, WHAL_STM32H5_GPIO_MODE_ALTFN, - WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, - WHAL_STM32H5_GPIO_PULL_NONE, 5), - /* SPI CS on PD14 */ - [SPI_CS_PIN] = WHAL_STM32H5_GPIO_PIN( - WHAL_STM32H5_GPIO_PORT_D, 14, WHAL_STM32H5_GPIO_MODE_OUT, - WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, - WHAL_STM32H5_GPIO_PULL_UP, 0), - /* RMII REF_CLK on PA1 */ - [ETH_RMII_REF_CLK_PIN] = WHAL_STM32H5_GPIO_PIN( - WHAL_STM32H5_GPIO_PORT_A, 1, WHAL_STM32H5_GPIO_MODE_ALTFN, - WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, - WHAL_STM32H5_GPIO_PULL_NONE, 11), - /* RMII MDIO on PA2 */ - [ETH_RMII_MDIO_PIN] = WHAL_STM32H5_GPIO_PIN( - WHAL_STM32H5_GPIO_PORT_A, 2, WHAL_STM32H5_GPIO_MODE_ALTFN, - WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, - WHAL_STM32H5_GPIO_PULL_NONE, 11), - /* RMII MDC on PC1 */ - [ETH_RMII_MDC_PIN] = WHAL_STM32H5_GPIO_PIN( - WHAL_STM32H5_GPIO_PORT_C, 1, WHAL_STM32H5_GPIO_MODE_ALTFN, - WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, - WHAL_STM32H5_GPIO_PULL_NONE, 11), - /* RMII CRS_DV on PA7 */ - [ETH_RMII_CRS_DV_PIN] = WHAL_STM32H5_GPIO_PIN( - WHAL_STM32H5_GPIO_PORT_A, 7, WHAL_STM32H5_GPIO_MODE_ALTFN, - WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, - WHAL_STM32H5_GPIO_PULL_NONE, 11), - /* RMII RXD0 on PC4 */ - [ETH_RMII_RXD0_PIN] = WHAL_STM32H5_GPIO_PIN( - WHAL_STM32H5_GPIO_PORT_C, 4, WHAL_STM32H5_GPIO_MODE_ALTFN, - WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, - WHAL_STM32H5_GPIO_PULL_NONE, 11), - /* RMII RXD1 on PC5 */ - [ETH_RMII_RXD1_PIN] = WHAL_STM32H5_GPIO_PIN( - WHAL_STM32H5_GPIO_PORT_C, 5, WHAL_STM32H5_GPIO_MODE_ALTFN, - WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, - WHAL_STM32H5_GPIO_PULL_NONE, 11), - /* RMII TX_EN on PG11 */ - [ETH_RMII_TX_EN_PIN] = WHAL_STM32H5_GPIO_PIN( - WHAL_STM32H5_GPIO_PORT_G, 11, WHAL_STM32H5_GPIO_MODE_ALTFN, - WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, - WHAL_STM32H5_GPIO_PULL_NONE, 11), - /* RMII TXD0 on PG13 */ - [ETH_RMII_TXD0_PIN] = WHAL_STM32H5_GPIO_PIN( - WHAL_STM32H5_GPIO_PORT_G, 13, WHAL_STM32H5_GPIO_MODE_ALTFN, - WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, - WHAL_STM32H5_GPIO_PULL_NONE, 11), - /* RMII TXD1 on PB15 */ - [ETH_RMII_TXD1_PIN] = WHAL_STM32H5_GPIO_PIN( - WHAL_STM32H5_GPIO_PORT_B, 15, WHAL_STM32H5_GPIO_MODE_ALTFN, - WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, - WHAL_STM32H5_GPIO_PULL_NONE, 11), - }, - .pinCount = PIN_COUNT, - }, -}; - -/* Timer */ -whal_Timer g_whalTimer = { - .base = WHAL_CORTEX_M33_SYSTICK_BASE, - .driver = WHAL_CORTEX_M33_SYSTICK_DRIVER, - - .cfg = &(whal_SysTick_Cfg) { - .cyclesPerTick = 168000000 / 1000, /* 168 MHz / 1 kHz = 1 ms tick */ - .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, - .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, - }, -}; +/* GPIO, RNG, ETH, EthPhy singletons live in board.h as `static const`. */ /* UART */ whal_Uart g_whalUart = { @@ -176,17 +74,6 @@ whal_Spi g_whalSpi = { }, }; -/* RNG */ -whal_Rng g_whalRng = { - .base = WHAL_STM32H563_RNG_BASE, - /* .driver: direct API mapping */ - - .cfg = &(whal_Stm32h5_Rng_Cfg) { - .timeout = &g_whalTimeout, - }, -}; - - /* Flash */ whal_Flash g_whalFlash = { .base = WHAL_STM32H563_FLASH_BASE, @@ -199,50 +86,17 @@ whal_Flash g_whalFlash = { }, }; -/* Ethernet */ -#define ETH_TX_DESC_COUNT 4 -#define ETH_RX_DESC_COUNT 4 -#define ETH_TX_BUF_SIZE 1536 -#define ETH_RX_BUF_SIZE 1536 - -static whal_Stm32h5_Eth_TxDesc ethTxDescs[ETH_TX_DESC_COUNT] +/* Ethernet descriptor rings + buffer pool (referenced by the ETH singleton + * cfg in board.h). */ +whal_Stm32h5_Eth_TxDesc ethTxDescs[BOARD_ETH_TX_DESC_COUNT] __attribute__((aligned(16))); -static whal_Stm32h5_Eth_RxDesc ethRxDescs[ETH_RX_DESC_COUNT] +whal_Stm32h5_Eth_RxDesc ethRxDescs[BOARD_ETH_RX_DESC_COUNT] __attribute__((aligned(16))); -static uint8_t ethTxBufs[ETH_TX_DESC_COUNT * ETH_TX_BUF_SIZE] +uint8_t ethTxBufs[BOARD_ETH_TX_DESC_COUNT * BOARD_ETH_TX_BUF_SIZE] __attribute__((aligned(4))); -static uint8_t ethRxBufs[ETH_RX_DESC_COUNT * ETH_RX_BUF_SIZE] +uint8_t ethRxBufs[BOARD_ETH_RX_DESC_COUNT * BOARD_ETH_RX_BUF_SIZE] __attribute__((aligned(4))); -whal_Eth g_whalEth = { - .base = WHAL_STM32H563_ETH_BASE, - /* .driver: direct API mapping */ - - .macAddr = {0x00, 0x80, 0xE1, 0x00, 0x00, 0x01}, - .cfg = &(whal_Stm32h5_Eth_Cfg) { - .txDescs = ethTxDescs, - .txBufs = ethTxBufs, - .txDescCount = ETH_TX_DESC_COUNT, - .txBufSize = ETH_TX_BUF_SIZE, - .rxDescs = ethRxDescs, - .rxBufs = ethRxBufs, - .rxDescCount = ETH_RX_DESC_COUNT, - .rxBufSize = ETH_RX_BUF_SIZE, - .timeout = &g_whalTimeout, - }, -}; - -/* Ethernet PHY (LAN8742A) */ -whal_EthPhy g_whalEthPhy = { - .eth = &g_whalEth, - .addr = BOARD_ETH_PHY_ADDR, - /* .driver: direct API mapping */ - - .cfg = &(whal_Lan8742a_Cfg) { - .timeout = &g_whalTimeout, - }, -}; - void Board_WaitMs(size_t ms) { uint32_t startCount = g_tick; @@ -314,7 +168,7 @@ whal_Error Board_Init(void) if (err) return err; - err = whal_Gpio_Init(&g_whalGpio); + err = whal_Gpio_Init(WHAL_SINGLETON); if (err) return err; @@ -326,23 +180,23 @@ whal_Error Board_Init(void) if (err) return err; - err = whal_Rng_Init(&g_whalRng); + err = whal_Rng_Init(WHAL_SINGLETON); if (err) return err; - err = whal_Eth_Init(&g_whalEth); + err = whal_Eth_Init(WHAL_SINGLETON); if (err) return err; - err = whal_EthPhy_Init(&g_whalEthPhy); + err = whal_EthPhy_Init(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Init(&g_whalTimer); + err = whal_Timer_Init(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Start(&g_whalTimer); + err = whal_Timer_Start(WHAL_SINGLETON); if (err) return err; @@ -361,23 +215,23 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Timer_Stop(&g_whalTimer); + err = whal_Timer_Stop(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Deinit(&g_whalTimer); + err = whal_Timer_Deinit(WHAL_SINGLETON); if (err) return err; - err = whal_EthPhy_Deinit(&g_whalEthPhy); + err = whal_EthPhy_Deinit(WHAL_SINGLETON); if (err) return err; - err = whal_Eth_Deinit(&g_whalEth); + err = whal_Eth_Deinit(WHAL_SINGLETON); if (err) return err; - err = whal_Rng_Deinit(&g_whalRng); + err = whal_Rng_Deinit(WHAL_SINGLETON); if (err) return err; @@ -389,7 +243,7 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Gpio_Deinit(&g_whalGpio); + err = whal_Gpio_Deinit(WHAL_SINGLETON); if (err) return err; diff --git a/boards/stm32h563zi_nucleo/board.h b/boards/stm32h563zi_nucleo/board.h index 1c59fe8..0f13e18 100644 --- a/boards/stm32h563zi_nucleo/board.h +++ b/boards/stm32h563zi_nucleo/board.h @@ -4,16 +4,13 @@ #include #include #include +#include +#include extern whal_Clock g_whalClock; -extern whal_Gpio g_whalGpio; -extern whal_Timer g_whalTimer; extern whal_Uart g_whalUart; extern whal_Spi g_whalSpi; -extern whal_Rng g_whalRng; extern whal_Flash g_whalFlash; -extern whal_Eth g_whalEth; -extern whal_EthPhy g_whalEthPhy; extern whal_Timeout g_whalTimeout; extern volatile uint32_t g_tick; @@ -51,6 +48,138 @@ enum { #define BOARD_ETH_PHY_ID1 0x0007 #define BOARD_ETH_PHY_ID2 0xC131 +/* GPIO singleton — referenced by stm32wb_gpio.c directly. */ +static const whal_Gpio whal_Stm32h5_Gpio_Dev = { + .base = WHAL_STM32H563_GPIO_BASE, + .cfg = (void *)&(const whal_Stm32h5_Gpio_Cfg){ + .pinCfg = (const whal_Stm32h5_Gpio_PinCfg[PIN_COUNT]){ + [LED_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_B, 0, WHAL_STM32H5_GPIO_MODE_OUT, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_LOW, + WHAL_STM32H5_GPIO_PULL_NONE, 0), + [UART_TX_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_D, 8, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, + WHAL_STM32H5_GPIO_PULL_UP, 7), + [UART_RX_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_D, 9, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, + WHAL_STM32H5_GPIO_PULL_UP, 7), + [SPI_SCK_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_A, 5, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, + WHAL_STM32H5_GPIO_PULL_NONE, 5), + [SPI_MISO_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_G, 9, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, + WHAL_STM32H5_GPIO_PULL_NONE, 5), + [SPI_MOSI_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_B, 5, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, + WHAL_STM32H5_GPIO_PULL_NONE, 5), + [SPI_CS_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_D, 14, WHAL_STM32H5_GPIO_MODE_OUT, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, + WHAL_STM32H5_GPIO_PULL_UP, 0), + [ETH_RMII_REF_CLK_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_A, 1, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), + [ETH_RMII_MDIO_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_A, 2, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), + [ETH_RMII_MDC_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_C, 1, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), + [ETH_RMII_CRS_DV_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_A, 7, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), + [ETH_RMII_RXD0_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_C, 4, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), + [ETH_RMII_RXD1_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_C, 5, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), + [ETH_RMII_TX_EN_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_G, 11, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), + [ETH_RMII_TXD0_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_G, 13, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), + [ETH_RMII_TXD1_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_B, 15, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), + }, + .pinCount = PIN_COUNT, + }, +}; + +/* RNG singleton — referenced by stm32h5_rng.c directly. */ +static const whal_Rng whal_Stm32h5_Rng_Dev = { + .base = WHAL_STM32H563_RNG_BASE, + .cfg = (void *)&(const whal_Stm32h5_Rng_Cfg){ + .timeout = &g_whalTimeout, + }, +}; + +/* ETH descriptor rings + buffer pool — defined in board.c, addresses + * captured by the ETH singleton's cfg below at compile time. */ +#define BOARD_ETH_TX_DESC_COUNT 4 +#define BOARD_ETH_RX_DESC_COUNT 4 +#define BOARD_ETH_TX_BUF_SIZE 1536 +#define BOARD_ETH_RX_BUF_SIZE 1536 + +extern whal_Stm32h5_Eth_TxDesc ethTxDescs[BOARD_ETH_TX_DESC_COUNT]; +extern whal_Stm32h5_Eth_RxDesc ethRxDescs[BOARD_ETH_RX_DESC_COUNT]; +extern uint8_t ethTxBufs[BOARD_ETH_TX_DESC_COUNT * BOARD_ETH_TX_BUF_SIZE]; +extern uint8_t ethRxBufs[BOARD_ETH_RX_DESC_COUNT * BOARD_ETH_RX_BUF_SIZE]; + +/* ETH singleton — referenced by stm32h5_eth.c directly. */ +static const whal_Eth whal_Stm32h5_Eth_Dev = { + .base = WHAL_STM32H563_ETH_BASE, + .macAddr = {0x00, 0x80, 0xE1, 0x00, 0x00, 0x01}, + .cfg = (void *)&(const whal_Stm32h5_Eth_Cfg){ + .txDescs = ethTxDescs, + .txBufs = ethTxBufs, + .txDescCount = BOARD_ETH_TX_DESC_COUNT, + .txBufSize = BOARD_ETH_TX_BUF_SIZE, + .rxDescs = ethRxDescs, + .rxBufs = ethRxBufs, + .rxDescCount = BOARD_ETH_RX_DESC_COUNT, + .rxBufSize = BOARD_ETH_RX_BUF_SIZE, + .timeout = &g_whalTimeout, + }, +}; + +/* LAN8742A PHY singleton — referenced by lan8742a_eth_phy.c directly. */ +static const whal_EthPhy whal_Lan8742a_Dev = { + .eth = NULL, + .addr = BOARD_ETH_PHY_ADDR, + .cfg = (void *)&(const whal_Lan8742a_Cfg){ + .timeout = &g_whalTimeout, + }, +}; + +/* SysTick singleton — referenced by systick.c directly. */ +static const whal_Timer whal_SysTick_Dev = { + .base = WHAL_CORTEX_M33_SYSTICK_BASE, + /* .driver: direct API mapping */ + + .cfg = (void *)&(const whal_SysTick_Cfg){ + .cyclesPerTick = 168000000 / 1000, + .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, + .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, + }, +}; + whal_Error Board_Init(void); whal_Error Board_Deinit(void); void Board_WaitMs(size_t ms); diff --git a/boards/stm32h563zi_nucleo/board.mk b/boards/stm32h563zi_nucleo/board.mk index a0a6365..94d5110 100644 --- a/boards/stm32h563zi_nucleo/board.mk +++ b/boards/stm32h563zi_nucleo/board.mk @@ -17,7 +17,8 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -DWHAL_CFG_STM32H5_SPI_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32H5_RNG_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32H5_ETH_DIRECT_API_MAPPING \ - -DWHAL_CFG_LAN8742A_ETH_PHY_DIRECT_API_MAPPING + -DWHAL_CFG_LAN8742A_ETH_PHY_DIRECT_API_MAPPING \ + -DWHAL_CFG_SYSTICK_TIMER_DIRECT_API_MAPPING LDFLAGS = --omagic -static --gc-sections LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld @@ -27,7 +28,6 @@ INCLUDE += -I$(_BOARD_DIR) -I$(WHAL_DIR)/boards/peripheral BOARD_SOURCE = $(_BOARD_DIR)/ivt.c BOARD_SOURCE += $(_BOARD_DIR)/board.c BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*.c) -BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/timer.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/flash.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/crypto.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/block.c) diff --git a/boards/stm32l152re_nucleo/board.c b/boards/stm32l152re_nucleo/board.c index ac1d063..6272f8b 100644 --- a/boards/stm32l152re_nucleo/board.c +++ b/boards/stm32l152re_nucleo/board.c @@ -57,73 +57,6 @@ whal_Power g_whalPower = { .base = WHAL_STM32L152_PWR_BASE, }; -/* GPIO */ -whal_Gpio g_whalGpio = { - .base = WHAL_STM32L152_GPIO_BASE, - - .cfg = &(whal_Stm32l1_Gpio_Cfg) { - .pinCfg = (whal_Stm32l1_Gpio_PinCfg[PIN_COUNT]) { - /* LD2 Green LED on PA5 (per UM1724, NUCLEO-L152RE) */ - [LED_PIN] = WHAL_STM32L1_GPIO_PIN( - WHAL_STM32L1_GPIO_PORT_A, 5, WHAL_STM32L1_GPIO_MODE_OUT, - WHAL_STM32L1_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32L1_GPIO_SPEED_LOW, - WHAL_STM32L1_GPIO_PULL_NONE, 0), - /* USART2 TX on PA2, AF7 */ - [UART_TX_PIN] = WHAL_STM32L1_GPIO_PIN( - WHAL_STM32L1_GPIO_PORT_A, 2, WHAL_STM32L1_GPIO_MODE_ALTFN, - WHAL_STM32L1_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32L1_GPIO_SPEED_FAST, - WHAL_STM32L1_GPIO_PULL_UP, 7), - /* USART2 RX on PA3, AF7 */ - [UART_RX_PIN] = WHAL_STM32L1_GPIO_PIN( - WHAL_STM32L1_GPIO_PORT_A, 3, WHAL_STM32L1_GPIO_MODE_ALTFN, - WHAL_STM32L1_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32L1_GPIO_SPEED_FAST, - WHAL_STM32L1_GPIO_PULL_UP, 7), - /* SPI3 SCK on PB3, AF6 (avoids LD2 conflict on PA5) */ - [SPI_SCK_PIN] = WHAL_STM32L1_GPIO_PIN( - WHAL_STM32L1_GPIO_PORT_B, 3, WHAL_STM32L1_GPIO_MODE_ALTFN, - WHAL_STM32L1_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32L1_GPIO_SPEED_FAST, - WHAL_STM32L1_GPIO_PULL_NONE, 6), - /* SPI3 MISO on PB4, AF6 */ - [SPI_MISO_PIN] = WHAL_STM32L1_GPIO_PIN( - WHAL_STM32L1_GPIO_PORT_B, 4, WHAL_STM32L1_GPIO_MODE_ALTFN, - WHAL_STM32L1_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32L1_GPIO_SPEED_FAST, - WHAL_STM32L1_GPIO_PULL_NONE, 6), - /* SPI3 MOSI on PB5, AF6 */ - [SPI_MOSI_PIN] = WHAL_STM32L1_GPIO_PIN( - WHAL_STM32L1_GPIO_PORT_B, 5, WHAL_STM32L1_GPIO_MODE_ALTFN, - WHAL_STM32L1_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32L1_GPIO_SPEED_FAST, - WHAL_STM32L1_GPIO_PULL_NONE, 6), - /* SPI CS on PB12, output, push-pull */ - [SPI_CS_PIN] = WHAL_STM32L1_GPIO_PIN( - WHAL_STM32L1_GPIO_PORT_B, 12, WHAL_STM32L1_GPIO_MODE_OUT, - WHAL_STM32L1_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32L1_GPIO_SPEED_FAST, - WHAL_STM32L1_GPIO_PULL_UP, 0), - /* I2C1 SCL on PB8, AF4, open-drain */ - [I2C_SCL_PIN] = WHAL_STM32L1_GPIO_PIN( - WHAL_STM32L1_GPIO_PORT_B, 8, WHAL_STM32L1_GPIO_MODE_ALTFN, - WHAL_STM32L1_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32L1_GPIO_SPEED_FAST, - WHAL_STM32L1_GPIO_PULL_UP, 4), - /* I2C1 SDA on PB9, AF4, open-drain */ - [I2C_SDA_PIN] = WHAL_STM32L1_GPIO_PIN( - WHAL_STM32L1_GPIO_PORT_B, 9, WHAL_STM32L1_GPIO_MODE_ALTFN, - WHAL_STM32L1_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32L1_GPIO_SPEED_FAST, - WHAL_STM32L1_GPIO_PULL_UP, 4), - }, - .pinCount = PIN_COUNT, - }, -}; - -/* Timer -- SysTick at 1 ms (32 MHz / 1000) */ -whal_Timer g_whalTimer = { - .base = WHAL_CORTEX_M3_SYSTICK_BASE, - .driver = WHAL_CORTEX_M3_SYSTICK_DRIVER, - - .cfg = &(whal_SysTick_Cfg) { - .cyclesPerTick = 32000000 / 1000, - .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, - .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, - }, -}; /* UART -- USART2 at 115200 baud */ whal_Uart g_whalUart = { @@ -246,7 +179,7 @@ whal_Error Board_Init(void) return err; } - err = whal_Gpio_Init(&g_whalGpio); + err = whal_Gpio_Init(WHAL_SINGLETON); if (err) return err; @@ -262,11 +195,11 @@ whal_Error Board_Init(void) if (err) return err; - err = whal_Timer_Init(&g_whalTimer); + err = whal_Timer_Init(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Start(&g_whalTimer); + err = whal_Timer_Start(WHAL_SINGLETON); if (err) return err; @@ -285,11 +218,11 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Timer_Stop(&g_whalTimer); + err = whal_Timer_Stop(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Deinit(&g_whalTimer); + err = whal_Timer_Deinit(WHAL_SINGLETON); if (err) return err; @@ -305,7 +238,7 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Gpio_Deinit(&g_whalGpio); + err = whal_Gpio_Deinit(WHAL_SINGLETON); if (err) return err; diff --git a/boards/stm32l152re_nucleo/board.h b/boards/stm32l152re_nucleo/board.h index 665d431..a840eb2 100644 --- a/boards/stm32l152re_nucleo/board.h +++ b/boards/stm32l152re_nucleo/board.h @@ -4,10 +4,9 @@ #include #include #include +#include extern whal_Clock g_whalClock; -extern whal_Gpio g_whalGpio; -extern whal_Timer g_whalTimer; extern whal_Uart g_whalUart; extern whal_Spi g_whalSpi; extern whal_I2c g_whalI2c; @@ -37,6 +36,73 @@ enum { #define BOARD_FLASH_TEST_ADDR 0x0807FF00 #define BOARD_FLASH_SECTOR_SZ 0x100 +static const whal_Gpio whal_Stm32l1_Gpio_Dev = { + .base = WHAL_STM32L152_GPIO_BASE, + + .cfg = (void *)&(const whal_Stm32l1_Gpio_Cfg){ + .pinCfg = (const whal_Stm32l1_Gpio_PinCfg[PIN_COUNT]){ + /* LD2 Green LED on PA5 (per UM1724, NUCLEO-L152RE) */ + [LED_PIN] = WHAL_STM32L1_GPIO_PIN( + WHAL_STM32L1_GPIO_PORT_A, 5, WHAL_STM32L1_GPIO_MODE_OUT, + WHAL_STM32L1_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32L1_GPIO_SPEED_LOW, + WHAL_STM32L1_GPIO_PULL_NONE, 0), + /* USART2 TX on PA2, AF7 */ + [UART_TX_PIN] = WHAL_STM32L1_GPIO_PIN( + WHAL_STM32L1_GPIO_PORT_A, 2, WHAL_STM32L1_GPIO_MODE_ALTFN, + WHAL_STM32L1_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32L1_GPIO_SPEED_FAST, + WHAL_STM32L1_GPIO_PULL_UP, 7), + /* USART2 RX on PA3, AF7 */ + [UART_RX_PIN] = WHAL_STM32L1_GPIO_PIN( + WHAL_STM32L1_GPIO_PORT_A, 3, WHAL_STM32L1_GPIO_MODE_ALTFN, + WHAL_STM32L1_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32L1_GPIO_SPEED_FAST, + WHAL_STM32L1_GPIO_PULL_UP, 7), + /* SPI3 SCK on PB3, AF6 (avoids LD2 conflict on PA5) */ + [SPI_SCK_PIN] = WHAL_STM32L1_GPIO_PIN( + WHAL_STM32L1_GPIO_PORT_B, 3, WHAL_STM32L1_GPIO_MODE_ALTFN, + WHAL_STM32L1_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32L1_GPIO_SPEED_FAST, + WHAL_STM32L1_GPIO_PULL_NONE, 6), + /* SPI3 MISO on PB4, AF6 */ + [SPI_MISO_PIN] = WHAL_STM32L1_GPIO_PIN( + WHAL_STM32L1_GPIO_PORT_B, 4, WHAL_STM32L1_GPIO_MODE_ALTFN, + WHAL_STM32L1_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32L1_GPIO_SPEED_FAST, + WHAL_STM32L1_GPIO_PULL_NONE, 6), + /* SPI3 MOSI on PB5, AF6 */ + [SPI_MOSI_PIN] = WHAL_STM32L1_GPIO_PIN( + WHAL_STM32L1_GPIO_PORT_B, 5, WHAL_STM32L1_GPIO_MODE_ALTFN, + WHAL_STM32L1_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32L1_GPIO_SPEED_FAST, + WHAL_STM32L1_GPIO_PULL_NONE, 6), + /* SPI CS on PB12, output, push-pull */ + [SPI_CS_PIN] = WHAL_STM32L1_GPIO_PIN( + WHAL_STM32L1_GPIO_PORT_B, 12, WHAL_STM32L1_GPIO_MODE_OUT, + WHAL_STM32L1_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32L1_GPIO_SPEED_FAST, + WHAL_STM32L1_GPIO_PULL_UP, 0), + /* I2C1 SCL on PB8, AF4, open-drain */ + [I2C_SCL_PIN] = WHAL_STM32L1_GPIO_PIN( + WHAL_STM32L1_GPIO_PORT_B, 8, WHAL_STM32L1_GPIO_MODE_ALTFN, + WHAL_STM32L1_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32L1_GPIO_SPEED_FAST, + WHAL_STM32L1_GPIO_PULL_UP, 4), + /* I2C1 SDA on PB9, AF4, open-drain */ + [I2C_SDA_PIN] = WHAL_STM32L1_GPIO_PIN( + WHAL_STM32L1_GPIO_PORT_B, 9, WHAL_STM32L1_GPIO_MODE_ALTFN, + WHAL_STM32L1_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32L1_GPIO_SPEED_FAST, + WHAL_STM32L1_GPIO_PULL_UP, 4), + }, + .pinCount = PIN_COUNT, + }, +}; + +/* SysTick singleton — referenced by systick.c directly. */ +static const whal_Timer whal_SysTick_Dev = { + .base = WHAL_CORTEX_M3_SYSTICK_BASE, + /* .driver: direct API mapping */ + + .cfg = (void *)&(const whal_SysTick_Cfg){ + .cyclesPerTick = 32000000 / 1000, + .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, + .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, + }, +}; + whal_Error Board_Init(void); whal_Error Board_Deinit(void); void Board_WaitMs(size_t ms); diff --git a/boards/stm32l152re_nucleo/board.mk b/boards/stm32l152re_nucleo/board.mk index ce84336..1284e78 100644 --- a/boards/stm32l152re_nucleo/board.mk +++ b/boards/stm32l152re_nucleo/board.mk @@ -17,7 +17,8 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -DWHAL_CFG_STM32L1_SPI_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32L1_I2C_DIRECT_API_MAPPING \ $(if $(filter iwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_IWDG) \ - $(if $(filter wwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_WWDG) + $(if $(filter wwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_WWDG) \ + -DWHAL_CFG_SYSTICK_TIMER_DIRECT_API_MAPPING LDFLAGS = -mcpu=cortex-m3 -mthumb \ -ffreestanding -nostartfiles -Wl,--omagic -Wl,--gc-sections -static @@ -28,7 +29,6 @@ INCLUDE += -I$(_BOARD_DIR) -I$(WHAL_DIR)/boards/peripheral BOARD_SOURCE = $(_BOARD_DIR)/ivt.c BOARD_SOURCE += $(_BOARD_DIR)/board.c BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*.c) -BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/timer.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/flash.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/rng.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/crypto.c) diff --git a/boards/stm32n657a0_nucleo/board.c b/boards/stm32n657a0_nucleo/board.c index 59c346e..76e44ee 100644 --- a/boards/stm32n657a0_nucleo/board.c +++ b/boards/stm32n657a0_nucleo/board.c @@ -25,12 +25,6 @@ whal_Timeout g_whalTimeout = { .GetTick = Board_GetTick, }; -/* IRQ */ -whal_Irq g_whalIrq = { - .base = WHAL_CORTEX_M55_NVIC_BASE, - .driver = WHAL_CORTEX_M55_NVIC_DRIVER, -}; - /* Clock: HSI at 64 MHz (default after reset). * The STM32N6 boots from ROM into HSI; PLL setup is complex (PLL1+IC dividers). * For initial bring-up, run at HSI 64 MHz. */ @@ -67,105 +61,6 @@ static const whal_Stm32n6_Rcc_PeriphClk g_ethClocks[] = { /* GPIO */ /* API is directly mapped */ -whal_Gpio g_whalGpio = { - .base = WHAL_STM32N657_GPIO_BASE, - - .cfg = &(whal_Stm32n6_Gpio_Cfg) { - .pinCfg = (whal_Stm32n6_Gpio_PinCfg[PIN_COUNT]) { - /* LD1 Green LED on PB0 */ - [LED_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_B, 0, WHAL_STM32N6_GPIO_MODE_OUT, - WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_LOW, - WHAL_STM32N6_GPIO_PULL_NONE, 0), - /* USART1 TX on PE5, AF7 */ - [UART_TX_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_E, 5, WHAL_STM32N6_GPIO_MODE_ALTFN, - WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_FAST, - WHAL_STM32N6_GPIO_PULL_UP, 7), - /* USART1 RX on PE6, AF7 */ - [UART_RX_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_E, 6, WHAL_STM32N6_GPIO_MODE_ALTFN, - WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_FAST, - WHAL_STM32N6_GPIO_PULL_UP, 7), - /* SPI1 SCK on PA5, AF5 */ - [SPI_SCK_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_A, 5, WHAL_STM32N6_GPIO_MODE_ALTFN, - WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_FAST, - WHAL_STM32N6_GPIO_PULL_NONE, 5), - /* SPI1 MISO on PA6, AF5 */ - [SPI_MISO_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_A, 6, WHAL_STM32N6_GPIO_MODE_ALTFN, - WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_FAST, - WHAL_STM32N6_GPIO_PULL_NONE, 5), - /* SPI1 MOSI on PA7, AF5 */ - [SPI_MOSI_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_A, 7, WHAL_STM32N6_GPIO_MODE_ALTFN, - WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_FAST, - WHAL_STM32N6_GPIO_PULL_NONE, 5), - /* SPI CS on PA4, output */ - [SPI_CS_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_A, 4, WHAL_STM32N6_GPIO_MODE_OUT, - WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_FAST, - WHAL_STM32N6_GPIO_PULL_UP, 0), - /* I2C1 SCL on PB6, AF4, open-drain */ - [I2C_SCL_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_B, 6, WHAL_STM32N6_GPIO_MODE_ALTFN, - WHAL_STM32N6_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32N6_GPIO_SPEED_FAST, - WHAL_STM32N6_GPIO_PULL_UP, 4), - /* I2C1 SDA on PB7, AF4, open-drain */ - [I2C_SDA_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_B, 7, WHAL_STM32N6_GPIO_MODE_ALTFN, - WHAL_STM32N6_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32N6_GPIO_SPEED_FAST, - WHAL_STM32N6_GPIO_PULL_UP, 4), - /* RMII REF_CLK on PF7, AF11 */ - [ETH_RMII_REF_CLK_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_F, 7, WHAL_STM32N6_GPIO_MODE_ALTFN, - WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, - WHAL_STM32N6_GPIO_PULL_NONE, 11), - /* RMII MDIO on PF4, AF11 */ - [ETH_RMII_MDIO_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_F, 4, WHAL_STM32N6_GPIO_MODE_ALTFN, - WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, - WHAL_STM32N6_GPIO_PULL_NONE, 11), - /* RMII MDC on PG11, AF11 */ - [ETH_RMII_MDC_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_G, 11, WHAL_STM32N6_GPIO_MODE_ALTFN, - WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, - WHAL_STM32N6_GPIO_PULL_NONE, 11), - /* RMII CRS_DV on PF10, AF11 */ - [ETH_RMII_CRS_DV_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_F, 10, WHAL_STM32N6_GPIO_MODE_ALTFN, - WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, - WHAL_STM32N6_GPIO_PULL_NONE, 11), - /* RMII RXD0 on PF14, AF11 */ - [ETH_RMII_RXD0_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_F, 14, WHAL_STM32N6_GPIO_MODE_ALTFN, - WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, - WHAL_STM32N6_GPIO_PULL_NONE, 11), - /* RMII RXD1 on PF15, AF11 */ - [ETH_RMII_RXD1_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_F, 15, WHAL_STM32N6_GPIO_MODE_ALTFN, - WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, - WHAL_STM32N6_GPIO_PULL_NONE, 11), - /* RMII TX_EN on PF11, AF11 */ - [ETH_RMII_TX_EN_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_F, 11, WHAL_STM32N6_GPIO_MODE_ALTFN, - WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, - WHAL_STM32N6_GPIO_PULL_NONE, 11), - /* RMII TXD0 on PF12, AF11 */ - [ETH_RMII_TXD0_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_F, 12, WHAL_STM32N6_GPIO_MODE_ALTFN, - WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, - WHAL_STM32N6_GPIO_PULL_NONE, 11), - /* RMII TXD1 on PF13, AF11 */ - [ETH_RMII_TXD1_PIN] = WHAL_STM32N6_GPIO_PIN( - WHAL_STM32N6_GPIO_PORT_F, 13, WHAL_STM32N6_GPIO_MODE_ALTFN, - WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, - WHAL_STM32N6_GPIO_PULL_NONE, 11), - }, - .pinCount = PIN_COUNT, - }, -}; /* I2C */ /* API is directly mapped */ @@ -189,17 +84,6 @@ whal_Spi g_whalSpi = { }, }; -/* Timer (SysTick at 64 MHz HSI) */ -whal_Timer g_whalTimer = { - .base = WHAL_CORTEX_M55_SYSTICK_BASE, - .driver = WHAL_CORTEX_M55_SYSTICK_DRIVER, - - .cfg = &(whal_SysTick_Cfg) { - .cyclesPerTick = 64000000 / 1000, /* 64 MHz / 1 kHz = 1 ms tick */ - .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, - .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, - }, -}; /* DMA */ #ifdef BOARD_DMA @@ -226,15 +110,7 @@ whal_Uart g_whalUart = { }, }; -/* RNG */ -/* API is directly mapped */ -whal_Rng g_whalRng = { - .base = WHAL_STM32N657_RNG_BASE, - - .cfg = &(whal_Stm32n6_Rng_Cfg) { - .timeout = &g_whalTimeout, - }, -}; +/* RNG, ETH, EthPhy singletons live in board.h as `static const`. */ /* Crypto (CRYP hardware accelerator) */ whal_Crypto g_whalCrypto = { @@ -356,52 +232,19 @@ whal_Watchdog g_whalWatchdog = { #endif /* Ethernet */ -#define ETH_TX_DESC_COUNT 4 -#define ETH_RX_DESC_COUNT 4 -#define ETH_TX_BUF_SIZE 1536 -#define ETH_RX_BUF_SIZE 1536 - /* ETH DMA descriptors and frame buffers must live in AXI-master-visible * RAM. The default RAM region (FLEXRAM at 0x34000000) is allocated as * Cortex-M55 TCM and is not reachable by the ETH AXI master, so place * these in AXISRAM1 via the .axisram1 section. */ -static whal_Stm32n6_Eth_TxDesc ethTxDescs[ETH_TX_DESC_COUNT] +whal_Stm32n6_Eth_TxDesc ethTxDescs[BOARD_ETH_TX_DESC_COUNT] __attribute__((aligned(16), section(".axisram1"))); -static whal_Stm32n6_Eth_RxDesc ethRxDescs[ETH_RX_DESC_COUNT] +whal_Stm32n6_Eth_RxDesc ethRxDescs[BOARD_ETH_RX_DESC_COUNT] __attribute__((aligned(16), section(".axisram1"))); -static uint8_t ethTxBufs[ETH_TX_DESC_COUNT * ETH_TX_BUF_SIZE] +uint8_t ethTxBufs[BOARD_ETH_TX_DESC_COUNT * BOARD_ETH_TX_BUF_SIZE] __attribute__((aligned(8), section(".axisram1"))); -static uint8_t ethRxBufs[ETH_RX_DESC_COUNT * ETH_RX_BUF_SIZE] +uint8_t ethRxBufs[BOARD_ETH_RX_DESC_COUNT * BOARD_ETH_RX_BUF_SIZE] __attribute__((aligned(8), section(".axisram1"))); -/* API is directly mapped */ -whal_Eth g_whalEth = { - .base = WHAL_STM32N657_ETH_BASE, - - .macAddr = {0x00, 0x80, 0xE1, 0x00, 0x00, 0x01}, - .cfg = &(whal_Stm32n6_Eth_Cfg) { - .txDescs = ethTxDescs, - .txBufs = ethTxBufs, - .txDescCount = ETH_TX_DESC_COUNT, - .txBufSize = ETH_TX_BUF_SIZE, - .rxDescs = ethRxDescs, - .rxBufs = ethRxBufs, - .rxDescCount = ETH_RX_DESC_COUNT, - .rxBufSize = ETH_RX_BUF_SIZE, - .timeout = &g_whalTimeout, - }, -}; - -/* Ethernet PHY (LAN8742A) — API is directly mapped */ -whal_EthPhy g_whalEthPhy = { - .eth = &g_whalEth, - .addr = BOARD_ETH_PHY_ADDR, - - .cfg = &(whal_Lan8742a_Cfg) { - .timeout = &g_whalTimeout, - }, -}; - void Board_WaitMs(size_t ms) { uint32_t startCount = g_tick; @@ -468,7 +311,7 @@ whal_Error Board_Init(void) return err; } - err = whal_Irq_Init(&g_whalIrq); + err = whal_Irq_Init(WHAL_SINGLETON); if (err) return err; @@ -481,7 +324,7 @@ whal_Error Board_Init(void) return err; #endif - err = whal_Gpio_Init(&g_whalGpio); + err = whal_Gpio_Init(WHAL_SINGLETON); if (err) return err; @@ -497,7 +340,7 @@ whal_Error Board_Init(void) if (err) return err; - err = whal_Rng_Init(&g_whalRng); + err = whal_Rng_Init(WHAL_SINGLETON); if (err) return err; @@ -509,19 +352,19 @@ whal_Error Board_Init(void) if (err) return err; - err = whal_Eth_Init(&g_whalEth); + err = whal_Eth_Init(WHAL_SINGLETON); if (err) return err; - err = whal_EthPhy_Init(&g_whalEthPhy); + err = whal_EthPhy_Init(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Init(&g_whalTimer); + err = whal_Timer_Init(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Start(&g_whalTimer); + err = whal_Timer_Start(WHAL_SINGLETON); if (err) return err; @@ -540,19 +383,19 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Timer_Stop(&g_whalTimer); + err = whal_Timer_Stop(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Deinit(&g_whalTimer); + err = whal_Timer_Deinit(WHAL_SINGLETON); if (err) return err; - err = whal_EthPhy_Deinit(&g_whalEthPhy); + err = whal_EthPhy_Deinit(WHAL_SINGLETON); if (err) return err; - err = whal_Eth_Deinit(&g_whalEth); + err = whal_Eth_Deinit(WHAL_SINGLETON); if (err) return err; @@ -564,7 +407,7 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Rng_Deinit(&g_whalRng); + err = whal_Rng_Deinit(WHAL_SINGLETON); if (err) return err; @@ -580,7 +423,7 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Gpio_Deinit(&g_whalGpio); + err = whal_Gpio_Deinit(WHAL_SINGLETON); if (err) return err; @@ -593,7 +436,7 @@ whal_Error Board_Deinit(void) return err; #endif - err = whal_Irq_Deinit(&g_whalIrq); + err = whal_Irq_Deinit(WHAL_SINGLETON); if (err) return err; diff --git a/boards/stm32n657a0_nucleo/board.h b/boards/stm32n657a0_nucleo/board.h index e349226..ec18906 100644 --- a/boards/stm32n657a0_nucleo/board.h +++ b/boards/stm32n657a0_nucleo/board.h @@ -4,15 +4,14 @@ #include #include #include +#include +#include #include #include extern whal_Clock g_whalClock; -extern whal_Gpio g_whalGpio; -extern whal_Timer g_whalTimer; extern whal_Uart g_whalUart; extern whal_Spi g_whalSpi; -extern whal_Rng g_whalRng; extern whal_I2c g_whalI2c; extern whal_Crypto g_whalCrypto; extern whal_AesEcb g_whalAesEcb; @@ -28,10 +27,7 @@ extern whal_Sha256 g_whalSha256; extern whal_HmacSha1 g_whalHmacSha1; extern whal_HmacSha224 g_whalHmacSha224; extern whal_HmacSha256 g_whalHmacSha256; -extern whal_Irq g_whalIrq; extern whal_Watchdog g_whalWatchdog; -extern whal_Eth g_whalEth; -extern whal_EthPhy g_whalEthPhy; #ifdef BOARD_DMA extern whal_Dma g_whalDma1; #endif @@ -68,6 +64,171 @@ enum { #define BOARD_ETH_PHY_ID1 0x0007 #define BOARD_ETH_PHY_ID2 0xC131 +static const whal_Gpio whal_Stm32n6_Gpio_Dev = { + .base = WHAL_STM32N657_GPIO_BASE, + + .cfg = (void *)&(const whal_Stm32n6_Gpio_Cfg){ + .pinCfg = (const whal_Stm32n6_Gpio_PinCfg[PIN_COUNT]){ + /* LD1 Green LED on PB0 */ + [LED_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_B, 0, WHAL_STM32N6_GPIO_MODE_OUT, + WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_LOW, + WHAL_STM32N6_GPIO_PULL_NONE, 0), + /* USART1 TX on PE5, AF7 */ + [UART_TX_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_E, 5, WHAL_STM32N6_GPIO_MODE_ALTFN, + WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_FAST, + WHAL_STM32N6_GPIO_PULL_UP, 7), + /* USART1 RX on PE6, AF7 */ + [UART_RX_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_E, 6, WHAL_STM32N6_GPIO_MODE_ALTFN, + WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_FAST, + WHAL_STM32N6_GPIO_PULL_UP, 7), + /* SPI1 SCK on PA5, AF5 */ + [SPI_SCK_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_A, 5, WHAL_STM32N6_GPIO_MODE_ALTFN, + WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_FAST, + WHAL_STM32N6_GPIO_PULL_NONE, 5), + /* SPI1 MISO on PA6, AF5 */ + [SPI_MISO_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_A, 6, WHAL_STM32N6_GPIO_MODE_ALTFN, + WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_FAST, + WHAL_STM32N6_GPIO_PULL_NONE, 5), + /* SPI1 MOSI on PA7, AF5 */ + [SPI_MOSI_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_A, 7, WHAL_STM32N6_GPIO_MODE_ALTFN, + WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_FAST, + WHAL_STM32N6_GPIO_PULL_NONE, 5), + /* SPI CS on PA4, output */ + [SPI_CS_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_A, 4, WHAL_STM32N6_GPIO_MODE_OUT, + WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_FAST, + WHAL_STM32N6_GPIO_PULL_UP, 0), + /* I2C1 SCL on PB6, AF4, open-drain */ + [I2C_SCL_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_B, 6, WHAL_STM32N6_GPIO_MODE_ALTFN, + WHAL_STM32N6_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32N6_GPIO_SPEED_FAST, + WHAL_STM32N6_GPIO_PULL_UP, 4), + /* I2C1 SDA on PB7, AF4, open-drain */ + [I2C_SDA_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_B, 7, WHAL_STM32N6_GPIO_MODE_ALTFN, + WHAL_STM32N6_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32N6_GPIO_SPEED_FAST, + WHAL_STM32N6_GPIO_PULL_UP, 4), + /* RMII REF_CLK on PF7, AF11 */ + [ETH_RMII_REF_CLK_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_F, 7, WHAL_STM32N6_GPIO_MODE_ALTFN, + WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, + WHAL_STM32N6_GPIO_PULL_NONE, 11), + /* RMII MDIO on PF4, AF11 */ + [ETH_RMII_MDIO_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_F, 4, WHAL_STM32N6_GPIO_MODE_ALTFN, + WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, + WHAL_STM32N6_GPIO_PULL_NONE, 11), + /* RMII MDC on PG11, AF11 */ + [ETH_RMII_MDC_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_G, 11, WHAL_STM32N6_GPIO_MODE_ALTFN, + WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, + WHAL_STM32N6_GPIO_PULL_NONE, 11), + /* RMII CRS_DV on PF10, AF11 */ + [ETH_RMII_CRS_DV_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_F, 10, WHAL_STM32N6_GPIO_MODE_ALTFN, + WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, + WHAL_STM32N6_GPIO_PULL_NONE, 11), + /* RMII RXD0 on PF14, AF11 */ + [ETH_RMII_RXD0_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_F, 14, WHAL_STM32N6_GPIO_MODE_ALTFN, + WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, + WHAL_STM32N6_GPIO_PULL_NONE, 11), + /* RMII RXD1 on PF15, AF11 */ + [ETH_RMII_RXD1_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_F, 15, WHAL_STM32N6_GPIO_MODE_ALTFN, + WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, + WHAL_STM32N6_GPIO_PULL_NONE, 11), + /* RMII TX_EN on PF11, AF11 */ + [ETH_RMII_TX_EN_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_F, 11, WHAL_STM32N6_GPIO_MODE_ALTFN, + WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, + WHAL_STM32N6_GPIO_PULL_NONE, 11), + /* RMII TXD0 on PF12, AF11 */ + [ETH_RMII_TXD0_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_F, 12, WHAL_STM32N6_GPIO_MODE_ALTFN, + WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, + WHAL_STM32N6_GPIO_PULL_NONE, 11), + /* RMII TXD1 on PF13, AF11 */ + [ETH_RMII_TXD1_PIN] = WHAL_STM32N6_GPIO_PIN( + WHAL_STM32N6_GPIO_PORT_F, 13, WHAL_STM32N6_GPIO_MODE_ALTFN, + WHAL_STM32N6_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32N6_GPIO_SPEED_HIGH, + WHAL_STM32N6_GPIO_PULL_NONE, 11), + }, + .pinCount = PIN_COUNT, + }, +}; + +/* RNG singleton — referenced by stm32n6_rng.c directly. */ +static const whal_Rng whal_Stm32h5_Rng_Dev = { + .base = WHAL_STM32N657_RNG_BASE, + .cfg = (void *)&(const whal_Stm32n6_Rng_Cfg){ + .timeout = &g_whalTimeout, + }, +}; + +/* ETH descriptor rings + buffer pool. Live in board.c with the .axisram1 + * section attribute; declared here so the ETH singleton cfg below can + * take their addresses at compile time. */ +#define BOARD_ETH_TX_DESC_COUNT 4 +#define BOARD_ETH_RX_DESC_COUNT 4 +#define BOARD_ETH_TX_BUF_SIZE 1536 +#define BOARD_ETH_RX_BUF_SIZE 1536 + +extern whal_Stm32n6_Eth_TxDesc ethTxDescs[BOARD_ETH_TX_DESC_COUNT]; +extern whal_Stm32n6_Eth_RxDesc ethRxDescs[BOARD_ETH_RX_DESC_COUNT]; +extern uint8_t ethTxBufs[BOARD_ETH_TX_DESC_COUNT * BOARD_ETH_TX_BUF_SIZE]; +extern uint8_t ethRxBufs[BOARD_ETH_RX_DESC_COUNT * BOARD_ETH_RX_BUF_SIZE]; + +/* ETH singleton — referenced by stm32n6_eth.c directly. */ +static const whal_Eth whal_Stm32h5_Eth_Dev = { + .base = WHAL_STM32N657_ETH_BASE, + .macAddr = {0x00, 0x80, 0xE1, 0x00, 0x00, 0x01}, + .cfg = (void *)&(const whal_Stm32n6_Eth_Cfg){ + .txDescs = ethTxDescs, + .txBufs = ethTxBufs, + .txDescCount = BOARD_ETH_TX_DESC_COUNT, + .txBufSize = BOARD_ETH_TX_BUF_SIZE, + .rxDescs = ethRxDescs, + .rxBufs = ethRxBufs, + .rxDescCount = BOARD_ETH_RX_DESC_COUNT, + .rxBufSize = BOARD_ETH_RX_BUF_SIZE, + .timeout = &g_whalTimeout, + }, +}; + +/* LAN8742A PHY singleton — referenced by lan8742a_eth_phy.c directly. */ +static const whal_EthPhy whal_Lan8742a_Dev = { + .eth = NULL, + .addr = BOARD_ETH_PHY_ADDR, + .cfg = (void *)&(const whal_Lan8742a_Cfg){ + .timeout = &g_whalTimeout, + }, +}; + +/* NVIC singleton — referenced by cortex_m4_nvic.c directly. */ +static const whal_Irq whal_Nvic_Dev = { + .base = WHAL_CORTEX_M55_NVIC_BASE, + /* .driver: direct API mapping */ +}; + +/* SysTick singleton — referenced by systick.c directly. */ +static const whal_Timer whal_SysTick_Dev = { + .base = WHAL_CORTEX_M55_SYSTICK_BASE, + /* .driver: direct API mapping */ + + .cfg = (void *)&(const whal_SysTick_Cfg){ + .cyclesPerTick = 64000000 / 1000, + .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, + .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, + }, +}; + whal_Error Board_Init(void); whal_Error Board_Deinit(void); void Board_WaitMs(size_t ms); diff --git a/boards/stm32n657a0_nucleo/board.mk b/boards/stm32n657a0_nucleo/board.mk index 01b39cd..43ebfe3 100644 --- a/boards/stm32n657a0_nucleo/board.mk +++ b/boards/stm32n657a0_nucleo/board.mk @@ -34,7 +34,9 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -DWHAL_CFG_STM32N6_HASH_SHA256_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32N6_HASH_HMAC_SHA1_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32N6_HASH_HMAC_SHA224_DIRECT_API_MAPPING \ - -DWHAL_CFG_STM32N6_HASH_HMAC_SHA256_DIRECT_API_MAPPING + -DWHAL_CFG_STM32N6_HASH_HMAC_SHA256_DIRECT_API_MAPPING \ + -DWHAL_CFG_SYSTICK_TIMER_DIRECT_API_MAPPING \ + -DWHAL_CFG_NVIC_IRQ_DIRECT_API_MAPPING LDFLAGS = --omagic -static --gc-sections LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld @@ -44,13 +46,11 @@ INCLUDE += -I$(_BOARD_DIR) -I$(WHAL_DIR)/boards/peripheral BOARD_SOURCE = $(_BOARD_DIR)/ivt.c BOARD_SOURCE += $(_BOARD_DIR)/board.c BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*.c) -BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/timer.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/sensor.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/watchdog.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/crypto.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/flash.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/block.c) -BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/irq.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/irq/cortex_m4_nvic.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/stm32n6_*.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/lan8742a_*.c) diff --git a/boards/stm32wb55xx_nucleo/board.c b/boards/stm32wb55xx_nucleo/board.c index df76bbb..8f1a3c0 100644 --- a/boards/stm32wb55xx_nucleo/board.c +++ b/boards/stm32wb55xx_nucleo/board.c @@ -25,12 +25,6 @@ whal_Timeout g_whalTimeout = { .GetTick = Board_GetTick, }; -/* IRQ */ -whal_Irq g_whalIrq = { - .base = WHAL_CORTEX_M4_NVIC_BASE, - .driver = WHAL_CORTEX_M4_NVIC_DRIVER, -}; - /* Clock */ whal_Clock g_whalClock = { .base = WHAL_STM32WB55_RCC_BASE, @@ -51,62 +45,7 @@ static const whal_Stm32wb_Rcc_PeriphClk g_periphClks[] = { }; #define PERIPH_CLK_COUNT (sizeof(g_periphClks) / sizeof(g_periphClks[0])) -/* GPIO */ -whal_Gpio g_whalGpio = { - .base = WHAL_STM32WB55_GPIO_BASE, - /* .driver: direct API mapping */ - - .cfg = &(whal_Stm32wb_Gpio_Cfg) { - .pinCfg = (whal_Stm32wb_Gpio_PinCfg[PIN_COUNT]) { - /* LED: PB5, output, push-pull, low speed, pull-up */ - [LED_PIN] = WHAL_STM32WB_GPIO_PIN( - WHAL_STM32WB_GPIO_PORT_B, 5, WHAL_STM32WB_GPIO_MODE_OUT, - WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_LOW, - WHAL_STM32WB_GPIO_PULL_UP, 0), - /* UART1 TX: PB6, AF7 */ - [UART_TX_PIN] = WHAL_STM32WB_GPIO_PIN( - WHAL_STM32WB_GPIO_PORT_B, 6, WHAL_STM32WB_GPIO_MODE_ALTFN, - WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, - WHAL_STM32WB_GPIO_PULL_UP, 7), - /* UART1 RX: PB7, AF7 */ - [UART_RX_PIN] = WHAL_STM32WB_GPIO_PIN( - WHAL_STM32WB_GPIO_PORT_B, 7, WHAL_STM32WB_GPIO_MODE_ALTFN, - WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, - WHAL_STM32WB_GPIO_PULL_UP, 7), - /* SPI1 SCK: PA5, AF5 */ - [SPI_SCK_PIN] = WHAL_STM32WB_GPIO_PIN( - WHAL_STM32WB_GPIO_PORT_A, 5, WHAL_STM32WB_GPIO_MODE_ALTFN, - WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, - WHAL_STM32WB_GPIO_PULL_NONE, 5), - /* SPI1 MISO: PA6, AF5 */ - [SPI_MISO_PIN] = WHAL_STM32WB_GPIO_PIN( - WHAL_STM32WB_GPIO_PORT_A, 6, WHAL_STM32WB_GPIO_MODE_ALTFN, - WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, - WHAL_STM32WB_GPIO_PULL_NONE, 5), - /* SPI1 MOSI: PA7, AF5 */ - [SPI_MOSI_PIN] = WHAL_STM32WB_GPIO_PIN( - WHAL_STM32WB_GPIO_PORT_A, 7, WHAL_STM32WB_GPIO_MODE_ALTFN, - WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, - WHAL_STM32WB_GPIO_PULL_NONE, 5), - /* SPI CS: PA4, output, push-pull */ - [SPI_CS_PIN] = WHAL_STM32WB_GPIO_PIN( - WHAL_STM32WB_GPIO_PORT_A, 4, WHAL_STM32WB_GPIO_MODE_OUT, - WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, - WHAL_STM32WB_GPIO_PULL_UP, 0), - /* I2C1 SCL: PB8, AF4, open-drain */ - [I2C_SCL_PIN] = WHAL_STM32WB_GPIO_PIN( - WHAL_STM32WB_GPIO_PORT_B, 8, WHAL_STM32WB_GPIO_MODE_ALTFN, - WHAL_STM32WB_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32WB_GPIO_SPEED_FAST, - WHAL_STM32WB_GPIO_PULL_UP, 4), - /* I2C1 SDA: PB9, AF4, open-drain */ - [I2C_SDA_PIN] = WHAL_STM32WB_GPIO_PIN( - WHAL_STM32WB_GPIO_PORT_B, 9, WHAL_STM32WB_GPIO_MODE_ALTFN, - WHAL_STM32WB_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32WB_GPIO_SPEED_FAST, - WHAL_STM32WB_GPIO_PULL_UP, 4), - }, - .pinCount = PIN_COUNT, - }, -}; +/* GPIO singleton lives in board.h as `static const`. */ /* I2C */ whal_I2c g_whalI2c = { @@ -130,18 +69,6 @@ whal_Spi g_whalSpi = { }, }; -/* Timer */ -whal_Timer g_whalTimer = { - .base = WHAL_CORTEX_M4_SYSTICK_BASE, - .driver = WHAL_CORTEX_M4_SYSTICK_DRIVER, - - .cfg = &(whal_SysTick_Cfg) { - .cyclesPerTick = 64000000 / 1000, - .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, - .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, - }, -}; - /* DMA */ #ifdef BOARD_DMA @@ -194,27 +121,11 @@ whal_Uart g_whalUart = { }; #endif -/* Flash */ +/* Flash — dispatcher stub. The const cfg lives in board.h as + * whal_Stm32wb_Flash_Dev; this only carries .driver so whal_Flash_* can + * dispatch through the vtable. */ whal_Flash g_whalFlash = { - .base = WHAL_STM32WB55_FLASH_BASE, .driver = WHAL_STM32WB55_FLASH_DRIVER, - - .cfg = &(whal_Stm32wb_Flash_Cfg) { - .timeout = &g_whalTimeout, - - .startAddr = 0x08000000, - .size = 0x80000, /* 512 KB (upper half reserved for BLE stack) */ - }, -}; - -/* RNG */ -whal_Rng g_whalRng = { - .base = WHAL_STM32WB55_RNG_BASE, - /* .driver: direct API mapping */ - - .cfg = &(whal_Stm32wb_Rng_Cfg) { - .timeout = &g_whalTimeout, - }, }; /* Crypto */ @@ -262,30 +173,6 @@ whal_AesCcm g_whalAesCcm = { .state = &g_aesCcmState, }; -#ifdef BOARD_WATCHDOG_IWDG -whal_Watchdog g_whalWatchdog = { - .base = WHAL_STM32WB55_IWDG_BASE, - .driver = WHAL_STM32WB55_IWDG_DRIVER, - - .cfg = &(whal_Stm32wb_Iwdg_Cfg) { - .prescaler = WHAL_STM32WB_IWDG_PR_32, - .reload = 100, - .timeout = &g_whalTimeout, - }, -}; -#elif defined(BOARD_WATCHDOG_WWDG) -whal_Watchdog g_whalWatchdog = { - .base = WHAL_STM32WB55_WWDG_BASE, - .driver = WHAL_STM32WB55_WWDG_DRIVER, - - .cfg = &(whal_Stm32wb_Wwdg_Cfg) { - .prescaler = WHAL_STM32WB_WWDG_TB_128, - .window = 0x7F, - .counter = 0x7F, - }, -}; -#endif - void Board_WaitMs(size_t ms) { uint32_t startCount = g_tick; @@ -337,7 +224,7 @@ whal_Error Board_Init(void) return err; } - err = whal_Irq_Init(&g_whalIrq); + err = whal_Irq_Init(WHAL_SINGLETON); if (err) return err; @@ -355,16 +242,16 @@ whal_Error Board_Init(void) return err; /* Enable NVIC interrupts for DMA1 channel 4 (IRQ 14) and channel 5 (IRQ 15) */ - err = whal_Irq_Enable(&g_whalIrq, 14, NULL); + err = whal_Irq_Enable(WHAL_SINGLETON, 14, NULL); if (err) return err; - err = whal_Irq_Enable(&g_whalIrq, 15, NULL); + err = whal_Irq_Enable(WHAL_SINGLETON, 15, NULL); if (err) return err; #endif - err = whal_Gpio_Init(&g_whalGpio); + err = whal_Gpio_Init(WHAL_SINGLETON); if (err) { return err; } @@ -389,7 +276,7 @@ whal_Error Board_Init(void) return err; } - err = whal_Rng_Init(&g_whalRng); + err = whal_Rng_Init(WHAL_SINGLETON); if (err) { return err; } @@ -399,12 +286,12 @@ whal_Error Board_Init(void) return err; } - err = whal_Timer_Init(&g_whalTimer); + err = whal_Timer_Init(WHAL_SINGLETON); if (err) { return err; } - err = whal_Timer_Start(&g_whalTimer); + err = whal_Timer_Start(WHAL_SINGLETON); if (err) { return err; } @@ -426,12 +313,12 @@ whal_Error Board_Deinit(void) return err; } - err = whal_Timer_Stop(&g_whalTimer); + err = whal_Timer_Stop(WHAL_SINGLETON); if (err) { return err; } - err = whal_Timer_Deinit(&g_whalTimer); + err = whal_Timer_Deinit(WHAL_SINGLETON); if (err) { return err; } @@ -442,7 +329,7 @@ whal_Error Board_Deinit(void) return err; } - err = whal_Rng_Deinit(&g_whalRng); + err = whal_Rng_Deinit(WHAL_SINGLETON); if (err) { return err; } @@ -467,14 +354,14 @@ whal_Error Board_Deinit(void) return err; } - err = whal_Gpio_Deinit(&g_whalGpio); + err = whal_Gpio_Deinit(WHAL_SINGLETON); if (err) { return err; } #ifdef BOARD_DMA - whal_Irq_Disable(&g_whalIrq, 14); - whal_Irq_Disable(&g_whalIrq, 15); + whal_Irq_Disable(WHAL_SINGLETON, 14); + whal_Irq_Disable(WHAL_SINGLETON, 15); err = whal_Dma_Deinit(&g_whalDma1); if (err) @@ -487,7 +374,7 @@ whal_Error Board_Deinit(void) return err; #endif - err = whal_Irq_Deinit(&g_whalIrq); + err = whal_Irq_Deinit(WHAL_SINGLETON); if (err) return err; diff --git a/boards/stm32wb55xx_nucleo/board.h b/boards/stm32wb55xx_nucleo/board.h index 16c928d..62520de 100644 --- a/boards/stm32wb55xx_nucleo/board.h +++ b/boards/stm32wb55xx_nucleo/board.h @@ -4,14 +4,12 @@ #include #include #include +#include extern whal_Clock g_whalClock; -extern whal_Gpio g_whalGpio; -extern whal_Timer g_whalTimer; extern whal_Uart g_whalUart; extern whal_Spi g_whalSpi; extern whal_Flash g_whalFlash; -extern whal_Rng g_whalRng; extern whal_Crypto g_whalCrypto; extern whal_AesEcb g_whalAesEcb; extern whal_AesCbc g_whalAesCbc; @@ -20,8 +18,6 @@ extern whal_AesGcm g_whalAesGcm; extern whal_AesGmac g_whalAesGmac; extern whal_AesCcm g_whalAesCcm; extern whal_I2c g_whalI2c; -extern whal_Irq g_whalIrq; -extern whal_Watchdog g_whalWatchdog; extern whal_Timeout g_whalTimeout; extern volatile uint32_t g_tick; @@ -46,6 +42,161 @@ enum { #define BOARD_FLASH_SECTOR_SZ 0x1000 +/* GPIO singleton — referenced by stm32wb_gpio.c directly. */ +static const whal_Gpio whal_Stm32wb_Gpio_Dev = { + .base = WHAL_STM32WB55_GPIO_BASE, + .cfg = (void *)&(const whal_Stm32wb_Gpio_Cfg){ + .pinCfg = (const whal_Stm32wb_Gpio_PinCfg[PIN_COUNT]){ + [LED_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_B, 5, WHAL_STM32WB_GPIO_MODE_OUT, + WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_LOW, + WHAL_STM32WB_GPIO_PULL_UP, 0), + [UART_TX_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_B, 6, WHAL_STM32WB_GPIO_MODE_ALTFN, + WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, + WHAL_STM32WB_GPIO_PULL_UP, 7), + [UART_RX_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_B, 7, WHAL_STM32WB_GPIO_MODE_ALTFN, + WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, + WHAL_STM32WB_GPIO_PULL_UP, 7), + [SPI_SCK_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_A, 5, WHAL_STM32WB_GPIO_MODE_ALTFN, + WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, + WHAL_STM32WB_GPIO_PULL_NONE, 5), + [SPI_MISO_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_A, 6, WHAL_STM32WB_GPIO_MODE_ALTFN, + WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, + WHAL_STM32WB_GPIO_PULL_NONE, 5), + [SPI_MOSI_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_A, 7, WHAL_STM32WB_GPIO_MODE_ALTFN, + WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, + WHAL_STM32WB_GPIO_PULL_NONE, 5), + [SPI_CS_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_A, 4, WHAL_STM32WB_GPIO_MODE_OUT, + WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, + WHAL_STM32WB_GPIO_PULL_UP, 0), + [I2C_SCL_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_B, 8, WHAL_STM32WB_GPIO_MODE_ALTFN, + WHAL_STM32WB_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32WB_GPIO_SPEED_FAST, + WHAL_STM32WB_GPIO_PULL_UP, 4), + [I2C_SDA_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_B, 9, WHAL_STM32WB_GPIO_MODE_ALTFN, + WHAL_STM32WB_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32WB_GPIO_SPEED_FAST, + WHAL_STM32WB_GPIO_PULL_UP, 4), + }, + .pinCount = PIN_COUNT, + }, +}; + +/* AES crypto + mode singletons — referenced by stm32wb_aes.c directly. */ +static const whal_Crypto whal_Stm32wb_Aes_Dev = { + .base = WHAL_STM32WB55_AES1_BASE, + /* .driver: direct API mapping */ + .cfg = (void *)&(const whal_Stm32wb_Aes_Cfg){ + .timeout = &g_whalTimeout, + }, +}; + +static const whal_AesEcb whal_Stm32wb_AesEcb_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wb_Aes_Dev, + /* .driver: direct API mapping */ +}; + +static const whal_AesCbc whal_Stm32wb_AesCbc_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wb_Aes_Dev, + /* .driver: direct API mapping */ +}; + +static const whal_AesCtr whal_Stm32wb_AesCtr_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wb_Aes_Dev, + /* .driver: direct API mapping */ +}; + +static whal_Stm32wb_AesGcm_State g_aesGcmDevState; +static const whal_AesGcm whal_Stm32wb_AesGcm_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wb_Aes_Dev, + /* .driver: direct API mapping */ + .state = &g_aesGcmDevState, +}; + +static const whal_AesGmac whal_Stm32wb_AesGmac_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wb_Aes_Dev, + /* .driver: direct API mapping */ +}; + +static whal_Stm32wb_AesCcm_State g_aesCcmDevState; +static const whal_AesCcm whal_Stm32wb_AesCcm_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wb_Aes_Dev, + /* .driver: direct API mapping */ + .state = &g_aesCcmDevState, +}; + +/* Flash singleton — referenced by stm32wb_flash.c directly. Const cfg lives + * here; the dispatcher stub g_whalFlash in board.c carries only .driver so + * whal_Flash_* can be vtable-dispatched alongside other flash drivers (e.g. + * SPI NOR W25Q64). */ +static const whal_Flash whal_Stm32wb_Flash_Dev = { + .base = WHAL_STM32WB55_FLASH_BASE, + + .cfg = (void *)&(const whal_Stm32wb_Flash_Cfg){ + .timeout = &g_whalTimeout, + .startAddr = 0x08000000, + .size = 0x80000, /* 512 KB (upper half reserved for BLE stack) */ + }, +}; + +/* IWDG singleton — referenced by stm32wb_iwdg.c directly. */ +static const whal_Watchdog whal_Stm32wb_Iwdg_Dev = { + .base = WHAL_STM32WB55_IWDG_BASE, + /* .driver: direct API mapping */ + + .cfg = (void *)&(const whal_Stm32wb_Iwdg_Cfg){ + .prescaler = WHAL_STM32WB_IWDG_PR_32, + .reload = 100, + .timeout = &g_whalTimeout, + }, +}; + +/* WWDG singleton — referenced by stm32wb_wwdg.c directly. */ +static const whal_Watchdog whal_Stm32wb_Wwdg_Dev = { + .base = WHAL_STM32WB55_WWDG_BASE, + /* .driver: direct API mapping */ + + .cfg = (void *)&(const whal_Stm32wb_Wwdg_Cfg){ + .prescaler = WHAL_STM32WB_WWDG_TB_128, + .window = 0x7F, + .counter = 0x7F, + }, +}; + +/* RNG singleton — referenced by stm32wb_rng.c directly. */ +static const whal_Rng whal_Stm32wb_Rng_Dev = { + .base = WHAL_STM32WB55_RNG_BASE, + /* .driver: direct API mapping */ + + .cfg = (void *)&(const whal_Stm32wb_Rng_Cfg){ + .timeout = &g_whalTimeout, + }, +}; + +/* NVIC singleton — referenced by cortex_m4_nvic.c directly. */ +static const whal_Irq whal_Nvic_Dev = { + .base = WHAL_CORTEX_M4_NVIC_BASE, + /* .driver: direct API mapping */ +}; + +/* SysTick singleton — referenced by systick.c directly. */ +static const whal_Timer whal_SysTick_Dev = { + .base = WHAL_CORTEX_M4_SYSTICK_BASE, + /* .driver: direct API mapping */ + + .cfg = (void *)&(const whal_SysTick_Cfg){ + .cyclesPerTick = 64000000 / 1000, + .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, + .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, + }, +}; + whal_Error Board_Init(void); whal_Error Board_Deinit(void); void Board_WaitMs(size_t ms); diff --git a/boards/stm32wb55xx_nucleo/board.mk b/boards/stm32wb55xx_nucleo/board.mk index 1e606e2..0cb0427 100644 --- a/boards/stm32wb55xx_nucleo/board.mk +++ b/boards/stm32wb55xx_nucleo/board.mk @@ -11,8 +11,8 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -ffreestanding -nostdlib -mcpu=cortex-m4 \ -DPLATFORM_STM32WB -MMD -MP \ $(if $(DMA),-DBOARD_DMA) \ - $(if $(filter iwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_IWDG) \ - $(if $(filter wwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_WWDG) \ + $(if $(filter iwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_IWDG -DWHAL_CFG_STM32WB_IWDG_DIRECT_API_MAPPING) \ + $(if $(filter wwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_WWDG -DWHAL_CFG_STM32WB_WWDG_DIRECT_API_MAPPING) \ $(if $(DMA),-DWHAL_CFG_STM32WB_UART_DMA_DIRECT_API_MAPPING,-DWHAL_CFG_STM32WB_UART_DIRECT_API_MAPPING) \ -DWHAL_CFG_STM32WB_GPIO_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32WB_SPI_DIRECT_API_MAPPING \ @@ -26,7 +26,9 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -DWHAL_CFG_STM32WB_AES_CTR_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32WB_AES_GCM_DIRECT_API_MAPPING \ -DWHAL_CFG_STM32WB_AES_GMAC_DIRECT_API_MAPPING \ - -DWHAL_CFG_STM32WB_AES_CCM_DIRECT_API_MAPPING + -DWHAL_CFG_STM32WB_AES_CCM_DIRECT_API_MAPPING \ + -DWHAL_CFG_SYSTICK_TIMER_DIRECT_API_MAPPING \ + -DWHAL_CFG_NVIC_IRQ_DIRECT_API_MAPPING LDFLAGS = --omagic -static --gc-sections LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld @@ -36,12 +38,9 @@ INCLUDE += -I$(_BOARD_DIR) -I$(WHAL_DIR)/boards/peripheral BOARD_SOURCE = $(_BOARD_DIR)/ivt.c BOARD_SOURCE += $(_BOARD_DIR)/board.c BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*.c) -BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/timer.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/flash.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/sensor.c) -BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/watchdog.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/block.c) -BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/irq.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/irq/cortex_m4_nvic.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/stm32wb_*.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/systick.c) diff --git a/boards/stm32wba55cg_nucleo/board.c b/boards/stm32wba55cg_nucleo/board.c index 5deefd4..b6ce527 100644 --- a/boards/stm32wba55cg_nucleo/board.c +++ b/boards/stm32wba55cg_nucleo/board.c @@ -24,12 +24,6 @@ whal_Timeout g_whalTimeout = { .GetTick = Board_GetTick, }; -/* IRQ */ -whal_Irq g_whalIrq = { - .base = WHAL_CORTEX_M33_NVIC_BASE, - .driver = WHAL_CORTEX_M33_NVIC_DRIVER, -}; - /* Clock: PLL1 from HSE32, targeting 100 MHz * HSE32 = 32 MHz * PLL1M = 1 (div 2) -> ref_ck = 16 MHz @@ -59,62 +53,6 @@ static const whal_Stm32wba_Rcc_PeriphClk g_periphClks[] = { }; #define PERIPH_CLK_COUNT (sizeof(g_periphClks) / sizeof(g_periphClks[0])) -/* GPIO */ -whal_Gpio g_whalGpio = { - .base = WHAL_STM32WBA55_GPIO_BASE, - .driver = WHAL_STM32WBA55_GPIO_DRIVER, - - .cfg = &(whal_Stm32wba_Gpio_Cfg) { - .pinCfg = (whal_Stm32wba_Gpio_PinCfg[PIN_COUNT]) { - /* LED: PA9 (LD2, Green), output, push-pull, low speed, pull-up */ - [LED_PIN] = WHAL_STM32WBA_GPIO_PIN( - WHAL_STM32WBA_GPIO_PORT_A, 9, WHAL_STM32WBA_GPIO_MODE_OUT, - WHAL_STM32WBA_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WBA_GPIO_SPEED_LOW, - WHAL_STM32WBA_GPIO_PULL_UP, 0), - /* USART1 TX: PB12, AF7 */ - [UART_TX_PIN] = WHAL_STM32WBA_GPIO_PIN( - WHAL_STM32WBA_GPIO_PORT_B, 12, WHAL_STM32WBA_GPIO_MODE_ALTFN, - WHAL_STM32WBA_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WBA_GPIO_SPEED_FAST, - WHAL_STM32WBA_GPIO_PULL_UP, 7), - /* USART1 RX: PA8, AF7 */ - [UART_RX_PIN] = WHAL_STM32WBA_GPIO_PIN( - WHAL_STM32WBA_GPIO_PORT_A, 8, WHAL_STM32WBA_GPIO_MODE_ALTFN, - WHAL_STM32WBA_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WBA_GPIO_SPEED_FAST, - WHAL_STM32WBA_GPIO_PULL_UP, 7), - /* SPI1 SCK: PB4, AF5 */ - [SPI_SCK_PIN] = WHAL_STM32WBA_GPIO_PIN( - WHAL_STM32WBA_GPIO_PORT_B, 4, WHAL_STM32WBA_GPIO_MODE_ALTFN, - WHAL_STM32WBA_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WBA_GPIO_SPEED_FAST, - WHAL_STM32WBA_GPIO_PULL_NONE, 5), - /* SPI1 MISO: PB3, AF5 */ - [SPI_MISO_PIN] = WHAL_STM32WBA_GPIO_PIN( - WHAL_STM32WBA_GPIO_PORT_B, 3, WHAL_STM32WBA_GPIO_MODE_ALTFN, - WHAL_STM32WBA_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WBA_GPIO_SPEED_FAST, - WHAL_STM32WBA_GPIO_PULL_NONE, 5), - /* SPI1 MOSI: PA15, AF5 */ - [SPI_MOSI_PIN] = WHAL_STM32WBA_GPIO_PIN( - WHAL_STM32WBA_GPIO_PORT_A, 15, WHAL_STM32WBA_GPIO_MODE_ALTFN, - WHAL_STM32WBA_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WBA_GPIO_SPEED_FAST, - WHAL_STM32WBA_GPIO_PULL_NONE, 5), - /* SPI CS: PA12, output, push-pull */ - [SPI_CS_PIN] = WHAL_STM32WBA_GPIO_PIN( - WHAL_STM32WBA_GPIO_PORT_A, 12, WHAL_STM32WBA_GPIO_MODE_OUT, - WHAL_STM32WBA_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WBA_GPIO_SPEED_FAST, - WHAL_STM32WBA_GPIO_PULL_UP, 0), - /* I2C1 SCL: PB2, AF4, open-drain */ - [I2C_SCL_PIN] = WHAL_STM32WBA_GPIO_PIN( - WHAL_STM32WBA_GPIO_PORT_B, 2, WHAL_STM32WBA_GPIO_MODE_ALTFN, - WHAL_STM32WBA_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32WBA_GPIO_SPEED_FAST, - WHAL_STM32WBA_GPIO_PULL_UP, 4), - /* I2C1 SDA: PB1, AF4, open-drain */ - [I2C_SDA_PIN] = WHAL_STM32WBA_GPIO_PIN( - WHAL_STM32WBA_GPIO_PORT_B, 1, WHAL_STM32WBA_GPIO_MODE_ALTFN, - WHAL_STM32WBA_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32WBA_GPIO_SPEED_FAST, - WHAL_STM32WBA_GPIO_PULL_UP, 4), - }, - .pinCount = PIN_COUNT, - }, -}; /* I2C */ whal_I2c g_whalI2c = { @@ -138,18 +76,6 @@ whal_Spi g_whalSpi = { }, }; -/* Timer (SysTick at 100 MHz) */ -whal_Timer g_whalTimer = { - .base = WHAL_CORTEX_M33_SYSTICK_BASE, - .driver = WHAL_CORTEX_M33_SYSTICK_DRIVER, - - .cfg = &(whal_SysTick_Cfg) { - .cyclesPerTick = 100000000 / 1000, - .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, - .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, - }, -}; - /* DMA */ #ifdef BOARD_DMA @@ -450,7 +376,7 @@ whal_Error Board_Init(void) return err; } - err = whal_Irq_Init(&g_whalIrq); + err = whal_Irq_Init(WHAL_SINGLETON); if (err) return err; @@ -463,15 +389,15 @@ whal_Error Board_Init(void) return err; /* Enable NVIC interrupts for GPDMA1 channel 0 (IRQ 29) and channel 1 (IRQ 30) */ - err = whal_Irq_Enable(&g_whalIrq, 29, NULL); + err = whal_Irq_Enable(WHAL_SINGLETON, 29, NULL); if (err) return err; - err = whal_Irq_Enable(&g_whalIrq, 30, NULL); + err = whal_Irq_Enable(WHAL_SINGLETON, 30, NULL); if (err) return err; #endif - err = whal_Gpio_Init(&g_whalGpio); + err = whal_Gpio_Init(WHAL_SINGLETON); if (err) return err; @@ -499,11 +425,11 @@ whal_Error Board_Init(void) if (err) return err; - err = whal_Timer_Init(&g_whalTimer); + err = whal_Timer_Init(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Start(&g_whalTimer); + err = whal_Timer_Start(WHAL_SINGLETON); if (err) return err; @@ -522,11 +448,11 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Timer_Stop(&g_whalTimer); + err = whal_Timer_Stop(WHAL_SINGLETON); if (err) return err; - err = whal_Timer_Deinit(&g_whalTimer); + err = whal_Timer_Deinit(WHAL_SINGLETON); if (err) return err; @@ -554,13 +480,13 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Gpio_Deinit(&g_whalGpio); + err = whal_Gpio_Deinit(WHAL_SINGLETON); if (err) return err; #ifdef BOARD_DMA - whal_Irq_Disable(&g_whalIrq, 29); - whal_Irq_Disable(&g_whalIrq, 30); + whal_Irq_Disable(WHAL_SINGLETON, 29); + whal_Irq_Disable(WHAL_SINGLETON, 30); err = whal_Dma_Deinit(&g_whalDma1); if (err) @@ -570,7 +496,7 @@ whal_Error Board_Deinit(void) return err; #endif - err = whal_Irq_Deinit(&g_whalIrq); + err = whal_Irq_Deinit(WHAL_SINGLETON); if (err) return err; diff --git a/boards/stm32wba55cg_nucleo/board.h b/boards/stm32wba55cg_nucleo/board.h index de040f6..40a90a5 100644 --- a/boards/stm32wba55cg_nucleo/board.h +++ b/boards/stm32wba55cg_nucleo/board.h @@ -4,12 +4,11 @@ #include #include #include +#include #include #include extern whal_Clock g_whalClock; -extern whal_Gpio g_whalGpio; -extern whal_Timer g_whalTimer; extern whal_Uart g_whalUart; extern whal_Spi g_whalSpi; extern whal_Flash g_whalFlash; @@ -29,7 +28,6 @@ extern whal_Sha256 g_whalSha256; extern whal_HmacSha1 g_whalHmacSha1; extern whal_HmacSha224 g_whalHmacSha224; extern whal_HmacSha256 g_whalHmacSha256; -extern whal_Irq g_whalIrq; extern whal_Watchdog g_whalWatchdog; #ifdef BOARD_DMA extern whal_Dma g_whalDma1; @@ -58,6 +56,80 @@ enum { #define BOARD_FLASH_TEST_ADDR 0x080FE000 #define BOARD_FLASH_SECTOR_SZ 0x2000 /* 8 KB */ +static const whal_Gpio whal_Stm32wba_Gpio_Dev = { + .base = WHAL_STM32WBA55_GPIO_BASE, + .driver = WHAL_STM32WBA55_GPIO_DRIVER, + + .cfg = (void *)&(const whal_Stm32wba_Gpio_Cfg){ + .pinCfg = (const whal_Stm32wba_Gpio_PinCfg[PIN_COUNT]){ + /* LED: PA9 (LD2, Green), output, push-pull, low speed, pull-up */ + [LED_PIN] = WHAL_STM32WBA_GPIO_PIN( + WHAL_STM32WBA_GPIO_PORT_A, 9, WHAL_STM32WBA_GPIO_MODE_OUT, + WHAL_STM32WBA_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WBA_GPIO_SPEED_LOW, + WHAL_STM32WBA_GPIO_PULL_UP, 0), + /* USART1 TX: PB12, AF7 */ + [UART_TX_PIN] = WHAL_STM32WBA_GPIO_PIN( + WHAL_STM32WBA_GPIO_PORT_B, 12, WHAL_STM32WBA_GPIO_MODE_ALTFN, + WHAL_STM32WBA_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WBA_GPIO_SPEED_FAST, + WHAL_STM32WBA_GPIO_PULL_UP, 7), + /* USART1 RX: PA8, AF7 */ + [UART_RX_PIN] = WHAL_STM32WBA_GPIO_PIN( + WHAL_STM32WBA_GPIO_PORT_A, 8, WHAL_STM32WBA_GPIO_MODE_ALTFN, + WHAL_STM32WBA_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WBA_GPIO_SPEED_FAST, + WHAL_STM32WBA_GPIO_PULL_UP, 7), + /* SPI1 SCK: PB4, AF5 */ + [SPI_SCK_PIN] = WHAL_STM32WBA_GPIO_PIN( + WHAL_STM32WBA_GPIO_PORT_B, 4, WHAL_STM32WBA_GPIO_MODE_ALTFN, + WHAL_STM32WBA_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WBA_GPIO_SPEED_FAST, + WHAL_STM32WBA_GPIO_PULL_NONE, 5), + /* SPI1 MISO: PB3, AF5 */ + [SPI_MISO_PIN] = WHAL_STM32WBA_GPIO_PIN( + WHAL_STM32WBA_GPIO_PORT_B, 3, WHAL_STM32WBA_GPIO_MODE_ALTFN, + WHAL_STM32WBA_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WBA_GPIO_SPEED_FAST, + WHAL_STM32WBA_GPIO_PULL_NONE, 5), + /* SPI1 MOSI: PA15, AF5 */ + [SPI_MOSI_PIN] = WHAL_STM32WBA_GPIO_PIN( + WHAL_STM32WBA_GPIO_PORT_A, 15, WHAL_STM32WBA_GPIO_MODE_ALTFN, + WHAL_STM32WBA_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WBA_GPIO_SPEED_FAST, + WHAL_STM32WBA_GPIO_PULL_NONE, 5), + /* SPI CS: PA12, output, push-pull */ + [SPI_CS_PIN] = WHAL_STM32WBA_GPIO_PIN( + WHAL_STM32WBA_GPIO_PORT_A, 12, WHAL_STM32WBA_GPIO_MODE_OUT, + WHAL_STM32WBA_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WBA_GPIO_SPEED_FAST, + WHAL_STM32WBA_GPIO_PULL_UP, 0), + /* I2C1 SCL: PB2, AF4, open-drain */ + [I2C_SCL_PIN] = WHAL_STM32WBA_GPIO_PIN( + WHAL_STM32WBA_GPIO_PORT_B, 2, WHAL_STM32WBA_GPIO_MODE_ALTFN, + WHAL_STM32WBA_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32WBA_GPIO_SPEED_FAST, + WHAL_STM32WBA_GPIO_PULL_UP, 4), + /* I2C1 SDA: PB1, AF4, open-drain */ + [I2C_SDA_PIN] = WHAL_STM32WBA_GPIO_PIN( + WHAL_STM32WBA_GPIO_PORT_B, 1, WHAL_STM32WBA_GPIO_MODE_ALTFN, + WHAL_STM32WBA_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32WBA_GPIO_SPEED_FAST, + WHAL_STM32WBA_GPIO_PULL_UP, 4), + }, + .pinCount = PIN_COUNT, + }, +}; + +/* NVIC singleton — referenced by cortex_m4_nvic.c directly. */ +static const whal_Irq whal_Nvic_Dev = { + .base = WHAL_CORTEX_M33_NVIC_BASE, + /* .driver: direct API mapping */ +}; + +/* SysTick singleton — referenced by systick.c directly. */ +static const whal_Timer whal_SysTick_Dev = { + .base = WHAL_CORTEX_M33_SYSTICK_BASE, + /* .driver: direct API mapping */ + + .cfg = (void *)&(const whal_SysTick_Cfg){ + .cyclesPerTick = 100000000 / 1000, + .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, + .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, + }, +}; + whal_Error Board_Init(void); whal_Error Board_Deinit(void); void Board_WaitMs(size_t ms); diff --git a/boards/stm32wba55cg_nucleo/board.mk b/boards/stm32wba55cg_nucleo/board.mk index 4e9fd86..b0b45f3 100644 --- a/boards/stm32wba55cg_nucleo/board.mk +++ b/boards/stm32wba55cg_nucleo/board.mk @@ -25,7 +25,9 @@ CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ -DWHAL_CFG_STM32WBA_HASH_HMAC_SHA256_DIRECT_API_MAPPING \ $(if $(DMA),-DBOARD_DMA) \ $(if $(filter iwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_IWDG) \ - $(if $(filter wwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_WWDG) + $(if $(filter wwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_WWDG) \ + -DWHAL_CFG_SYSTICK_TIMER_DIRECT_API_MAPPING \ + -DWHAL_CFG_NVIC_IRQ_DIRECT_API_MAPPING LDFLAGS = --omagic -static --gc-sections LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld @@ -38,7 +40,6 @@ BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/gpio.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/clock.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/uart.c) -BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/timer.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/flash.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/spi.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/i2c.c) @@ -48,7 +49,6 @@ BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/rng.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/crypto.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/block.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/dma.c) -BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/irq.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/irq/cortex_m4_nvic.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/stm32wba_*.c) BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/systick.c) diff --git a/examples/blinky/main.c b/examples/blinky/main.c index 89760d6..9f5ab96 100644 --- a/examples/blinky/main.c +++ b/examples/blinky/main.c @@ -8,10 +8,10 @@ void main(void) goto loop; while (1) { - whal_Gpio_Set(&g_whalGpio, BOARD_LED_PIN, 1); + whal_Gpio_Set(WHAL_SINGLETON, BOARD_LED_PIN, 1); whal_Uart_Send(&g_whalUart, "Blink!\r\n", 8); Board_WaitMs(1000); - whal_Gpio_Set(&g_whalGpio, BOARD_LED_PIN, 0); + whal_Gpio_Set(WHAL_SINGLETON, BOARD_LED_PIN, 0); whal_Uart_Send(&g_whalUart, "Blink!\r\n", 8); Board_WaitMs(1000); } diff --git a/src/clock/stm32h5_rcc.c b/src/clock/stm32h5_rcc.c deleted file mode 100644 index 9e9e9c5..0000000 --- a/src/clock/stm32h5_rcc.c +++ /dev/null @@ -1,163 +0,0 @@ -#include -#include -#include -#include -#include - -#define RCC_CR_REG 0x000 -#define RCC_CR_HSIDIV_Pos 3 -#define RCC_CR_HSIDIV_Msk (WHAL_BITMASK(2) << RCC_CR_HSIDIV_Pos) -#define RCC_CR_PLL1ON_Msk (1UL << 24) -#define RCC_CR_PLL1RDY_Msk (1UL << 25) -#define RCC_CR_PLL1RDY_Pos 25 - -#define RCC_CFGR1_REG 0x01C -#define RCC_CFGR1_SW_Pos 0 -#define RCC_CFGR1_SW_Msk (WHAL_BITMASK(2) << RCC_CFGR1_SW_Pos) -#define RCC_CFGR1_SWS_Pos 3 -#define RCC_CFGR1_SWS_Msk (WHAL_BITMASK(2) << RCC_CFGR1_SWS_Pos) - -#define RCC_PLL1CFGR_REG 0x028 -#define RCC_PLL1CFGR_PLL1SRC_Pos 0 -#define RCC_PLL1CFGR_PLL1SRC_Msk (WHAL_BITMASK(2) << RCC_PLL1CFGR_PLL1SRC_Pos) -#define RCC_PLL1CFGR_PLL1RGE_Pos 2 -#define RCC_PLL1CFGR_PLL1RGE_Msk (WHAL_BITMASK(2) << RCC_PLL1CFGR_PLL1RGE_Pos) -#define RCC_PLL1CFGR_PLL1M_Pos 8 -#define RCC_PLL1CFGR_PLL1M_Msk (WHAL_BITMASK(6) << RCC_PLL1CFGR_PLL1M_Pos) -#define RCC_PLL1CFGR_PLL1PEN_Pos 16 -#define RCC_PLL1CFGR_PLL1PEN_Msk (1UL << RCC_PLL1CFGR_PLL1PEN_Pos) -#define RCC_PLL1CFGR_PLL1QEN_Pos 17 -#define RCC_PLL1CFGR_PLL1QEN_Msk (1UL << RCC_PLL1CFGR_PLL1QEN_Pos) -#define RCC_PLL1CFGR_PLL1REN_Pos 18 -#define RCC_PLL1CFGR_PLL1REN_Msk (1UL << RCC_PLL1CFGR_PLL1REN_Pos) - -#define RCC_PLL1DIVR_REG 0x034 -#define RCC_PLL1DIVR_PLL1N_Pos 0 -#define RCC_PLL1DIVR_PLL1N_Msk (WHAL_BITMASK(9) << RCC_PLL1DIVR_PLL1N_Pos) -#define RCC_PLL1DIVR_PLL1P_Pos 9 -#define RCC_PLL1DIVR_PLL1P_Msk (WHAL_BITMASK(7) << RCC_PLL1DIVR_PLL1P_Pos) -#define RCC_PLL1DIVR_PLL1Q_Pos 16 -#define RCC_PLL1DIVR_PLL1Q_Msk (WHAL_BITMASK(7) << RCC_PLL1DIVR_PLL1Q_Pos) -#define RCC_PLL1DIVR_PLL1R_Pos 24 -#define RCC_PLL1DIVR_PLL1R_Msk (WHAL_BITMASK(7) << RCC_PLL1DIVR_PLL1R_Pos) - -whal_Error whal_Stm32h5_Rcc_EnableOsc(whal_Clock *clkDev, - const whal_Stm32h5_Rcc_OscCfg *cfg) -{ - size_t rdy; - - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); - do { - whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, - cfg->rdyPos, &rdy); - } while (!rdy); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32h5_Rcc_DisableOsc(whal_Clock *clkDev, - const whal_Stm32h5_Rcc_OscCfg *cfg) -{ - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32h5_Rcc_EnablePll1(whal_Clock *clkDev, - const whal_Stm32h5_Rcc_PllCfg *cfg) -{ - size_t rdy; - - if (!clkDev || !cfg) - return WHAL_EINVAL; - - /* Disable PLL1 before reconfiguring; wait until off. */ - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); - do { - whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLL1RDY_Msk, - RCC_CR_PLL1RDY_Pos, &rdy); - } while (rdy); - - whal_Reg_Update(clkDev->base, RCC_PLL1CFGR_REG, - RCC_PLL1CFGR_PLL1SRC_Msk | RCC_PLL1CFGR_PLL1M_Msk | - RCC_PLL1CFGR_PLL1PEN_Msk | RCC_PLL1CFGR_PLL1QEN_Msk | - RCC_PLL1CFGR_PLL1REN_Msk, - whal_SetBits(RCC_PLL1CFGR_PLL1SRC_Msk, RCC_PLL1CFGR_PLL1SRC_Pos, cfg->clkSrc) | - whal_SetBits(RCC_PLL1CFGR_PLL1M_Msk, RCC_PLL1CFGR_PLL1M_Pos, cfg->m) | - whal_SetBits(RCC_PLL1CFGR_PLL1PEN_Msk, RCC_PLL1CFGR_PLL1PEN_Pos, 1) | - whal_SetBits(RCC_PLL1CFGR_PLL1QEN_Msk, RCC_PLL1CFGR_PLL1QEN_Pos, 1) | - whal_SetBits(RCC_PLL1CFGR_PLL1REN_Msk, RCC_PLL1CFGR_PLL1REN_Pos, 1)); - whal_Reg_Update(clkDev->base, RCC_PLL1DIVR_REG, - RCC_PLL1DIVR_PLL1N_Msk | RCC_PLL1DIVR_PLL1P_Msk | - RCC_PLL1DIVR_PLL1Q_Msk | RCC_PLL1DIVR_PLL1R_Msk, - whal_SetBits(RCC_PLL1DIVR_PLL1N_Msk, RCC_PLL1DIVR_PLL1N_Pos, cfg->n) | - whal_SetBits(RCC_PLL1DIVR_PLL1P_Msk, RCC_PLL1DIVR_PLL1P_Pos, cfg->p) | - whal_SetBits(RCC_PLL1DIVR_PLL1Q_Msk, RCC_PLL1DIVR_PLL1Q_Pos, cfg->q) | - whal_SetBits(RCC_PLL1DIVR_PLL1R_Msk, RCC_PLL1DIVR_PLL1R_Pos, cfg->r)); - - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, - RCC_CR_PLL1ON_Msk); - do { - whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLL1RDY_Msk, - RCC_CR_PLL1RDY_Pos, &rdy); - } while (!rdy); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32h5_Rcc_DisablePll1(whal_Clock *clkDev) -{ - if (!clkDev) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32h5_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32h5_Rcc_SysClockSrc src) -{ - size_t sws; - - if (!clkDev) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, RCC_CFGR1_REG, RCC_CFGR1_SW_Msk, - whal_SetBits(RCC_CFGR1_SW_Msk, RCC_CFGR1_SW_Pos, src)); - do { - whal_Reg_Get(clkDev->base, RCC_CFGR1_REG, RCC_CFGR1_SWS_Msk, - RCC_CFGR1_SWS_Pos, &sws); - } while (sws != (size_t)src); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32h5_Rcc_SetHsiDiv(whal_Clock *clkDev, uint8_t div) -{ - if (!clkDev) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_HSIDIV_Msk, - whal_SetBits(RCC_CR_HSIDIV_Msk, RCC_CR_HSIDIV_Pos, div)); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32h5_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32h5_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32h5_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32h5_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); - return WHAL_SUCCESS; -} diff --git a/src/clock/stm32wb_rcc.c b/src/clock/stm32wb_rcc.c deleted file mode 100644 index c40ac93..0000000 --- a/src/clock/stm32wb_rcc.c +++ /dev/null @@ -1,167 +0,0 @@ -#include -#include -#include -#include -#include - -/* - * STM32WB RCC Register Definitions - */ - -/* Clock Control Register */ -#define RCC_CR_REG 0x000 -#define RCC_CR_MSION_Msk (1UL << 0) -#define RCC_CR_MSIRDY_Msk (1UL << 1) -#define RCC_CR_MSIRDY_Pos 1 -#define RCC_CR_MSIRANGE_Pos 4 -#define RCC_CR_MSIRANGE_Msk (WHAL_BITMASK(4) << RCC_CR_MSIRANGE_Pos) -#define RCC_CR_PLLON_Msk (1UL << 24) -#define RCC_CR_PLLRDY_Msk (1UL << 25) -#define RCC_CR_PLLRDY_Pos 25 - -/* Clock Configuration Register */ -#define RCC_CFGR_REG 0x008 -#define RCC_CFGR_SW_Pos 0 -#define RCC_CFGR_SW_Msk (WHAL_BITMASK(2) << RCC_CFGR_SW_Pos) -#define RCC_CFGR_SWS_Pos 2 -#define RCC_CFGR_SWS_Msk (WHAL_BITMASK(2) << RCC_CFGR_SWS_Pos) - -/* PLL Configuration Register */ -#define RCC_PLLCFGR_REG 0x00C -#define RCC_PLLCFGR_PLLSRC_Pos 0 -#define RCC_PLLCFGR_PLLSRC_Msk (WHAL_BITMASK(2) << RCC_PLLCFGR_PLLSRC_Pos) -#define RCC_PLLCFGR_PLLM_Pos 4 -#define RCC_PLLCFGR_PLLM_Msk (WHAL_BITMASK(3) << RCC_PLLCFGR_PLLM_Pos) -#define RCC_PLLCFGR_PLLN_Pos 8 -#define RCC_PLLCFGR_PLLN_Msk (WHAL_BITMASK(7) << RCC_PLLCFGR_PLLN_Pos) -#define RCC_PLLCFGR_PLLP_Pos 17 -#define RCC_PLLCFGR_PLLP_Msk (WHAL_BITMASK(5) << RCC_PLLCFGR_PLLP_Pos) -#define RCC_PLLCFGR_PLLQ_Pos 25 -#define RCC_PLLCFGR_PLLQ_Msk (WHAL_BITMASK(3) << RCC_PLLCFGR_PLLQ_Pos) -#define RCC_PLLCFGR_PLLREN_Pos 28 -#define RCC_PLLCFGR_PLLREN_Msk (1UL << RCC_PLLCFGR_PLLREN_Pos) -#define RCC_PLLCFGR_PLLR_Pos 29 -#define RCC_PLLCFGR_PLLR_Msk (WHAL_BITMASK(3) << RCC_PLLCFGR_PLLR_Pos) -#define RCC_PLLCFGR_Msk \ - (RCC_PLLCFGR_PLLSRC_Msk | RCC_PLLCFGR_PLLM_Msk | RCC_PLLCFGR_PLLN_Msk | \ - RCC_PLLCFGR_PLLP_Msk | RCC_PLLCFGR_PLLQ_Msk | RCC_PLLCFGR_PLLREN_Msk | \ - RCC_PLLCFGR_PLLR_Msk) - -whal_Error whal_Stm32wb_Rcc_EnableOsc(whal_Clock *clkDev, - const whal_Stm32wb_Rcc_OscCfg *cfg) -{ - size_t rdy; - - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); - do { - whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, - cfg->rdyPos, &rdy); - } while (!rdy); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32wb_Rcc_DisableOsc(whal_Clock *clkDev, - const whal_Stm32wb_Rcc_OscCfg *cfg) -{ - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32wb_Rcc_EnableMsi(whal_Clock *clkDev, - whal_Stm32wb_Rcc_MsiRange range) -{ - size_t rdy; - - if (!clkDev) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_MSION_Msk, - RCC_CR_MSION_Msk); - do { - whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_MSIRDY_Msk, - RCC_CR_MSIRDY_Pos, &rdy); - } while (!rdy); - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_MSIRANGE_Msk, - whal_SetBits(RCC_CR_MSIRANGE_Msk, RCC_CR_MSIRANGE_Pos, - range)); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32wb_Rcc_EnablePll(whal_Clock *clkDev, - const whal_Stm32wb_Rcc_PllCfg *cfg) -{ - size_t rdy; - - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, RCC_PLLCFGR_REG, RCC_PLLCFGR_Msk, - whal_SetBits(RCC_PLLCFGR_PLLSRC_Msk, RCC_PLLCFGR_PLLSRC_Pos, cfg->clkSrc) | - whal_SetBits(RCC_PLLCFGR_PLLM_Msk, RCC_PLLCFGR_PLLM_Pos, cfg->m) | - whal_SetBits(RCC_PLLCFGR_PLLN_Msk, RCC_PLLCFGR_PLLN_Pos, cfg->n) | - whal_SetBits(RCC_PLLCFGR_PLLP_Msk, RCC_PLLCFGR_PLLP_Pos, cfg->p) | - whal_SetBits(RCC_PLLCFGR_PLLQ_Msk, RCC_PLLCFGR_PLLQ_Pos, cfg->q) | - whal_SetBits(RCC_PLLCFGR_PLLREN_Msk, RCC_PLLCFGR_PLLREN_Pos, 1) | - whal_SetBits(RCC_PLLCFGR_PLLR_Msk, RCC_PLLCFGR_PLLR_Pos, cfg->r)); - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, - RCC_CR_PLLON_Msk); - do { - whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, - RCC_CR_PLLRDY_Pos, &rdy); - } while (!rdy); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32wb_Rcc_DisablePll(whal_Clock *clkDev) -{ - if (!clkDev) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32wb_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32wb_Rcc_SysClockSrc src) -{ - size_t sws; - - if (!clkDev) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, - whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, src)); - do { - whal_Reg_Get(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, - RCC_CFGR_SWS_Pos, &sws); - } while (sws != (size_t)src); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32wb_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32wb_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32wb_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32wb_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); - return WHAL_SUCCESS; -} diff --git a/src/crypto/stm32wb_aes.c b/src/crypto/stm32wb_aes.c index 4418118..8f37255 100644 --- a/src/crypto/stm32wb_aes.c +++ b/src/crypto/stm32wb_aes.c @@ -1,4 +1,5 @@ #include +#include "board.h" /* provides whal_Stm32wb_Aes*_Dev singletons */ #include #include #include @@ -222,16 +223,14 @@ static void DisableAes(whal_Crypto *cryptoDev) whal_Error whal_Stm32wb_Aes_Init(whal_Crypto *dev) { - if (!dev) - return WHAL_EINVAL; + (void)dev; return WHAL_SUCCESS; } whal_Error whal_Stm32wb_Aes_Deinit(whal_Crypto *dev) { - if (!dev) - return WHAL_EINVAL; - DisableAes(dev); + (void)dev; + DisableAes((whal_Crypto *)&whal_Stm32wb_Aes_Dev); return WHAL_SUCCESS; } @@ -247,17 +246,16 @@ whal_Error whal_Stm32wb_AesEcb_Oneshot(whal_AesEcb *dev, whal_Crypto_Dir dir, const void *key, size_t keySz, const void *in, void *out, size_t sz) { - whal_Crypto *crypto; - size_t base; + whal_Crypto *crypto = whal_Stm32wb_AesEcb_Dev.crypto; + size_t base = crypto->base; size_t mode; size_t keySizeBit; whal_Error err; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key) - return WHAL_EINVAL; + (void)dev; - crypto = dev->crypto; - base = crypto->base; + if (!key) + return WHAL_EINVAL; if (keySz != 16 && keySz != 32) return WHAL_ENOTSUP; @@ -291,16 +289,15 @@ whal_Error whal_Stm32wb_AesEcb_Oneshot(whal_AesEcb *dev, whal_Crypto_Dir dir, whal_Error whal_Stm32wb_AesEcb_Start(whal_AesEcb *dev, whal_Crypto_Dir dir, const void *key, size_t keySz) { - whal_Crypto *crypto; - size_t base; + whal_Crypto *crypto = whal_Stm32wb_AesEcb_Dev.crypto; + size_t base = crypto->base; size_t mode; size_t keySizeBit; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key) - return WHAL_EINVAL; + (void)dev; - crypto = dev->crypto; - base = crypto->base; + if (!key) + return WHAL_EINVAL; if (keySz != 16 && keySz != 32) return WHAL_ENOTSUP; @@ -332,7 +329,8 @@ whal_Error whal_Stm32wb_AesEcb_Start(whal_AesEcb *dev, whal_Crypto_Dir dir, whal_Error whal_Stm32wb_AesEcb_Process(whal_AesEcb *dev, const void *in, void *out, size_t sz) { - return ProcessBlockCipher(dev->crypto, in, out, sz); + (void)dev; + return ProcessBlockCipher(whal_Stm32wb_AesEcb_Dev.crypto, in, out, sz); } const whal_AesEcbDriver whal_Stm32wb_Aes_EcbDriver = { @@ -349,17 +347,16 @@ whal_Error whal_Stm32wb_AesCbc_Oneshot(whal_AesCbc *dev, whal_Crypto_Dir dir, const void *iv, const void *in, void *out, size_t sz) { - whal_Crypto *crypto; - size_t base; + whal_Crypto *crypto = whal_Stm32wb_AesCbc_Dev.crypto; + size_t base = crypto->base; size_t mode; size_t keySizeBit; whal_Error err; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) - return WHAL_EINVAL; + (void)dev; - crypto = dev->crypto; - base = crypto->base; + if (!key || !iv) + return WHAL_EINVAL; if (keySz != 16 && keySz != 32) return WHAL_ENOTSUP; @@ -395,16 +392,15 @@ whal_Error whal_Stm32wb_AesCbc_Start(whal_AesCbc *dev, whal_Crypto_Dir dir, const void *key, size_t keySz, const void *iv) { - whal_Crypto *crypto; - size_t base; + whal_Crypto *crypto = whal_Stm32wb_AesCbc_Dev.crypto; + size_t base = crypto->base; size_t mode; size_t keySizeBit; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) - return WHAL_EINVAL; + (void)dev; - crypto = dev->crypto; - base = crypto->base; + if (!key || !iv) + return WHAL_EINVAL; if (keySz != 16 && keySz != 32) return WHAL_ENOTSUP; @@ -437,7 +433,8 @@ whal_Error whal_Stm32wb_AesCbc_Start(whal_AesCbc *dev, whal_Crypto_Dir dir, whal_Error whal_Stm32wb_AesCbc_Process(whal_AesCbc *dev, const void *in, void *out, size_t sz) { - return ProcessBlockCipher(dev->crypto, in, out, sz); + (void)dev; + return ProcessBlockCipher(whal_Stm32wb_AesCbc_Dev.crypto, in, out, sz); } const whal_AesCbcDriver whal_Stm32wb_Aes_CbcDriver = { @@ -454,16 +451,15 @@ whal_Error whal_Stm32wb_AesCtr_Oneshot(whal_AesCtr *dev, whal_Crypto_Dir dir, const void *iv, const void *in, void *out, size_t sz) { - whal_Crypto *crypto; - size_t base; + whal_Crypto *crypto = whal_Stm32wb_AesCtr_Dev.crypto; + size_t base = crypto->base; size_t keySizeBit; whal_Error err; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) - return WHAL_EINVAL; + (void)dev; - crypto = dev->crypto; - base = crypto->base; + if (!key || !iv) + return WHAL_EINVAL; if (keySz != 16 && keySz != 32) return WHAL_ENOTSUP; @@ -498,15 +494,14 @@ whal_Error whal_Stm32wb_AesCtr_Start(whal_AesCtr *dev, whal_Crypto_Dir dir, const void *key, size_t keySz, const void *iv) { - whal_Crypto *crypto; - size_t base; + whal_Crypto *crypto = whal_Stm32wb_AesCtr_Dev.crypto; + size_t base = crypto->base; size_t keySizeBit; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) - return WHAL_EINVAL; + (void)dev; - crypto = dev->crypto; - base = crypto->base; + if (!key || !iv) + return WHAL_EINVAL; if (keySz != 16 && keySz != 32) return WHAL_ENOTSUP; @@ -538,7 +533,8 @@ whal_Error whal_Stm32wb_AesCtr_Start(whal_AesCtr *dev, whal_Crypto_Dir dir, whal_Error whal_Stm32wb_AesCtr_Process(whal_AesCtr *dev, const void *in, void *out, size_t sz) { - return ProcessBlockCipher(dev->crypto, in, out, sz); + (void)dev; + return ProcessBlockCipher(whal_Stm32wb_AesCtr_Dev.crypto, in, out, sz); } const whal_AesCtrDriver whal_Stm32wb_Aes_CtrDriver = { @@ -557,9 +553,10 @@ whal_Error whal_Stm32wb_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, const void *in, void *out, size_t sz, void *tag, size_t tagSz) { - whal_Crypto *crypto; - const whal_Stm32wb_Aes_Cfg *cfg; - size_t base; + whal_Crypto *crypto = whal_Stm32wb_AesGcm_Dev.crypto; + const whal_Stm32wb_Aes_Cfg *cfg = + (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + size_t base = crypto->base; const uint8_t *ivBytes = (const uint8_t *)iv; const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; @@ -568,12 +565,10 @@ whal_Error whal_Stm32wb_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, uint8_t tagBuf[16]; whal_Error err; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) - return WHAL_EINVAL; + (void)dev; - crypto = dev->crypto; - cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - base = crypto->base; + if (!key || !iv) + return WHAL_EINVAL; if (keySz != 16 && keySz != 32) return WHAL_ENOTSUP; @@ -739,9 +734,10 @@ whal_Error whal_Stm32wb_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, const void *iv, size_t ivSz, const void *aad, size_t aadSz) { - whal_Crypto *crypto; - const whal_Stm32wb_Aes_Cfg *cfg; - size_t base; + whal_Crypto *crypto = whal_Stm32wb_AesGcm_Dev.crypto; + const whal_Stm32wb_Aes_Cfg *cfg = + (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + size_t base = crypto->base; const uint8_t *ivBytes = (const uint8_t *)iv; const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; @@ -749,12 +745,10 @@ whal_Error whal_Stm32wb_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, size_t i; whal_Error err; - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state || !key || !iv) - return WHAL_EINVAL; + (void)dev; - crypto = dev->crypto; - cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - base = crypto->base; + if (!key || !iv) + return WHAL_EINVAL; if (keySz != 16 && keySz != 32) return WHAL_ENOTSUP; @@ -843,7 +837,8 @@ whal_Error whal_Stm32wb_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); { - whal_Stm32wb_AesGcm_State *st = (whal_Stm32wb_AesGcm_State *)dev->state; + whal_Stm32wb_AesGcm_State *st = + (whal_Stm32wb_AesGcm_State *)whal_Stm32wb_AesGcm_Dev.state; st->aadSz = aadSz; st->dataSz = 0; } @@ -858,21 +853,17 @@ whal_Error whal_Stm32wb_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, whal_Error whal_Stm32wb_AesGcm_Process(whal_AesGcm *dev, const void *in, void *out, size_t sz) { - whal_Crypto *crypto; - const whal_Stm32wb_Aes_Cfg *cfg; - size_t base; - whal_Stm32wb_AesGcm_State *st; + whal_Crypto *crypto = whal_Stm32wb_AesGcm_Dev.crypto; + const whal_Stm32wb_Aes_Cfg *cfg = + (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + size_t base = crypto->base; + whal_Stm32wb_AesGcm_State *st = + (whal_Stm32wb_AesGcm_State *)whal_Stm32wb_AesGcm_Dev.state; size_t mode; size_t i; whal_Error err; - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) - return WHAL_EINVAL; - - crypto = dev->crypto; - cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - base = crypto->base; - st = (whal_Stm32wb_AesGcm_State *)dev->state; + (void)dev; if (sz == 0) return WHAL_SUCCESS; @@ -927,21 +918,17 @@ whal_Error whal_Stm32wb_AesGcm_Process(whal_AesGcm *dev, whal_Error whal_Stm32wb_AesGcm_Finalize(whal_AesGcm *dev, void *tag, size_t tagSz) { - whal_Crypto *crypto; - const whal_Stm32wb_Aes_Cfg *cfg; - size_t base; - whal_Stm32wb_AesGcm_State *st; + whal_Crypto *crypto = whal_Stm32wb_AesGcm_Dev.crypto; + const whal_Stm32wb_Aes_Cfg *cfg = + (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + size_t base = crypto->base; + whal_Stm32wb_AesGcm_State *st = + (whal_Stm32wb_AesGcm_State *)whal_Stm32wb_AesGcm_Dev.state; uint8_t tagBuf[16]; size_t i; whal_Error err; - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) - return WHAL_EINVAL; - - crypto = dev->crypto; - cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - base = crypto->base; - st = (whal_Stm32wb_AesGcm_State *)dev->state; + (void)dev; if (!tag || tagSz == 0 || tagSz > 16) return WHAL_EINVAL; @@ -993,9 +980,10 @@ whal_Error whal_Stm32wb_AesGmac_Oneshot(whal_AesGmac *dev, const void *aad, size_t aadSz, void *tag, size_t tagSz) { - whal_Crypto *crypto; - const whal_Stm32wb_Aes_Cfg *cfg; - size_t base; + whal_Crypto *crypto = whal_Stm32wb_AesGmac_Dev.crypto; + const whal_Stm32wb_Aes_Cfg *cfg = + (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + size_t base = crypto->base; const uint8_t *ivBytes = (const uint8_t *)iv; const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; @@ -1003,12 +991,10 @@ whal_Error whal_Stm32wb_AesGmac_Oneshot(whal_AesGmac *dev, uint8_t tagBuf[16]; whal_Error err; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) - return WHAL_EINVAL; + (void)dev; - crypto = dev->crypto; - cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - base = crypto->base; + if (!key || !iv) + return WHAL_EINVAL; if (keySz != 16 && keySz != 32) return WHAL_ENOTSUP; @@ -1130,9 +1116,10 @@ whal_Error whal_Stm32wb_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, const void *in, void *out, size_t sz, void *tag, size_t tagSz) { - whal_Crypto *crypto; - const whal_Stm32wb_Aes_Cfg *cfg; - size_t base; + whal_Crypto *crypto = whal_Stm32wb_AesCcm_Dev.crypto; + const whal_Stm32wb_Aes_Cfg *cfg = + (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + size_t base = crypto->base; const uint8_t *nonceBytes = (const uint8_t *)nonce; const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; @@ -1142,12 +1129,10 @@ whal_Error whal_Stm32wb_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, uint8_t tagBuf[16]; whal_Error err; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !nonce) - return WHAL_EINVAL; + (void)dev; - crypto = dev->crypto; - cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - base = crypto->base; + if (!key || !nonce) + return WHAL_EINVAL; if (keySz != 16 && keySz != 32) return WHAL_ENOTSUP; @@ -1344,9 +1329,10 @@ whal_Error whal_Stm32wb_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, const void *aad, size_t aadSz, size_t tagSz, size_t sz) { - whal_Crypto *crypto; - const whal_Stm32wb_Aes_Cfg *cfg; - size_t base; + whal_Crypto *crypto = whal_Stm32wb_AesCcm_Dev.crypto; + const whal_Stm32wb_Aes_Cfg *cfg = + (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + size_t base = crypto->base; const uint8_t *nonceBytes = (const uint8_t *)nonce; const uint8_t *aadBytes = (const uint8_t *)aad; size_t keySizeBit; @@ -1355,12 +1341,10 @@ whal_Error whal_Stm32wb_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, uint8_t b0[16]; whal_Error err; - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state || !key || !nonce) - return WHAL_EINVAL; + (void)dev; - crypto = dev->crypto; - cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - base = crypto->base; + if (!key || !nonce) + return WHAL_EINVAL; if (keySz != 16 && keySz != 32) return WHAL_ENOTSUP; @@ -1482,7 +1466,8 @@ whal_Error whal_Stm32wb_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, whal_Reg_Update(base, AES_CR_REG, AES_CR_EN_Msk, AES_CR_EN_Msk); { - whal_Stm32wb_AesCcm_State *st = (whal_Stm32wb_AesCcm_State *)dev->state; + whal_Stm32wb_AesCcm_State *st = + (whal_Stm32wb_AesCcm_State *)whal_Stm32wb_AesCcm_Dev.state; st->aadSz = aadSz; st->dataSz = 0; } @@ -1497,21 +1482,17 @@ whal_Error whal_Stm32wb_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, whal_Error whal_Stm32wb_AesCcm_Process(whal_AesCcm *dev, const void *in, void *out, size_t sz) { - whal_Crypto *crypto; - const whal_Stm32wb_Aes_Cfg *cfg; - size_t base; - whal_Stm32wb_AesCcm_State *st; + whal_Crypto *crypto = whal_Stm32wb_AesCcm_Dev.crypto; + const whal_Stm32wb_Aes_Cfg *cfg = + (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + size_t base = crypto->base; + whal_Stm32wb_AesCcm_State *st = + (whal_Stm32wb_AesCcm_State *)whal_Stm32wb_AesCcm_Dev.state; size_t mode; size_t i; whal_Error err; - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) - return WHAL_EINVAL; - - crypto = dev->crypto; - cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - base = crypto->base; - st = (whal_Stm32wb_AesCcm_State *)dev->state; + (void)dev; if (sz == 0) return WHAL_SUCCESS; @@ -1566,21 +1547,17 @@ whal_Error whal_Stm32wb_AesCcm_Process(whal_AesCcm *dev, whal_Error whal_Stm32wb_AesCcm_Finalize(whal_AesCcm *dev, void *tag, size_t tagSz) { - whal_Crypto *crypto; - const whal_Stm32wb_Aes_Cfg *cfg; - size_t base; - whal_Stm32wb_AesCcm_State *st; + whal_Crypto *crypto = whal_Stm32wb_AesCcm_Dev.crypto; + const whal_Stm32wb_Aes_Cfg *cfg = + (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; + size_t base = crypto->base; + whal_Stm32wb_AesCcm_State *st = + (whal_Stm32wb_AesCcm_State *)whal_Stm32wb_AesCcm_Dev.state; uint8_t tagBuf[16]; size_t i; whal_Error err; - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) - return WHAL_EINVAL; - - crypto = dev->crypto; - cfg = (const whal_Stm32wb_Aes_Cfg *)crypto->cfg; - base = crypto->base; - st = (whal_Stm32wb_AesCcm_State *)dev->state; + (void)dev; if (!tag || tagSz < 4 || tagSz > 16 || (tagSz & 1) != 0) return WHAL_EINVAL; diff --git a/src/dma/stm32wb_dma.c b/src/dma/stm32wb_dma.c index d683f62..2372272 100644 --- a/src/dma/stm32wb_dma.c +++ b/src/dma/stm32wb_dma.c @@ -1,4 +1,7 @@ #include +#ifdef WHAL_CFG_STM32WB_DMA_SINGLE_INSTANCE +#include "board.h" /* provides whal_Stm32wb_Dma_Dev singleton */ +#endif #include #include #include @@ -98,6 +101,12 @@ whal_Error whal_Stm32wb_Dma_Init(whal_Dma *dmaDev) { +#ifdef WHAL_CFG_STM32WB_DMA_SINGLE_INSTANCE + whal_Stm32wb_Dma_Cfg *cfg = + (whal_Stm32wb_Dma_Cfg *)whal_Stm32wb_Dma_Dev.cfg; + size_t base = whal_Stm32wb_Dma_Dev.base; + (void)dmaDev; +#else whal_Stm32wb_Dma_Cfg *cfg; size_t base; @@ -107,6 +116,7 @@ whal_Error whal_Stm32wb_Dma_Init(whal_Dma *dmaDev) cfg = (whal_Stm32wb_Dma_Cfg *)dmaDev->cfg; base = dmaDev->base; +#endif /* Clear all interrupt flags for all channels */ { @@ -122,6 +132,12 @@ whal_Error whal_Stm32wb_Dma_Init(whal_Dma *dmaDev) whal_Error whal_Stm32wb_Dma_Deinit(whal_Dma *dmaDev) { +#ifdef WHAL_CFG_STM32WB_DMA_SINGLE_INSTANCE + whal_Stm32wb_Dma_Cfg *cfg = + (whal_Stm32wb_Dma_Cfg *)whal_Stm32wb_Dma_Dev.cfg; + size_t base = whal_Stm32wb_Dma_Dev.base; + (void)dmaDev; +#else whal_Stm32wb_Dma_Cfg *cfg; size_t base; @@ -131,6 +147,7 @@ whal_Error whal_Stm32wb_Dma_Deinit(whal_Dma *dmaDev) cfg = (whal_Stm32wb_Dma_Cfg *)dmaDev->cfg; base = dmaDev->base; +#endif /* Disable all channels and clear all interrupt flags */ for (size_t i = 1; i <= cfg->numChannels; ++i) { @@ -153,9 +170,7 @@ whal_Error whal_Stm32wb_Dma_Deinit(whal_Dma *dmaDev) whal_Error whal_Stm32wb_Dma_Configure(whal_Dma *dmaDev, size_t ch, const void *chCfg) { - whal_Stm32wb_Dma_Cfg *cfg; const whal_Stm32wb_Dma_ChCfg *dmaChCfg; - size_t base; size_t hw_ch; size_t ccr; uint32_t periphAddr; @@ -164,14 +179,27 @@ whal_Error whal_Stm32wb_Dma_Configure(whal_Dma *dmaDev, size_t ch, size_t memInc; size_t periphSize; size_t memSize; +#ifdef WHAL_CFG_STM32WB_DMA_SINGLE_INSTANCE + whal_Stm32wb_Dma_Cfg *cfg = + (whal_Stm32wb_Dma_Cfg *)whal_Stm32wb_Dma_Dev.cfg; + size_t base = whal_Stm32wb_Dma_Dev.base; + (void)dmaDev; + + if (!chCfg) { + return WHAL_EINVAL; + } +#else + whal_Stm32wb_Dma_Cfg *cfg; + size_t base; if (!dmaDev || !dmaDev->cfg || !chCfg) { return WHAL_EINVAL; } cfg = (whal_Stm32wb_Dma_Cfg *)dmaDev->cfg; - dmaChCfg = (const whal_Stm32wb_Dma_ChCfg *)chCfg; base = dmaDev->base; +#endif + dmaChCfg = (const whal_Stm32wb_Dma_ChCfg *)chCfg; if (ch >= cfg->numChannels) { return WHAL_EINVAL; @@ -272,9 +300,15 @@ whal_Error whal_Stm32wb_Dma_Configure(whal_Dma *dmaDev, size_t ch, whal_Error whal_Stm32wb_Dma_Start(whal_Dma *dmaDev, size_t ch) { + size_t hw_ch; +#ifdef WHAL_CFG_STM32WB_DMA_SINGLE_INSTANCE + whal_Stm32wb_Dma_Cfg *cfg = + (whal_Stm32wb_Dma_Cfg *)whal_Stm32wb_Dma_Dev.cfg; + size_t base = whal_Stm32wb_Dma_Dev.base; + (void)dmaDev; +#else whal_Stm32wb_Dma_Cfg *cfg; size_t base; - size_t hw_ch; if (!dmaDev || !dmaDev->cfg) { return WHAL_EINVAL; @@ -282,6 +316,7 @@ whal_Error whal_Stm32wb_Dma_Start(whal_Dma *dmaDev, size_t ch) cfg = (whal_Stm32wb_Dma_Cfg *)dmaDev->cfg; base = dmaDev->base; +#endif if (ch >= cfg->numChannels) { return WHAL_EINVAL; @@ -302,9 +337,15 @@ whal_Error whal_Stm32wb_Dma_Start(whal_Dma *dmaDev, size_t ch) whal_Error whal_Stm32wb_Dma_Stop(whal_Dma *dmaDev, size_t ch) { + size_t hw_ch; +#ifdef WHAL_CFG_STM32WB_DMA_SINGLE_INSTANCE + whal_Stm32wb_Dma_Cfg *cfg = + (whal_Stm32wb_Dma_Cfg *)whal_Stm32wb_Dma_Dev.cfg; + size_t base = whal_Stm32wb_Dma_Dev.base; + (void)dmaDev; +#else whal_Stm32wb_Dma_Cfg *cfg; size_t base; - size_t hw_ch; if (!dmaDev || !dmaDev->cfg) { return WHAL_EINVAL; @@ -312,6 +353,7 @@ whal_Error whal_Stm32wb_Dma_Stop(whal_Dma *dmaDev, size_t ch) cfg = (whal_Stm32wb_Dma_Cfg *)dmaDev->cfg; base = dmaDev->base; +#endif if (ch >= cfg->numChannels) { return WHAL_EINVAL; @@ -333,14 +375,20 @@ whal_Error whal_Stm32wb_Dma_Stop(whal_Dma *dmaDev, size_t ch) void whal_Stm32wb_Dma_IRQHandler(whal_Dma *dmaDev, size_t ch, whal_Stm32wb_Dma_Callback cb, void *ctx) { - size_t base; size_t hw_ch; size_t isr; +#ifdef WHAL_CFG_STM32WB_DMA_SINGLE_INSTANCE + size_t base = whal_Stm32wb_Dma_Dev.base; + (void)dmaDev; +#else + size_t base; if (!dmaDev) return; base = dmaDev->base; +#endif + hw_ch = ch + 1; isr = whal_Reg_Read(base, DMA_ISR_REG); diff --git a/src/eth/stm32h5_eth.c b/src/eth/stm32h5_eth.c index 3ed8542..3472259 100644 --- a/src/eth/stm32h5_eth.c +++ b/src/eth/stm32h5_eth.c @@ -1,10 +1,19 @@ #include +#include "board.h" /* provides whal_Stm32h5_Eth_Dev singleton */ #include #include #include #include #include +/* Driver-internal runtime state. The cfg lives as a same-TU static const via + * board.h's whal_Stm32h5_Eth_Dev, so cfg field accesses fold without LTO; + * the mutable ring-tracking state stays here, separate from the cfg. */ +static struct { + size_t txHead; + size_t rxHead; +} eth_state; + /* * STM32H5 Ethernet MAC Register Definitions * @@ -120,8 +129,13 @@ /* Max TX frame size */ #define ETH_MAX_FRAME_SIZE 1536 -/* MDIO clock range for 168 MHz AHB: CR=4 gives /102 ≈ 1.6 MHz */ -#define ETH_MDIO_CR 4 +/* MDIO clock range select (CR field in MACMDIOAR). The MAC uses this to + * pick the AHB->MDC divider. Values map to AHB freq bands: + * CR=0: 60-100 MHz CR=1: 100-150 MHz + * CR=2: 20-35 MHz CR=3: 35-60 MHz + * CR=4: 150-250MHz CR=5: 250-300 MHz + * HSI default (32 MHz HCLK) -> CR=2. */ +#define ETH_MDIO_CR 2 #ifdef WHAL_CFG_STM32H5_ETH_DIRECT_API_MAPPING #define whal_Stm32h5_Eth_Init whal_Eth_Init @@ -142,20 +156,12 @@ static whal_Error MdioPoll(size_t base, whal_Timeout *timeout) whal_Error whal_Stm32h5_Eth_Init(whal_Eth *ethDev) { - whal_Stm32h5_Eth_Cfg *cfg; - size_t base; + const whal_Stm32h5_Eth_Cfg *cfg = + (const whal_Stm32h5_Eth_Cfg *)whal_Stm32h5_Eth_Dev.cfg; + size_t base = whal_Stm32h5_Eth_Dev.base; whal_Error err; - if (!ethDev || !ethDev->cfg) - return WHAL_EINVAL; - - cfg = (whal_Stm32h5_Eth_Cfg *)ethDev->cfg; - base = ethDev->base; - - if (!cfg->txDescs || !cfg->txBufs || cfg->txDescCount == 0 || - !cfg->rxDescs || !cfg->rxBufs || cfg->rxDescCount == 0 || - cfg->txBufSize == 0 || cfg->rxBufSize == 0) - return WHAL_EINVAL; + (void)ethDev; /* DMA software reset */ whal_Reg_Update(base, ETH_DMAMR_REG, ETH_DMAMR_SWR_Msk, @@ -217,27 +223,25 @@ whal_Error whal_Stm32h5_Eth_Init(whal_Eth *ethDev) /* MAC address */ whal_Reg_Write(base, ETH_MACA0LR_REG, - ((uint32_t)ethDev->macAddr[3] << 24) | - ((uint32_t)ethDev->macAddr[2] << 16) | - ((uint32_t)ethDev->macAddr[1] << 8) | - ((uint32_t)ethDev->macAddr[0])); + ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[3] << 24) | + ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[2] << 16) | + ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[1] << 8) | + ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[0])); whal_Reg_Write(base, ETH_MACA0HR_REG, - ((uint32_t)ethDev->macAddr[5] << 8) | - ((uint32_t)ethDev->macAddr[4])); + ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[5] << 8) | + ((uint32_t)whal_Stm32h5_Eth_Dev.macAddr[4])); /* Reset ring tracking state */ - cfg->txHead = 0; - cfg->rxHead = 0; + eth_state.txHead = 0; + eth_state.rxHead = 0; return WHAL_SUCCESS; } whal_Error whal_Stm32h5_Eth_Deinit(whal_Eth *ethDev) { - if (!ethDev) - return WHAL_EINVAL; - - whal_Reg_Update(ethDev->base, ETH_DMAMR_REG, + (void)ethDev; + whal_Reg_Update(whal_Stm32h5_Eth_Dev.base, ETH_DMAMR_REG, ETH_DMAMR_SWR_Msk, ETH_DMAMR_SWR_Msk); return WHAL_SUCCESS; @@ -246,14 +250,10 @@ whal_Error whal_Stm32h5_Eth_Deinit(whal_Eth *ethDev) whal_Error whal_Stm32h5_Eth_Start(whal_Eth *ethDev, uint8_t speed, uint8_t duplex) { - whal_Stm32h5_Eth_Cfg *cfg; - size_t base; - - if (!ethDev || !ethDev->cfg) - return WHAL_EINVAL; - - cfg = (whal_Stm32h5_Eth_Cfg *)ethDev->cfg; - base = ethDev->base; + const whal_Stm32h5_Eth_Cfg *cfg = + (const whal_Stm32h5_Eth_Cfg *)whal_Stm32h5_Eth_Dev.cfg; + size_t base = whal_Stm32h5_Eth_Dev.base; + (void)ethDev; /* Configure MAC speed and duplex to match PHY */ whal_Reg_Update(base, ETH_MACCR_REG, @@ -283,12 +283,8 @@ whal_Error whal_Stm32h5_Eth_Start(whal_Eth *ethDev, uint8_t speed, whal_Error whal_Stm32h5_Eth_Stop(whal_Eth *ethDev) { - size_t base; - - if (!ethDev) - return WHAL_EINVAL; - - base = ethDev->base; + size_t base = whal_Stm32h5_Eth_Dev.base; + (void)ethDev; /* Stop DMA TX */ whal_Reg_Update(base, ETH_DMACTXCR_REG, ETH_DMACTXCR_ST_Msk, 0); @@ -307,20 +303,16 @@ whal_Error whal_Stm32h5_Eth_Send(whal_Eth *ethDev, const void *frame, size_t len) { const uint8_t *frameBuf = (const uint8_t *)frame; - whal_Stm32h5_Eth_Cfg *cfg; + const whal_Stm32h5_Eth_Cfg *cfg = + (const whal_Stm32h5_Eth_Cfg *)whal_Stm32h5_Eth_Dev.cfg; whal_Stm32h5_Eth_TxDesc *desc; - size_t base; + size_t base = whal_Stm32h5_Eth_Dev.base; size_t idx; + (void)ethDev; - if (!ethDev || !ethDev->cfg || !frame || len == 0) - return WHAL_EINVAL; - - cfg = (whal_Stm32h5_Eth_Cfg *)ethDev->cfg; - - if (len > cfg->txBufSize) + if (!frame || len == 0 || len > cfg->txBufSize) return WHAL_EINVAL; - base = ethDev->base; - idx = cfg->txHead; + idx = eth_state.txHead; desc = &cfg->txDescs[idx]; /* Check if descriptor is available (OWN must be 0) */ @@ -339,7 +331,7 @@ whal_Error whal_Stm32h5_Eth_Send(whal_Eth *ethDev, const void *frame, desc->des[3] = TDES3_OWN | TDES3_FD | TDES3_LD | (len & 0x7FFF); /* Advance ring position */ - cfg->txHead = (idx + 1) % cfg->txDescCount; + eth_state.txHead = (idx + 1) % cfg->txDescCount; /* Kick DMA — tail pointer past the end of the ring */ whal_Reg_Write(base, ETH_DMACTXDTPR_REG, @@ -352,19 +344,19 @@ whal_Error whal_Stm32h5_Eth_Recv(whal_Eth *ethDev, void *frame, size_t *len) { uint8_t *frameBuf = (uint8_t *)frame; - whal_Stm32h5_Eth_Cfg *cfg; + const whal_Stm32h5_Eth_Cfg *cfg = + (const whal_Stm32h5_Eth_Cfg *)whal_Stm32h5_Eth_Dev.cfg; whal_Stm32h5_Eth_RxDesc *desc; - size_t base; + size_t base = whal_Stm32h5_Eth_Dev.base; size_t idx; uint32_t rdes3; size_t pktLen; + (void)ethDev; - if (!ethDev || !ethDev->cfg || !frame || !len) + if (!frame || !len) return WHAL_EINVAL; - cfg = (whal_Stm32h5_Eth_Cfg *)ethDev->cfg; - base = ethDev->base; - idx = cfg->rxHead; + idx = eth_state.rxHead; desc = &cfg->rxDescs[idx]; rdes3 = desc->des[3]; @@ -377,7 +369,7 @@ whal_Error whal_Stm32h5_Eth_Recv(whal_Eth *ethDev, void *frame, if (rdes3 & RDES3_ES) { desc->des[0] = (uintptr_t)(cfg->rxBufs + idx * cfg->rxBufSize); desc->des[3] = RDES3_OWN | RDES3_IOC | RDES3_BUF1V; - cfg->rxHead = (idx + 1) % cfg->rxDescCount; + eth_state.rxHead = (idx + 1) % cfg->rxDescCount; whal_Reg_Write(base, ETH_DMACRXDTPR_REG, (uintptr_t)&cfg->rxDescs[cfg->rxDescCount]); return WHAL_EHARDWARE; @@ -401,7 +393,7 @@ whal_Error whal_Stm32h5_Eth_Recv(whal_Eth *ethDev, void *frame, desc->des[3] = RDES3_OWN | RDES3_IOC | RDES3_BUF1V; /* Advance ring position */ - cfg->rxHead = (idx + 1) % cfg->rxDescCount; + eth_state.rxHead = (idx + 1) % cfg->rxDescCount; /* Update RX tail pointer — always past end of ring */ whal_Reg_Write(base, ETH_DMACRXDTPR_REG, @@ -413,16 +405,15 @@ whal_Error whal_Stm32h5_Eth_Recv(whal_Eth *ethDev, void *frame, whal_Error whal_Stm32h5_Eth_MdioRead(whal_Eth *ethDev, uint8_t phyAddr, uint8_t reg, uint16_t *val) { - whal_Stm32h5_Eth_Cfg *cfg; - size_t base; + const whal_Stm32h5_Eth_Cfg *cfg = + (const whal_Stm32h5_Eth_Cfg *)whal_Stm32h5_Eth_Dev.cfg; + size_t base = whal_Stm32h5_Eth_Dev.base; whal_Error err; + (void)ethDev; - if (!ethDev || !ethDev->cfg || !val) + if (!val) return WHAL_EINVAL; - cfg = (whal_Stm32h5_Eth_Cfg *)ethDev->cfg; - base = ethDev->base; - err = MdioPoll(base, cfg->timeout); if (err) return err; @@ -451,15 +442,11 @@ whal_Error whal_Stm32h5_Eth_MdioRead(whal_Eth *ethDev, uint8_t phyAddr, whal_Error whal_Stm32h5_Eth_MdioWrite(whal_Eth *ethDev, uint8_t phyAddr, uint8_t reg, uint16_t val) { - whal_Stm32h5_Eth_Cfg *cfg; - size_t base; + const whal_Stm32h5_Eth_Cfg *cfg = + (const whal_Stm32h5_Eth_Cfg *)whal_Stm32h5_Eth_Dev.cfg; + size_t base = whal_Stm32h5_Eth_Dev.base; whal_Error err; - - if (!ethDev || !ethDev->cfg) - return WHAL_EINVAL; - - cfg = (whal_Stm32h5_Eth_Cfg *)ethDev->cfg; - base = ethDev->base; + (void)ethDev; err = MdioPoll(base, cfg->timeout); if (err) @@ -491,10 +478,8 @@ whal_Error whal_Stm32h5_Eth_MdioWrite(whal_Eth *ethDev, uint8_t phyAddr, whal_Error whal_Stm32h5_Eth_Ext_EnableLoopback(whal_Eth *ethDev, uint8_t enable) { - if (!ethDev) - return WHAL_EINVAL; - - whal_Reg_Update(ethDev->base, ETH_MACCR_REG, ETH_MACCR_LM_Msk, + (void)ethDev; + whal_Reg_Update(whal_Stm32h5_Eth_Dev.base, ETH_MACCR_REG, ETH_MACCR_LM_Msk, whal_SetBits(ETH_MACCR_LM_Msk, ETH_MACCR_LM_Pos, enable ? 1 : 0)); diff --git a/src/eth_phy/lan8742a_eth_phy.c b/src/eth_phy/lan8742a_eth_phy.c index bdfcbfc..d1cfcf9 100644 --- a/src/eth_phy/lan8742a_eth_phy.c +++ b/src/eth_phy/lan8742a_eth_phy.c @@ -1,3 +1,4 @@ +#include "board.h" /* provides whal_Lan8742a_Dev singleton */ #include #include #include @@ -29,21 +30,18 @@ whal_Error whal_Lan8742a_Init(whal_EthPhy *phyDev) { - whal_Lan8742a_Cfg *cfg; + const whal_Lan8742a_Cfg *cfg = + (const whal_Lan8742a_Cfg *)whal_Lan8742a_Dev.cfg; + uint8_t addr = whal_Lan8742a_Dev.addr; whal_Error err; uint16_t val; - - if (!phyDev || !phyDev->eth || !phyDev->cfg) - return WHAL_EINVAL; - - cfg = (whal_Lan8742a_Cfg *)phyDev->cfg; + (void)phyDev; #ifdef WHAL_CFG_NO_TIMEOUT (void)cfg; #endif /* Software reset */ - err = whal_Eth_MdioWrite(phyDev->eth, phyDev->addr, PHY_BCR, - PHY_BCR_RESET); + err = whal_Eth_MdioWrite(NULL, addr, PHY_BCR, PHY_BCR_RESET); if (err) return err; @@ -52,17 +50,17 @@ whal_Error whal_Lan8742a_Init(whal_EthPhy *phyDev) do { if (WHAL_TIMEOUT_EXPIRED(cfg->timeout)) return WHAL_ETIMEOUT; - err = whal_Eth_MdioRead(phyDev->eth, phyDev->addr, PHY_BCR, &val); + err = whal_Eth_MdioRead(NULL, addr, PHY_BCR, &val); if (err) return err; } while (val & PHY_BCR_RESET); /* Enable autonegotiation */ - err = whal_Eth_MdioRead(phyDev->eth, phyDev->addr, PHY_BCR, &val); + err = whal_Eth_MdioRead(NULL, addr, PHY_BCR, &val); if (err) return err; val |= PHY_BCR_ANEN; - err = whal_Eth_MdioWrite(phyDev->eth, phyDev->addr, PHY_BCR, val); + err = whal_Eth_MdioWrite(NULL, addr, PHY_BCR, val); if (err) return err; @@ -71,38 +69,37 @@ whal_Error whal_Lan8742a_Init(whal_EthPhy *phyDev) whal_Error whal_Lan8742a_Deinit(whal_EthPhy *phyDev) { - if (!phyDev || !phyDev->eth) - return WHAL_EINVAL; - + (void)phyDev; return WHAL_SUCCESS; } whal_Error whal_Lan8742a_GetLinkState(whal_EthPhy *phyDev, uint8_t *up, uint8_t *speed, uint8_t *duplex) { + uint8_t addr = whal_Lan8742a_Dev.addr; whal_Error err; uint16_t bsr; uint16_t scsr; + (void)phyDev; - if (!phyDev || !phyDev->eth || !up || !speed || !duplex) + if (!up || !speed || !duplex) return WHAL_EINVAL; /* * BSR link bit is latching-low (IEEE 802.3). First read clears a * stale link-down event; second read gives current status. */ - err = whal_Eth_MdioRead(phyDev->eth, phyDev->addr, PHY_BSR, &bsr); + err = whal_Eth_MdioRead(NULL, addr, PHY_BSR, &bsr); if (err) return err; - err = whal_Eth_MdioRead(phyDev->eth, phyDev->addr, PHY_BSR, &bsr); + err = whal_Eth_MdioRead(NULL, addr, PHY_BSR, &bsr); if (err) return err; *up = (bsr & PHY_BSR_LINK) ? 1 : 0; if (*up) { - err = whal_Eth_MdioRead(phyDev->eth, phyDev->addr, PHY_PHYSCSR, - &scsr); + err = whal_Eth_MdioRead(NULL, addr, PHY_PHYSCSR, &scsr); if (err) return err; uint16_t spd = scsr & PHY_PHYSCSR_SPEED_Msk; diff --git a/src/flash/stm32wb_flash.c b/src/flash/stm32wb_flash.c index 39b0dd5..79ed0de 100644 --- a/src/flash/stm32wb_flash.c +++ b/src/flash/stm32wb_flash.c @@ -1,4 +1,5 @@ #include +#include "board.h" /* provides whal_Stm32wb_Flash_Dev singleton */ #include #include #include @@ -101,35 +102,23 @@ whal_Error whal_Stm32wb_Flash_Init(whal_Flash *flashDev) { - if (!flashDev) { - return WHAL_EINVAL; - } - + (void)flashDev; return WHAL_SUCCESS; } whal_Error whal_Stm32wb_Flash_Deinit(whal_Flash *flashDev) { - if (!flashDev) { - return WHAL_EINVAL; - } - + (void)flashDev; return WHAL_SUCCESS; } whal_Error whal_Stm32wb_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base; - + size_t base = whal_Stm32wb_Flash_Dev.base; + (void)flashDev; (void)addr; (void)len; - if (!flashDev) { - return WHAL_EINVAL; - } - - base = flashDev->base; - /* Setting LOCK bit prevents further flash modifications until next unlock */ whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, whal_SetBits(FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, 1)); @@ -139,17 +128,11 @@ whal_Error whal_Stm32wb_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len whal_Error whal_Stm32wb_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base; - + size_t base = whal_Stm32wb_Flash_Dev.base; + (void)flashDev; (void)addr; (void)len; - if (!flashDev) { - return WHAL_EINVAL; - } - - base = flashDev->base; - /* * Unlock sequence: write KEY1 then KEY2 to KEYR register. * Incorrect sequence or order will trigger a bus error. @@ -163,17 +146,17 @@ whal_Error whal_Stm32wb_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t l whal_Error whal_Stm32wb_Flash_Read(whal_Flash *flashDev, size_t addr, void *data, size_t dataSz) { - whal_Stm32wb_Flash_Cfg *cfg; + const whal_Stm32wb_Flash_Cfg *cfg = + (const whal_Stm32wb_Flash_Cfg *)whal_Stm32wb_Flash_Dev.cfg; uint8_t *dataBuf = (uint8_t *)data; + (void)flashDev; - if (!flashDev || !flashDev->cfg || !data) + if (!data) return WHAL_EINVAL; if (dataSz == 0) return WHAL_SUCCESS; - cfg = flashDev->cfg; - if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) return WHAL_EINVAL; @@ -194,17 +177,12 @@ whal_Error whal_Stm32wb_Flash_Read(whal_Flash *flashDev, size_t addr, void *data static whal_Error whal_Stm32wb_Flash_WriteOrErase(whal_Flash *flashDev, size_t addr, const uint8_t *data, size_t dataSz, uint8_t write) { - whal_Stm32wb_Flash_Cfg *cfg; - size_t base; + const whal_Stm32wb_Flash_Cfg *cfg = + (const whal_Stm32wb_Flash_Cfg *)whal_Stm32wb_Flash_Dev.cfg; + size_t base = whal_Stm32wb_Flash_Dev.base; size_t bsy; size_t pesd; - - if (!flashDev || !flashDev->cfg) { - return WHAL_EINVAL; - } - - cfg = flashDev->cfg; - base = flashDev->base; + (void)flashDev; if (dataSz == 0) return WHAL_SUCCESS; @@ -300,11 +278,9 @@ whal_Error whal_Stm32wb_Flash_Erase(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32wb_Flash_Ext_SetLatency(whal_Flash *flashDev, enum whal_Stm32wb_Flash_Latency latency) { - if (!flashDev) { - return WHAL_EINVAL; - } + size_t base = whal_Stm32wb_Flash_Dev.base; + (void)flashDev; - size_t base = flashDev->base; whal_Reg_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); return WHAL_SUCCESS; } diff --git a/src/gpio/stm32wb_gpio.c b/src/gpio/stm32wb_gpio.c index 5080f61..d75152a 100644 --- a/src/gpio/stm32wb_gpio.c +++ b/src/gpio/stm32wb_gpio.c @@ -1,4 +1,5 @@ #include +#include "board.h" /* provides whal_Stm32wb_Gpio_Dev singleton (possibly via platform alias macro) */ #include #include #include @@ -56,8 +57,7 @@ /* * Initialize a single GPIO pin with the specified configuration. */ -static inline whal_Error whal_Stm32wb_Gpio_InitPin(whal_Gpio *gpioDev, - whal_Stm32wb_Gpio_PinCfg cfg) +static inline whal_Error whal_Stm32wb_Gpio_InitPin(whal_Stm32wb_Gpio_PinCfg cfg) { uint8_t pin = WHAL_STM32WB_GPIO_GET_PIN(cfg); size_t portBase; @@ -67,7 +67,7 @@ static inline whal_Error whal_Stm32wb_Gpio_InitPin(whal_Gpio *gpioDev, if (pin > 15) return WHAL_EINVAL; - portBase = gpioDev->base + + portBase = whal_Stm32wb_Gpio_Dev.base + (WHAL_STM32WB_GPIO_GET_PORT(cfg) * GPIO_PORT_SIZE); pos2 = pin << 1; mask2 = WHAL_BITMASK(2) << pos2; @@ -99,20 +99,15 @@ static inline whal_Error whal_Stm32wb_Gpio_InitPin(whal_Gpio *gpioDev, whal_Error whal_Stm32wb_Gpio_Init(whal_Gpio *gpioDev) { + const whal_Stm32wb_Gpio_Cfg *cfg = + (const whal_Stm32wb_Gpio_Cfg *)whal_Stm32wb_Gpio_Dev.cfg; + const whal_Stm32wb_Gpio_PinCfg *pinCfg = cfg->pinCfg; whal_Error err; - whal_Stm32wb_Gpio_Cfg *cfg; - whal_Stm32wb_Gpio_PinCfg *pinCfg; - - if (!gpioDev || !gpioDev->cfg) { - return WHAL_EINVAL; - } - - cfg = (whal_Stm32wb_Gpio_Cfg *)gpioDev->cfg; - pinCfg = cfg->pinCfg; + (void)gpioDev; /* Initialize each pin in the configuration array */ for (size_t pin = 0; pin < cfg->pinCount; ++pin) { - err = whal_Stm32wb_Gpio_InitPin(gpioDev, pinCfg[pin]); + err = whal_Stm32wb_Gpio_InitPin(pinCfg[pin]); if (err) { return err; } @@ -123,10 +118,7 @@ whal_Error whal_Stm32wb_Gpio_Init(whal_Gpio *gpioDev) whal_Error whal_Stm32wb_Gpio_Deinit(whal_Gpio *gpioDev) { - if (!gpioDev) { - return WHAL_EINVAL; - } - + (void)gpioDev; return WHAL_SUCCESS; } @@ -139,16 +131,17 @@ whal_Error whal_Stm32wb_Gpio_Deinit(whal_Gpio *gpioDev) static whal_Error whal_Stm32wb_Gpio_SetOrGet(whal_Gpio *gpioDev, size_t idx, size_t *value, uint8_t set) { - whal_Stm32wb_Gpio_Cfg *cfg; + const whal_Stm32wb_Gpio_Cfg *cfg = + (const whal_Stm32wb_Gpio_Cfg *)whal_Stm32wb_Gpio_Dev.cfg; whal_Stm32wb_Gpio_PinCfg pinCfg; uint8_t port, pin; size_t portBase, mask; + (void)gpioDev; - if (!gpioDev || !gpioDev->cfg || !value) { + if (!value) { return WHAL_EINVAL; } - cfg = (whal_Stm32wb_Gpio_Cfg *)gpioDev->cfg; pinCfg = cfg->pinCfg[idx]; port = WHAL_STM32WB_GPIO_GET_PORT(pinCfg); pin = WHAL_STM32WB_GPIO_GET_PIN(pinCfg); @@ -157,7 +150,7 @@ static whal_Error whal_Stm32wb_Gpio_SetOrGet(whal_Gpio *gpioDev, size_t idx, return WHAL_EINVAL; } - portBase = gpioDev->base + (port * GPIO_PORT_SIZE); + portBase = whal_Stm32wb_Gpio_Dev.base + (port * GPIO_PORT_SIZE); mask = 1UL << pin; if (set) { diff --git a/src/i2c/stm32wb_i2c.c b/src/i2c/stm32wb_i2c.c index 23fbae1..2288412 100644 --- a/src/i2c/stm32wb_i2c.c +++ b/src/i2c/stm32wb_i2c.c @@ -1,4 +1,10 @@ #include +#if defined(WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F0_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F3_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_I2C_SINGLE_INSTANCE) +#include "board.h" /* provides whal_Stm32wb_I2c_Dev singleton (possibly via platform alias macro) */ +#endif #include #include #include @@ -371,6 +377,13 @@ static whal_Error Stm32wb_I2c_TransferMsg(size_t base, whal_I2c_Msg *msg, whal_Error whal_Stm32wb_I2c_Init(whal_I2c *i2cDev) { +#if defined(WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F0_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F3_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_I2C_SINGLE_INSTANCE) + size_t base = whal_Stm32wb_I2c_Dev.base; + (void)i2cDev; +#else size_t base; if (!i2cDev || !i2cDev->cfg) { @@ -378,6 +391,7 @@ whal_Error whal_Stm32wb_I2c_Init(whal_I2c *i2cDev) } base = i2cDev->base; +#endif /* Disable PE before configuring */ whal_Reg_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, @@ -398,6 +412,13 @@ whal_Error whal_Stm32wb_I2c_Init(whal_I2c *i2cDev) whal_Error whal_Stm32wb_I2c_Deinit(whal_I2c *i2cDev) { +#if defined(WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F0_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F3_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_I2C_SINGLE_INSTANCE) + size_t base = whal_Stm32wb_I2c_Dev.base; + (void)i2cDev; +#else size_t base; if (!i2cDev || !i2cDev->cfg) { @@ -405,6 +426,7 @@ whal_Error whal_Stm32wb_I2c_Deinit(whal_I2c *i2cDev) } base = i2cDev->base; +#endif /* Disable peripheral */ whal_Reg_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, @@ -415,20 +437,39 @@ whal_Error whal_Stm32wb_I2c_Deinit(whal_I2c *i2cDev) whal_Error whal_Stm32wb_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) { + uint32_t cr2 = 0; +#if defined(WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F0_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F3_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_I2C_SINGLE_INSTANCE) + whal_Stm32wb_I2c_Cfg *cfg = + (whal_Stm32wb_I2c_Cfg *)whal_Stm32wb_I2c_Dev.cfg; + size_t base = whal_Stm32wb_I2c_Dev.base; + (void)i2cDev; + + if (!comCfg) { + return WHAL_EINVAL; + } +#else size_t base; whal_Stm32wb_I2c_Cfg *cfg; - uint32_t cr2 = 0; if (!i2cDev || !i2cDev->cfg || !comCfg) { return WHAL_EINVAL; } +#endif if ((comCfg->addrSz != 7 && comCfg->addrSz != 10) || comCfg->freq == 0) { return WHAL_EINVAL; } +#if !defined(WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE) && \ + !defined(WHAL_CFG_STM32F0_I2C_SINGLE_INSTANCE) && \ + !defined(WHAL_CFG_STM32F3_I2C_SINGLE_INSTANCE) && \ + !defined(WHAL_CFG_STM32N6_I2C_SINGLE_INSTANCE) base = i2cDev->base; cfg = (whal_Stm32wb_I2c_Cfg *)i2cDev->cfg; +#endif /* Disable PE to configure timing */ whal_Reg_Update(base, I2C_CR1_REG, I2C_CR1_PE_Msk, @@ -460,6 +501,13 @@ whal_Error whal_Stm32wb_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) whal_Error whal_Stm32wb_I2c_EndCom(whal_I2c *i2cDev) { +#if defined(WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F0_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F3_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_I2C_SINGLE_INSTANCE) + size_t base = whal_Stm32wb_I2c_Dev.base; + (void)i2cDev; +#else size_t base; if (!i2cDev || !i2cDev->cfg) { @@ -467,6 +515,7 @@ whal_Error whal_Stm32wb_I2c_EndCom(whal_I2c *i2cDev) } base = i2cDev->base; +#endif /* Clear target address and addressing mode */ whal_Reg_Update(base, I2C_CR2_REG, @@ -478,9 +527,22 @@ whal_Error whal_Stm32wb_I2c_EndCom(whal_I2c *i2cDev) whal_Error whal_Stm32wb_I2c_Transfer(whal_I2c *i2cDev, whal_I2c_Msg *msgs, size_t numMsgs) { + whal_Error err; +#if defined(WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F0_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F3_I2C_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_I2C_SINGLE_INSTANCE) + whal_Stm32wb_I2c_Cfg *cfg = + (whal_Stm32wb_I2c_Cfg *)whal_Stm32wb_I2c_Dev.cfg; + size_t base = whal_Stm32wb_I2c_Dev.base; + (void)i2cDev; + + if (!msgs || numMsgs == 0) { + return WHAL_EINVAL; + } +#else size_t base; whal_Stm32wb_I2c_Cfg *cfg; - whal_Error err; if (!i2cDev || !i2cDev->cfg || !msgs || numMsgs == 0) { return WHAL_EINVAL; @@ -488,6 +550,7 @@ whal_Error whal_Stm32wb_I2c_Transfer(whal_I2c *i2cDev, whal_I2c_Msg *msgs, base = i2cDev->base; cfg = (whal_Stm32wb_I2c_Cfg *)i2cDev->cfg; +#endif for (size_t i = 0; i < numMsgs; i++) { /* diff --git a/src/irq/cortex_m4_nvic.c b/src/irq/cortex_m4_nvic.c index 5d7b437..a4e204c 100644 --- a/src/irq/cortex_m4_nvic.c +++ b/src/irq/cortex_m4_nvic.c @@ -1,3 +1,4 @@ +#include "board.h" /* provides whal_Nvic_Dev singleton */ #include #include #include @@ -23,30 +24,21 @@ whal_Error whal_Nvic_Init(whal_Irq *irqDev) { - if (!irqDev) { - return WHAL_EINVAL; - } - + (void)irqDev; return WHAL_SUCCESS; } whal_Error whal_Nvic_Deinit(whal_Irq *irqDev) { - if (!irqDev) { - return WHAL_EINVAL; - } - + (void)irqDev; return WHAL_SUCCESS; } whal_Error whal_Nvic_Enable(whal_Irq *irqDev, size_t irq, const void *irqCfg) { - if (!irqDev) { - return WHAL_EINVAL; - } - - size_t base = irqDev->base; + size_t base = whal_Nvic_Dev.base; + (void)irqDev; /* Set priority if config provided */ if (irqCfg) { @@ -65,11 +57,8 @@ whal_Error whal_Nvic_Enable(whal_Irq *irqDev, size_t irq, whal_Error whal_Nvic_Disable(whal_Irq *irqDev, size_t irq) { - if (!irqDev) { - return WHAL_EINVAL; - } - - size_t base = irqDev->base; + size_t base = whal_Nvic_Dev.base; + (void)irqDev; whal_Reg_Write(base, NVIC_ICER_REG(irq), (1UL << (irq & 0x1F))); diff --git a/src/rng/stm32h5_rng.c b/src/rng/stm32h5_rng.c index 8b487c6..c0eaf3d 100644 --- a/src/rng/stm32h5_rng.c +++ b/src/rng/stm32h5_rng.c @@ -1,4 +1,5 @@ #include +#include "board.h" /* provides whal_Stm32h5_Rng_Dev singleton */ #include #include #include @@ -63,15 +64,11 @@ whal_Error whal_Stm32h5_Rng_Init(whal_Rng *rngDev) { - whal_Stm32h5_Rng_Cfg *cfg; - size_t base; + const whal_Stm32h5_Rng_Cfg *cfg = + (const whal_Stm32h5_Rng_Cfg *)whal_Stm32h5_Rng_Dev.cfg; + size_t base = whal_Stm32h5_Rng_Dev.base; whal_Error err; - - if (!rngDev || !rngDev->cfg) - return WHAL_EINVAL; - - cfg = (whal_Stm32h5_Rng_Cfg *)rngDev->cfg; - base = rngDev->base; + (void)rngDev; /* * Apply NIST-certified configuration via CONDRST sequence: @@ -99,11 +96,9 @@ whal_Error whal_Stm32h5_Rng_Init(whal_Rng *rngDev) whal_Error whal_Stm32h5_Rng_Deinit(whal_Rng *rngDev) { - if (!rngDev || !rngDev->cfg) - return WHAL_EINVAL; - + (void)rngDev; /* Disable the RNG peripheral */ - whal_Reg_Update(rngDev->base, RNG_CR_REG, RNG_CR_RNGEN_Msk, + whal_Reg_Update(whal_Stm32h5_Rng_Dev.base, RNG_CR_REG, RNG_CR_RNGEN_Msk, whal_SetBits(RNG_CR_RNGEN_Msk, RNG_CR_RNGEN_Pos, 0)); return WHAL_SUCCESS; @@ -114,16 +109,15 @@ whal_Error whal_Stm32h5_Rng_Generate(whal_Rng *rngDev, void *rngData, { uint8_t *rngBuf = (uint8_t *)rngData; whal_Error err = WHAL_SUCCESS; - whal_Stm32h5_Rng_Cfg *cfg; - size_t base; + const whal_Stm32h5_Rng_Cfg *cfg = + (const whal_Stm32h5_Rng_Cfg *)whal_Stm32h5_Rng_Dev.cfg; + size_t base = whal_Stm32h5_Rng_Dev.base; size_t sr; size_t offset = 0; + (void)rngDev; - if (!rngDev || !rngDev->cfg || !rngData) + if (!rngData) return WHAL_EINVAL; - - cfg = (whal_Stm32h5_Rng_Cfg *)rngDev->cfg; - base = rngDev->base; #ifdef WHAL_CFG_NO_TIMEOUT (void)(cfg); #endif diff --git a/src/rng/stm32wb_rng.c b/src/rng/stm32wb_rng.c index c9fa014..eb851f1 100644 --- a/src/rng/stm32wb_rng.c +++ b/src/rng/stm32wb_rng.c @@ -1,4 +1,5 @@ #include +#include "board.h" /* provides whal_Stm32wb_Rng_Dev singleton */ #include #include #include @@ -49,19 +50,13 @@ whal_Error whal_Stm32wb_Rng_Init(whal_Rng *rngDev) { - if (!rngDev || !rngDev->cfg) { - return WHAL_EINVAL; - } - + (void)rngDev; return WHAL_SUCCESS; } whal_Error whal_Stm32wb_Rng_Deinit(whal_Rng *rngDev) { - if (!rngDev || !rngDev->cfg) { - return WHAL_EINVAL; - } - + (void)rngDev; return WHAL_SUCCESS; } @@ -69,17 +64,16 @@ whal_Error whal_Stm32wb_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rng { uint8_t *rngBuf = (uint8_t *)rngData; whal_Error err = WHAL_SUCCESS; - whal_Stm32wb_Rng_Cfg *cfg; - size_t base; + const whal_Stm32wb_Rng_Cfg *cfg = + (const whal_Stm32wb_Rng_Cfg *)whal_Stm32wb_Rng_Dev.cfg; + size_t base = whal_Stm32wb_Rng_Dev.base; size_t sr; size_t offset = 0; + (void)rngDev; - if (!rngDev || !rngDev->cfg || !rngData) { + if (!rngData) { return WHAL_EINVAL; } - - cfg = (whal_Stm32wb_Rng_Cfg *)rngDev->cfg; - base = rngDev->base; #ifdef WHAL_CFG_NO_TIMEOUT (void)(cfg); #endif diff --git a/src/spi/stm32wb_spi.c b/src/spi/stm32wb_spi.c index e114233..6255958 100644 --- a/src/spi/stm32wb_spi.c +++ b/src/spi/stm32wb_spi.c @@ -1,4 +1,10 @@ #include +#if defined(WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32C0_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F0_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F3_SPI_SINGLE_INSTANCE) +#include "board.h" /* provides whal_Stm32wb_Spi_Dev singleton (possibly via platform alias macro) */ +#endif #include #include #include @@ -94,6 +100,13 @@ static uint32_t whal_Stm32wb_Spi_CalcBr(size_t pclk, uint32_t targetBaud) whal_Error whal_Stm32wb_Spi_Init(whal_Spi *spiDev) { +#if defined(WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32C0_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F0_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F3_SPI_SINGLE_INSTANCE) + size_t base = whal_Stm32wb_Spi_Dev.base; + (void)spiDev; +#else size_t base; if (!spiDev || !spiDev->cfg) { @@ -101,6 +114,7 @@ whal_Error whal_Stm32wb_Spi_Init(whal_Spi *spiDev) } base = spiDev->base; +#endif /* Master mode with software slave management */ whal_Reg_Update(base, SPI_CR1_REG, @@ -114,6 +128,13 @@ whal_Error whal_Stm32wb_Spi_Init(whal_Spi *spiDev) whal_Error whal_Stm32wb_Spi_Deinit(whal_Spi *spiDev) { +#if defined(WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32C0_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F0_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F3_SPI_SINGLE_INSTANCE) + size_t base = whal_Stm32wb_Spi_Dev.base; + (void)spiDev; +#else size_t base; if (!spiDev || !spiDev->cfg) { @@ -121,6 +142,7 @@ whal_Error whal_Stm32wb_Spi_Deinit(whal_Spi *spiDev) } base = spiDev->base; +#endif /* Disable SPI */ whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, @@ -131,13 +153,27 @@ whal_Error whal_Stm32wb_Spi_Deinit(whal_Spi *spiDev) whal_Error whal_Stm32wb_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) { + uint32_t cpol, cpha, br, ds, frxth; +#if defined(WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32C0_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F0_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F3_SPI_SINGLE_INSTANCE) + whal_Stm32wb_Spi_Cfg *cfg = + (whal_Stm32wb_Spi_Cfg *)whal_Stm32wb_Spi_Dev.cfg; + size_t base = whal_Stm32wb_Spi_Dev.base; + (void)spiDev; + + if (!comCfg) { + return WHAL_EINVAL; + } +#else size_t base; whal_Stm32wb_Spi_Cfg *cfg; - uint32_t cpol, cpha, br, ds, frxth; if (!spiDev || !spiDev->cfg || !comCfg) { return WHAL_EINVAL; } +#endif /* DS field encodes word size as (bits - 1); valid range 4-16 */ if (comCfg->wordSz < 4 || comCfg->wordSz > 16) { @@ -148,8 +184,13 @@ whal_Error whal_Stm32wb_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) return WHAL_EINVAL; } +#if !defined(WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE) && \ + !defined(WHAL_CFG_STM32C0_SPI_SINGLE_INSTANCE) && \ + !defined(WHAL_CFG_STM32F0_SPI_SINGLE_INSTANCE) && \ + !defined(WHAL_CFG_STM32F3_SPI_SINGLE_INSTANCE) base = spiDev->base; cfg = (whal_Stm32wb_Spi_Cfg *)spiDev->cfg; +#endif br = whal_Stm32wb_Spi_CalcBr(cfg->pclk, comCfg->freq); @@ -184,6 +225,13 @@ whal_Error whal_Stm32wb_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) whal_Error whal_Stm32wb_Spi_EndCom(whal_Spi *spiDev) { +#if defined(WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32C0_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F0_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F3_SPI_SINGLE_INSTANCE) + size_t base = whal_Stm32wb_Spi_Dev.base; + (void)spiDev; +#else size_t base; if (!spiDev || !spiDev->cfg) { @@ -191,6 +239,7 @@ whal_Error whal_Stm32wb_Spi_EndCom(whal_Spi *spiDev) } base = spiDev->base; +#endif /* Disable SPE */ whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, @@ -205,11 +254,24 @@ whal_Error whal_Stm32wb_Spi_SendRecv(whal_Spi *spiDev, { const uint8_t *txBuf = (const uint8_t *)tx; uint8_t *rxBuf = (uint8_t *)rx; - size_t base; - whal_Stm32wb_Spi_Cfg *cfg; size_t totalLen; whal_Error err; uint8_t txByte; +#if defined(WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32C0_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F0_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F3_SPI_SINGLE_INSTANCE) + whal_Stm32wb_Spi_Cfg *cfg = + (whal_Stm32wb_Spi_Cfg *)whal_Stm32wb_Spi_Dev.cfg; + size_t base = whal_Stm32wb_Spi_Dev.base; + (void)spiDev; + + if ((!tx && txLen) || (!rx && rxLen)) { + return WHAL_EINVAL; + } +#else + size_t base; + whal_Stm32wb_Spi_Cfg *cfg; if (!spiDev || !spiDev->cfg || (!tx && txLen) || (!rx && rxLen)) { return WHAL_EINVAL; @@ -217,6 +279,7 @@ whal_Error whal_Stm32wb_Spi_SendRecv(whal_Spi *spiDev, base = spiDev->base; cfg = (whal_Stm32wb_Spi_Cfg *)spiDev->cfg; +#endif totalLen = txLen > rxLen ? txLen : rxLen; for (size_t i = 0; i < totalLen; i++) { diff --git a/src/timer/systick.c b/src/timer/systick.c index bde5c8b..e5dd5b1 100644 --- a/src/timer/systick.c +++ b/src/timer/systick.c @@ -1,3 +1,4 @@ +#include "board.h" /* provides whal_SysTick_Dev singleton */ #include #include #include @@ -31,16 +32,10 @@ whal_Error whal_SysTick_Init(whal_Timer *timerDev) { - whal_SysTick_Cfg *cfg; - size_t base; - - if (!timerDev || !timerDev->cfg) { - return WHAL_EINVAL; - } - - base = timerDev->base; - - cfg = (whal_SysTick_Cfg *)timerDev->cfg; + const whal_SysTick_Cfg *cfg = + (const whal_SysTick_Cfg *)whal_SysTick_Dev.cfg; + size_t base = whal_SysTick_Dev.base; + (void)timerDev; whal_Reg_Update(base, SYSTICK_CSR_REG, SYSTICK_CSR_CLKSOURCE_Msk | SYSTICK_CSR_TICKINT_Msk, @@ -56,22 +51,14 @@ whal_Error whal_SysTick_Init(whal_Timer *timerDev) whal_Error whal_SysTick_Deinit(whal_Timer *timerDev) { - if (!timerDev) { - return WHAL_EINVAL; - } - + (void)timerDev; return WHAL_SUCCESS; } whal_Error whal_SysTick_Start(whal_Timer *timerDev) { - size_t base; - - if (!timerDev || !timerDev->cfg) { - return WHAL_EINVAL; - } - - base = timerDev->base; + size_t base = whal_SysTick_Dev.base; + (void)timerDev; whal_Reg_Update(base, SYSTICK_CSR_REG, SYSTICK_CSR_ENABLE_Msk, whal_SetBits(SYSTICK_CSR_ENABLE_Msk, SYSTICK_CSR_ENABLE_Pos, 1)); @@ -81,13 +68,8 @@ whal_Error whal_SysTick_Start(whal_Timer *timerDev) whal_Error whal_SysTick_Stop(whal_Timer *timerDev) { - size_t base; - - if (!timerDev || !timerDev->cfg) { - return WHAL_EINVAL; - } - - base = timerDev->base; + size_t base = whal_SysTick_Dev.base; + (void)timerDev; whal_Reg_Update(base, SYSTICK_CSR_REG, SYSTICK_CSR_ENABLE_Msk, whal_SetBits(SYSTICK_CSR_ENABLE_Msk, SYSTICK_CSR_ENABLE_Pos, 0)); @@ -97,10 +79,7 @@ whal_Error whal_SysTick_Stop(whal_Timer *timerDev) whal_Error whal_SysTick_Reset(whal_Timer *timerDev) { - if (!timerDev) { - return WHAL_EINVAL; - } - + (void)timerDev; return WHAL_SUCCESS; } diff --git a/src/uart/stm32wb_uart.c b/src/uart/stm32wb_uart.c index ff8c48d..6380ab1 100644 --- a/src/uart/stm32wb_uart.c +++ b/src/uart/stm32wb_uart.c @@ -1,4 +1,10 @@ #include +#if defined(WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32H5_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32C0_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_UART_SINGLE_INSTANCE) +#include "board.h" /* provides whal_Stm32wb_Uart_Dev singleton (possibly via platform alias macro) */ +#endif #include #include #include @@ -60,9 +66,18 @@ whal_Error whal_Stm32wb_Uart_Init(whal_Uart *uartDev) { + uint32_t brr; +#if defined(WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32H5_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32C0_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_UART_SINGLE_INSTANCE) + const whal_Stm32wb_Uart_Cfg *cfg = + (const whal_Stm32wb_Uart_Cfg *)whal_Stm32wb_Uart_Dev.cfg; + size_t base = whal_Stm32wb_Uart_Dev.base; + (void)uartDev; +#else whal_Stm32wb_Uart_Cfg *cfg; size_t base; - uint32_t brr; if (!uartDev || !uartDev->cfg) { return WHAL_EINVAL; @@ -70,6 +85,7 @@ whal_Error whal_Stm32wb_Uart_Init(whal_Uart *uartDev) base = uartDev->base; cfg = (whal_Stm32wb_Uart_Cfg *)uartDev->cfg; +#endif brr = cfg->brr; @@ -89,6 +105,13 @@ whal_Error whal_Stm32wb_Uart_Init(whal_Uart *uartDev) whal_Error whal_Stm32wb_Uart_Deinit(whal_Uart *uartDev) { +#if defined(WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32H5_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32C0_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_UART_SINGLE_INSTANCE) + size_t base = whal_Stm32wb_Uart_Dev.base; + (void)uartDev; +#else size_t base; if (!uartDev) { @@ -96,6 +119,7 @@ whal_Error whal_Stm32wb_Uart_Deinit(whal_Uart *uartDev) } base = uartDev->base; +#endif whal_Reg_Update(base, UART_CR1_REG, UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, @@ -112,9 +136,22 @@ whal_Error whal_Stm32wb_Uart_Deinit(whal_Uart *uartDev) whal_Error whal_Stm32wb_Uart_Send(whal_Uart *uartDev, const void *data, size_t dataSz) { + const uint8_t *buf = data; +#if defined(WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32H5_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32C0_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_UART_SINGLE_INSTANCE) + const whal_Stm32wb_Uart_Cfg *cfg = + (const whal_Stm32wb_Uart_Cfg *)whal_Stm32wb_Uart_Dev.cfg; + size_t base = whal_Stm32wb_Uart_Dev.base; + (void)uartDev; + + if (!data) { + return WHAL_EINVAL; + } +#else size_t base; whal_Stm32wb_Uart_Cfg *cfg; - const uint8_t *buf = data; if (!uartDev || !uartDev->cfg || !data) { return WHAL_EINVAL; @@ -122,6 +159,7 @@ whal_Error whal_Stm32wb_Uart_Send(whal_Uart *uartDev, const void *data, size_t d base = uartDev->base; cfg = (whal_Stm32wb_Uart_Cfg *)uartDev->cfg; +#endif for (size_t i = 0; i < dataSz; ++i) { whal_Error err; @@ -139,9 +177,22 @@ whal_Error whal_Stm32wb_Uart_Send(whal_Uart *uartDev, const void *data, size_t d whal_Error whal_Stm32wb_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) { + uint8_t *buf = data; +#if defined(WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32H5_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32C0_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_UART_SINGLE_INSTANCE) + const whal_Stm32wb_Uart_Cfg *cfg = + (const whal_Stm32wb_Uart_Cfg *)whal_Stm32wb_Uart_Dev.cfg; + size_t base = whal_Stm32wb_Uart_Dev.base; + (void)uartDev; + + if (!data) { + return WHAL_EINVAL; + } +#else size_t base; whal_Stm32wb_Uart_Cfg *cfg; - uint8_t *buf = data; if (!uartDev || !uartDev->cfg || !data) { return WHAL_EINVAL; @@ -149,6 +200,7 @@ whal_Error whal_Stm32wb_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) base = uartDev->base; cfg = (whal_Stm32wb_Uart_Cfg *)uartDev->cfg; +#endif size_t d; for (size_t i = 0; i < dataSz; ++i) { diff --git a/src/uart/stm32wb_uart_dma.c b/src/uart/stm32wb_uart_dma.c index 6e3e8a7..65c1988 100644 --- a/src/uart/stm32wb_uart_dma.c +++ b/src/uart/stm32wb_uart_dma.c @@ -1,4 +1,7 @@ #include +#ifdef WHAL_CFG_STM32WB_UART_DMA_SINGLE_INSTANCE +#include "board.h" /* provides whal_Stm32wb_UartDma_Dev singleton */ +#endif #include #include #include @@ -38,23 +41,32 @@ whal_Error whal_Stm32wb_UartDma_SendAsync(whal_Uart *uartDev, const void *data, size_t dataSz) { + whal_Error err; +#ifdef WHAL_CFG_STM32WB_UART_DMA_SINGLE_INSTANCE + whal_Stm32wb_UartDma_Cfg *cfg = + (whal_Stm32wb_UartDma_Cfg *)whal_Stm32wb_UartDma_Dev.cfg; + size_t base = whal_Stm32wb_UartDma_Dev.base; + (void)uartDev; + + if (!data || dataSz > UINT16_MAX) + return WHAL_EINVAL; +#else whal_Stm32wb_UartDma_Cfg *cfg; size_t base; - whal_Error err; if (!uartDev || !uartDev->cfg || !data || dataSz > UINT16_MAX) return WHAL_EINVAL; + cfg = (whal_Stm32wb_UartDma_Cfg *)uartDev->cfg; + base = uartDev->base; +#endif + if (dataSz == 0) return WHAL_SUCCESS; - cfg = (whal_Stm32wb_UartDma_Cfg *)uartDev->cfg; - if (cfg->txResult == WHAL_ENOTREADY) return WHAL_ENOTREADY; - base = uartDev->base; - cfg->txChCfg->srcAddr = (uint32_t)(uintptr_t)data; cfg->txChCfg->dstAddr = (uint32_t)(base + UART_TDR_REG); cfg->txChCfg->length = dataSz; @@ -83,23 +95,32 @@ whal_Error whal_Stm32wb_UartDma_SendAsync(whal_Uart *uartDev, const void *data, whal_Error whal_Stm32wb_UartDma_RecvAsync(whal_Uart *uartDev, void *data, size_t dataSz) { + whal_Error err; +#ifdef WHAL_CFG_STM32WB_UART_DMA_SINGLE_INSTANCE + whal_Stm32wb_UartDma_Cfg *cfg = + (whal_Stm32wb_UartDma_Cfg *)whal_Stm32wb_UartDma_Dev.cfg; + size_t base = whal_Stm32wb_UartDma_Dev.base; + (void)uartDev; + + if (!data || dataSz > UINT16_MAX) + return WHAL_EINVAL; +#else whal_Stm32wb_UartDma_Cfg *cfg; size_t base; - whal_Error err; if (!uartDev || !uartDev->cfg || !data || dataSz > UINT16_MAX) return WHAL_EINVAL; + cfg = (whal_Stm32wb_UartDma_Cfg *)uartDev->cfg; + base = uartDev->base; +#endif + if (dataSz == 0) return WHAL_SUCCESS; - cfg = (whal_Stm32wb_UartDma_Cfg *)uartDev->cfg; - if (cfg->rxResult == WHAL_ENOTREADY) return WHAL_ENOTREADY; - base = uartDev->base; - cfg->rxChCfg->srcAddr = (uint32_t)(base + UART_RDR_REG); cfg->rxChCfg->dstAddr = (uint32_t)(uintptr_t)data; cfg->rxChCfg->length = dataSz; @@ -129,13 +150,20 @@ whal_Error whal_Stm32wb_UartDma_Send(whal_Uart *uartDev, const void *data, size_t dataSz) { whal_Stm32wb_UartDma_Cfg *cfg; + size_t base; whal_Error err; err = whal_Stm32wb_UartDma_SendAsync(uartDev, data, dataSz); if (err) return err; +#ifdef WHAL_CFG_STM32WB_UART_DMA_SINGLE_INSTANCE + cfg = (whal_Stm32wb_UartDma_Cfg *)whal_Stm32wb_UartDma_Dev.cfg; + base = whal_Stm32wb_UartDma_Dev.base; +#else cfg = (whal_Stm32wb_UartDma_Cfg *)uartDev->cfg; + base = uartDev->base; +#endif WHAL_TIMEOUT_START(cfg->base.timeout); while (cfg->txResult == WHAL_ENOTREADY) { @@ -150,12 +178,12 @@ whal_Error whal_Stm32wb_UartDma_Send(whal_Uart *uartDev, const void *data, goto cleanup; } - err = whal_Reg_ReadPoll(uartDev->base, UART_ISR_REG, + err = whal_Reg_ReadPoll(base, UART_ISR_REG, UART_ISR_TC_Msk, UART_ISR_TC_Msk, cfg->base.timeout); cleanup: whal_Dma_Stop(cfg->dma, cfg->txCh); - whal_Reg_Update(uartDev->base, UART_CR3_REG, UART_CR3_DMAT_Msk, 0); + whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAT_Msk, 0); cfg->txResult = err; return err; @@ -165,13 +193,20 @@ whal_Error whal_Stm32wb_UartDma_Recv(whal_Uart *uartDev, void *data, size_t dataSz) { whal_Stm32wb_UartDma_Cfg *cfg; + size_t base; whal_Error err; err = whal_Stm32wb_UartDma_RecvAsync(uartDev, data, dataSz); if (err) return err; +#ifdef WHAL_CFG_STM32WB_UART_DMA_SINGLE_INSTANCE + cfg = (whal_Stm32wb_UartDma_Cfg *)whal_Stm32wb_UartDma_Dev.cfg; + base = whal_Stm32wb_UartDma_Dev.base; +#else cfg = (whal_Stm32wb_UartDma_Cfg *)uartDev->cfg; + base = uartDev->base; +#endif WHAL_TIMEOUT_START(cfg->base.timeout); while (cfg->rxResult == WHAL_ENOTREADY) { @@ -185,7 +220,7 @@ whal_Error whal_Stm32wb_UartDma_Recv(whal_Uart *uartDev, void *data, cleanup: whal_Dma_Stop(cfg->dma, cfg->rxCh); - whal_Reg_Update(uartDev->base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); + whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); cfg->rxResult = err; return err; @@ -213,4 +248,3 @@ const whal_UartDriver whal_Stm32wb_UartDma_Driver = { .RecvAsync = whal_Stm32wb_UartDma_RecvAsync, }; #endif /* !WHAL_CFG_STM32WB_UART_DMA_DIRECT_API_MAPPING */ - diff --git a/src/watchdog/stm32wb_iwdg.c b/src/watchdog/stm32wb_iwdg.c index 9c1df96..76770d3 100644 --- a/src/watchdog/stm32wb_iwdg.c +++ b/src/watchdog/stm32wb_iwdg.c @@ -1,3 +1,4 @@ +#include "board.h" /* provides whal_Stm32wb_Iwdg_Dev singleton */ #include #include #include @@ -46,16 +47,11 @@ whal_Error whal_Stm32wb_Iwdg_Init(whal_Watchdog *wdgDev) { - size_t base; - whal_Stm32wb_Iwdg_Cfg *cfg; + const whal_Stm32wb_Iwdg_Cfg *cfg = + (const whal_Stm32wb_Iwdg_Cfg *)whal_Stm32wb_Iwdg_Dev.cfg; + size_t base = whal_Stm32wb_Iwdg_Dev.base; whal_Error err; - - if (!wdgDev || !wdgDev->cfg) { - return WHAL_EINVAL; - } - - base = wdgDev->base; - cfg = wdgDev->cfg; + (void)wdgDev; if (cfg->prescaler > 6 || cfg->reload > 0xFFF) { return WHAL_EINVAL; @@ -88,20 +84,14 @@ whal_Error whal_Stm32wb_Iwdg_Init(whal_Watchdog *wdgDev) whal_Error whal_Stm32wb_Iwdg_Deinit(whal_Watchdog *wdgDev) { - if (!wdgDev) { - return WHAL_EINVAL; - } - + (void)wdgDev; return WHAL_SUCCESS; } whal_Error whal_Stm32wb_Iwdg_Refresh(whal_Watchdog *wdgDev) { - if (!wdgDev) { - return WHAL_EINVAL; - } - - whal_Reg_Write(wdgDev->base, IWDG_KR_REG, IWDG_KEY_RELOAD); + (void)wdgDev; + whal_Reg_Write(whal_Stm32wb_Iwdg_Dev.base, IWDG_KR_REG, IWDG_KEY_RELOAD); return WHAL_SUCCESS; } diff --git a/src/watchdog/stm32wb_wwdg.c b/src/watchdog/stm32wb_wwdg.c index 2a7adad..182508e 100644 --- a/src/watchdog/stm32wb_wwdg.c +++ b/src/watchdog/stm32wb_wwdg.c @@ -1,3 +1,4 @@ +#include "board.h" /* provides whal_Stm32wb_Wwdg_Dev singleton */ #include #include #include @@ -32,14 +33,10 @@ whal_Error whal_Stm32wb_Wwdg_Init(whal_Watchdog *wdgDev) { - size_t base; - whal_Stm32wb_Wwdg_Cfg *cfg; - - if (!wdgDev || !wdgDev->cfg) - return WHAL_EINVAL; - - base = wdgDev->base; - cfg = wdgDev->cfg; + const whal_Stm32wb_Wwdg_Cfg *cfg = + (const whal_Stm32wb_Wwdg_Cfg *)whal_Stm32wb_Wwdg_Dev.cfg; + size_t base = whal_Stm32wb_Wwdg_Dev.base; + (void)wdgDev; if (cfg->prescaler > 7 || cfg->window > 0x7F || cfg->counter > 0x7F) return WHAL_EINVAL; @@ -59,23 +56,16 @@ whal_Error whal_Stm32wb_Wwdg_Init(whal_Watchdog *wdgDev) whal_Error whal_Stm32wb_Wwdg_Deinit(whal_Watchdog *wdgDev) { - if (!wdgDev) { - return WHAL_EINVAL; - } - + (void)wdgDev; return WHAL_SUCCESS; } whal_Error whal_Stm32wb_Wwdg_Refresh(whal_Watchdog *wdgDev) { - size_t base; - whal_Stm32wb_Wwdg_Cfg *cfg; - - if (!wdgDev || !wdgDev->cfg) - return WHAL_EINVAL; - - base = wdgDev->base; - cfg = wdgDev->cfg; + const whal_Stm32wb_Wwdg_Cfg *cfg = + (const whal_Stm32wb_Wwdg_Cfg *)whal_Stm32wb_Wwdg_Dev.cfg; + size_t base = whal_Stm32wb_Wwdg_Dev.base; + (void)wdgDev; whal_Reg_Update(base, CR_REG, CR_T_Msk, whal_SetBits(CR_T_Msk, CR_T_Pos, cfg->counter)); diff --git a/wolfHAL/clock/stm32h5_rcc.h b/wolfHAL/clock/stm32h5_rcc.h index 9f3e6ea..7aaced6 100644 --- a/wolfHAL/clock/stm32h5_rcc.h +++ b/wolfHAL/clock/stm32h5_rcc.h @@ -2,26 +2,54 @@ #define WHAL_STM32H5_RCC_H #include -#include #include +#include +#include +#include +#include /* * @file stm32h5_rcc.h * @brief STM32H5 RCC (Reset and Clock Control) driver. * * Boards bring up the clock tree imperatively from Board_Init. - * - * Clock sources: - * HSI = 64 MHz internal RC (with HSIDIV) - * CSI = 4 MHz low-power internal - * HSE = external crystal/oscillator - * HSI48 = 48 MHz (for RNG/USB) - * PLL1 = source/m * (n+1) / (p+1) (SYSCLK) */ -/* - * @brief System clock source selection (RCC_CFGR1.SW). - */ +#define WHAL_STM32H5_RCC_CR_REG 0x000 +#define WHAL_STM32H5_RCC_CR_HSIDIV_Pos 3 +#define WHAL_STM32H5_RCC_CR_HSIDIV_Msk (WHAL_BITMASK(2) << WHAL_STM32H5_RCC_CR_HSIDIV_Pos) +#define WHAL_STM32H5_RCC_CR_PLL1ON_Msk (1UL << 24) +#define WHAL_STM32H5_RCC_CR_PLL1RDY_Msk (1UL << 25) +#define WHAL_STM32H5_RCC_CR_PLL1RDY_Pos 25 + +#define WHAL_STM32H5_RCC_CFGR1_REG 0x01C +#define WHAL_STM32H5_RCC_CFGR1_SW_Pos 0 +#define WHAL_STM32H5_RCC_CFGR1_SW_Msk (WHAL_BITMASK(2) << WHAL_STM32H5_RCC_CFGR1_SW_Pos) +#define WHAL_STM32H5_RCC_CFGR1_SWS_Pos 3 +#define WHAL_STM32H5_RCC_CFGR1_SWS_Msk (WHAL_BITMASK(2) << WHAL_STM32H5_RCC_CFGR1_SWS_Pos) + +#define WHAL_STM32H5_RCC_PLL1CFGR_REG 0x028 +#define WHAL_STM32H5_RCC_PLL1CFGR_PLL1SRC_Pos 0 +#define WHAL_STM32H5_RCC_PLL1CFGR_PLL1SRC_Msk (WHAL_BITMASK(2) << WHAL_STM32H5_RCC_PLL1CFGR_PLL1SRC_Pos) +#define WHAL_STM32H5_RCC_PLL1CFGR_PLL1M_Pos 8 +#define WHAL_STM32H5_RCC_PLL1CFGR_PLL1M_Msk (WHAL_BITMASK(6) << WHAL_STM32H5_RCC_PLL1CFGR_PLL1M_Pos) +#define WHAL_STM32H5_RCC_PLL1CFGR_PLL1PEN_Pos 16 +#define WHAL_STM32H5_RCC_PLL1CFGR_PLL1PEN_Msk (1UL << WHAL_STM32H5_RCC_PLL1CFGR_PLL1PEN_Pos) +#define WHAL_STM32H5_RCC_PLL1CFGR_PLL1QEN_Pos 17 +#define WHAL_STM32H5_RCC_PLL1CFGR_PLL1QEN_Msk (1UL << WHAL_STM32H5_RCC_PLL1CFGR_PLL1QEN_Pos) +#define WHAL_STM32H5_RCC_PLL1CFGR_PLL1REN_Pos 18 +#define WHAL_STM32H5_RCC_PLL1CFGR_PLL1REN_Msk (1UL << WHAL_STM32H5_RCC_PLL1CFGR_PLL1REN_Pos) + +#define WHAL_STM32H5_RCC_PLL1DIVR_REG 0x034 +#define WHAL_STM32H5_RCC_PLL1DIVR_PLL1N_Pos 0 +#define WHAL_STM32H5_RCC_PLL1DIVR_PLL1N_Msk (WHAL_BITMASK(9) << WHAL_STM32H5_RCC_PLL1DIVR_PLL1N_Pos) +#define WHAL_STM32H5_RCC_PLL1DIVR_PLL1P_Pos 9 +#define WHAL_STM32H5_RCC_PLL1DIVR_PLL1P_Msk (WHAL_BITMASK(7) << WHAL_STM32H5_RCC_PLL1DIVR_PLL1P_Pos) +#define WHAL_STM32H5_RCC_PLL1DIVR_PLL1Q_Pos 16 +#define WHAL_STM32H5_RCC_PLL1DIVR_PLL1Q_Msk (WHAL_BITMASK(7) << WHAL_STM32H5_RCC_PLL1DIVR_PLL1Q_Pos) +#define WHAL_STM32H5_RCC_PLL1DIVR_PLL1R_Pos 24 +#define WHAL_STM32H5_RCC_PLL1DIVR_PLL1R_Msk (WHAL_BITMASK(7) << WHAL_STM32H5_RCC_PLL1DIVR_PLL1R_Pos) + typedef enum { WHAL_STM32H5_RCC_SYSCLK_SRC_HSI, WHAL_STM32H5_RCC_SYSCLK_SRC_CSI, @@ -29,9 +57,6 @@ typedef enum { WHAL_STM32H5_RCC_SYSCLK_SRC_PLL1, } whal_Stm32h5_Rcc_SysClockSrc; -/* - * @brief PLL input clock source selection. - */ typedef enum { WHAL_STM32H5_RCC_PLLCLK_SRC_NONE, WHAL_STM32H5_RCC_PLLCLK_SRC_HSI, @@ -39,12 +64,6 @@ typedef enum { WHAL_STM32H5_RCC_PLLCLK_SRC_HSE, } whal_Stm32h5_Rcc_PllClockSrc; -/* - * @brief PLL1 configuration parameters. - * m: 1-63 (input / m must be 1-16 MHz) - * n: 3-511 (VCO = input * (n+1)) - * p, q, r: 0-127 (output / (value+1)) - */ typedef struct { whal_Stm32h5_Rcc_PllClockSrc clkSrc; uint16_t n; @@ -54,18 +73,12 @@ typedef struct { uint8_t r; } whal_Stm32h5_Rcc_PllCfg; -/* - * @brief Peripheral clock descriptor. - */ typedef struct { size_t regOffset; size_t enableMask; size_t enablePos; } whal_Stm32h5_Rcc_PeriphClk; -/* - * @brief Cfg for EnableOsc/DisableOsc — on bit + ready bit. - */ typedef struct { size_t onReg; size_t onMsk; @@ -87,48 +100,128 @@ typedef struct { .onReg = 0x000, .onMsk = (1UL << 16), \ .rdyReg = 0x000, .rdyMsk = (1UL << 17), .rdyPos = 17 -/* - * @brief Enable an oscillator (HSI/CSI/HSI48/HSE). Blocks until ready. - */ -whal_Error whal_Stm32h5_Rcc_EnableOsc(whal_Clock *clkDev, - const whal_Stm32h5_Rcc_OscCfg *cfg); -/* - * @brief Disable an oscillator. - */ -whal_Error whal_Stm32h5_Rcc_DisableOsc(whal_Clock *clkDev, - const whal_Stm32h5_Rcc_OscCfg *cfg); +static inline whal_Error whal_Stm32h5_Rcc_EnableOsc( + const whal_Clock *clkDev, const whal_Stm32h5_Rcc_OscCfg *cfg) +{ + size_t rdy; -/* - * @brief Configure and enable PLL1. Caller must have the PLL source - * oscillator already enabled. Blocks until PLL1 is ready. - */ -whal_Error whal_Stm32h5_Rcc_EnablePll1(whal_Clock *clkDev, - const whal_Stm32h5_Rcc_PllCfg *cfg); -/* - * @brief Disable PLL1. - */ -whal_Error whal_Stm32h5_Rcc_DisablePll1(whal_Clock *clkDev); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); + do { + whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} -/* - * @brief Switch SYSCLK to the given source. Blocks until SWS confirms. - */ -whal_Error whal_Stm32h5_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32h5_Rcc_SysClockSrc src); +static inline whal_Error whal_Stm32h5_Rcc_DisableOsc( + const whal_Clock *clkDev, const whal_Stm32h5_Rcc_OscCfg *cfg) +{ + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); + return WHAL_SUCCESS; +} -/* - * @brief Set the HSI divider (0=div1, 1=div2, 2=div4, 3=div8). - */ -whal_Error whal_Stm32h5_Rcc_SetHsiDiv(whal_Clock *clkDev, uint8_t div); +static inline whal_Error whal_Stm32h5_Rcc_EnablePll1( + const whal_Clock *clkDev, const whal_Stm32h5_Rcc_PllCfg *cfg) +{ + size_t rdy; -/* - * @brief Enable a peripheral clock. - */ -whal_Error whal_Stm32h5_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32h5_Rcc_PeriphClk *clk); -/* - * @brief Disable a peripheral clock. - */ -whal_Error whal_Stm32h5_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32h5_Rcc_PeriphClk *clk); + whal_Reg_Update(clkDev->base, WHAL_STM32H5_RCC_CR_REG, + WHAL_STM32H5_RCC_CR_PLL1ON_Msk, 0); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32H5_RCC_CR_REG, + WHAL_STM32H5_RCC_CR_PLL1RDY_Msk, + WHAL_STM32H5_RCC_CR_PLL1RDY_Pos, &rdy); + } while (rdy); + + whal_Reg_Update(clkDev->base, WHAL_STM32H5_RCC_PLL1CFGR_REG, + WHAL_STM32H5_RCC_PLL1CFGR_PLL1SRC_Msk | + WHAL_STM32H5_RCC_PLL1CFGR_PLL1M_Msk | + WHAL_STM32H5_RCC_PLL1CFGR_PLL1PEN_Msk | + WHAL_STM32H5_RCC_PLL1CFGR_PLL1QEN_Msk | + WHAL_STM32H5_RCC_PLL1CFGR_PLL1REN_Msk, + whal_SetBits(WHAL_STM32H5_RCC_PLL1CFGR_PLL1SRC_Msk, + WHAL_STM32H5_RCC_PLL1CFGR_PLL1SRC_Pos, cfg->clkSrc) | + whal_SetBits(WHAL_STM32H5_RCC_PLL1CFGR_PLL1M_Msk, + WHAL_STM32H5_RCC_PLL1CFGR_PLL1M_Pos, cfg->m) | + whal_SetBits(WHAL_STM32H5_RCC_PLL1CFGR_PLL1PEN_Msk, + WHAL_STM32H5_RCC_PLL1CFGR_PLL1PEN_Pos, 1) | + whal_SetBits(WHAL_STM32H5_RCC_PLL1CFGR_PLL1QEN_Msk, + WHAL_STM32H5_RCC_PLL1CFGR_PLL1QEN_Pos, 1) | + whal_SetBits(WHAL_STM32H5_RCC_PLL1CFGR_PLL1REN_Msk, + WHAL_STM32H5_RCC_PLL1CFGR_PLL1REN_Pos, 1)); + whal_Reg_Update(clkDev->base, WHAL_STM32H5_RCC_PLL1DIVR_REG, + WHAL_STM32H5_RCC_PLL1DIVR_PLL1N_Msk | + WHAL_STM32H5_RCC_PLL1DIVR_PLL1P_Msk | + WHAL_STM32H5_RCC_PLL1DIVR_PLL1Q_Msk | + WHAL_STM32H5_RCC_PLL1DIVR_PLL1R_Msk, + whal_SetBits(WHAL_STM32H5_RCC_PLL1DIVR_PLL1N_Msk, + WHAL_STM32H5_RCC_PLL1DIVR_PLL1N_Pos, cfg->n) | + whal_SetBits(WHAL_STM32H5_RCC_PLL1DIVR_PLL1P_Msk, + WHAL_STM32H5_RCC_PLL1DIVR_PLL1P_Pos, cfg->p) | + whal_SetBits(WHAL_STM32H5_RCC_PLL1DIVR_PLL1Q_Msk, + WHAL_STM32H5_RCC_PLL1DIVR_PLL1Q_Pos, cfg->q) | + whal_SetBits(WHAL_STM32H5_RCC_PLL1DIVR_PLL1R_Msk, + WHAL_STM32H5_RCC_PLL1DIVR_PLL1R_Pos, cfg->r)); + + whal_Reg_Update(clkDev->base, WHAL_STM32H5_RCC_CR_REG, + WHAL_STM32H5_RCC_CR_PLL1ON_Msk, + WHAL_STM32H5_RCC_CR_PLL1ON_Msk); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32H5_RCC_CR_REG, + WHAL_STM32H5_RCC_CR_PLL1RDY_Msk, + WHAL_STM32H5_RCC_CR_PLL1RDY_Pos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + +static inline whal_Error whal_Stm32h5_Rcc_DisablePll1(const whal_Clock *clkDev) +{ + whal_Reg_Update(clkDev->base, WHAL_STM32H5_RCC_CR_REG, + WHAL_STM32H5_RCC_CR_PLL1ON_Msk, 0); + return WHAL_SUCCESS; +} + +static inline whal_Error whal_Stm32h5_Rcc_SetSysClock( + const whal_Clock *clkDev, whal_Stm32h5_Rcc_SysClockSrc src) +{ + size_t sws; + + whal_Reg_Update(clkDev->base, WHAL_STM32H5_RCC_CFGR1_REG, + WHAL_STM32H5_RCC_CFGR1_SW_Msk, + whal_SetBits(WHAL_STM32H5_RCC_CFGR1_SW_Msk, + WHAL_STM32H5_RCC_CFGR1_SW_Pos, src)); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32H5_RCC_CFGR1_REG, + WHAL_STM32H5_RCC_CFGR1_SWS_Msk, + WHAL_STM32H5_RCC_CFGR1_SWS_Pos, &sws); + } while (sws != (size_t)src); + return WHAL_SUCCESS; +} + +static inline whal_Error whal_Stm32h5_Rcc_SetHsiDiv( + const whal_Clock *clkDev, uint8_t div) +{ + whal_Reg_Update(clkDev->base, WHAL_STM32H5_RCC_CR_REG, + WHAL_STM32H5_RCC_CR_HSIDIV_Msk, + whal_SetBits(WHAL_STM32H5_RCC_CR_HSIDIV_Msk, + WHAL_STM32H5_RCC_CR_HSIDIV_Pos, div)); + return WHAL_SUCCESS; +} + +static inline whal_Error whal_Stm32h5_Rcc_EnablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32h5_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); + return WHAL_SUCCESS; +} + +static inline whal_Error whal_Stm32h5_Rcc_DisablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32h5_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); + return WHAL_SUCCESS; +} #endif /* WHAL_STM32H5_RCC_H */ diff --git a/wolfHAL/clock/stm32wb_rcc.h b/wolfHAL/clock/stm32wb_rcc.h index 7a597af..d45edc6 100644 --- a/wolfHAL/clock/stm32wb_rcc.h +++ b/wolfHAL/clock/stm32wb_rcc.h @@ -2,29 +2,57 @@ #define WHAL_STM32WB_RCC_H #include -#include #include +#include +#include +#include +#include /* * @file stm32wb_rcc.h * @brief STM32WB RCC (Reset and Clock Control) driver. * * Boards bring up the clock tree imperatively from Board_Init by calling - * the helpers below in order: - * - * whal_Stm32wb_Rcc_EnableMsi(...); - * whal_Stm32wb_Rcc_EnablePll(..., &pllCfg); - * whal_Stm32wb_Rcc_EnableOsc(..., &hsi48Cfg); - * whal_Stm32wb_Rcc_SetSysClock(..., WHAL_STM32WB_RCC_SYSCLK_SRC_PLL); - * for each peripheral clock: whal_Stm32wb_Rcc_EnablePeriphClk(...); - * - * The driver does not provide a declarative tree or an Init/Deinit - * walker — boards know their own bring-up order. + * the helpers below in order. */ -/* - * @brief System clock source selection (RCC_CFGR.SW). - */ +#define WHAL_STM32WB_RCC_CR_REG 0x000 +#define WHAL_STM32WB_RCC_CR_MSION_Msk (1UL << 0) +#define WHAL_STM32WB_RCC_CR_MSIRDY_Msk (1UL << 1) +#define WHAL_STM32WB_RCC_CR_MSIRDY_Pos 1 +#define WHAL_STM32WB_RCC_CR_MSIRANGE_Pos 4 +#define WHAL_STM32WB_RCC_CR_MSIRANGE_Msk (WHAL_BITMASK(4) << WHAL_STM32WB_RCC_CR_MSIRANGE_Pos) +#define WHAL_STM32WB_RCC_CR_PLLON_Msk (1UL << 24) +#define WHAL_STM32WB_RCC_CR_PLLRDY_Msk (1UL << 25) +#define WHAL_STM32WB_RCC_CR_PLLRDY_Pos 25 + +#define WHAL_STM32WB_RCC_CFGR_REG 0x008 +#define WHAL_STM32WB_RCC_CFGR_SW_Pos 0 +#define WHAL_STM32WB_RCC_CFGR_SW_Msk (WHAL_BITMASK(2) << WHAL_STM32WB_RCC_CFGR_SW_Pos) +#define WHAL_STM32WB_RCC_CFGR_SWS_Pos 2 +#define WHAL_STM32WB_RCC_CFGR_SWS_Msk (WHAL_BITMASK(2) << WHAL_STM32WB_RCC_CFGR_SWS_Pos) + +#define WHAL_STM32WB_RCC_PLLCFGR_REG 0x00C +#define WHAL_STM32WB_RCC_PLLCFGR_PLLSRC_Pos 0 +#define WHAL_STM32WB_RCC_PLLCFGR_PLLSRC_Msk (WHAL_BITMASK(2) << WHAL_STM32WB_RCC_PLLCFGR_PLLSRC_Pos) +#define WHAL_STM32WB_RCC_PLLCFGR_PLLM_Pos 4 +#define WHAL_STM32WB_RCC_PLLCFGR_PLLM_Msk (WHAL_BITMASK(3) << WHAL_STM32WB_RCC_PLLCFGR_PLLM_Pos) +#define WHAL_STM32WB_RCC_PLLCFGR_PLLN_Pos 8 +#define WHAL_STM32WB_RCC_PLLCFGR_PLLN_Msk (WHAL_BITMASK(7) << WHAL_STM32WB_RCC_PLLCFGR_PLLN_Pos) +#define WHAL_STM32WB_RCC_PLLCFGR_PLLP_Pos 17 +#define WHAL_STM32WB_RCC_PLLCFGR_PLLP_Msk (WHAL_BITMASK(5) << WHAL_STM32WB_RCC_PLLCFGR_PLLP_Pos) +#define WHAL_STM32WB_RCC_PLLCFGR_PLLQ_Pos 25 +#define WHAL_STM32WB_RCC_PLLCFGR_PLLQ_Msk (WHAL_BITMASK(3) << WHAL_STM32WB_RCC_PLLCFGR_PLLQ_Pos) +#define WHAL_STM32WB_RCC_PLLCFGR_PLLREN_Pos 28 +#define WHAL_STM32WB_RCC_PLLCFGR_PLLREN_Msk (1UL << WHAL_STM32WB_RCC_PLLCFGR_PLLREN_Pos) +#define WHAL_STM32WB_RCC_PLLCFGR_PLLR_Pos 29 +#define WHAL_STM32WB_RCC_PLLCFGR_PLLR_Msk (WHAL_BITMASK(3) << WHAL_STM32WB_RCC_PLLCFGR_PLLR_Pos) +#define WHAL_STM32WB_RCC_PLLCFGR_Msk \ + (WHAL_STM32WB_RCC_PLLCFGR_PLLSRC_Msk | WHAL_STM32WB_RCC_PLLCFGR_PLLM_Msk | \ + WHAL_STM32WB_RCC_PLLCFGR_PLLN_Msk | WHAL_STM32WB_RCC_PLLCFGR_PLLP_Msk | \ + WHAL_STM32WB_RCC_PLLCFGR_PLLQ_Msk | WHAL_STM32WB_RCC_PLLCFGR_PLLREN_Msk | \ + WHAL_STM32WB_RCC_PLLCFGR_PLLR_Msk) + typedef enum { WHAL_STM32WB_RCC_SYSCLK_SRC_MSI, WHAL_STM32WB_RCC_SYSCLK_SRC_HSI16, @@ -32,9 +60,6 @@ typedef enum { WHAL_STM32WB_RCC_SYSCLK_SRC_PLL, } whal_Stm32wb_Rcc_SysClockSrc; -/* - * @brief PLL input clock source selection (RCC_PLLCFGR.PLLSRC). - */ typedef enum { WHAL_STM32WB_RCC_PLLCLK_SRC_NONE, WHAL_STM32WB_RCC_PLLCLK_SRC_MSI, @@ -42,9 +67,6 @@ typedef enum { WHAL_STM32WB_RCC_PLLCLK_SRC_HSE, } whal_Stm32wb_Rcc_PllClockSrc; -/* - * @brief MSI oscillator frequency range (RCC_CR.MSIRANGE). - */ typedef enum { WHAL_STM32WB_RCC_MSIRANGE_100kHz, WHAL_STM32WB_RCC_MSIRANGE_200kHz, @@ -60,20 +82,12 @@ typedef enum { WHAL_STM32WB_RCC_MSIRANGE_48MHz, } whal_Stm32wb_Rcc_MsiRange; -/* - * @brief Peripheral clock descriptor (RCC *ENR enable bit). - */ typedef struct { size_t regOffset; size_t enableMask; size_t enablePos; } whal_Stm32wb_Rcc_PeriphClk; -/* - * @brief Cfg for EnableOsc/DisableOsc — on bit + ready bit. Boards - * construct one with the WHAL_STM32WB_RCC_*_CFG macros below. - * NOTE: LSE assumes PWR_CR1.DBP has been set by the caller. - */ typedef struct { size_t onReg; size_t onMsk; @@ -98,23 +112,6 @@ typedef struct { .onReg = 0x090, .onMsk = (1UL << 0), \ .rdyReg = 0x090, .rdyMsk = (1UL << 1), .rdyPos = 1 -/* - * @brief PLL configuration parameters. - * - * The PLL output frequency is calculated as: - * f_vco = (f_input / m) * n - * f_pllr = f_vco / r (main PLL output, used for SYSCLK) - * f_pllq = f_vco / q (used for USB, RNG, etc.) - * f_pllp = f_vco / p (used for SAI, etc.) - * - * Constraints: - * - VCO frequency must be 96-344 MHz - * - PLL input (f_input / m) must be 2.66-16 MHz - * - n: 8-127 - * - m: 1-8 (register value 0-7) - * - r, q: 2, 4, 6, 8 (register value 0-3 maps to div by 2/4/6/8) - * - p: 2-32 (register value 1-31, 0 reserved) - */ typedef struct { whal_Stm32wb_Rcc_PllClockSrc clkSrc; uint8_t r; @@ -124,51 +121,116 @@ typedef struct { uint8_t m; } whal_Stm32wb_Rcc_PllCfg; -/* - * @brief Enable an oscillator (HSI/HSE/HSI48/LSI/LSE) and block until - * the ready bit is set. - */ -whal_Error whal_Stm32wb_Rcc_EnableOsc(whal_Clock *clkDev, - const whal_Stm32wb_Rcc_OscCfg *cfg); -/* - * @brief Disable an oscillator. - */ -whal_Error whal_Stm32wb_Rcc_DisableOsc(whal_Clock *clkDev, - const whal_Stm32wb_Rcc_OscCfg *cfg); +static inline whal_Error whal_Stm32wb_Rcc_EnableOsc( + const whal_Clock *clkDev, const whal_Stm32wb_Rcc_OscCfg *cfg) +{ + size_t rdy; -/* - * @brief Enable the MSI oscillator at the given range. Blocks until ready. - */ -whal_Error whal_Stm32wb_Rcc_EnableMsi(whal_Clock *clkDev, - whal_Stm32wb_Rcc_MsiRange range); + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); + do { + whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} -/* - * @brief Configure the PLL dividers/source and enable it. Blocks until - * the PLL ready bit is set. - */ -whal_Error whal_Stm32wb_Rcc_EnablePll(whal_Clock *clkDev, - const whal_Stm32wb_Rcc_PllCfg *cfg); -/* - * @brief Disable the PLL. - */ -whal_Error whal_Stm32wb_Rcc_DisablePll(whal_Clock *clkDev); +static inline whal_Error whal_Stm32wb_Rcc_DisableOsc( + const whal_Clock *clkDev, const whal_Stm32wb_Rcc_OscCfg *cfg) +{ + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); + return WHAL_SUCCESS; +} -/* - * @brief Switch SYSCLK to the given source. Blocks until RCC_CFGR.SWS - * reflects the new source. - */ -whal_Error whal_Stm32wb_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32wb_Rcc_SysClockSrc src); +static inline whal_Error whal_Stm32wb_Rcc_EnableMsi( + const whal_Clock *clkDev, whal_Stm32wb_Rcc_MsiRange range) +{ + size_t rdy; -/* - * @brief Enable a peripheral clock. - */ -whal_Error whal_Stm32wb_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32wb_Rcc_PeriphClk *clk); -/* - * @brief Disable a peripheral clock. - */ -whal_Error whal_Stm32wb_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32wb_Rcc_PeriphClk *clk); + whal_Reg_Update(clkDev->base, WHAL_STM32WB_RCC_CR_REG, + WHAL_STM32WB_RCC_CR_MSION_Msk, + WHAL_STM32WB_RCC_CR_MSION_Msk); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32WB_RCC_CR_REG, + WHAL_STM32WB_RCC_CR_MSIRDY_Msk, + WHAL_STM32WB_RCC_CR_MSIRDY_Pos, &rdy); + } while (!rdy); + whal_Reg_Update(clkDev->base, WHAL_STM32WB_RCC_CR_REG, + WHAL_STM32WB_RCC_CR_MSIRANGE_Msk, + whal_SetBits(WHAL_STM32WB_RCC_CR_MSIRANGE_Msk, + WHAL_STM32WB_RCC_CR_MSIRANGE_Pos, range)); + return WHAL_SUCCESS; +} + +static inline whal_Error whal_Stm32wb_Rcc_EnablePll( + const whal_Clock *clkDev, const whal_Stm32wb_Rcc_PllCfg *cfg) +{ + size_t rdy; + + whal_Reg_Update(clkDev->base, WHAL_STM32WB_RCC_PLLCFGR_REG, + WHAL_STM32WB_RCC_PLLCFGR_Msk, + whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLSRC_Msk, + WHAL_STM32WB_RCC_PLLCFGR_PLLSRC_Pos, cfg->clkSrc) | + whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLM_Msk, + WHAL_STM32WB_RCC_PLLCFGR_PLLM_Pos, cfg->m) | + whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLN_Msk, + WHAL_STM32WB_RCC_PLLCFGR_PLLN_Pos, cfg->n) | + whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLP_Msk, + WHAL_STM32WB_RCC_PLLCFGR_PLLP_Pos, cfg->p) | + whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLQ_Msk, + WHAL_STM32WB_RCC_PLLCFGR_PLLQ_Pos, cfg->q) | + whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLREN_Msk, + WHAL_STM32WB_RCC_PLLCFGR_PLLREN_Pos, 1) | + whal_SetBits(WHAL_STM32WB_RCC_PLLCFGR_PLLR_Msk, + WHAL_STM32WB_RCC_PLLCFGR_PLLR_Pos, cfg->r)); + whal_Reg_Update(clkDev->base, WHAL_STM32WB_RCC_CR_REG, + WHAL_STM32WB_RCC_CR_PLLON_Msk, + WHAL_STM32WB_RCC_CR_PLLON_Msk); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32WB_RCC_CR_REG, + WHAL_STM32WB_RCC_CR_PLLRDY_Msk, + WHAL_STM32WB_RCC_CR_PLLRDY_Pos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + +static inline whal_Error whal_Stm32wb_Rcc_DisablePll(const whal_Clock *clkDev) +{ + whal_Reg_Update(clkDev->base, WHAL_STM32WB_RCC_CR_REG, + WHAL_STM32WB_RCC_CR_PLLON_Msk, 0); + return WHAL_SUCCESS; +} + +static inline whal_Error whal_Stm32wb_Rcc_SetSysClock( + const whal_Clock *clkDev, whal_Stm32wb_Rcc_SysClockSrc src) +{ + size_t sws; + + whal_Reg_Update(clkDev->base, WHAL_STM32WB_RCC_CFGR_REG, + WHAL_STM32WB_RCC_CFGR_SW_Msk, + whal_SetBits(WHAL_STM32WB_RCC_CFGR_SW_Msk, + WHAL_STM32WB_RCC_CFGR_SW_Pos, src)); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32WB_RCC_CFGR_REG, + WHAL_STM32WB_RCC_CFGR_SWS_Msk, + WHAL_STM32WB_RCC_CFGR_SWS_Pos, &sws); + } while (sws != (size_t)src); + return WHAL_SUCCESS; +} + +static inline whal_Error whal_Stm32wb_Rcc_EnablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32wb_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); + return WHAL_SUCCESS; +} + +static inline whal_Error whal_Stm32wb_Rcc_DisablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32wb_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); + return WHAL_SUCCESS; +} #endif /* WHAL_STM32WB_RCC_H */ diff --git a/wolfHAL/eth/stm32h5_eth.h b/wolfHAL/eth/stm32h5_eth.h index a976c78..7804e85 100644 --- a/wolfHAL/eth/stm32h5_eth.h +++ b/wolfHAL/eth/stm32h5_eth.h @@ -41,9 +41,6 @@ typedef struct whal_Stm32h5_Eth_Cfg { size_t rxDescCount; /* Number of RX descriptors */ size_t rxBufSize; /* Size of each RX buffer in bytes */ whal_Timeout *timeout; - /* Runtime state (set by driver, not by user) */ - size_t txHead; /* Next TX descriptor to use */ - size_t rxHead; /* Next RX descriptor to check */ } whal_Stm32h5_Eth_Cfg; #ifndef WHAL_CFG_STM32H5_ETH_DIRECT_API_MAPPING diff --git a/wolfHAL/gpio/stm32c0_gpio.h b/wolfHAL/gpio/stm32c0_gpio.h index bda3ccd..6ce53b0 100644 --- a/wolfHAL/gpio/stm32c0_gpio.h +++ b/wolfHAL/gpio/stm32c0_gpio.h @@ -15,6 +15,8 @@ typedef whal_Stm32wb_Gpio_Cfg whal_Stm32c0_Gpio_Cfg; typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32c0_Gpio_PinCfg; +#define whal_Stm32c0_Gpio_Dev whal_Stm32wb_Gpio_Dev + #ifndef WHAL_CFG_STM32C0_GPIO_DIRECT_API_MAPPING #define whal_Stm32c0_Gpio_Driver whal_Stm32wb_Gpio_Driver #define whal_Stm32c0_Gpio_Init whal_Stm32wb_Gpio_Init diff --git a/wolfHAL/gpio/stm32f0_gpio.h b/wolfHAL/gpio/stm32f0_gpio.h index 2793cc4..4491750 100644 --- a/wolfHAL/gpio/stm32f0_gpio.h +++ b/wolfHAL/gpio/stm32f0_gpio.h @@ -15,6 +15,8 @@ typedef whal_Stm32wb_Gpio_Cfg whal_Stm32f0_Gpio_Cfg; typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32f0_Gpio_PinCfg; +#define whal_Stm32f0_Gpio_Dev whal_Stm32wb_Gpio_Dev + #ifndef WHAL_CFG_STM32F0_GPIO_DIRECT_API_MAPPING #define whal_Stm32f0_Gpio_Driver whal_Stm32wb_Gpio_Driver #define whal_Stm32f0_Gpio_Init whal_Stm32wb_Gpio_Init diff --git a/wolfHAL/gpio/stm32f3_gpio.h b/wolfHAL/gpio/stm32f3_gpio.h index a949f0d..167412a 100644 --- a/wolfHAL/gpio/stm32f3_gpio.h +++ b/wolfHAL/gpio/stm32f3_gpio.h @@ -15,6 +15,8 @@ typedef whal_Stm32wb_Gpio_Cfg whal_Stm32f3_Gpio_Cfg; typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32f3_Gpio_PinCfg; +#define whal_Stm32f3_Gpio_Dev whal_Stm32wb_Gpio_Dev + #ifndef WHAL_CFG_STM32F3_GPIO_DIRECT_API_MAPPING #define whal_Stm32f3_Gpio_Driver whal_Stm32wb_Gpio_Driver #define whal_Stm32f3_Gpio_Init whal_Stm32wb_Gpio_Init diff --git a/wolfHAL/gpio/stm32f4_gpio.h b/wolfHAL/gpio/stm32f4_gpio.h index f993eed..d5f7e23 100644 --- a/wolfHAL/gpio/stm32f4_gpio.h +++ b/wolfHAL/gpio/stm32f4_gpio.h @@ -15,6 +15,8 @@ typedef whal_Stm32wb_Gpio_Cfg whal_Stm32f4_Gpio_Cfg; typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32f4_Gpio_PinCfg; +#define whal_Stm32f4_Gpio_Dev whal_Stm32wb_Gpio_Dev + #ifndef WHAL_CFG_STM32F4_GPIO_DIRECT_API_MAPPING #define whal_Stm32f4_Gpio_Driver whal_Stm32wb_Gpio_Driver #define whal_Stm32f4_Gpio_Init whal_Stm32wb_Gpio_Init diff --git a/wolfHAL/gpio/stm32h5_gpio.h b/wolfHAL/gpio/stm32h5_gpio.h index eff581a..0d56f33 100644 --- a/wolfHAL/gpio/stm32h5_gpio.h +++ b/wolfHAL/gpio/stm32h5_gpio.h @@ -15,6 +15,8 @@ typedef whal_Stm32wb_Gpio_Cfg whal_Stm32h5_Gpio_Cfg; typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32h5_Gpio_PinCfg; +#define whal_Stm32h5_Gpio_Dev whal_Stm32wb_Gpio_Dev + #ifndef WHAL_CFG_STM32H5_GPIO_DIRECT_API_MAPPING #define whal_Stm32h5_Gpio_Driver whal_Stm32wb_Gpio_Driver #define whal_Stm32h5_Gpio_Init whal_Stm32wb_Gpio_Init diff --git a/wolfHAL/gpio/stm32l1_gpio.h b/wolfHAL/gpio/stm32l1_gpio.h index 5462a0d..df70ca0 100644 --- a/wolfHAL/gpio/stm32l1_gpio.h +++ b/wolfHAL/gpio/stm32l1_gpio.h @@ -15,6 +15,8 @@ typedef whal_Stm32wb_Gpio_Cfg whal_Stm32l1_Gpio_Cfg; typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32l1_Gpio_PinCfg; +#define whal_Stm32l1_Gpio_Dev whal_Stm32wb_Gpio_Dev + #ifndef WHAL_CFG_STM32L1_GPIO_DIRECT_API_MAPPING #define whal_Stm32l1_Gpio_Driver whal_Stm32wb_Gpio_Driver #define whal_Stm32l1_Gpio_Init whal_Stm32wb_Gpio_Init diff --git a/wolfHAL/gpio/stm32n6_gpio.h b/wolfHAL/gpio/stm32n6_gpio.h index 5729844..f939acd 100644 --- a/wolfHAL/gpio/stm32n6_gpio.h +++ b/wolfHAL/gpio/stm32n6_gpio.h @@ -15,6 +15,8 @@ typedef whal_Stm32wb_Gpio_Cfg whal_Stm32n6_Gpio_Cfg; typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32n6_Gpio_PinCfg; +#define whal_Stm32n6_Gpio_Dev whal_Stm32wb_Gpio_Dev + #ifndef WHAL_CFG_STM32N6_GPIO_DIRECT_API_MAPPING #define whal_Stm32n6_Gpio_Driver whal_Stm32wb_Gpio_Driver #define whal_Stm32n6_Gpio_Init whal_Stm32wb_Gpio_Init diff --git a/wolfHAL/gpio/stm32wb_gpio.h b/wolfHAL/gpio/stm32wb_gpio.h index df8f1f8..4cce32f 100644 --- a/wolfHAL/gpio/stm32wb_gpio.h +++ b/wolfHAL/gpio/stm32wb_gpio.h @@ -103,8 +103,8 @@ typedef uint32_t whal_Stm32wb_Gpio_PinCfg; * Contains clock control references and an array of pin configurations. */ typedef struct { - whal_Stm32wb_Gpio_PinCfg *pinCfg; /* Array of pin configurations */ - size_t pinCount; /* Number of pins to configure */ + const whal_Stm32wb_Gpio_PinCfg *pinCfg; /* Array of pin configurations */ + size_t pinCount; /* Number of pins to configure */ } whal_Stm32wb_Gpio_Cfg; #if !defined(WHAL_CFG_STM32WB_GPIO_DIRECT_API_MAPPING) && \ diff --git a/wolfHAL/gpio/stm32wba_gpio.h b/wolfHAL/gpio/stm32wba_gpio.h index fa4a1c9..2e47097 100644 --- a/wolfHAL/gpio/stm32wba_gpio.h +++ b/wolfHAL/gpio/stm32wba_gpio.h @@ -15,6 +15,8 @@ typedef whal_Stm32wb_Gpio_Cfg whal_Stm32wba_Gpio_Cfg; typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32wba_Gpio_PinCfg; +#define whal_Stm32wba_Gpio_Dev whal_Stm32wb_Gpio_Dev + #ifndef WHAL_CFG_STM32WBA_GPIO_DIRECT_API_MAPPING #define whal_Stm32wba_Gpio_Driver whal_Stm32wb_Gpio_Driver #define whal_Stm32wba_Gpio_Init whal_Stm32wb_Gpio_Init diff --git a/wolfHAL/uart/stm32c0_uart.h b/wolfHAL/uart/stm32c0_uart.h index 2ee27ad..7e70297 100644 --- a/wolfHAL/uart/stm32c0_uart.h +++ b/wolfHAL/uart/stm32c0_uart.h @@ -14,6 +14,8 @@ typedef whal_Stm32wb_Uart_Cfg whal_Stm32c0_Uart_Cfg; +#define whal_Stm32c0_Uart_Dev whal_Stm32wb_Uart_Dev + /* * @brief Compute UART BRR register value. * diff --git a/wolfHAL/uart/stm32h5_uart.h b/wolfHAL/uart/stm32h5_uart.h index 0a47eef..2960a39 100644 --- a/wolfHAL/uart/stm32h5_uart.h +++ b/wolfHAL/uart/stm32h5_uart.h @@ -14,6 +14,8 @@ typedef whal_Stm32wb_Uart_Cfg whal_Stm32h5_Uart_Cfg; +#define whal_Stm32h5_Uart_Dev whal_Stm32wb_Uart_Dev + /* * @brief Compute UART BRR register value. * diff --git a/wolfHAL/uart/stm32n6_uart.h b/wolfHAL/uart/stm32n6_uart.h index a5a5031..e93b4ee 100644 --- a/wolfHAL/uart/stm32n6_uart.h +++ b/wolfHAL/uart/stm32n6_uart.h @@ -14,6 +14,8 @@ typedef whal_Stm32wb_Uart_Cfg whal_Stm32n6_Uart_Cfg; +#define whal_Stm32n6_Uart_Dev whal_Stm32wb_Uart_Dev + #ifndef WHAL_CFG_STM32N6_UART_DIRECT_API_MAPPING #define whal_Stm32n6_Uart_Driver whal_Stm32wb_Uart_Driver #define whal_Stm32n6_Uart_Init whal_Stm32wb_Uart_Init diff --git a/wolfHAL/uart/stm32wba_uart.h b/wolfHAL/uart/stm32wba_uart.h index 8c43daa..b32c3ef 100644 --- a/wolfHAL/uart/stm32wba_uart.h +++ b/wolfHAL/uart/stm32wba_uart.h @@ -14,6 +14,8 @@ typedef whal_Stm32wb_Uart_Cfg whal_Stm32wba_Uart_Cfg; +#define whal_Stm32wba_Uart_Dev whal_Stm32wb_Uart_Dev + #ifndef WHAL_CFG_STM32WBA_UART_DIRECT_API_MAPPING #define whal_Stm32wba_Uart_Driver whal_Stm32wb_Uart_Driver #define whal_Stm32wba_Uart_Init whal_Stm32wb_Uart_Init diff --git a/wolfHAL/wolfHAL.h b/wolfHAL/wolfHAL.h index f1f55e1..f828872 100644 --- a/wolfHAL/wolfHAL.h +++ b/wolfHAL/wolfHAL.h @@ -9,6 +9,12 @@ #include #include +/* Handle sentinel for singleton-internal drivers: the driver references its + * singleton (e.g., `whal_Stm32h5_Eth_Dev`) directly and ignores the handle + * argument. Pass WHAL_SINGLETON to make that intent explicit at the call + * site. */ +#define WHAL_SINGLETON ((void *)0) + #include #include #include From 5c95977e88dfb73f019753d8493ce9a9a5876acd Mon Sep 17 00:00:00 2001 From: Alex Lanzano Date: Thu, 14 May 2026 16:34:18 -0400 Subject: [PATCH 7/7] [drivers, stm32, pic32] Refactor drivers to allow single instance --- .claude/skills/port-stm32-platform/SKILL.md | 140 +++++- README.md | 3 +- boards/README.md | 11 +- boards/peripheral/block/sdhc_spi_sdcard32gb.c | 4 +- boards/peripheral/flash/spi_nor_w25q64.c | 4 +- boards/peripheral/sensor/imu/bmi270.c | 2 +- boards/pic32cz_curiosity_ultra/board.c | 30 +- boards/pic32cz_curiosity_ultra/board.h | 27 ++ boards/stm32c031_nucleo/board.c | 11 +- boards/stm32c031_nucleo/board.h | 21 + boards/stm32f091rc_nucleo/board.c | 11 +- boards/stm32f091rc_nucleo/board.h | 44 ++ boards/stm32f302r8_nucleo/board.c | 11 +- boards/stm32f302r8_nucleo/board.h | 44 ++ boards/stm32f411_blackpill/board.c | 19 +- boards/stm32f411_blackpill/board.h | 28 ++ boards/stm32h563zi_nucleo/board.c | 11 +- boards/stm32h563zi_nucleo/board.h | 25 + boards/stm32l152re_nucleo/board.c | 19 +- boards/stm32l152re_nucleo/board.h | 51 ++ boards/stm32n657a0_nucleo/board.c | 82 +--- boards/stm32n657a0_nucleo/board.h | 126 ++++- boards/stm32wb55xx_nucleo/board.c | 36 -- boards/stm32wb55xx_nucleo/board.h | 23 +- boards/stm32wba55cg_nucleo/board.c | 111 +---- boards/stm32wba55cg_nucleo/board.h | 147 +++++- docs/adding_a_board.md | 184 +++++-- docs/adding_a_peripheral.md | 12 +- docs/adding_a_test.md | 14 +- docs/adding_an_example.md | 12 +- docs/getting_started.md | 162 +++++-- docs/writing_a_driver.md | 126 ++++- examples/blinky/main.c | 8 +- src/block/sdhc_spi_block.c | 43 +- src/clock/pic32cz_clock.c | 176 ------- src/clock/stm32c0_rcc.c | 83 ---- src/clock/stm32f0_rcc.c | 131 ----- src/clock/stm32f3_rcc.c | 146 ------ src/clock/stm32f4_rcc.c | 147 ------ src/clock/stm32l1_rcc.c | 129 ----- src/clock/stm32n6_rcc.c | 176 ------- src/clock/stm32wba_rcc.c | 199 -------- src/crypto/stm32n6_cryp.c | 300 +++++------- src/crypto/stm32wba_hash.c | 264 ++++------- src/dma/stm32wba_gpdma.c | 68 ++- src/eth/stm32n6_eth.c | 99 ++-- src/flash/pic32cz_flash.c | 65 +-- src/flash/spi_nor_flash.c | 223 ++++++++- src/flash/stm32c0_flash.c | 48 +- src/flash/stm32f0_flash.c | 43 +- src/flash/stm32f4_flash.c | 55 +-- src/flash/stm32h5_flash.c | 56 +-- src/flash/stm32l1_flash.c | 46 +- src/flash/stm32wba_flash.c | 68 +-- src/gpio/pic32cz_gpio.c | 69 ++- src/i2c/stm32l1_i2c.c | 51 +- src/power/pic32cz_supc.c | 30 -- src/power/stm32l1_pwr.c | 33 -- src/rng/stm32wba_rng.c | 29 +- src/sensor/imu/bmi270_sensor.c | 22 + src/spi/stm32f4_spi.c | 53 ++- src/spi/stm32h5_spi.c | 60 ++- src/uart/pic32cz_uart.c | 45 +- src/uart/stm32f0_uart.c | 44 +- src/uart/stm32f4_uart.c | 48 +- src/uart/stm32wba_uart_dma.c | 55 ++- src/watchdog/stm32f0_wwdg.c | 29 +- tests/clock/test_pic32cz_clock.c | 6 +- tests/clock/test_stm32wb_clock.c | 6 +- tests/crypto/test_aes_cbc.c | 6 +- tests/crypto/test_aes_ccm.c | 36 +- tests/crypto/test_aes_ctr.c | 6 +- tests/crypto/test_aes_ecb.c | 6 +- tests/crypto/test_aes_gcm.c | 38 +- tests/crypto/test_aes_gmac.c | 6 +- tests/crypto/test_hmac_sha1.c | 10 +- tests/crypto/test_hmac_sha224.c | 10 +- tests/crypto/test_hmac_sha256.c | 10 +- tests/crypto/test_sha1.c | 10 +- tests/crypto/test_sha224.c | 10 +- tests/crypto/test_sha256.c | 10 +- tests/eth/test_eth.c | 14 +- tests/eth/test_stm32h5_eth.c | 12 +- tests/eth/test_stm32n6_eth.c | 18 +- tests/flash/test_flash.c | 2 +- tests/flash/test_stm32wb_flash.c | 2 +- tests/gpio/test_gpio.c | 10 +- tests/gpio/test_pic32cz_gpio.c | 10 +- tests/gpio/test_stm32wb_gpio.c | 16 +- tests/i2c/test_i2c.c | 4 +- tests/ipc/test_ipc.c | 10 +- tests/main.c | 12 +- tests/rng/test_rng.c | 8 +- tests/spi/test_spi_loopback.c | 24 +- tests/uart/test_uart.c | 4 +- tests/watchdog/test_watchdog.c | 24 +- wolfHAL/clock/pic32cz_clock.h | 236 ++++++++- wolfHAL/clock/stm32c0_rcc.h | 113 ++++- wolfHAL/clock/stm32f0_rcc.h | 187 +++++++- wolfHAL/clock/stm32f3_rcc.h | 207 +++++++- wolfHAL/clock/stm32f4_rcc.h | 210 +++++++- wolfHAL/clock/stm32h5_rcc.h | 87 ++++ wolfHAL/clock/stm32l1_rcc.h | 187 +++++++- wolfHAL/clock/stm32n6_rcc.h | 259 ++++++++-- wolfHAL/clock/stm32wb_rcc.h | 87 ++++ wolfHAL/clock/stm32wba_rcc.h | 288 +++++++++-- wolfHAL/crypto/crypto.h | 448 ++++++++++++++++++ wolfHAL/crypto/stm32n6_hash.h | 8 + wolfHAL/crypto/stm32wba_aes.h | 8 + wolfHAL/flash/stm32f3_flash.h | 2 + wolfHAL/platform/arm/cortex_m0.h | 8 + wolfHAL/platform/arm/cortex_m0plus.h | 8 + wolfHAL/platform/arm/cortex_m3.h | 8 + wolfHAL/platform/arm/cortex_m33.h | 8 + wolfHAL/platform/arm/cortex_m4.h | 8 + wolfHAL/platform/arm/cortex_m55.h | 8 + wolfHAL/platform/arm/cortex_m7.h | 8 + wolfHAL/platform/microchip/pic32cz.h | 5 + wolfHAL/power/pic32cz_supc.h | 43 +- wolfHAL/power/stm32l1_pwr.h | 53 ++- wolfHAL/rng/stm32n6_rng.h | 2 + wolfHAL/sensor/imu/bmi270_config_data.h | 17 +- wolfHAL/watchdog/stm32f0_iwdg.h | 2 + wolfHAL/watchdog/stm32f3_iwdg.h | 2 + wolfHAL/watchdog/stm32f3_wwdg.h | 2 + wolfHAL/watchdog/stm32l1_iwdg.h | 2 + wolfHAL/watchdog/stm32l1_wwdg.h | 2 + wolfHAL/watchdog/stm32n6_iwdg.h | 2 + wolfHAL/watchdog/stm32n6_wwdg.h | 2 + wolfHAL/watchdog/stm32wba_iwdg.h | 2 + wolfHAL/watchdog/stm32wba_wwdg.h | 2 + 131 files changed, 4708 insertions(+), 2845 deletions(-) delete mode 100644 src/clock/pic32cz_clock.c delete mode 100644 src/clock/stm32c0_rcc.c delete mode 100644 src/clock/stm32f0_rcc.c delete mode 100644 src/clock/stm32f3_rcc.c delete mode 100644 src/clock/stm32f4_rcc.c delete mode 100644 src/clock/stm32l1_rcc.c delete mode 100644 src/clock/stm32n6_rcc.c delete mode 100644 src/clock/stm32wba_rcc.c delete mode 100644 src/power/pic32cz_supc.c delete mode 100644 src/power/stm32l1_pwr.c diff --git a/.claude/skills/port-stm32-platform/SKILL.md b/.claude/skills/port-stm32-platform/SKILL.md index e020440..2708832 100644 --- a/.claude/skills/port-stm32-platform/SKILL.md +++ b/.claude/skills/port-stm32-platform/SKILL.md @@ -51,7 +51,15 @@ For each device type, decide **reuse existing driver (with alias)** OR **write a The clock driver is almost always new per family. GPIO, I2C, and IWDG/WWDG are almost always reusable. UART, flash, RNG, DMA require careful diffing. -**Clock is an architectural exception.** Unlike most driver types, the clock subsystem has no `whal_ClockDriver` vtable and no generic `whal_Clock_Init`/`Enable`/`Disable` API. Chip clock drivers expose imperative `Enable*`/`Disable*`/`Set*` helpers (e.g. `whal__Rcc_EnableOsc`, `EnablePll`, `SetSysClock`, `EnablePeriphClk`) and boards call them directly. See `docs/writing_a_driver.md` "Clock" section. The platform header does NOT define a `WHAL__RCC_DRIVER` macro, and the chip's `g_whalClock` global has only `.base = ...` — no `.driver`, no `.cfg`. Reference: `wolfHAL/clock/stm32wb_rcc.h` and `boards/stm32wb55xx_nucleo/board.c`. +**Clock is an architectural exception (1): header-only inline.** Clock drivers are implemented entirely as `static inline` functions in `wolfHAL/clock/_rcc.h` — there is no `.c` file under `src/clock/`. Register defines live in the header alongside the function bodies. Reference: `wolfHAL/clock/stm32wb_rcc.h`. + +**Clock is an architectural exception (2): no vtable.** Unlike most driver types, the clock subsystem has no `whal_ClockDriver` vtable and no generic `whal_Clock_Init`/`Enable`/`Disable` API. Chip clock drivers expose imperative `Enable*`/`Disable*`/`Set*` helpers (e.g. `whal__Rcc_EnableOsc`, `EnablePll`, `SetSysClock`, `EnablePeriphClk`) and boards call them directly. The platform header does NOT define a `WHAL__RCC_DRIVER` macro, and the chip's `g_whalClock` global has only `.base = ...` — no `.driver`, no `.cfg`. + +**Most other drivers are single-instance**, reading their cfg/base from a `static const` singleton declared in `board.h` (`whal___Dev`) rather than dereferencing the device pointer parameter. Two flavors: +- **Unconditional single-instance** for true singletons (one per chip): RNG, GPIO, NVIC, SysTick, Power, Watchdog, Crypto, Hash, Ethernet, Flash. Driver body always reads from the singleton; NULL checks dropped. Examples: `src/rng/stm32wb_rng.c`, `src/eth/stm32n6_eth.c`. +- **Conditional single-instance** gated on `WHAL_CFG___SINGLE_INSTANCE` for multi-instance peripherals (UART, SPI, I2C, DMA). Default builds keep the pointer-based path; boards opt in per device. Example: `src/uart/stm32wb_uart.c`. + +**Flash with peripheral coexistence (e.g. on-chip + SPI NOR W25Q64)** uses a split: const cfg singleton in `board.h` (no `.driver`), minimal dispatcher stub `g_whalFlash` in `board.c` carrying only `.driver`. Driver body reads from the singleton; the stub routes generic `whal_Flash_*` calls to the right driver. Reference: `boards/stm32wb55xx_nucleo/board.h` + `board.c`. **Crypto is also an architectural exception.** Crypto uses per-algorithm device structs (`whal_AesGcm`, `whal_Sha256`, etc.) instead of a single `whal_Crypto` with generic dispatch. Each algo struct has `.crypto` (pointer to the hardware device), `.driver` (per-algo vtable with Oneshot/Start/Process/Finalize), and `.state` (driver-managed streaming state). `whal_Crypto` itself is a platform driver with just Init/Deinit for hardware lifecycle. Direct API mapping is per-algorithm (e.g. `WHAL_CFG_STM32WB_AES_GCM_DIRECT_API_MAPPING`), not per-device-type. See `docs/writing_a_driver.md` "Crypto" section. Reference: `wolfHAL/crypto/stm32wb_aes.h` and `wolfHAL/crypto/stm32wba_hash.h`. @@ -61,8 +69,9 @@ Create `wolfHAL/platform/st/.h` (e.g., `stm32g431cb.h`). Reference: `stm32 Conventions: 1. Every driver include uses the **new platform's prefix** — for reused drivers that means the alias header created in Phase 3, not the original family's header. -2. Every device macro uses `.driver = &whal__Driver` — the alias header `#define`s this to the original symbol at preprocess time, so no renaming of actual code is needed but callers see the new-prefix name. -3. Defines clock enable macros and, when applicable, DMA request mapping macros. +2. Every base-address `#define` (e.g., `WHAL__USART1_BASE`, `WHAL__AES_BASE`) lands here. Board.h's singletons (Phase 4) pull these. +3. Vtable-pointer `#define`s like `WHAL___DRIVER` are only needed for drivers that still use vtable dispatch in this chip (typically flash, since multiple flash drivers can coexist via the SPI NOR peripheral). Single-instance drivers don't need them. +4. Defines clock enable macros and, when applicable, DMA request mapping macros. Skeleton: @@ -75,9 +84,14 @@ Skeleton: #include _uart.h> /* ...one include per device type... */ -#define WHAL__USART1_DEVICE \ - .base = 0x, \ - .driver = &whal_Uart_Driver +/* Base addresses — referenced by board.h singletons. */ +#define WHAL__USART1_BASE 0x +#define WHAL__AES_BASE 0x +#define WHAL__FLASH_BASE 0x + +/* Vtable-pointer macros — only for drivers that still use vtable dispatch + * (typically flash, due to SPI NOR peripheral coexistence). */ +#define WHAL__FLASH_DRIVER &whal__Flash_Driver #define WHAL__USART1_CLOCK \ .regOffset = 0x, \ @@ -123,6 +137,12 @@ typedef whal__Cfg whal__Cfg; typedef whal__PinCfg whal__PinCfg; /* ...repeat for every exposed type... */ +/* Singleton alias — REQUIRED for any single-instance driver. board.h declares + * the singleton using the new platform's name; this macro renames it at + * preprocess time so the leaf driver's references resolve correctly. Place + * unconditionally (not under any DIRECT_API_MAPPING guard). */ +#define whal__Dev whal__Dev + /* Driver and function aliases — one #define per exposed function/driver */ #define whal__Driver whal__Driver #define whal__Init whal__Init @@ -144,25 +164,27 @@ typedef whal__PinCfg whal__PinCfg; That is the entire file. Examples in-tree: `src/gpio/stm32f4_gpio.c`, `src/gpio/stm32wba_gpio.c`, `src/i2c/stm32wba_i2c.c`, `src/uart/stm32wba_uart.c`, `src/watchdog/stm32wba_iwdg.c` — each is one line. The stub exists so the board's Makefile wildcard (`src/*/_*.c`) compiles the original implementation under the new-prefix filename. The original `.c` is NOT added to the Makefile separately; the `#include` pulls it into this translation unit exactly once. -**API mapping macros stay in the leaf driver, not in the alias .c.** Most leaf drivers contain a guarded block that aliases the platform-specific function names directly to the generic `whal__*` API: +**Direct API mapping macros stay in the leaf driver, not in the alias .c.** Most leaf drivers contain a guarded block that renames the platform-specific function names directly to the generic `whal__*` API. The flag is `WHAL_CFG___DIRECT_API_MAPPING` (note the order: platform-then-type): ```c /* in src//_.c — the LEAF */ -#if defined(WHAL_CFG__API_MAPPING_) || \ - defined(WHAL_CFG__API_MAPPING_) +#if defined(WHAL_CFG___DIRECT_API_MAPPING) || \ + defined(WHAL_CFG___DIRECT_API_MAPPING) #define whal__Init whal__Init /* ...one #define per driver entry point... */ #endif /* ...driver implementation... */ -#if !defined(WHAL_CFG__API_MAPPING_) && \ - !defined(WHAL_CFG__API_MAPPING_) +#if !defined(WHAL_CFG___DIRECT_API_MAPPING) && \ + !defined(WHAL_CFG___DIRECT_API_MAPPING) const whal_Driver whal__Driver = { ... }; #endif ``` -Add the new platform's `WHAL_CFG__API_MAPPING_` macro to **both** guards in the leaf driver. Do **not** translate the macro inside the alias `.c` stub like `#ifdef #define #endif` — every leaf has to learn about every alias platform anyway, and putting the recognition in two places (alias shim + leaf driver) creates drift. Keep the alias `.c` as a single `#include` line. +Add the new platform's `WHAL_CFG___DIRECT_API_MAPPING` macro to **both** guards in the leaf driver. Do **not** translate the macro inside the alias `.c` stub like `#ifdef #define #endif` — every leaf has to learn about every alias platform anyway, and putting the recognition in two places (alias shim + leaf driver) creates drift. Keep the alias `.c` as a single `#include` line. + +**For conditional single-instance drivers (UART, SPI, I2C, DMA)**, the leaf driver also has a separate `WHAL_CFG___SINGLE_INSTANCE` gate that bifurcates each function body — SI branch reads from `whal___Dev`, else branch keeps the pointer-based code. The new platform's `_SINGLE_INSTANCE` macro must be added to that disjunction in the leaf too. See `src/uart/stm32wb_uart.c` for the canonical form. **Alias the leaf directly — never daisy-chain.** If `` itself aliases another driver, alias `` to the **leaf** (the one with the actual implementation), not to the intermediate alias. Two-hop chains (`` → `` → ``) make every macro recognition twice as painful and obscure the dependency graph. Trace the include chain in the existing `.h` and `.c` files until you find the file with real driver code, and point your new alias at that. @@ -187,10 +209,99 @@ This is the same one-line pattern as the driver stub. The build system auto-disc Create `boards//` with: ### `board.h` -Exports `extern whal_` instances and declares `Board_Init`/`Board_Deinit`/`Board_WaitMs`. Follow `docs/adding_a_board.md`. + +Three concerns: extern declarations for pointer-based globals that still live in `board.c`, `static const` singleton declarations for single-instance drivers, and the `BOARD__DEV` macro block that lets tests/apps portably reach each peripheral. Use the new platform's prefix for each singleton (the alias-header `_Dev` macro from Phase 3 renames it to the canonical at preprocess time). Follow `docs/adding_a_board.md`. + +Skeleton: + +```c +#include +#include .h> + +/* Pointer-based globals — defined in board.c, declared here for reachability. */ +extern whal_Clock g_whalClock; +extern whal_Uart g_whalUart; +extern whal_Flash g_whalFlash; /* dispatcher stub when flash coexists with SPI NOR */ + +extern whal_Timeout g_whalTimeout; +extern volatile uint32_t g_tick; + +/* BOARD_*_DEV macros — how this board reaches each peripheral. + * WHAL_SINGLETON for single-instance drivers; (&g_whal) for pointer-based. */ +#define BOARD_GPIO_DEV WHAL_SINGLETON +#define BOARD_UART_DEV (&g_whalUart) +#define BOARD_FLASH_DEV (&g_whalFlash) +#define BOARD_CLOCK_DEV (&g_whalClock) +#define BOARD_RNG_DEV WHAL_SINGLETON +#define BOARD_WATCHDOG_DEV WHAL_SINGLETON +/* ...one per peripheral the board exposes... */ + +/* Single-instance singletons, using THIS board's platform name (aliased to + * the leaf driver's canonical name via the Phase 3 alias header). */ +static const whal_Gpio whal__Gpio_Dev = { + .base = WHAL__GPIO_BASE, + .cfg = (void *)&(const whal__Gpio_Cfg){ + .pinCfg = (const whal__Gpio_PinCfg[PIN_COUNT]){ + [LED_PIN] = WHAL__GPIO_PIN(...), + /* ...one entry per board pin... */ + }, + .pinCount = PIN_COUNT, + }, +}; + +static const whal_Rng whal__Rng_Dev = { + .base = WHAL__RNG_BASE, + .cfg = (void *)&(const whal__Rng_Cfg){ + .timeout = &g_whalTimeout, + }, +}; + +/* Watchdog: declare both IWDG and WWDG singletons unconditionally — even if + * the board only uses one, the alias .c that includes the leaf is always + * compiled and references the singleton. */ +static const whal_Watchdog whal__Iwdg_Dev = { ... }; +static const whal_Watchdog whal__Wwdg_Dev = { ... }; + +/* SysTick is platform-agnostic — the singleton uses the canonical name. */ +static const whal_Timer whal_SysTick_Dev = { + .base = WHAL_CORTEX_M4_SYSTICK_BASE, + .cfg = (void *)&(const whal_SysTick_Cfg){ + .cyclesPerTick = / 1000, + .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, + .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, + }, +}; +``` + +**Names follow the board's own platform.** `whal_Stm32g4_Iwdg_Dev` in a g4-board's board.h, not `whal_Stm32wb_Iwdg_Dev` even if the IWDG driver is an alias of wb's. The Phase 3 alias header's `_Dev` macro rename does the bridge at preprocess time. Allowed cross-platform names: `whal_Nvic_Dev`, `whal_SysTick_Dev`, `whal_Lan8742a_Dev` (these are genuinely platform-agnostic). + +**State for AEAD streaming** (AES GCM/CCM, HMAC) goes immediately above its singleton in `board.h` as a `static` variable. The state pointer in the singleton takes its address. Each TU including board.h gets its own copy; only the driver TU writes through it; `--gc-sections` strips unused copies. ### `board.c` -Define each `whal_` global with its platform macro + board-specific config (pins, baud rates, timeout, DMA channel assignments). The `whal_Clock` global is just `.base = ...` (no `.driver`, no `.cfg`) since the clock subsystem has no vtable. Implement `Board_Init` in dependency order: PWR → bring up clock tree imperatively (oscillator on, PLL configure+enable, sysclk switch) → enable peripheral clocks → GPIO → UART → Timer → the rest. Keep the watchdog out of `Board_Init` (the app starts it when ready to refresh) per `docs/adding_a_board.md`. Guard DMA-specific setup under `#ifdef BOARD_DMA`, matching `boards/stm32wba55cg_nucleo/board.c`. + +Define remaining pointer-based globals (`g_whalClock`, `g_whalUart` for the still-vtable-dispatched peripherals, `g_whalTimeout`, the SysTick handler) and implement `Board_Init`/`Board_Deinit`/`Board_WaitMs`. + +For peripherals where multiple drivers coexist on one generic API (most commonly flash: on-chip + SPI NOR), define a minimal **dispatcher stub** here — it carries only `.driver` so generic `whal_Flash_*` calls can vtable-dispatch through it. The const cfg lives in `board.h`'s singleton: + +```c +/* Flash dispatcher stub — const cfg is in board.h as whal__Flash_Dev. */ +whal_Flash g_whalFlash = { + .driver = WHAL__FLASH_DRIVER, +}; +``` + +The `whal_Clock` global is just `.base = ...` (no `.driver`, no `.cfg`) since the clock subsystem has no vtable. + +Init/Deinit call sites use `BOARD__DEV`, NOT the raw globals — this lets the board switch a peripheral between single-instance and pointer-based by flipping one macro: + +```c +err = whal_Gpio_Init(BOARD_GPIO_DEV); +err = whal_Uart_Init(BOARD_UART_DEV); +err = whal_Flash_Init(BOARD_FLASH_DEV); +err = whal_Timer_Init(BOARD_TIMER_DEV); +``` + +Implement `Board_Init` in dependency order: PWR → bring up clock tree imperatively (oscillator on, PLL configure+enable, sysclk switch) → enable peripheral clocks → GPIO → UART → Timer → the rest. Keep the watchdog out of `Board_Init` (the app starts it when ready to refresh) per `docs/adding_a_board.md`. Guard DMA-specific setup under `#ifdef BOARD_DMA`, matching `boards/stm32wba55cg_nucleo/board.c`. ### GPIO pin conflict check After writing the `pinCfg` array in `board.c`, scan every entry pair and verify no two entries share the same physical port+pin. This is a common mistake when a pin serves double duty (e.g., PA5 used as both an LED and SPI1_SCK). If a conflict is found, consult the chip's alternate-function table in the datasheet and remap the conflicting peripheral to an alternate pin on a different port. @@ -220,6 +331,7 @@ Add the new board to `.github/workflows/boards.yml` by appending it to the `boar 1. `make BOARD=` from the repo root. Fix errors in order. Typical failures: - Missing symbol for an aliased driver → the alias header is missing a `#define` for that function/type, or the stub `.c` isn't present. + - `'whal_Stm32__Dev' undeclared` in a single-instance leaf driver → the alias header for the new platform is missing the `#define whal_Stm32__Dev whal_Stm32__Dev` line, OR the board.h didn't declare the singleton. - Duplicate symbol → the Makefile is picking up both `_*.c` and the original `_*.c`; restrict the wildcard to the new prefix only. - Implicit declaration warnings for `whal_Reg_*` / `whal_SetBits` in a stub include → you probably wrote `#include ` with angle brackets in the stub instead of `#include "_.c"` with quotes. The stub must use quoted include so the preprocessor finds the sibling `.c` in the same directory. 2. Flash the binary (user runs this) and run the test suite. Each suite prints `PASS`, `FAIL`, or `SKIP`. diff --git a/README.md b/README.md index 1341e78..c1409f0 100644 --- a/README.md +++ b/README.md @@ -2,7 +2,8 @@ wolfHAL is a lightweight, OS-agnostic, compiler-agnostic hardware abstraction layer for embedded targets written in C. It provides a uniform driver model -based on vtable dispatch. +with vtable dispatch by default and an opt-in single-instance fast path for +size-constrained builds. ## Repository layout diff --git a/boards/README.md b/boards/README.md index f8e1887..a7338f2 100644 --- a/boards/README.md +++ b/boards/README.md @@ -32,10 +32,13 @@ Each board directory contains: - **`board.mk`** - Build configuration: toolchain, CPU flags, platform drivers, and linker script. Included by application Makefiles via `include $(BOARD_DIR)/board.mk`. -- **`board.h`** - Board-level declarations: global peripheral instances, - pin definitions, and `Board_Init()`/`Board_Deinit()` prototypes. -- **`board.c`** - Peripheral instantiation and `Board_Init()` implementation - (power, clock, GPIO, UART, flash, timer). +- **`board.h`** - Board-level declarations: `extern` globals for vtable-dispatched + peripherals, `static const` singletons for single-instance drivers, + `BOARD__DEV` macros that resolve to `WHAL_SINGLETON` or + `&g_whal` depending on how each peripheral is wired, pin definitions, + and `Board_Init()`/`Board_Deinit()` prototypes. +- **`board.c`** - Peripheral instantiation for vtable-dispatched drivers and + `Board_Init()` implementation (power, clock, GPIO, UART, flash, timer). - **`linker.ld`** - Linker script defining memory regions (flash, RAM). - Any additional board-specific source files (e.g. interrupt vector table, architecture-specific startup code). diff --git a/boards/peripheral/block/sdhc_spi_sdcard32gb.c b/boards/peripheral/block/sdhc_spi_sdcard32gb.c index f452a87..c8e41a5 100644 --- a/boards/peripheral/block/sdhc_spi_sdcard32gb.c +++ b/boards/peripheral/block/sdhc_spi_sdcard32gb.c @@ -12,9 +12,9 @@ static whal_Spi_ComCfg g_sdcardComCfg = { whal_Block g_whalSdhcSpiSdcard32gb = { .driver = &whal_SdhcSpi_Driver, .cfg = &(whal_SdhcSpi_Cfg) { - .spiDev = &g_whalSpi, + .spiDev = BOARD_SPI_DEV, .spiComCfg = &g_sdcardComCfg, - .gpioDev = &g_whalGpio, + .gpioDev = BOARD_GPIO_DEV, .csPin = SPI_CS_PIN, .timeout = &g_whalTimeout, }, diff --git a/boards/peripheral/flash/spi_nor_w25q64.c b/boards/peripheral/flash/spi_nor_w25q64.c index db263d9..d6a5db2 100644 --- a/boards/peripheral/flash/spi_nor_w25q64.c +++ b/boards/peripheral/flash/spi_nor_w25q64.c @@ -24,9 +24,9 @@ static whal_Spi_ComCfg g_w25q64ComCfg = { whal_Flash g_whalSpiNorW25q64 = { .driver = &whal_SpiNor_Driver, .cfg = &(whal_SpiNor_Cfg) { - .spiDev = &g_whalSpi, + .spiDev = BOARD_SPI_DEV, .spiComCfg = &g_w25q64ComCfg, - .gpioDev = &whal_Stm32wb_Gpio_Dev, + .gpioDev = BOARD_GPIO_DEV, .csPin = SPI_CS_PIN, .timeout = &g_whalTimeout, .pageSz = W25Q64_PAGE_SZ, diff --git a/boards/peripheral/sensor/imu/bmi270.c b/boards/peripheral/sensor/imu/bmi270.c index 811ddd7..b0855a5 100644 --- a/boards/peripheral/sensor/imu/bmi270.c +++ b/boards/peripheral/sensor/imu/bmi270.c @@ -20,7 +20,7 @@ whal_I2c_ComCfg g_bmi270ComCfg = { whal_Sensor g_whalBmi270 = { .driver = &whal_Bmi270_Driver, .cfg = &(whal_Bmi270_Cfg) { - .i2c = &g_whalI2c, + .i2c = BOARD_I2C_DEV, .comCfg = &g_bmi270ComCfg, .configData = whal_bmi270_config_data, .configDataSz = WHAL_BMI270_CONFIG_DATA_SZ, diff --git a/boards/pic32cz_curiosity_ultra/board.c b/boards/pic32cz_curiosity_ultra/board.c index c943931..3ee2553 100644 --- a/boards/pic32cz_curiosity_ultra/board.c +++ b/boards/pic32cz_curiosity_ultra/board.c @@ -6,11 +6,23 @@ #include #include "peripheral.h" -/* Power */ -static whal_Power g_whalPower = { - .base = WHAL_PIC32CZ_SUPC_BASE, +/* SysTick timing (must precede g_whalTimeout below) */ +volatile uint32_t g_tick = 0; +volatile uint8_t g_waiting = 0; +volatile uint8_t g_tickOverflow = 0; + +uint32_t Board_GetTick(void) +{ + return g_tick; +} + +whal_Timeout g_whalTimeout = { + .timeoutTicks = 1000, + .GetTick = Board_GetTick, }; +/* SUPC singleton lives in board.h as `static const`. */ + /* Clock */ whal_Clock g_whalClock = { .base = WHAL_PIC32CZ_CLOCK_BASE, @@ -41,17 +53,13 @@ whal_Uart g_whalUart = { }, }; -/* Flash */ +/* Flash — dispatcher stub. The const cfg lives in board.h as + * whal_Pic32cz_Flash_Dev; this only carries .driver so whal_Flash_* can + * dispatch through the vtable. */ whal_Flash g_whalFlash = { - .base = WHAL_PIC32CZ_FLASH_BASE, .driver = WHAL_PIC32CZ_FLASH_DRIVER, }; -/* SysTick timing */ -volatile uint32_t g_tick = 0; -volatile uint8_t g_waiting = 0; -volatile uint8_t g_tickOverflow = 0; - void SysTick_Handler() { uint32_t tickBefore = g_tick++; @@ -85,7 +93,7 @@ whal_Error Board_Init(void) whal_Error err; /* Enable PLL power supply before clock init */ - err = whal_Pic32cz_Supc_EnableSupply(&g_whalPower, + err = whal_Pic32cz_Supc_EnableSupply(WHAL_SINGLETON, &(whal_Pic32cz_Supc_Supply){WHAL_PIC32CZ_SUPC_PLL}); if (err) { return err; diff --git a/boards/pic32cz_curiosity_ultra/board.h b/boards/pic32cz_curiosity_ultra/board.h index 57bbaa6..73d359c 100644 --- a/boards/pic32cz_curiosity_ultra/board.h +++ b/boards/pic32cz_curiosity_ultra/board.h @@ -5,10 +5,12 @@ #include #include #include +#include extern whal_Clock g_whalClock; extern whal_Uart g_whalUart; extern whal_Flash g_whalFlash; +extern whal_Timeout g_whalTimeout; extern volatile uint32_t g_tick; @@ -16,6 +18,31 @@ extern volatile uint32_t g_tick; #define BOARD_FLASH_TEST_ADDR 0x0C000000 #define BOARD_FLASH_SECTOR_SZ 0x1000 +/* BOARD_*_DEV: how this board reaches each peripheral. */ +#define BOARD_GPIO_DEV WHAL_SINGLETON +#define BOARD_UART_DEV (&g_whalUart) +#define BOARD_FLASH_DEV (&g_whalFlash) +#define BOARD_CLOCK_DEV (&g_whalClock) + +/* SUPC singleton — referenced by pic32cz_supc.c directly. */ +static const whal_Power whal_Pic32cz_Supc_Dev = { + .base = WHAL_PIC32CZ_SUPC_BASE, +}; + +/* Flash singleton — referenced by pic32cz_flash.c directly. Const cfg lives + * here; the dispatcher stub g_whalFlash in board.c carries only .driver so + * whal_Flash_* can be vtable-dispatched alongside other flash drivers (e.g. + * SPI NOR W25Q64). */ +static const whal_Flash whal_Pic32cz_Flash_Dev = { + .base = WHAL_PIC32CZ_FLASH_BASE, + + .cfg = (void *)&(const whal_Pic32cz_Flash_Cfg){ + .startAddr = 0x0C000000, + .size = 0x00800000, /* 8 MB max */ + .timeout = &g_whalTimeout, + }, +}; + static const whal_Gpio whal_Pic32cz_Gpio_Dev = { .base = WHAL_PIC32CZ_GPIO_BASE, diff --git a/boards/stm32c031_nucleo/board.c b/boards/stm32c031_nucleo/board.c index 64b2be9..d609e89 100644 --- a/boards/stm32c031_nucleo/board.c +++ b/boards/stm32c031_nucleo/board.c @@ -67,16 +67,11 @@ whal_Spi g_whalSpi = { }, }; -/* Flash */ +/* Flash — dispatcher stub. The const cfg lives in board.h as + * whal_Stm32c0_Flash_Dev; this only carries .driver so whal_Flash_* can + * dispatch through the vtable. */ whal_Flash g_whalFlash = { - .base = WHAL_STM32C031_FLASH_BASE, .driver = WHAL_STM32C031_FLASH_DRIVER, - - .cfg = &(whal_Stm32c0_Flash_Cfg) { - .startAddr = 0x08000000, - .size = 0x8000, /* 32 KB */ - .timeout = &g_whalTimeout, - }, }; void Board_WaitMs(size_t ms) diff --git a/boards/stm32c031_nucleo/board.h b/boards/stm32c031_nucleo/board.h index 6b49cf8..69a6147 100644 --- a/boards/stm32c031_nucleo/board.h +++ b/boards/stm32c031_nucleo/board.h @@ -31,6 +31,27 @@ enum { #define BOARD_FLASH_TEST_ADDR 0x08007800 #define BOARD_FLASH_SECTOR_SZ 0x800 +/* BOARD_*_DEV: how this board reaches each peripheral. */ +#define BOARD_GPIO_DEV WHAL_SINGLETON +#define BOARD_UART_DEV (&g_whalUart) +#define BOARD_SPI_DEV (&g_whalSpi) +#define BOARD_FLASH_DEV (&g_whalFlash) +#define BOARD_CLOCK_DEV (&g_whalClock) + +/* Flash singleton — referenced by stm32c0_flash.c directly. Const cfg lives + * here; the dispatcher stub g_whalFlash in board.c carries only .driver so + * whal_Flash_* can be vtable-dispatched alongside other flash drivers (e.g. + * SPI NOR W25Q64). */ +static const whal_Flash whal_Stm32c0_Flash_Dev = { + .base = WHAL_STM32C031_FLASH_BASE, + + .cfg = (void *)&(const whal_Stm32c0_Flash_Cfg){ + .startAddr = 0x08000000, + .size = 0x8000, /* 32 KB */ + .timeout = &g_whalTimeout, + }, +}; + static const whal_Gpio whal_Stm32c0_Gpio_Dev = { .base = WHAL_STM32C031_GPIO_BASE, diff --git a/boards/stm32f091rc_nucleo/board.c b/boards/stm32f091rc_nucleo/board.c index 12bd6cb..c3ed39e 100644 --- a/boards/stm32f091rc_nucleo/board.c +++ b/boards/stm32f091rc_nucleo/board.c @@ -73,16 +73,11 @@ whal_I2c g_whalI2c = { }, }; -/* Flash — 256 KB */ +/* Flash — 256 KB. Dispatcher stub; the const cfg lives in board.h as + * whal_Stm32f0_Flash_Dev. This only carries .driver so whal_Flash_* can + * dispatch through the vtable. */ whal_Flash g_whalFlash = { - .base = WHAL_STM32F091_FLASH_BASE, .driver = WHAL_STM32F091_FLASH_DRIVER, - - .cfg = &(whal_Stm32f0_Flash_Cfg) { - .startAddr = 0x08000000, - .size = 0x40000, - .timeout = &g_whalTimeout, - }, }; #ifdef BOARD_WATCHDOG_IWDG diff --git a/boards/stm32f091rc_nucleo/board.h b/boards/stm32f091rc_nucleo/board.h index e31221f..f30a3ce 100644 --- a/boards/stm32f091rc_nucleo/board.h +++ b/boards/stm32f091rc_nucleo/board.h @@ -36,6 +36,50 @@ enum { #define BOARD_FLASH_TEST_ADDR 0x0803F800 #define BOARD_FLASH_SECTOR_SZ 0x800 +/* BOARD_*_DEV: how this board reaches each peripheral. */ +#define BOARD_GPIO_DEV WHAL_SINGLETON +#define BOARD_UART_DEV (&g_whalUart) +#define BOARD_SPI_DEV (&g_whalSpi) +#define BOARD_I2C_DEV (&g_whalI2c) +#define BOARD_FLASH_DEV (&g_whalFlash) +#define BOARD_CLOCK_DEV (&g_whalClock) +#define BOARD_WATCHDOG_DEV (&g_whalWatchdog) + +/* WWDG singleton — referenced by stm32f0_wwdg.c directly. Declared + * unconditionally because the compiled .c always references it. */ +static const whal_Watchdog whal_Stm32f0_Wwdg_Dev = { + .base = WHAL_STM32F091_WWDG_BASE, + .cfg = (void *)&(const whal_Stm32f0_Wwdg_Cfg){ + .prescaler = 3, + .window = 0x7F, + .counter = 0x7F, + }, +}; + +/* IWDG singleton — referenced by stm32wb_iwdg.c via stm32f0_iwdg.c alias. */ +static const whal_Watchdog whal_Stm32f0_Iwdg_Dev = { + .base = WHAL_STM32F091_IWDG_BASE, + .cfg = (void *)&(const whal_Stm32f0_Iwdg_Cfg){ + .prescaler = WHAL_STM32F0_IWDG_PR_64, + .reload = 500, + .timeout = &g_whalTimeout, + }, +}; + +/* Flash singleton — referenced by stm32f0_flash.c directly. Const cfg lives + * here; the dispatcher stub g_whalFlash in board.c carries only .driver so + * whal_Flash_* can be vtable-dispatched alongside other flash drivers (e.g. + * SPI NOR W25Q64). */ +static const whal_Flash whal_Stm32f0_Flash_Dev = { + .base = WHAL_STM32F091_FLASH_BASE, + + .cfg = (void *)&(const whal_Stm32f0_Flash_Cfg){ + .startAddr = 0x08000000, + .size = 0x40000, + .timeout = &g_whalTimeout, + }, +}; + static const whal_Gpio whal_Stm32f0_Gpio_Dev = { .base = WHAL_STM32F091_GPIO_BASE, diff --git a/boards/stm32f302r8_nucleo/board.c b/boards/stm32f302r8_nucleo/board.c index 072e46d..df950c0 100644 --- a/boards/stm32f302r8_nucleo/board.c +++ b/boards/stm32f302r8_nucleo/board.c @@ -76,16 +76,11 @@ whal_I2c g_whalI2c = { }, }; -/* Flash — 64 KB */ +/* Flash — 64 KB. Dispatcher stub; the const cfg lives in board.h as + * whal_Stm32f0_Flash_Dev (the f3 driver is an alias for the f0 driver). + * This only carries .driver so whal_Flash_* can dispatch through the vtable. */ whal_Flash g_whalFlash = { - .base = WHAL_STM32F302_FLASH_BASE, .driver = WHAL_STM32F302_FLASH_DRIVER, - - .cfg = &(whal_Stm32f3_Flash_Cfg) { - .startAddr = 0x08000000, - .size = 0x10000, - .timeout = &g_whalTimeout, - }, }; #ifdef BOARD_WATCHDOG_IWDG diff --git a/boards/stm32f302r8_nucleo/board.h b/boards/stm32f302r8_nucleo/board.h index 03c81e0..0698628 100644 --- a/boards/stm32f302r8_nucleo/board.h +++ b/boards/stm32f302r8_nucleo/board.h @@ -36,6 +36,50 @@ enum { #define BOARD_FLASH_TEST_ADDR 0x0800F800 #define BOARD_FLASH_SECTOR_SZ 0x800 +/* BOARD_*_DEV: how this board reaches each peripheral. */ +#define BOARD_GPIO_DEV WHAL_SINGLETON +#define BOARD_UART_DEV (&g_whalUart) +#define BOARD_SPI_DEV (&g_whalSpi) +#define BOARD_I2C_DEV (&g_whalI2c) +#define BOARD_FLASH_DEV (&g_whalFlash) +#define BOARD_CLOCK_DEV (&g_whalClock) +#define BOARD_WATCHDOG_DEV (&g_whalWatchdog) + +/* WWDG singleton — referenced by stm32f0_wwdg.c via stm32f3_wwdg.c alias. + * Declared unconditionally because the compiled .c always references it. */ +static const whal_Watchdog whal_Stm32f3_Wwdg_Dev = { + .base = WHAL_STM32F302_WWDG_BASE, + .cfg = (void *)&(const whal_Stm32f3_Wwdg_Cfg){ + .prescaler = 3, + .window = 0x7F, + .counter = 0x7F, + }, +}; + +/* IWDG singleton — referenced by stm32wb_iwdg.c via stm32f3_iwdg.c alias. */ +static const whal_Watchdog whal_Stm32f3_Iwdg_Dev = { + .base = WHAL_STM32F302_IWDG_BASE, + .cfg = (void *)&(const whal_Stm32f3_Iwdg_Cfg){ + .prescaler = WHAL_STM32F3_IWDG_PR_64, + .reload = 500, + .timeout = &g_whalTimeout, + }, +}; + +/* Flash singleton — referenced by stm32f0_flash.c (compiled via stm32f3_flash.c + * alias). Const cfg lives here; the dispatcher stub g_whalFlash in board.c + * carries only .driver so whal_Flash_* can be vtable-dispatched alongside + * other flash drivers (e.g. SPI NOR W25Q64). */ +static const whal_Flash whal_Stm32f3_Flash_Dev = { + .base = WHAL_STM32F302_FLASH_BASE, + + .cfg = (void *)&(const whal_Stm32f3_Flash_Cfg){ + .startAddr = 0x08000000, + .size = 0x10000, + .timeout = &g_whalTimeout, + }, +}; + static const whal_Gpio whal_Stm32f3_Gpio_Dev = { .base = WHAL_STM32F302_GPIO_BASE, diff --git a/boards/stm32f411_blackpill/board.c b/boards/stm32f411_blackpill/board.c index 49b8d4e..ad6a401 100644 --- a/boards/stm32f411_blackpill/board.c +++ b/boards/stm32f411_blackpill/board.c @@ -24,8 +24,9 @@ whal_Timeout g_whalTimeout = { .GetTick = Board_GetTick, }; -/* STM32F411CE sector layout (512 KB) */ -static const whal_Stm32f4_Flash_Sector g_flashSectors[] = { +/* STM32F411CE sector layout (512 KB). Referenced by the flash singleton's + * cfg in board.h, so this must be globally visible (not static). */ +const whal_Stm32f4_Flash_Sector g_flashSectors[FLASH_SECTOR_COUNT] = { { .addr = 0x08000000, .size = 0x04000 }, /* Sector 0: 16 KB */ { .addr = 0x08004000, .size = 0x04000 }, /* Sector 1: 16 KB */ { .addr = 0x08008000, .size = 0x04000 }, /* Sector 2: 16 KB */ @@ -35,7 +36,6 @@ static const whal_Stm32f4_Flash_Sector g_flashSectors[] = { { .addr = 0x08040000, .size = 0x20000 }, /* Sector 6: 128 KB */ { .addr = 0x08060000, .size = 0x20000 }, /* Sector 7: 128 KB */ }; -#define FLASH_SECTOR_COUNT (sizeof(g_flashSectors) / sizeof(g_flashSectors[0])) /* Clock */ whal_Clock g_whalClock = { @@ -73,18 +73,11 @@ whal_Spi g_whalSpi = { }, }; -/* Flash */ +/* Flash — dispatcher stub. The const cfg lives in board.h as + * whal_Stm32f4_Flash_Dev; this only carries .driver so whal_Flash_* can + * dispatch through the vtable. */ whal_Flash g_whalFlash = { - .base = WHAL_STM32F411_FLASH_BASE, .driver = WHAL_STM32F411_FLASH_DRIVER, - - .cfg = &(whal_Stm32f4_Flash_Cfg) { - .startAddr = 0x08000000, - .size = 0x80000, /* 512 KB */ - .sectors = g_flashSectors, - .sectorCount = FLASH_SECTOR_COUNT, - .timeout = &g_whalTimeout, - }, }; void Board_WaitMs(size_t ms) diff --git a/boards/stm32f411_blackpill/board.h b/boards/stm32f411_blackpill/board.h index f5fad4d..972380f 100644 --- a/boards/stm32f411_blackpill/board.h +++ b/boards/stm32f411_blackpill/board.h @@ -31,6 +31,34 @@ enum { #define BOARD_FLASH_SECTOR_SZ 0x20000 #define BOARD_FLASH_WRITE_SZ 4 +/* BOARD_*_DEV: how this board reaches each peripheral. */ +#define BOARD_GPIO_DEV WHAL_SINGLETON +#define BOARD_UART_DEV (&g_whalUart) +#define BOARD_SPI_DEV (&g_whalSpi) +#define BOARD_FLASH_DEV (&g_whalFlash) +#define BOARD_CLOCK_DEV (&g_whalClock) + +/* Flash sector layout (defined in board.c) — referenced by the flash singleton's + * cfg below. */ +#define FLASH_SECTOR_COUNT 8 +extern const whal_Stm32f4_Flash_Sector g_flashSectors[FLASH_SECTOR_COUNT]; + +/* Flash singleton — referenced by stm32f4_flash.c directly. Const cfg lives + * here; the dispatcher stub g_whalFlash in board.c carries only .driver so + * whal_Flash_* can be vtable-dispatched alongside other flash drivers (e.g. + * SPI NOR W25Q64). */ +static const whal_Flash whal_Stm32f4_Flash_Dev = { + .base = WHAL_STM32F411_FLASH_BASE, + + .cfg = (void *)&(const whal_Stm32f4_Flash_Cfg){ + .startAddr = 0x08000000, + .size = 0x80000, /* 512 KB */ + .sectors = g_flashSectors, + .sectorCount = FLASH_SECTOR_COUNT, + .timeout = &g_whalTimeout, + }, +}; + static const whal_Gpio whal_Stm32f4_Gpio_Dev = { .base = WHAL_STM32F411_GPIO_BASE, diff --git a/boards/stm32h563zi_nucleo/board.c b/boards/stm32h563zi_nucleo/board.c index 73302bd..ca907f1 100644 --- a/boards/stm32h563zi_nucleo/board.c +++ b/boards/stm32h563zi_nucleo/board.c @@ -74,16 +74,11 @@ whal_Spi g_whalSpi = { }, }; -/* Flash */ +/* Flash — dispatcher stub. The const cfg lives in board.h as + * whal_Stm32h5_Flash_Dev; this only carries .driver so whal_Flash_* can + * dispatch through the vtable. */ whal_Flash g_whalFlash = { - .base = WHAL_STM32H563_FLASH_BASE, .driver = WHAL_STM32H563_FLASH_DRIVER, - - .cfg = &(whal_Stm32h5_Flash_Cfg) { - .startAddr = 0x08000000, - .size = 0x200000, /* 2 MB */ - .timeout = &g_whalTimeout, - }, }; /* Ethernet descriptor rings + buffer pool (referenced by the ETH singleton diff --git a/boards/stm32h563zi_nucleo/board.h b/boards/stm32h563zi_nucleo/board.h index 0f13e18..0d439de 100644 --- a/boards/stm32h563zi_nucleo/board.h +++ b/boards/stm32h563zi_nucleo/board.h @@ -48,6 +48,17 @@ enum { #define BOARD_ETH_PHY_ID1 0x0007 #define BOARD_ETH_PHY_ID2 0xC131 +/* BOARD_*_DEV: how this board reaches each peripheral. WHAL_SINGLETON for + * single-instance drivers; &g_whal for pointer-based drivers. */ +#define BOARD_GPIO_DEV WHAL_SINGLETON +#define BOARD_UART_DEV (&g_whalUart) +#define BOARD_SPI_DEV (&g_whalSpi) +#define BOARD_FLASH_DEV (&g_whalFlash) +#define BOARD_RNG_DEV WHAL_SINGLETON +#define BOARD_ETH_DEV WHAL_SINGLETON +#define BOARD_ETH_PHY_DEV WHAL_SINGLETON +#define BOARD_CLOCK_DEV (&g_whalClock) + /* GPIO singleton — referenced by stm32wb_gpio.c directly. */ static const whal_Gpio whal_Stm32h5_Gpio_Dev = { .base = WHAL_STM32H563_GPIO_BASE, @@ -130,6 +141,20 @@ static const whal_Rng whal_Stm32h5_Rng_Dev = { }, }; +/* Flash singleton — referenced by stm32h5_flash.c directly. Const cfg lives + * here; the dispatcher stub g_whalFlash in board.c carries only .driver so + * whal_Flash_* can be vtable-dispatched alongside other flash drivers (e.g. + * SPI NOR W25Q64). */ +static const whal_Flash whal_Stm32h5_Flash_Dev = { + .base = WHAL_STM32H563_FLASH_BASE, + + .cfg = (void *)&(const whal_Stm32h5_Flash_Cfg){ + .startAddr = 0x08000000, + .size = 0x200000, /* 2 MB */ + .timeout = &g_whalTimeout, + }, +}; + /* ETH descriptor rings + buffer pool — defined in board.c, addresses * captured by the ETH singleton's cfg below at compile time. */ #define BOARD_ETH_TX_DESC_COUNT 4 diff --git a/boards/stm32l152re_nucleo/board.c b/boards/stm32l152re_nucleo/board.c index 6272f8b..e2c0edc 100644 --- a/boards/stm32l152re_nucleo/board.c +++ b/boards/stm32l152re_nucleo/board.c @@ -52,11 +52,7 @@ static const whal_Stm32l1_Rcc_PeriphClk g_periphClks[] = { }; #define PERIPH_CLK_COUNT (sizeof(g_periphClks) / sizeof(g_periphClks[0])) -/* PWR -- Range 1 (1.8 V) to allow SYSCLK up to 32 MHz. */ -whal_Power g_whalPower = { - .base = WHAL_STM32L152_PWR_BASE, -}; - +/* PWR singleton lives in board.h as `static const`. */ /* UART -- USART2 at 115200 baud */ whal_Uart g_whalUart = { @@ -88,16 +84,11 @@ whal_I2c g_whalI2c = { }, }; -/* Flash -- 512 KB */ +/* Flash -- 512 KB. Dispatcher stub; the const cfg lives in board.h as + * whal_Stm32l1_Flash_Dev. This only carries .driver so whal_Flash_* can + * dispatch through the vtable. */ whal_Flash g_whalFlash = { - .base = WHAL_STM32L152_FLASH_BASE, .driver = WHAL_STM32L152_FLASH_DRIVER, - - .cfg = &(whal_Stm32l1_Flash_Cfg) { - .startAddr = 0x08000000, - .size = 0x80000, - .timeout = &g_whalTimeout, - }, }; #ifdef BOARD_WATCHDOG_IWDG @@ -145,7 +136,7 @@ whal_Error Board_Init(void) /* Switch regulator to range 1 (1.8 V) so the PLL can reach 32 MHz. * Reset default is range 2, which caps PLL VCO at 48 MHz and SYSCLK at * 16 MHz. */ - err = whal_Stm32l1_Pwr_SetVosRange(&g_whalPower, + err = whal_Stm32l1_Pwr_SetVosRange(WHAL_SINGLETON, WHAL_STM32L1_PWR_VOS_RANGE_1, &g_whalTimeout); if (err) diff --git a/boards/stm32l152re_nucleo/board.h b/boards/stm32l152re_nucleo/board.h index a840eb2..d18562d 100644 --- a/boards/stm32l152re_nucleo/board.h +++ b/boards/stm32l152re_nucleo/board.h @@ -5,6 +5,7 @@ #include #include #include +#include extern whal_Clock g_whalClock; extern whal_Uart g_whalUart; @@ -36,6 +37,56 @@ enum { #define BOARD_FLASH_TEST_ADDR 0x0807FF00 #define BOARD_FLASH_SECTOR_SZ 0x100 +/* BOARD_*_DEV: how this board reaches each peripheral. */ +#define BOARD_GPIO_DEV WHAL_SINGLETON +#define BOARD_UART_DEV (&g_whalUart) +#define BOARD_SPI_DEV (&g_whalSpi) +#define BOARD_I2C_DEV (&g_whalI2c) +#define BOARD_FLASH_DEV (&g_whalFlash) +#define BOARD_CLOCK_DEV (&g_whalClock) +#define BOARD_WATCHDOG_DEV (&g_whalWatchdog) + +/* PWR singleton — referenced by stm32l1_pwr.c directly. */ +static const whal_Power whal_Stm32l1_Pwr_Dev = { + .base = WHAL_STM32L152_PWR_BASE, +}; + +/* WWDG singleton — referenced by stm32wb_wwdg.c via stm32l1_wwdg.c alias + * (which #includes stm32f0_wwdg.c). Declared unconditionally because the + * compiled .c always references it. */ +static const whal_Watchdog whal_Stm32l1_Wwdg_Dev = { + .base = WHAL_STM32L152_WWDG_BASE, + .cfg = (void *)&(const whal_Stm32l1_Wwdg_Cfg){ + .prescaler = 3, + .window = 0x7F, + .counter = 0x7F, + }, +}; + +/* IWDG singleton — referenced by stm32wb_iwdg.c via stm32l1_iwdg.c alias. */ +static const whal_Watchdog whal_Stm32l1_Iwdg_Dev = { + .base = WHAL_STM32L152_IWDG_BASE, + .cfg = (void *)&(const whal_Stm32l1_Iwdg_Cfg){ + .prescaler = WHAL_STM32L1_IWDG_PR_64, + .reload = 500, + .timeout = &g_whalTimeout, + }, +}; + +/* Flash singleton — referenced by stm32l1_flash.c directly. Const cfg lives + * here; the dispatcher stub g_whalFlash in board.c carries only .driver so + * whal_Flash_* can be vtable-dispatched alongside other flash drivers (e.g. + * SPI NOR W25Q64). */ +static const whal_Flash whal_Stm32l1_Flash_Dev = { + .base = WHAL_STM32L152_FLASH_BASE, + + .cfg = (void *)&(const whal_Stm32l1_Flash_Cfg){ + .startAddr = 0x08000000, + .size = 0x80000, + .timeout = &g_whalTimeout, + }, +}; + static const whal_Gpio whal_Stm32l1_Gpio_Dev = { .base = WHAL_STM32L152_GPIO_BASE, diff --git a/boards/stm32n657a0_nucleo/board.c b/boards/stm32n657a0_nucleo/board.c index 76e44ee..b43cc96 100644 --- a/boards/stm32n657a0_nucleo/board.c +++ b/boards/stm32n657a0_nucleo/board.c @@ -110,9 +110,10 @@ whal_Uart g_whalUart = { }, }; -/* RNG, ETH, EthPhy singletons live in board.h as `static const`. */ +/* RNG, ETH, EthPhy, AES mode, HASH algorithm singletons live in board.h as + * `static const`. */ -/* Crypto (CRYP hardware accelerator) */ +/* Crypto (CRYP hardware accelerator) — vtable dispatcher for whal_Crypto_Init/Deinit. */ whal_Crypto g_whalCrypto = { .base = WHAL_STM32N657_CRYP_BASE, .driver = &whal_Stm32n6_Cryp_CryptoDriver, @@ -122,43 +123,7 @@ whal_Crypto g_whalCrypto = { }, }; -whal_AesEcb g_whalAesEcb = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ -}; - -whal_AesCbc g_whalAesCbc = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ -}; - -whal_AesCtr g_whalAesCtr = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ -}; - -static whal_Stm32n6_AesGcm_State g_aesGcmState; - -whal_AesGcm g_whalAesGcm = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ - .state = &g_aesGcmState, -}; - -whal_AesGmac g_whalAesGmac = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ -}; - -static whal_Stm32n6_AesCcm_State g_aesCcmState; - -whal_AesCcm g_whalAesCcm = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ - .state = &g_aesCcmState, -}; - -/* Hash (HASH hardware accelerator) */ +/* Hash (HASH hardware accelerator) — vtable dispatcher for whal_Crypto_Init/Deinit. */ whal_Crypto g_whalHash = { .base = WHAL_STM32N657_HASH_BASE, .driver = &whal_Stm32n6_Hash_CryptoDriver, @@ -168,45 +133,6 @@ whal_Crypto g_whalHash = { }, }; -whal_Sha1 g_whalSha1 = { - .crypto = &g_whalHash, - /* .driver: direct API mapping */ -}; - -whal_Sha224 g_whalSha224 = { - .crypto = &g_whalHash, - /* .driver: direct API mapping */ -}; - -whal_Sha256 g_whalSha256 = { - .crypto = &g_whalHash, - /* .driver: direct API mapping */ -}; - -static whal_Stm32n6_HmacSha1_State g_hmacSha1State; - -whal_HmacSha1 g_whalHmacSha1 = { - .crypto = &g_whalHash, - /* .driver: direct API mapping */ - .state = &g_hmacSha1State, -}; - -static whal_Stm32n6_HmacSha224_State g_hmacSha224State; - -whal_HmacSha224 g_whalHmacSha224 = { - .crypto = &g_whalHash, - /* .driver: direct API mapping */ - .state = &g_hmacSha224State, -}; - -static whal_Stm32n6_HmacSha256_State g_hmacSha256State; - -whal_HmacSha256 g_whalHmacSha256 = { - .crypto = &g_whalHash, - /* .driver: direct API mapping */ - .state = &g_hmacSha256State, -}; - #ifdef BOARD_WATCHDOG_IWDG whal_Watchdog g_whalWatchdog = { .base = WHAL_STM32N657_IWDG_BASE, diff --git a/boards/stm32n657a0_nucleo/board.h b/boards/stm32n657a0_nucleo/board.h index ec18906..da60d01 100644 --- a/boards/stm32n657a0_nucleo/board.h +++ b/boards/stm32n657a0_nucleo/board.h @@ -8,25 +8,14 @@ #include #include #include +#include extern whal_Clock g_whalClock; extern whal_Uart g_whalUart; extern whal_Spi g_whalSpi; extern whal_I2c g_whalI2c; extern whal_Crypto g_whalCrypto; -extern whal_AesEcb g_whalAesEcb; -extern whal_AesCbc g_whalAesCbc; -extern whal_AesCtr g_whalAesCtr; -extern whal_AesGcm g_whalAesGcm; -extern whal_AesGmac g_whalAesGmac; -extern whal_AesCcm g_whalAesCcm; extern whal_Crypto g_whalHash; -extern whal_Sha1 g_whalSha1; -extern whal_Sha224 g_whalSha224; -extern whal_Sha256 g_whalSha256; -extern whal_HmacSha1 g_whalHmacSha1; -extern whal_HmacSha224 g_whalHmacSha224; -extern whal_HmacSha256 g_whalHmacSha256; extern whal_Watchdog g_whalWatchdog; #ifdef BOARD_DMA extern whal_Dma g_whalDma1; @@ -64,6 +53,49 @@ enum { #define BOARD_ETH_PHY_ID1 0x0007 #define BOARD_ETH_PHY_ID2 0xC131 +/* BOARD_*_DEV: how this board reaches each peripheral. */ +#define BOARD_GPIO_DEV WHAL_SINGLETON +#define BOARD_UART_DEV (&g_whalUart) +#define BOARD_SPI_DEV (&g_whalSpi) +#define BOARD_I2C_DEV (&g_whalI2c) +#define BOARD_CLOCK_DEV (&g_whalClock) +#define BOARD_WATCHDOG_DEV (&g_whalWatchdog) +#define BOARD_RNG_DEV WHAL_SINGLETON +#define BOARD_ETH_DEV WHAL_SINGLETON +#define BOARD_ETH_PHY_DEV WHAL_SINGLETON +#define BOARD_AES_ECB_DEV WHAL_SINGLETON +#define BOARD_AES_CBC_DEV WHAL_SINGLETON +#define BOARD_AES_CTR_DEV WHAL_SINGLETON +#define BOARD_AES_GCM_DEV WHAL_SINGLETON +#define BOARD_AES_GMAC_DEV WHAL_SINGLETON +#define BOARD_AES_CCM_DEV WHAL_SINGLETON +#define BOARD_SHA1_DEV WHAL_SINGLETON +#define BOARD_SHA224_DEV WHAL_SINGLETON +#define BOARD_SHA256_DEV WHAL_SINGLETON +#define BOARD_HMAC_SHA1_DEV WHAL_SINGLETON +#define BOARD_HMAC_SHA224_DEV WHAL_SINGLETON +#define BOARD_HMAC_SHA256_DEV WHAL_SINGLETON + +/* IWDG/WWDG singletons — referenced by stm32wb_iwdg.c/stm32wb_wwdg.c + * via stm32n6_iwdg.c/stm32n6_wwdg.c aliases. */ +static const whal_Watchdog whal_Stm32n6_Iwdg_Dev = { + .base = WHAL_STM32N657_IWDG_BASE, + .cfg = (void *)&(const whal_Stm32n6_Iwdg_Cfg){ + .prescaler = WHAL_STM32N6_IWDG_PR_32, + .reload = 100, + .timeout = &g_whalTimeout, + }, +}; + +static const whal_Watchdog whal_Stm32n6_Wwdg_Dev = { + .base = WHAL_STM32N657_WWDG_BASE, + .cfg = (void *)&(const whal_Stm32n6_Wwdg_Cfg){ + .prescaler = WHAL_STM32N6_WWDG_TB_128, + .window = 0x7F, + .counter = 0x7F, + }, +}; + static const whal_Gpio whal_Stm32n6_Gpio_Dev = { .base = WHAL_STM32N657_GPIO_BASE, @@ -164,14 +196,78 @@ static const whal_Gpio whal_Stm32n6_Gpio_Dev = { }, }; -/* RNG singleton — referenced by stm32n6_rng.c directly. */ -static const whal_Rng whal_Stm32h5_Rng_Dev = { +/* RNG singleton — referenced by stm32wba_rng.c (via stm32n6_rng.c alias). */ +static const whal_Rng whal_Stm32n6_Rng_Dev = { .base = WHAL_STM32N657_RNG_BASE, .cfg = (void *)&(const whal_Stm32n6_Rng_Cfg){ .timeout = &g_whalTimeout, }, }; +/* CRYP + mode singletons — referenced by stm32n6_cryp.c directly. */ +static const whal_Crypto whal_Stm32n6_Cryp_Dev = { + .base = WHAL_STM32N657_CRYP_BASE, + .cfg = (void *)&(const whal_Stm32n6_Cryp_Cfg){ + .timeout = &g_whalTimeout, + }, +}; + +static const whal_AesEcb whal_Stm32n6_CrypEcb_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32n6_Cryp_Dev, +}; + +static const whal_AesCbc whal_Stm32n6_CrypCbc_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32n6_Cryp_Dev, +}; + +static const whal_AesCtr whal_Stm32n6_CrypCtr_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32n6_Cryp_Dev, +}; + +static const whal_AesGcm whal_Stm32n6_CrypGcm_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32n6_Cryp_Dev, +}; + +static const whal_AesGmac whal_Stm32n6_CrypGmac_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32n6_Cryp_Dev, +}; + +static const whal_AesCcm whal_Stm32n6_CrypCcm_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32n6_Cryp_Dev, +}; + +/* HASH + algorithm singletons — referenced by stm32wba_hash.c (via stm32n6_hash.c alias). */ +static const whal_Crypto whal_Stm32n6_Hash_Dev = { + .base = WHAL_STM32N657_HASH_BASE, + .cfg = (void *)&(const whal_Stm32n6_Hash_Cfg){ + .timeout = &g_whalTimeout, + }, +}; + +static const whal_Sha1 whal_Stm32n6_Sha1_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32n6_Hash_Dev, +}; + +static const whal_Sha224 whal_Stm32n6_Sha224_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32n6_Hash_Dev, +}; + +static const whal_Sha256 whal_Stm32n6_Sha256_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32n6_Hash_Dev, +}; + +static const whal_HmacSha1 whal_Stm32n6_HmacSha1_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32n6_Hash_Dev, +}; + +static const whal_HmacSha224 whal_Stm32n6_HmacSha224_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32n6_Hash_Dev, +}; + +static const whal_HmacSha256 whal_Stm32n6_HmacSha256_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32n6_Hash_Dev, +}; + /* ETH descriptor rings + buffer pool. Live in board.c with the .axisram1 * section attribute; declared here so the ETH singleton cfg below can * take their addresses at compile time. */ @@ -186,7 +282,7 @@ extern uint8_t ethTxBufs[BOARD_ETH_TX_DESC_COUNT * BOARD_ETH_TX_BUF_SIZE]; extern uint8_t ethRxBufs[BOARD_ETH_RX_DESC_COUNT * BOARD_ETH_RX_BUF_SIZE]; /* ETH singleton — referenced by stm32n6_eth.c directly. */ -static const whal_Eth whal_Stm32h5_Eth_Dev = { +static const whal_Eth whal_Stm32n6_Eth_Dev = { .base = WHAL_STM32N657_ETH_BASE, .macAddr = {0x00, 0x80, 0xE1, 0x00, 0x00, 0x01}, .cfg = (void *)&(const whal_Stm32n6_Eth_Cfg){ diff --git a/boards/stm32wb55xx_nucleo/board.c b/boards/stm32wb55xx_nucleo/board.c index 8f1a3c0..c86076a 100644 --- a/boards/stm32wb55xx_nucleo/board.c +++ b/boards/stm32wb55xx_nucleo/board.c @@ -137,42 +137,6 @@ whal_Crypto g_whalCrypto = { }, }; -whal_AesEcb g_whalAesEcb = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ -}; - -whal_AesCbc g_whalAesCbc = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ -}; - -whal_AesCtr g_whalAesCtr = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ -}; - -static whal_Stm32wb_AesGcm_State g_aesGcmState; - -whal_AesGcm g_whalAesGcm = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ - .state = &g_aesGcmState, -}; - -whal_AesGmac g_whalAesGmac = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ -}; - -static whal_Stm32wb_AesCcm_State g_aesCcmState; - -whal_AesCcm g_whalAesCcm = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ - .state = &g_aesCcmState, -}; - void Board_WaitMs(size_t ms) { uint32_t startCount = g_tick; diff --git a/boards/stm32wb55xx_nucleo/board.h b/boards/stm32wb55xx_nucleo/board.h index 62520de..02c2558 100644 --- a/boards/stm32wb55xx_nucleo/board.h +++ b/boards/stm32wb55xx_nucleo/board.h @@ -11,12 +11,6 @@ extern whal_Uart g_whalUart; extern whal_Spi g_whalSpi; extern whal_Flash g_whalFlash; extern whal_Crypto g_whalCrypto; -extern whal_AesEcb g_whalAesEcb; -extern whal_AesCbc g_whalAesCbc; -extern whal_AesCtr g_whalAesCtr; -extern whal_AesGcm g_whalAesGcm; -extern whal_AesGmac g_whalAesGmac; -extern whal_AesCcm g_whalAesCcm; extern whal_I2c g_whalI2c; extern whal_Timeout g_whalTimeout; @@ -41,6 +35,23 @@ enum { #define BOARD_FLASH_TEST_ADDR 0x0807F000 #define BOARD_FLASH_SECTOR_SZ 0x1000 +/* BOARD_*_DEV: how this board reaches each peripheral. WHAL_SINGLETON for + * single-instance drivers (driver ignores the pointer); &g_whal for + * drivers still using vtable dispatch / pointer-based path. */ +#define BOARD_GPIO_DEV WHAL_SINGLETON +#define BOARD_UART_DEV (&g_whalUart) +#define BOARD_SPI_DEV (&g_whalSpi) +#define BOARD_I2C_DEV (&g_whalI2c) +#define BOARD_FLASH_DEV (&g_whalFlash) +#define BOARD_CLOCK_DEV (&g_whalClock) +#define BOARD_WATCHDOG_DEV WHAL_SINGLETON +#define BOARD_RNG_DEV WHAL_SINGLETON +#define BOARD_AES_ECB_DEV WHAL_SINGLETON +#define BOARD_AES_CBC_DEV WHAL_SINGLETON +#define BOARD_AES_CTR_DEV WHAL_SINGLETON +#define BOARD_AES_GCM_DEV WHAL_SINGLETON +#define BOARD_AES_GMAC_DEV WHAL_SINGLETON +#define BOARD_AES_CCM_DEV WHAL_SINGLETON /* GPIO singleton — referenced by stm32wb_gpio.c directly. */ static const whal_Gpio whal_Stm32wb_Gpio_Dev = { diff --git a/boards/stm32wba55cg_nucleo/board.c b/boards/stm32wba55cg_nucleo/board.c index b6ce527..998401d 100644 --- a/boards/stm32wba55cg_nucleo/board.c +++ b/boards/stm32wba55cg_nucleo/board.c @@ -134,74 +134,16 @@ whal_Uart g_whalUart = { }; #endif -/* Flash */ +/* Flash — dispatcher stub. The const cfg lives in board.h as + * whal_Stm32wba_Flash_Dev; this only carries .driver so whal_Flash_* can + * dispatch through the vtable. */ whal_Flash g_whalFlash = { - .base = WHAL_STM32WBA55_FLASH_BASE, .driver = WHAL_STM32WBA55_FLASH_DRIVER, - - .cfg = &(whal_Stm32wba_Flash_Cfg) { - .timeout = &g_whalTimeout, - .startAddr = 0x08000000, - .size = 0x100000, /* 1 MB */ - }, }; -/* RNG */ -whal_Rng g_whalRng = { - .base = WHAL_STM32WBA55_RNG_BASE, - .driver = WHAL_STM32WBA55_RNG_DRIVER, - - .cfg = &(whal_Stm32wba_Rng_Cfg) { - .timeout = &g_whalTimeout, - }, -}; - -/* Crypto (AES hardware accelerator) */ -whal_Crypto g_whalCrypto = { - .base = WHAL_STM32WBA55_AES_BASE, - - .cfg = &(whal_Stm32wba_Aes_Cfg) { - .timeout = &g_whalTimeout, - }, -}; - -whal_AesEcb g_whalAesEcb = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ -}; - -whal_AesCbc g_whalAesCbc = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ -}; - -whal_AesCtr g_whalAesCtr = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ -}; - -static whal_Stm32wba_AesGcm_State g_aesGcmState; - -whal_AesGcm g_whalAesGcm = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ - .state = &g_aesGcmState, -}; +/* RNG, AES + mode, HASH + algorithm singletons live in board.h as `static const`. */ -whal_AesGmac g_whalAesGmac = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ -}; - -static whal_Stm32wba_AesCcm_State g_aesCcmState; - -whal_AesCcm g_whalAesCcm = { - .crypto = &g_whalCrypto, - /* .driver: direct API mapping */ - .state = &g_aesCcmState, -}; - -/* Hash (HASH hardware accelerator) */ +/* Hash (HASH hardware accelerator) — vtable dispatcher for whal_Crypto_Init/Deinit. */ whal_Crypto g_whalHash = { .base = WHAL_STM32WBA55_HASH_BASE, .driver = &whal_Stm32wba_Hash_CryptoDriver, @@ -211,45 +153,6 @@ whal_Crypto g_whalHash = { }, }; -whal_Sha1 g_whalSha1 = { - .crypto = &g_whalHash, - /* .driver: direct API mapping */ -}; - -whal_Sha224 g_whalSha224 = { - .crypto = &g_whalHash, - /* .driver: direct API mapping */ -}; - -whal_Sha256 g_whalSha256 = { - .crypto = &g_whalHash, - /* .driver: direct API mapping */ -}; - -static whal_Stm32wba_HmacSha1_State g_hmacSha1State; - -whal_HmacSha1 g_whalHmacSha1 = { - .crypto = &g_whalHash, - /* .driver: direct API mapping */ - .state = &g_hmacSha1State, -}; - -static whal_Stm32wba_HmacSha224_State g_hmacSha224State; - -whal_HmacSha224 g_whalHmacSha224 = { - .crypto = &g_whalHash, - /* .driver: direct API mapping */ - .state = &g_hmacSha224State, -}; - -static whal_Stm32wba_HmacSha256_State g_hmacSha256State; - -whal_HmacSha256 g_whalHmacSha256 = { - .crypto = &g_whalHash, - /* .driver: direct API mapping */ - .state = &g_hmacSha256State, -}; - #ifdef BOARD_WATCHDOG_IWDG whal_Watchdog g_whalWatchdog = { .base = WHAL_STM32WBA55_IWDG_BASE, @@ -417,7 +320,7 @@ whal_Error Board_Init(void) if (err) return err; - err = whal_Rng_Init(&g_whalRng); + err = whal_Rng_Init(WHAL_SINGLETON); if (err) return err; @@ -460,7 +363,7 @@ whal_Error Board_Deinit(void) if (err) return err; - err = whal_Rng_Deinit(&g_whalRng); + err = whal_Rng_Deinit(WHAL_SINGLETON); if (err) return err; diff --git a/boards/stm32wba55cg_nucleo/board.h b/boards/stm32wba55cg_nucleo/board.h index 40a90a5..c02b0af 100644 --- a/boards/stm32wba55cg_nucleo/board.h +++ b/boards/stm32wba55cg_nucleo/board.h @@ -7,27 +7,13 @@ #include #include #include +#include extern whal_Clock g_whalClock; extern whal_Uart g_whalUart; extern whal_Spi g_whalSpi; extern whal_Flash g_whalFlash; -extern whal_Rng g_whalRng; extern whal_I2c g_whalI2c; -extern whal_Crypto g_whalCrypto; -extern whal_AesEcb g_whalAesEcb; -extern whal_AesCbc g_whalAesCbc; -extern whal_AesCtr g_whalAesCtr; -extern whal_AesGcm g_whalAesGcm; -extern whal_AesGmac g_whalAesGmac; -extern whal_AesCcm g_whalAesCcm; -extern whal_Crypto g_whalHash; -extern whal_Sha1 g_whalSha1; -extern whal_Sha224 g_whalSha224; -extern whal_Sha256 g_whalSha256; -extern whal_HmacSha1 g_whalHmacSha1; -extern whal_HmacSha224 g_whalHmacSha224; -extern whal_HmacSha256 g_whalHmacSha256; extern whal_Watchdog g_whalWatchdog; #ifdef BOARD_DMA extern whal_Dma g_whalDma1; @@ -56,6 +42,137 @@ enum { #define BOARD_FLASH_TEST_ADDR 0x080FE000 #define BOARD_FLASH_SECTOR_SZ 0x2000 /* 8 KB */ +/* IWDG/WWDG singletons — referenced by stm32wb_iwdg.c/stm32wb_wwdg.c directly. */ +static const whal_Watchdog whal_Stm32wba_Iwdg_Dev = { + .base = WHAL_STM32WBA55_IWDG_BASE, + .cfg = (void *)&(const whal_Stm32wba_Iwdg_Cfg){ + .prescaler = WHAL_STM32WBA_IWDG_PR_32, + .reload = 100, + .timeout = &g_whalTimeout, + }, +}; + +static const whal_Watchdog whal_Stm32wba_Wwdg_Dev = { + .base = WHAL_STM32WBA55_WWDG_BASE, + .cfg = (void *)&(const whal_Stm32wba_Wwdg_Cfg){ + .prescaler = WHAL_STM32WBA_WWDG_TB_128, + .window = 0x7F, + .counter = 0x7F, + }, +}; + +/* AES + mode singletons — referenced by stm32wb_aes.c directly. */ +static const whal_Crypto whal_Stm32wba_Aes_Dev = { + .base = WHAL_STM32WBA55_AES_BASE, + .cfg = (void *)&(const whal_Stm32wba_Aes_Cfg){ + .timeout = &g_whalTimeout, + }, +}; + +static const whal_AesEcb whal_Stm32wba_AesEcb_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wba_Aes_Dev, +}; + +static const whal_AesCbc whal_Stm32wba_AesCbc_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wba_Aes_Dev, +}; + +static const whal_AesCtr whal_Stm32wba_AesCtr_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wba_Aes_Dev, +}; + +static whal_Stm32wba_AesGcm_State g_wbaAesGcmDevState; +static const whal_AesGcm whal_Stm32wba_AesGcm_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wba_Aes_Dev, + .state = &g_wbaAesGcmDevState, +}; + +static const whal_AesGmac whal_Stm32wba_AesGmac_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wba_Aes_Dev, +}; + +static whal_Stm32wba_AesCcm_State g_wbaAesCcmDevState; +static const whal_AesCcm whal_Stm32wba_AesCcm_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wba_Aes_Dev, + .state = &g_wbaAesCcmDevState, +}; + +/* RNG singleton — referenced by stm32wba_rng.c directly. */ +static const whal_Rng whal_Stm32wba_Rng_Dev = { + .base = WHAL_STM32WBA55_RNG_BASE, + .cfg = (void *)&(const whal_Stm32wba_Rng_Cfg){ + .timeout = &g_whalTimeout, + }, +}; + +/* Flash singleton — referenced by stm32wba_flash.c directly. Const cfg lives + * here; the dispatcher stub g_whalFlash in board.c carries only .driver so + * whal_Flash_* can be vtable-dispatched alongside other flash drivers (e.g. + * SPI NOR W25Q64). */ +static const whal_Flash whal_Stm32wba_Flash_Dev = { + .base = WHAL_STM32WBA55_FLASH_BASE, + + .cfg = (void *)&(const whal_Stm32wba_Flash_Cfg){ + .timeout = &g_whalTimeout, + .startAddr = 0x08000000, + .size = 0x100000, /* 1 MB */ + }, +}; + +/* HASH + algorithm singletons — referenced by stm32wba_hash.c directly. */ +static const whal_Crypto whal_Stm32wba_Hash_Dev = { + .base = WHAL_STM32WBA55_HASH_BASE, + .cfg = (void *)&(const whal_Stm32wba_Hash_Cfg){ + .timeout = &g_whalTimeout, + }, +}; + +static const whal_Sha1 whal_Stm32wba_Sha1_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wba_Hash_Dev, +}; + +static const whal_Sha224 whal_Stm32wba_Sha224_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wba_Hash_Dev, +}; + +static const whal_Sha256 whal_Stm32wba_Sha256_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wba_Hash_Dev, +}; + +static const whal_HmacSha1 whal_Stm32wba_HmacSha1_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wba_Hash_Dev, +}; + +static const whal_HmacSha224 whal_Stm32wba_HmacSha224_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wba_Hash_Dev, +}; + +static const whal_HmacSha256 whal_Stm32wba_HmacSha256_Dev = { + .crypto = (whal_Crypto *)&whal_Stm32wba_Hash_Dev, +}; + +/* BOARD_*_DEV: how this board reaches each peripheral. */ +#define BOARD_GPIO_DEV WHAL_SINGLETON +#define BOARD_UART_DEV (&g_whalUart) +#define BOARD_SPI_DEV (&g_whalSpi) +#define BOARD_I2C_DEV (&g_whalI2c) +#define BOARD_FLASH_DEV (&g_whalFlash) +#define BOARD_CLOCK_DEV (&g_whalClock) +#define BOARD_WATCHDOG_DEV (&g_whalWatchdog) +#define BOARD_RNG_DEV WHAL_SINGLETON +#define BOARD_AES_ECB_DEV WHAL_SINGLETON +#define BOARD_AES_CBC_DEV WHAL_SINGLETON +#define BOARD_AES_CTR_DEV WHAL_SINGLETON +#define BOARD_AES_GCM_DEV WHAL_SINGLETON +#define BOARD_AES_GMAC_DEV WHAL_SINGLETON +#define BOARD_AES_CCM_DEV WHAL_SINGLETON +#define BOARD_SHA1_DEV WHAL_SINGLETON +#define BOARD_SHA224_DEV WHAL_SINGLETON +#define BOARD_SHA256_DEV WHAL_SINGLETON +#define BOARD_HMAC_SHA1_DEV WHAL_SINGLETON +#define BOARD_HMAC_SHA224_DEV WHAL_SINGLETON +#define BOARD_HMAC_SHA256_DEV WHAL_SINGLETON + static const whal_Gpio whal_Stm32wba_Gpio_Dev = { .base = WHAL_STM32WBA55_GPIO_BASE, .driver = WHAL_STM32WBA55_GPIO_DRIVER, diff --git a/docs/adding_a_board.md b/docs/adding_a_board.md index 215f148..6840dab 100644 --- a/docs/adding_a_board.md +++ b/docs/adding_a_board.md @@ -12,37 +12,91 @@ directory under `boards/` named `_/`. ### board.h -Exports global peripheral instances and board-specific constants: +`board.h` is where the board describes each peripheral to the rest of the +project. It contains four kinds of declaration: + +1. `extern` globals for vtable-dispatched drivers (`g_whalUart`, + `g_whalSpi`, `g_whalI2c`, ...) defined over in `board.c`. +2. `static const` singletons (`whal___Dev`) for + single-instance drivers — these are read directly by the driver + bodies (`#include "board.h"` from the driver source). Each + translation unit including `board.h` gets its own const copy in + `.rodata`; `--gc-sections` folds the unused ones. +3. `BOARD__DEV` macros that the application and tests use to + reach each peripheral — these resolve to either `WHAL_SINGLETON` or + `&g_whal`, depending on how this board has wired the driver. +4. Board constants (pin indices, flash test addresses, etc.) and the + `Board_Init` / `Board_Deinit` / `Board_WaitMs` prototypes. ```c #pragma once #include +#include extern whal_Clock g_whalClock; -extern whal_Gpio g_whalGpio; extern whal_Uart g_whalUart; -extern whal_Timer g_whalTimer; -extern whal_Flash g_whalFlash; extern whal_Timeout g_whalTimeout; #define BOARD_LED_PIN 0 +/* BOARD__DEV: how this board reaches each peripheral. + * WHAL_SINGLETON for single-instance drivers whose body reads from a + * named singleton below; &g_whal for drivers that still use vtable + * dispatch (or for the coexistence-stub variant). */ +#define BOARD_GPIO_DEV WHAL_SINGLETON +#define BOARD_UART_DEV (&g_whalUart) +#define BOARD_CLOCK_DEV (&g_whalClock) +#define BOARD_WATCHDOG_DEV WHAL_SINGLETON +#define BOARD_RNG_DEV WHAL_SINGLETON + +/* Singleton consumed by the GPIO driver body directly. */ +static const whal_Gpio whal_Myplatform_Gpio_Dev = { + .base = WHAL_MYPLATFORM_GPIO_BASE, + .cfg = (void *)&(const whal_Myplatform_Gpio_Cfg){ + /* ...pin table... */ + }, +}; + +/* Singleton consumed by the RNG driver body directly. */ +static const whal_Rng whal_Myplatform_Rng_Dev = { + .base = WHAL_MYPLATFORM_RNG_BASE, + .cfg = (void *)&(const whal_Myplatform_Rng_Cfg){ + .timeout = &g_whalTimeout, + }, +}; + whal_Error Board_Init(void); whal_Error Board_Deinit(void); void Board_WaitMs(size_t ms); ``` +When a chip's driver is implemented as an alias of another chip's driver +(e.g. STM32N6 IWDG reusing the STM32WB body), the singleton must be +declared under this board's own platform name — the alias header bridges +the two names with a `#define` (see `wolfHAL/watchdog/stm32n6_iwdg.h`). +A small number of singletons are inherently cross-platform and keep +neutral names: `whal_Nvic_Dev` (Cortex-M NVIC), `whal_SysTick_Dev` +(Cortex-M SysTick), `whal_Lan8742a_Dev` (generic Ethernet PHY). + +Single-instance drivers that need per-instance mutable state (e.g. +AES-GCM / AES-CCM accumulators) declare the state as a `static` variable +in `board.h` immediately above the singleton that points at it. Each +including translation unit gets its own copy, but only the driver TU +writes to it, and `--gc-sections` strips the rest. + ### board.c -Defines global device instances with their configurations and implements -`Board_Init()` and `Board_Deinit()`. +Defines the `extern` device instances declared in `board.h` (the +vtable-dispatched ones) and implements `Board_Init()` / `Board_Deinit()`. +Per-instance const cfg for single-instance drivers lives in `board.h` +alongside the singleton; `board.c` does not need to repeat it. -`Board_Init()` is responsible for initializing all peripherals in dependency -order. For example, the clock controller must be initialized before peripherals -that depend on it, and a power supply controller (if present) may need to come -before the clock. It should return `WHAL_SUCCESS` on success or an error code -on failure. +`Board_Init()` is responsible for initializing all peripherals in +dependency order. For example, the clock controller must be initialized +before peripherals that depend on it, and a power supply controller (if +present) may need to come before the clock. It should return +`WHAL_SUCCESS` on success or an error code on failure. `Board_Deinit()` tears down peripherals in reverse order. @@ -51,21 +105,22 @@ on failure. #include #include "peripheral.h" -static whal_Myplatform_Gpio_PinCfg pinCfg[] = { /* ... */ }; - -static whal_Myplatform_Gpio_Cfg gpioConfig = { - .pinCfg = pinCfg, - .pinCount = sizeof(pinCfg) / sizeof(pinCfg[0]), +whal_Clock g_whalClock = { + .base = WHAL_MYPLATFORM_CLOCK_BASE, }; -whal_Gpio g_whalGpio = { - .base = WHAL_MYPLATFORM_GPIO_BASE, - .cfg = &gpioConfig, +whal_Uart g_whalUart = { + .base = WHAL_MYPLATFORM_UART1_BASE, + /* .driver: direct API mapping */ + .cfg = &(whal_Myplatform_Uart_Cfg) { + .brr = WHAL_MYPLATFORM_UART_BRR(SYSCLK_HZ, 115200), + .timeout = &g_whalTimeout, + }, }; static const whal_Myplatform_Clock_PeriphClk g_periphClks[] = { - {MY_PLATFORM_GPIO_CLOCK}, - {MY_PLATFORM_UART_CLOCK}, + {WHAL_MYPLATFORM_GPIOA_GATE}, + {WHAL_MYPLATFORM_UART1_GATE}, }; #define PERIPH_CLK_COUNT \ (sizeof(g_periphClks) / sizeof(g_periphClks[0])) @@ -73,6 +128,7 @@ static const whal_Myplatform_Clock_PeriphClk g_periphClks[] = { whal_Error Board_Init(void) { whal_Error err; + size_t i; /* Bring up the clock tree imperatively. The chip's clock driver * exposes Enable*/Disable*/Set* helpers; boards call them in order. @@ -86,26 +142,30 @@ whal_Error Board_Init(void) if (err) return err; - for (size_t i = 0; i < PERIPH_CLK_COUNT; i++) { + for (i = 0; i < PERIPH_CLK_COUNT; i++) { err = whal_Myplatform_Clock_EnablePeriphClk(&g_whalClock, - &g_periphClks[i]); + &g_periphClks[i]); if (err) return err; } - err = whal_Gpio_Init(&g_whalGpio); + /* Initialize peripherals. Pass the corresponding BOARD__DEV + * macro — it will be WHAL_SINGLETON for single-instance drivers or + * &g_whal for vtable-dispatched drivers, whichever this board + * declared in board.h. */ + err = whal_Gpio_Init(BOARD_GPIO_DEV); if (err) return err; - err = whal_Uart_Init(&g_whalUart); + err = whal_Uart_Init(BOARD_UART_DEV); if (err) return err; - err = whal_Timer_Init(&g_whalTimer); + err = whal_Timer_Init(BOARD_TIMER_DEV); if (err) return err; - err = whal_Timer_Start(&g_whalTimer); + err = whal_Timer_Start(BOARD_TIMER_DEV); if (err) return err; @@ -117,14 +177,46 @@ whal_Error Board_Init(void) } ``` +#### Coexisting drivers of the same type + +When two drivers of the same generic type share a board (the typical case +is on-chip flash plus an external SPI-NOR flash), the const cfg singleton +in `board.h` is not enough on its own — the generic dispatcher +(`whal_Flash_Read`, etc.) must still vtable-dispatch to pick which +driver runs. The pattern is a "stub" in `board.c` carrying only the +`.driver` field, paired with the const cfg singleton in `board.h`: + +```c +/* board.h */ +static const whal_Flash whal_Myplatform_Flash_Dev = { + .base = WHAL_MYPLATFORM_FLASH_BASE, + .cfg = (void *)&(const whal_Myplatform_Flash_Cfg){ /* ... */ }, +}; + +#define BOARD_FLASH_DEV (&g_whalFlash) + +/* board.c — dispatcher stub. The driver body still reads .base and .cfg + * from whal_Myplatform_Flash_Dev; this struct only exists so that + * whal_Flash_* can vtable-dispatch to it. */ +whal_Flash g_whalFlash = { + .driver = WHAL_MYPLATFORM_FLASH_DRIVER, +}; +``` + +The external SPI-NOR side does not need this dance — it is already a +peripheral driver with its own `g_whal` and vtable, and lives in +`boards/peripheral/`. + The watchdog is intentionally excluded from `Board_Init()` and `Board_Deinit()`. Once started, most watchdog peripherals cannot be stopped — if `Board_Init()` starts the watchdog, any delay before the application begins refreshing it will cause an unexpected reset. The application or test should call -`whal_Watchdog_Init()` directly when it is ready to begin refreshing. The board -still defines the `g_whalWatchdog` instance and enables any required clocks -(e.g., WWDG APB clock, IWDG LSI oscillator) so the watchdog is ready to be -started. +`whal_Watchdog_Init(BOARD_WATCHDOG_DEV)` directly when it is ready to begin +refreshing. The board still declares the watchdog device (whether as a +singleton in `board.h` or as `g_whalWatchdog` in `board.c`, depending on the +driver), points `BOARD_WATCHDOG_DEV` at it, and enables any required clocks +(e.g., WWDG APB clock, IWDG LSI oscillator) in `Board_Init()` so the +watchdog is ready to be started. ```c whal_Error Board_Deinit(void) @@ -135,14 +227,14 @@ whal_Error Board_Deinit(void) if (err) return err; - whal_Timer_Stop(&g_whalTimer); - whal_Timer_Deinit(&g_whalTimer); - whal_Uart_Deinit(&g_whalUart); - whal_Gpio_Deinit(&g_whalGpio); + whal_Timer_Stop(BOARD_TIMER_DEV); + whal_Timer_Deinit(BOARD_TIMER_DEV); + whal_Uart_Deinit(BOARD_UART_DEV); + whal_Gpio_Deinit(BOARD_GPIO_DEV); for (size_t i = PERIPH_CLK_COUNT; i-- > 0; ) { err = whal_Myplatform_Clock_DisablePeriphClk(&g_whalClock, - &g_periphClks[i]); + &g_periphClks[i]); if (err) return err; } @@ -166,9 +258,9 @@ LD = arm-none-eabi-gcc OBJCOPY = arm-none-eabi-objcopy CFLAGS = -mcpu=cortex-m4 -mthumb -Os -Wall -MMD $(INCLUDE) -I$(_BOARD_DIR) \ - -DWHAL_CFG_GPIO_API_MAPPING_MYPLATFORM \ - -DWHAL_CFG_CLOCK_API_MAPPING_MYPLATFORM \ - -DWHAL_CFG_UART_API_MAPPING_MYPLATFORM + -DWHAL_CFG_MYPLATFORM_GPIO_DIRECT_API_MAPPING \ + -DWHAL_CFG_MYPLATFORM_UART_DIRECT_API_MAPPING \ + -DWHAL_CFG_MYPLATFORM_UART_SINGLE_INSTANCE LDFLAGS = -mcpu=cortex-m4 -mthumb -nostdlib -lgcc LINKER_SCRIPT = $(_BOARD_DIR)/linker.ld @@ -190,6 +282,20 @@ BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/systick.c) include $(WHAL_DIR)/boards/peripheral/board.mk ``` +Two families of build-time knobs commonly appear in `board.mk`: + +- `WHAL_CFG__DIRECT_API_MAPPING` renames the chip-specific + driver functions to the generic API names, eliminating the vtable + dispatch wrapper. Safe whenever a generic-API type has at most one + driver linked into the build. +- `WHAL_CFG___SINGLE_INSTANCE` makes a conditionally + single-instance driver read its `.base` and `.cfg` from the + corresponding `whal___Dev` singleton in `board.h` instead + of dereferencing the handle argument. The flag is per-driver + per-platform; default builds keep the pointer-based path. Other + drivers are unconditionally single-instance and need no flag — their + driver bodies always read from the singleton. + ## Peripheral Devices Boards support optional external peripheral devices (e.g., SPI-NOR flash, SD diff --git a/docs/adding_a_peripheral.md b/docs/adding_a_peripheral.md index 9dc5c26..629e104 100644 --- a/docs/adding_a_peripheral.md +++ b/docs/adding_a_peripheral.md @@ -73,9 +73,11 @@ extern whal_Flash g_whalSpiNorW25q64; ### Source -Define the device instance with its configuration. The device references board -globals (`g_whalSpi`, `g_whalGpio`, `SPI_CS_PIN`, `g_whalTimeout`) from -`board.h`: +Define the device instance with its configuration. The device reaches its +underlying bus (SPI here) and any other host-side peripherals through the +board's `BOARD__DEV` macros so the same peripheral source works +regardless of how each board has wired those drivers. Other board values +(`SPI_CS_PIN`, `g_whalTimeout`) come from `board.h` directly: ```c #include "spi_nor_w25q64.h" @@ -95,9 +97,9 @@ static whal_Spi_ComCfg g_w25q64ComCfg = { whal_Flash g_whalSpiNorW25q64 = { .driver = &whal_SpiNor_Driver, .cfg = &(whal_SpiNor_Cfg) { - .spiDev = &g_whalSpi, + .spiDev = BOARD_SPI_DEV, .spiComCfg = &g_w25q64ComCfg, - .gpioDev = &g_whalGpio, + .gpioDev = BOARD_GPIO_DEV, .csPin = SPI_CS_PIN, .timeout = &g_whalTimeout, .pageSz = W25Q64_PAGE_SZ, diff --git a/docs/adding_a_test.md b/docs/adding_a_test.md index fb40e60..c2ad887 100644 --- a/docs/adding_a_test.md +++ b/docs/adding_a_test.md @@ -23,9 +23,11 @@ function returns early and the test is marked as failed. ## Generic Tests Generic tests exercise the wolfHAL API using only the public interface. They -rely on global peripheral instances and board constants from `board.h` (e.g., -`g_whalGpio`, `BOARD_LED_PIN`), so they run on any board that supports the -device type without modification. +reach peripherals through the `BOARD__DEV` macros and board +constants from `board.h` (e.g., `BOARD_GPIO_DEV`, `BOARD_LED_PIN`), so they +run on any board that supports the device type without modification — the +board decides whether `BOARD__DEV` resolves to `WHAL_SINGLETON` or +to a pointer such as `&g_whalUart`. Generic tests should verify the API contract — that functions return the expected error codes, that Set followed by Get produces the correct value, that @@ -41,7 +43,7 @@ Create `tests//test_.c`: static void Test_Foo_BasicOperation(void) { - WHAL_ASSERT_EQ(whal_Foo_Init(&g_whalFoo), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Foo_Init(BOARD_FOO_DEV), WHAL_SUCCESS); } void whal_Test_Foo(void) @@ -79,7 +81,9 @@ Create `tests//test__.c`: static void Test_Foo_SomeRegister(void) { size_t val = 0; - whal_Reg_Get(g_whalFoo.base, REG_OFFSET, MASK, POS, &val); + /* Read the register block base from the platform's singleton in board.h. + * For vtable-dispatched drivers, use BOARD_FOO_DEV->base instead. */ + whal_Reg_Get(whal__Foo_Dev.base, REG_OFFSET, MASK, POS, &val); WHAL_ASSERT_EQ(val, EXPECTED); } diff --git a/docs/adding_an_example.md b/docs/adding_an_example.md index 8dc7827..447042f 100644 --- a/docs/adding_an_example.md +++ b/docs/adding_an_example.md @@ -26,7 +26,9 @@ void main(void) if (Board_Init() != WHAL_SUCCESS) goto loop; - /* Application code using g_whal* peripherals from board.h */ + /* Application code using the BOARD__DEV macros from board.h */ + whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 1); + whal_Uart_Send(BOARD_UART_DEV, "Hello!\r\n", 8); loop: while (1); @@ -35,9 +37,13 @@ loop: Key points: - Include `wolfHAL/wolfHAL.h` for the wolfHAL API -- Include `board.h` for peripheral instances and board constants +- Include `board.h` for peripheral device macros and board constants - Call `Board_Init()` before using any peripherals -- Use the global peripheral instances (e.g., `g_whalGpio`, `g_whalUart`) +- Use the `BOARD__DEV` macros (e.g., `BOARD_GPIO_DEV`, + `BOARD_UART_DEV`) for the device handle. Each board defines these to + resolve to `WHAL_SINGLETON` for single-instance drivers or to + `&g_whal` for vtable-dispatched drivers, so the same application + source works across boards that wire the peripheral differently. - Use board constants (e.g., `BOARD_LED_PIN`) for portability across boards ### Makefile diff --git a/docs/getting_started.md b/docs/getting_started.md index 436fa6b..9b749e0 100644 --- a/docs/getting_started.md +++ b/docs/getting_started.md @@ -44,16 +44,19 @@ src/flash/flash.c 3. Compile the platform-specific driver sources for your target: ``` -src/clock/_clock.c src/gpio/_gpio.c src/uart/_uart.c -src/uart/_flash.c +src/flash/_flash.c ... ``` You only need to include the modules and platform drivers your project actually uses. +Clock drivers are header-only — every `whal___*` helper in +`wolfHAL/clock/_*.h` is a `static inline` function, so there is no +matching `.c` file to compile. + ## The Device Model wolfHAL has three driver categories — platform, peripheral, and board-level @@ -84,6 +87,7 @@ so you only need to fill in the `cfg`: ```c #include +/* In board.c (vtable-dispatched driver): */ whal_Gpio g_whalGpio = { .base = WHAL_STM32WB55_GPIO_BASE, .driver = WHAL_STM32WB55_GPIO_DRIVER, @@ -92,7 +96,44 @@ whal_Gpio g_whalGpio = { ``` When direct API mapping is active for a device type, the `.driver` field is -omitted since calls go directly to the driver implementation. +omitted since calls go directly to the driver implementation. When the driver +is wired as single-instance, the device lives in `board.h` as a `static const` +singleton rather than a global in `board.c` — see the next section. + +#### Single-instance platform drivers + +Some platform drivers are wired as **single-instance**: rather than reading +`.base` and `.cfg` from a handle the caller passes in, the driver reads +directly from a named `static const` singleton declared in `board.h`. The +device handle parameter becomes a formal-only argument — the board passes +`WHAL_SINGLETON` (defined as `((void *)0)`) to make that intent explicit. + +There are two flavors: + +- **Unconditional** — the driver always reads from its singleton. Used + for driver types where every supported chip exposes a single instance, + so the pointer-based path would never get exercised. +- **Conditional** — gated on `WHAL_CFG___SINGLE_INSTANCE`. + Used for driver types where chips commonly have more than one instance + (UART, SPI, I2C, DMA, etc.). The default build keeps the pointer-based + path; boards opt in per driver via the macro when they only use one + instance. + +For an unconditional single-instance driver, the board provides a +singleton in `board.h` (a `static const` so each translation unit gets its +own copy that the linker can fold via `--gc-sections`): + +```c +/* board.h */ +static const whal_Rng whal_Stm32wb_Rng_Dev = { + .base = WHAL_STM32WB55_RNG_BASE, + .cfg = (void *)&(const whal_Stm32wb_Rng_Cfg){ .timeout = &g_whalTimeout }, +}; +``` + +Aliased drivers (where one chip's driver re-exports another's) reuse the +upstream singleton through a `#define` in the alias header — see +`wolfHAL/watchdog/stm32n6_iwdg.h` for an example. ### Peripheral drivers @@ -105,7 +146,7 @@ chip-specific addressing inside its cfg: whal_Flash g_whalSpiFlash = { .driver = WHAL_SPI_NOR_W25Q64_FLASH_DRIVER, .cfg = &(whal_SpiNor_W25q64_Cfg) { - .spi = &g_whalSpi, /* underlying bus driver */ + .spi = BOARD_SPI_DEV, /* underlying bus driver, per board.h */ .csPin = SPI_FLASH_CS_PIN, /* ...chip-specific fields... */ }, @@ -141,13 +182,16 @@ it needs. For example, a GPIO driver takes a pin configuration table; the platform usually provides a `WHAL__GPIO_PIN(...)` macro to populate each entry compactly: +For GPIO (a single-instance driver — see above), the device lives in +`board.h` as a `static const` singleton: + ```c -whal_Gpio g_whalGpio = { +static const whal_Gpio whal_Stm32wb_Gpio_Dev = { .base = WHAL_STM32WB55_GPIO_BASE, /* .driver: direct API mapping */ - .cfg = &(whal_Stm32wb_Gpio_Cfg) { - .pinCfg = (whal_Stm32wb_Gpio_PinCfg[PIN_COUNT]) { + .cfg = (void *)&(const whal_Stm32wb_Gpio_Cfg){ + .pinCfg = (const whal_Stm32wb_Gpio_PinCfg[PIN_COUNT]){ [LED_PIN] = WHAL_STM32WB_GPIO_PIN( WHAL_STM32WB_GPIO_PORT_B, 5, WHAL_STM32WB_GPIO_MODE_OUT, WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_LOW, @@ -159,7 +203,9 @@ whal_Gpio g_whalGpio = { ``` A UART driver typically takes a pre-computed baud rate register value and a -timeout: +timeout. For boards that opt the UART into single-instance, the device +goes alongside GPIO in `board.h`; otherwise it stays in `board.c` as a +regular `g_whal` global: ```c whal_Uart g_whalUart = { @@ -213,37 +259,37 @@ whal_Error Board_Init(void) whal_Error err; /* Bring up clocks (chip-specific helpers, called in order) */ - err = whal_Myplatform_Clock_EnableOsc(&g_whalClock, + err = whal_Myplatform_Clock_EnableOsc(BOARD_CLOCK_DEV, &(whal_Myplatform_Clock_OscCfg){WHAL_MYPLATFORM_CLOCK_OSC0_CFG}); if (err) return err; - err = whal_Myplatform_Clock_SetSysClock(&g_whalClock, + err = whal_Myplatform_Clock_SetSysClock(BOARD_CLOCK_DEV, WHAL_MYPLATFORM_CLOCK_SYSCLK_SRC_OSC0); if (err) return err; /* Enable peripheral clocks */ for (size_t i = 0; i < PERIPH_CLK_COUNT; i++) { - err = whal_Myplatform_Clock_EnablePeriphClk(&g_whalClock, + err = whal_Myplatform_Clock_EnablePeriphClk(BOARD_CLOCK_DEV, &g_periphClks[i]); if (err) return err; } - /* Initialize peripherals */ - err = whal_Gpio_Init(&g_whalGpio); + /* Initialize peripherals through the board's BOARD__DEV macros */ + err = whal_Gpio_Init(BOARD_GPIO_DEV); if (err) return err; - err = whal_Uart_Init(&g_whalUart); + err = whal_Uart_Init(BOARD_UART_DEV); if (err) return err; - err = whal_Timer_Init(&g_whalTimer); + err = whal_Timer_Init(BOARD_TIMER_DEV); if (err) return err; - err = whal_Timer_Start(&g_whalTimer); + err = whal_Timer_Start(BOARD_TIMER_DEV); if (err) return err; @@ -256,7 +302,11 @@ including platform-specific steps. ## Using the API -After initialization, use the wolfHAL API to interact with peripherals: +After initialization, use the wolfHAL API to interact with peripherals. +Reach each device through the `BOARD__DEV` macro that `board.h` +provides — the board picks whether that resolves to `WHAL_SINGLETON` (for +single-instance drivers) or `&g_whal` (for vtable-dispatched drivers), +so the application source stays portable. ```c #include @@ -268,11 +318,11 @@ void main(void) while (1); while (1) { - whal_Gpio_Set(&g_whalGpio, BOARD_LED_PIN, 1); - whal_Uart_Send(&g_whalUart, "Hello!\r\n", 8); + whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 1); + whal_Uart_Send(BOARD_UART_DEV, "Hello!\r\n", 8); Board_WaitMs(1000); - whal_Gpio_Set(&g_whalGpio, BOARD_LED_PIN, 0); + whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 0); Board_WaitMs(1000); } } @@ -331,21 +381,23 @@ Only one mapping flag may be active per device type per build. ### Custom Vtables The platform drivers provide a pre-built vtable with all operations populated. -If you only use a subset of a driver's functionality, you can define your own -vtable that only includes the functions you need: +For vtable-dispatched devices, if you only use a subset of a driver's +functionality, you can define your own vtable that only includes the functions +you need: ```c -static const whal_GpioDriver myGpioDriver = { - .Init = whal_Stm32wb_Gpio_Init, - .Deinit = whal_Stm32wb_Gpio_Deinit, - .Set = whal_Stm32wb_Gpio_Set, - /* Get left as NULL — calls return WHAL_ENOTSUP, saves pulling in that code */ +static const whal_SpiDriver mySpiDriver = { + .Init = whal_Stm32wb_Spi_Init, + .Deinit = whal_Stm32wb_Spi_Deinit, + .StartCom = whal_Stm32wb_Spi_StartCom, + .EndCom = whal_Stm32wb_Spi_EndCom, + .SendRecv = whal_Stm32wb_Spi_SendRecv, }; -whal_Gpio g_whalGpio = { - .base = 0x48000000, - .driver = &myGpioDriver, - .cfg = &gpioConfig, +whal_Spi g_whalSpi = { + .base = WHAL_STM32WB55_SPI1_BASE, + .driver = &mySpiDriver, + .cfg = &spiConfig, }; ``` @@ -353,20 +405,54 @@ With link-time optimization (`-flto`) or garbage collection (`-ffunction-section + `-Wl,--gc-sections`), any driver functions not referenced through the vtable will be stripped from the final binary. +Single-instance drivers (see above) are not vtable-dispatched in their +single-instance form — the driver body reads its `.base` and `.cfg` straight +out of the named singleton in `board.h`. The "custom vtable" knob does not +apply; any unreferenced entry point is dropped by `--gc-sections`. + ### Calling Driver Functions Directly -For maximum control, you can skip the vtable entirely and call the underlying -platform driver functions directly: +For maximum control on a vtable-dispatched driver, you can skip the vtable +and call the underlying platform driver functions directly: ```c -#include +#include -whal_Stm32wb_Gpio_Init(&g_whalGpio); -whal_Stm32wb_Gpio_Set(&g_whalGpio, BOARD_LED_PIN, 1); +whal_Stm32wb_Uart_Init(&g_whalUart); +whal_Stm32wb_Uart_Send(&g_whalUart, "hi\r\n", 4); ``` -This eliminates the vtable indirection and lets the compiler inline or optimize -the calls more aggressively. +This eliminates the vtable indirection and lets the compiler inline or +optimize the calls more aggressively. + +Single-instance drivers fall into two cases depending on whether direct API +mapping is also active for them: + +- **Single-instance + direct API mapping** (the common case for RNG, + watchdog, NVIC, etc.). The chip-specific functions are renamed to the + generic API names, the driver body reads from the singleton in + `board.h`, and the board does not declare a `g_whal` global at all. + Call sites pass `WHAL_SINGLETON`: + + ```c + whal_Stm32wb_Gpio_Set(WHAL_SINGLETON, BOARD_LED_PIN, 1); + ``` + +- **Single-instance without direct API mapping** (used when several + drivers of the same type must coexist on one board — for example + on-chip flash plus an external SPI-NOR flash). The chip's `_Dev` + singleton in `board.h` still holds the const cfg, but the board also + defines a minimal dispatcher stub `g_whal` in `board.c` carrying + only `.driver`, so generic API calls can vtable-dispatch through it. + Call sites pass `&g_whal`: + + ```c + whal_Stm32wb_Flash_Read(&g_whalFlash, addr, buf, sz); + ``` + +The `BOARD__DEV` macros described above abstract this distinction +away from application code — boards point each macro at whichever shape +they wired. Register-level drivers do not call other drivers internally, so this works without any caveats. Peripheral drivers (e.g., SPI flash) still call their diff --git a/docs/writing_a_driver.md b/docs/writing_a_driver.md index b1673d4..4305eb2 100644 --- a/docs/writing_a_driver.md +++ b/docs/writing_a_driver.md @@ -66,9 +66,11 @@ For a peripheral driver implementing device type `foo` for chip `mychip`: For a board-level driver implementing device type `foo` on platform `myplatform`: - `wolfHAL/foo/myplatform_foo.h` — types, enums, descriptor macros, and - chip-specific helper declarations (no driver extern, no `_DRIVER` macro) -- `src/foo/myplatform_foo.c` — chip-specific helper implementations (no - vtable, no `DIRECT_API_MAPPING` block) + chip-specific helper declarations or definitions (no driver extern, no + `_DRIVER` macro). Clock drivers in particular are header-only — every + `whal___*` helper is defined as a `static inline` directly + in the header. Other board-level drivers (power, supply) may still keep + their definitions in `src/foo/myplatform_foo.c`. ### Driver Vtable @@ -136,6 +138,57 @@ static whal_Error whal_Myplatform_Foo_Init(whal_Foo *fooDev) } ``` +#### Single-instance drivers + +For peripherals that a board only ever uses one instance of, the driver +does not need to take the device handle at all. The convention is +**single-instance**: the driver source `#include`s `board.h` and reads +its `.base` and `.cfg` directly from a `static const whal_` +singleton that the board declares there. The function signature still +takes the generic handle so it can sit behind the generic vtable, but +the body ignores it: + +```c +#include "board.h" /* provides whal_Myplatform_Foo_Dev singleton */ + +whal_Error whal_Myplatform_Foo_Init(whal_Foo *fooDev) +{ + const whal_Myplatform_Foo_Cfg *cfg = + (const whal_Myplatform_Foo_Cfg *)whal_Myplatform_Foo_Dev.cfg; + size_t base = whal_Myplatform_Foo_Dev.base; + (void)fooDev; + /* ... */ +} +``` + +Boards call the entry points with `WHAL_SINGLETON` (defined as +`((void *)0)` in `wolfHAL/wolfHAL.h`) — the sentinel just makes the +intent explicit at the call site. Singletons declared with `static const` +in `board.h` are duplicated into every translation unit that includes the +header, but only the driver TU reads the storage; `--gc-sections` drops +the rest. + +There are two flavors: + +- **Unconditional single-instance.** Used for peripherals where every + supported chip exposes a single instance, so the SI path is the only + path. The driver source `#include`s `board.h` at the top, drops the + handle null-check, and accesses the singleton directly. No `#if` + fences inside the driver body. +- **Conditional single-instance.** Used on driver types where the chip + generally has more than one instance (UART, SPI, I2C, DMA, etc.), so + boards must opt in per peripheral with + `-DWHAL_CFG___SINGLE_INSTANCE`. The driver body is + bifurcated with `#if defined(...SINGLE_INSTANCE...) / #else`: the SI + branch reads the singleton, the `#else` branch is the original + pointer-based path. See `src/uart/stm32wb_uart.c` for the canonical + shape. + +Single-instance is independent of direct API mapping (described below). +A driver may be single-instance and vtable-dispatched, single-instance +and directly mapped, or pointer-based and either. The two knobs do not +imply each other. + ### No Cross-Driver Calls Platform drivers should only touch their own registers. The board handles all @@ -304,7 +357,7 @@ for the alias platform: typedef whal_Stm32wb_Gpio_Cfg whal_Stm32h5_Gpio_Cfg; typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32h5_Gpio_PinCfg; -#ifndef WHAL_CFG_GPIO_API_MAPPING_STM32H5 +#ifndef WHAL_CFG_STM32H5_GPIO_DIRECT_API_MAPPING #define whal_Stm32h5_Gpio_Driver whal_Stm32wb_Gpio_Driver #define whal_Stm32h5_Gpio_Init whal_Stm32wb_Gpio_Init #define whal_Stm32h5_Gpio_Deinit whal_Stm32wb_Gpio_Deinit @@ -323,6 +376,23 @@ Use `typedef` for types (gives proper type-checking and debugger visibility) and `#define` for the driver instance and functions (which are values, not types). +For single-instance drivers, the alias header must also bridge the +singleton name so the upstream driver body (which reads +`whal_Stm32wb__Dev`) finds the storage declared under the alias +platform's name in the consuming board's `board.h`. Add one more +`#define`: + +```c +#define whal_Stm32h5_Gpio_Dev whal_Stm32wb_Gpio_Dev +``` + +The board declares its singleton under `whal___Dev` so +that the rest of the board source talks about its own platform; the +`#define` lets the upstream driver source keep reading from its +canonical name. A small number of singletons are inherently +platform-agnostic and keep neutral names everywhere +(`whal_Nvic_Dev`, `whal_SysTick_Dev`, `whal_Lan8742a_Dev`). + #### Source The source file includes the original implementation directly: @@ -443,9 +513,11 @@ naming convention. ### Reference implementation -`wolfHAL/clock/stm32wb_rcc.h` and `src/clock/stm32wb_rcc.c` are the -canonical reference. New chip clock drivers should be modeled on its -shape. `wolfHAL/clock/pic32cz_clock.h` shows how the same convention +Clock drivers are header-only — every `whal___*` helper is +defined as a `static inline` in the chip's clock header, and there is no +matching `.c` file under `src/clock/`. `wolfHAL/clock/stm32wb_rcc.h` is +the canonical reference shape; new chip clock drivers should be modeled +on it. `wolfHAL/clock/pic32cz_clock.h` shows how the same convention covers a fundamentally different topology (oscillators + GCLK generators + peripheral channels). @@ -1145,10 +1217,15 @@ hardware retains all necessary context internally. ### API Usage +Applications reach each algorithm through its `BOARD__DEV` macro +(`BOARD_AES_GCM_DEV`, `BOARD_SHA256_DEV`, etc.). Boards point those at +`WHAL_SINGLETON` for the common single-instance case or at a +`&g_whalAesGcm` pointer if they have kept the device in `board.c`. + One-shot: ```c -whal_AesGcm_Oneshot(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, +whal_AesGcm_Oneshot(BOARD_AES_GCM_DEV, WHAL_CRYPTO_ENCRYPT, key, 32, iv, 12, aad, aadSz, pt, ct, ptSz, tag, 16); ``` @@ -1156,28 +1233,28 @@ whal_AesGcm_Oneshot(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, Streaming (AEAD): ```c -whal_AesGcm_Start(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, +whal_AesGcm_Start(BOARD_AES_GCM_DEV, WHAL_CRYPTO_ENCRYPT, key, 32, iv, 12, aad, aadSz); -whal_AesGcm_Process(&g_whalAesGcm, chunk1, out1, chunk1Sz); -whal_AesGcm_Process(&g_whalAesGcm, chunk2, out2, chunk2Sz); -whal_AesGcm_Finalize(&g_whalAesGcm, tag, 16); +whal_AesGcm_Process(BOARD_AES_GCM_DEV, chunk1, out1, chunk1Sz); +whal_AesGcm_Process(BOARD_AES_GCM_DEV, chunk2, out2, chunk2Sz); +whal_AesGcm_Finalize(BOARD_AES_GCM_DEV, tag, 16); ``` Streaming (hash): ```c -whal_Sha256_Start(&g_whalSha256); -whal_Sha256_Process(&g_whalSha256, chunk1, chunk1Sz); -whal_Sha256_Process(&g_whalSha256, chunk2, chunk2Sz); -whal_Sha256_Finalize(&g_whalSha256, digest, 32); +whal_Sha256_Start(BOARD_SHA256_DEV); +whal_Sha256_Process(BOARD_SHA256_DEV, chunk1, chunk1Sz); +whal_Sha256_Process(BOARD_SHA256_DEV, chunk2, chunk2Sz); +whal_Sha256_Finalize(BOARD_SHA256_DEV, digest, 32); ``` Streaming (block cipher): ```c -whal_AesCbc_Start(&g_whalAesCbc, WHAL_CRYPTO_ENCRYPT, key, 32, iv); -whal_AesCbc_Process(&g_whalAesCbc, block1, out1, 16); -whal_AesCbc_Process(&g_whalAesCbc, block2, out2, 16); +whal_AesCbc_Start(BOARD_AES_CBC_DEV, WHAL_CRYPTO_ENCRYPT, key, 32, iv); +whal_AesCbc_Process(BOARD_AES_CBC_DEV, block1, out1, 16); +whal_AesCbc_Process(BOARD_AES_CBC_DEV, block2, out2, 16); ``` ### Writing a Crypto Driver @@ -1371,6 +1448,17 @@ When direct API mapping is active for an algorithm, the `.driver` field is omitted from that per-algorithm device. When Init/Deinit mapping is active, the `.driver` field is omitted from the `whal_Crypto` device. +Crypto drivers that are single-instance (most on-MCU AES/hash blocks +qualify, since the chip exposes one of each) follow the pattern in the +"Single-instance drivers" section above: the board declares the +`whal_Crypto` and each per-algorithm device as `static const +whal___Dev` in `board.h` rather than as `g_whal` in +`board.c`, the per-algorithm device's `.crypto` points at the cast +address of the `whal_Crypto` singleton, and any streaming state is +declared as a `static` immediately above the singleton that uses it. +The board's `BOARD__DEV` macro is then `WHAL_SINGLETON`. See +`boards/stm32wb55xx_nucleo/board.h` for a worked example. + ### Reference Implementations - **AES (ECB/CBC/CTR/GCM/GMAC/CCM)**: `wolfHAL/crypto/stm32wb_aes.h` and diff --git a/examples/blinky/main.c b/examples/blinky/main.c index 9f5ab96..49d04ba 100644 --- a/examples/blinky/main.c +++ b/examples/blinky/main.c @@ -8,11 +8,11 @@ void main(void) goto loop; while (1) { - whal_Gpio_Set(WHAL_SINGLETON, BOARD_LED_PIN, 1); - whal_Uart_Send(&g_whalUart, "Blink!\r\n", 8); + whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 1); + whal_Uart_Send(BOARD_UART_DEV, "Blink!\r\n", 8); Board_WaitMs(1000); - whal_Gpio_Set(WHAL_SINGLETON, BOARD_LED_PIN, 0); - whal_Uart_Send(&g_whalUart, "Blink!\r\n", 8); + whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 0); + whal_Uart_Send(BOARD_UART_DEV, "Blink!\r\n", 8); Board_WaitMs(1000); } diff --git a/src/block/sdhc_spi_block.c b/src/block/sdhc_spi_block.c index f6bc80c..0151b57 100644 --- a/src/block/sdhc_spi_block.c +++ b/src/block/sdhc_spi_block.c @@ -1,4 +1,7 @@ #include +#ifdef WHAL_CFG_SDHC_SPI_SINGLE_INSTANCE +#include "board.h" /* provides whal_SdhcSpi_Dev singleton */ +#endif #include #include #include @@ -147,10 +150,15 @@ whal_Error whal_SdhcSpi_Init(whal_Block *blockDev) uint8_t dummy = DUMMY; int i; +#ifdef WHAL_CFG_SDHC_SPI_SINGLE_INSTANCE + cfg = (whal_SdhcSpi_Cfg *)whal_SdhcSpi_Dev.cfg; + (void)blockDev; +#else if (!blockDev || !blockDev->cfg) return WHAL_EINVAL; cfg = (whal_SdhcSpi_Cfg *)blockDev->cfg; +#endif if (!cfg->spiDev || !cfg->spiComCfg || !cfg->gpioDev) return WHAL_EINVAL; @@ -266,10 +274,19 @@ whal_Error whal_SdhcSpi_Init(whal_Block *blockDev) whal_Error whal_SdhcSpi_Deinit(whal_Block *blockDev) { + whal_SdhcSpi_Cfg *cfg; + +#ifdef WHAL_CFG_SDHC_SPI_SINGLE_INSTANCE + cfg = (whal_SdhcSpi_Cfg *)whal_SdhcSpi_Dev.cfg; + (void)blockDev; +#else if (!blockDev || !blockDev->cfg) return WHAL_EINVAL; - SdhcSpi_CsDeassert((whal_SdhcSpi_Cfg *)blockDev->cfg); + cfg = (whal_SdhcSpi_Cfg *)blockDev->cfg; +#endif + + SdhcSpi_CsDeassert(cfg); return WHAL_SUCCESS; } @@ -285,10 +302,18 @@ whal_Error whal_SdhcSpi_Read(whal_Block *blockDev, uint32_t block, uint8_t dummy = DUMMY; uint32_t i; +#ifdef WHAL_CFG_SDHC_SPI_SINGLE_INSTANCE + cfg = (whal_SdhcSpi_Cfg *)whal_SdhcSpi_Dev.cfg; + (void)blockDev; + + if (!data || blockCount == 0) + return WHAL_EINVAL; +#else if (!blockDev || !blockDev->cfg || !data || blockCount == 0) return WHAL_EINVAL; cfg = (whal_SdhcSpi_Cfg *)blockDev->cfg; +#endif err = whal_Spi_StartCom(cfg->spiDev, cfg->spiComCfg); if (err) @@ -355,10 +380,18 @@ whal_Error whal_SdhcSpi_Write(whal_Block *blockDev, uint32_t block, uint8_t dummy = DUMMY; uint32_t i; +#ifdef WHAL_CFG_SDHC_SPI_SINGLE_INSTANCE + cfg = (whal_SdhcSpi_Cfg *)whal_SdhcSpi_Dev.cfg; + (void)blockDev; + + if (!data || blockCount == 0) + return WHAL_EINVAL; +#else if (!blockDev || !blockDev->cfg || !data || blockCount == 0) return WHAL_EINVAL; cfg = (whal_SdhcSpi_Cfg *)blockDev->cfg; +#endif err = whal_Spi_StartCom(cfg->spiDev, cfg->spiComCfg); if (err) @@ -430,10 +463,18 @@ whal_Error whal_SdhcSpi_Erase(whal_Block *blockDev, uint32_t block, uint8_t r1; uint32_t endBlock; +#ifdef WHAL_CFG_SDHC_SPI_SINGLE_INSTANCE + cfg = (whal_SdhcSpi_Cfg *)whal_SdhcSpi_Dev.cfg; + (void)blockDev; + + if (blockCount == 0) + return WHAL_EINVAL; +#else if (!blockDev || !blockDev->cfg || blockCount == 0) return WHAL_EINVAL; cfg = (whal_SdhcSpi_Cfg *)blockDev->cfg; +#endif if (blockCount - 1u > UINT32_MAX - block) return WHAL_EINVAL; diff --git a/src/clock/pic32cz_clock.c b/src/clock/pic32cz_clock.c deleted file mode 100644 index f243931..0000000 --- a/src/clock/pic32cz_clock.c +++ /dev/null @@ -1,176 +0,0 @@ -#include -#include -#include -#include -#include - -/* - * PIC32CZ Clock System Register Map. - * OSCCTRL @ 0x00000, GCLK @ 0x10000, MCLK @ 0x12000. - */ - -#define OSCCTRL 0x00000 - -#define OSCCTRL_PLLxCTRL_REG(pllInst) (0x40 + ((pllInst) * 20)) -#define OSCCTRL_PLLxCTRL_ENABLE_Pos 1 -#define OSCCTRL_PLLxCTRL_ENABLE_Msk (1UL << OSCCTRL_PLLxCTRL_ENABLE_Pos) -#define OSCCTRL_PLLxCTRL_REFSEL_Pos 8 -#define OSCCTRL_PLLxCTRL_REFSEL_Msk (WHAL_BITMASK(3) << OSCCTRL_PLLxCTRL_REFSEL_Pos) -#define OSCCTRL_PLLxCTRL_BWSEL_Pos 11 -#define OSCCTRL_PLLxCTRL_BWSEL_Msk (WHAL_BITMASK(3) << OSCCTRL_PLLxCTRL_BWSEL_Pos) - -#define OSCCTRL_PLLxFBDIV_REG(pllInst) (0x44 + ((pllInst) * 20)) -#define OSCCTRL_PLLxFBDIV_Pos 0 -#define OSCCTRL_PLLxFBDIV_Msk (WHAL_BITMASK(10) << OSCCTRL_PLLxFBDIV_Pos) - -#define OSCCTRL_PLLxREFDIV_REG(pllInst) (0x48 + ((pllInst) * 20)) -#define OSCCTRL_PLLxREFDIV_Pos 0 -#define OSCCTRL_PLLxREFDIV_Msk (WHAL_BITMASK(6) << OSCCTRL_PLLxREFDIV_Pos) - -#define OSCCTRL_PLLxPOSTDIVA_REG(pllInst) (0x4C + ((pllInst) * 20)) - -#define OSCCTRL_STATUS_REG (OSCCTRL + 0x10) -#define OSCCTRL_STATUS_PLLxLOCK_Pos(pllInst) (24 + (pllInst)) -#define OSCCTRL_STATUS_PLLxLOCK_Msk(pllInst) (1UL << OSCCTRL_STATUS_PLLxLOCK_Pos(pllInst)) - -#define GCLK 0x10000 - -#define GCLK_GENCTRLx_REG(gclkInst) ((GCLK + 0x20 + ((gclkInst) * 0x4))) -#define GCLK_GENCTRLx_SRC_Pos 0 -#define GCLK_GENCTRLx_SRC_Msk (WHAL_BITMASK(5) << GCLK_GENCTRLx_SRC_Pos) -#define GCLK_GENCTRLx_GENEN_Pos 8 -#define GCLK_GENCTRLx_GENEN_Msk (1UL << GCLK_GENCTRLx_GENEN_Pos) -#define GCLK_GENCTRLx_DIV_Pos 16 -#define GCLK_GENCTRLx_DIV_Msk (WHAL_BITMASK(16) << GCLK_GENCTRLx_DIV_Pos) - -#define GCLK_PCHCTRLx_REG(periphChannel) (GCLK + 0x80 + ((periphChannel) * 0x4)) -#define GCLK_PCHCTRLx_GEN_Pos 0 -#define GCLK_PCHCTRLx_GEN_Msk (WHAL_BITMASK(4) << GCLK_PCHCTRLx_GEN_Pos) -#define GCLK_PCHCTRLx_CHEN_Pos 6 -#define GCLK_PCHCTRLx_CHEN_Msk (1UL << GCLK_PCHCTRLx_CHEN_Pos) - -#define GCLK_SYNCBUSY_REG (GCLK + 0x04) -#define GCLK_SYNCBUSY_GENCTRLx_Pos(gclkInst) (2 + (gclkInst)) -#define GCLK_SYNCBUSY_GENCTRLx_Msk(gclkInst) (1UL << GCLK_SYNCBUSY_GENCTRLx_Pos(gclkInst)) - -#define MCLK 0x12000 -#define MCLK_INTFLAG_REG (MCLK + 0x08) -#define MCLK_INTFLAG_CKRDY_Pos 0 -#define MCLK_INTFLAG_CKRDY_Msk (1UL << MCLK_INTFLAG_CKRDY_Pos) -#define MCLK_DIV1_REG (MCLK + 0x10) -#define MCLK_DIV1_Pos 0 -#define MCLK_DIV1_Msk (WHAL_BITMASK(8) << MCLK_DIV1_Pos) -#define MCLK_CLKxMSK_REG(enableInst) (MCLK + 0x3C + ((enableInst) * 0x4)) - -whal_Error whal_Pic32cz_Clock_EnablePll(whal_Clock *clkDev, - const whal_Pic32cz_Clock_PllCfg *cfg) -{ - size_t status; - uint8_t i; - size_t pllCtrlReg, pllFbdivReg, pllRefdivReg, pllPostdivaReg; - - if (!clkDev || !cfg) - return WHAL_EINVAL; - - pllCtrlReg = OSCCTRL_PLLxCTRL_REG(cfg->pllInst); - pllFbdivReg = OSCCTRL_PLLxFBDIV_REG(cfg->pllInst); - pllRefdivReg = OSCCTRL_PLLxREFDIV_REG(cfg->pllInst); - pllPostdivaReg = OSCCTRL_PLLxPOSTDIVA_REG(cfg->pllInst); - - whal_Reg_Update(clkDev->base, pllFbdivReg, OSCCTRL_PLLxFBDIV_Msk, - whal_SetBits(OSCCTRL_PLLxFBDIV_Msk, OSCCTRL_PLLxFBDIV_Pos, - cfg->fbDiv)); - whal_Reg_Update(clkDev->base, pllRefdivReg, OSCCTRL_PLLxREFDIV_Msk, - whal_SetBits(OSCCTRL_PLLxREFDIV_Msk, OSCCTRL_PLLxREFDIV_Pos, - cfg->refDiv)); - for (i = 0; i < cfg->outCfgCount; i++) { - const whal_Pic32cz_Clock_PllOutCfg *out = &cfg->outCfg[i]; - whal_Reg_Update(clkDev->base, pllPostdivaReg, - out->outEnMask | out->postDivMask, - whal_SetBits(out->postDivMask, out->postDivPos, out->postDiv) | - whal_SetBits(out->outEnMask, out->outEnPos, 1)); - } - - whal_Reg_Update(clkDev->base, pllCtrlReg, - OSCCTRL_PLLxCTRL_ENABLE_Msk | - OSCCTRL_PLLxCTRL_REFSEL_Msk | - OSCCTRL_PLLxCTRL_BWSEL_Msk, - OSCCTRL_PLLxCTRL_ENABLE_Msk | - whal_SetBits(OSCCTRL_PLLxCTRL_REFSEL_Msk, OSCCTRL_PLLxCTRL_REFSEL_Pos, cfg->refSel) | - whal_SetBits(OSCCTRL_PLLxCTRL_BWSEL_Msk, OSCCTRL_PLLxCTRL_BWSEL_Pos, cfg->bwSel)); - - do { - whal_Reg_Get(clkDev->base, OSCCTRL_STATUS_REG, - OSCCTRL_STATUS_PLLxLOCK_Msk(cfg->pllInst), - OSCCTRL_STATUS_PLLxLOCK_Pos(cfg->pllInst), &status); - } while (!status); - return WHAL_SUCCESS; -} - -whal_Error whal_Pic32cz_Clock_EnableGclkGen(whal_Clock *clkDev, - const whal_Pic32cz_Clock_GenCfg *cfg) -{ - size_t status; - - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, GCLK_GENCTRLx_REG(cfg->gen), - GCLK_GENCTRLx_SRC_Msk | GCLK_GENCTRLx_GENEN_Msk | - GCLK_GENCTRLx_DIV_Msk, - whal_SetBits(GCLK_GENCTRLx_SRC_Msk, GCLK_GENCTRLx_SRC_Pos, cfg->genSrc) | - GCLK_GENCTRLx_GENEN_Msk | - whal_SetBits(GCLK_GENCTRLx_DIV_Msk, GCLK_GENCTRLx_DIV_Pos, cfg->genDiv)); - do { - whal_Reg_Get(clkDev->base, GCLK_SYNCBUSY_REG, - GCLK_SYNCBUSY_GENCTRLx_Msk(cfg->gen), - GCLK_SYNCBUSY_GENCTRLx_Pos(cfg->gen), &status); - } while (status); - return WHAL_SUCCESS; -} - -whal_Error whal_Pic32cz_Clock_SetMclkDiv(whal_Clock *clkDev, uint8_t div) -{ - size_t status; - - if (!clkDev) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, MCLK_DIV1_REG, MCLK_DIV1_Msk, - whal_SetBits(MCLK_DIV1_Msk, MCLK_DIV1_Pos, div)); - do { - whal_Reg_Get(clkDev->base, MCLK_INTFLAG_REG, - MCLK_INTFLAG_CKRDY_Msk, MCLK_INTFLAG_CKRDY_Pos, &status); - } while (!status); - return WHAL_SUCCESS; -} - -whal_Error whal_Pic32cz_Clock_EnablePeriphClk(whal_Clock *clkDev, - const whal_Pic32cz_Clock_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, GCLK_PCHCTRLx_REG(clk->gclkPeriphChannel), - GCLK_PCHCTRLx_GEN_Msk | GCLK_PCHCTRLx_CHEN_Msk, - whal_SetBits(GCLK_PCHCTRLx_GEN_Msk, GCLK_PCHCTRLx_GEN_Pos, clk->gclkPeriphSrc) | - GCLK_PCHCTRLx_CHEN_Msk); - whal_Reg_Update(clkDev->base, MCLK_CLKxMSK_REG(clk->mclkEnableInst), - clk->mclkEnableMask, - whal_SetBits(clk->mclkEnableMask, clk->mclkEnablePos, 1)); - return WHAL_SUCCESS; -} - -whal_Error whal_Pic32cz_Clock_DisablePeriphClk(whal_Clock *clkDev, - const whal_Pic32cz_Clock_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, MCLK_CLKxMSK_REG(clk->mclkEnableInst), - clk->mclkEnableMask, - whal_SetBits(clk->mclkEnableMask, clk->mclkEnablePos, 0)); - whal_Reg_Update(clkDev->base, GCLK_PCHCTRLx_REG(clk->gclkPeriphChannel), - GCLK_PCHCTRLx_CHEN_Msk, 0); - return WHAL_SUCCESS; -} diff --git a/src/clock/stm32c0_rcc.c b/src/clock/stm32c0_rcc.c deleted file mode 100644 index 89e4c47..0000000 --- a/src/clock/stm32c0_rcc.c +++ /dev/null @@ -1,83 +0,0 @@ -#include -#include -#include -#include -#include - -/* - * STM32C0 RCC Register Definitions - */ - -/* Clock Control Register */ -#define RCC_CR_REG 0x000 -#define RCC_CR_HSION_Pos 8 -#define RCC_CR_HSION_Msk (1UL << RCC_CR_HSION_Pos) -#define RCC_CR_HSIRDY_Pos 10 -#define RCC_CR_HSIRDY_Msk (1UL << RCC_CR_HSIRDY_Pos) -#define RCC_CR_HSIDIV_Pos 11 -#define RCC_CR_HSIDIV_Msk (WHAL_BITMASK(3) << RCC_CR_HSIDIV_Pos) - -/* Clock Configuration Register */ -#define RCC_CFGR_REG 0x008 -#define RCC_CFGR_SW_Pos 0 -#define RCC_CFGR_SW_Msk (WHAL_BITMASK(3) << RCC_CFGR_SW_Pos) -#define RCC_CFGR_SWS_Pos 3 -#define RCC_CFGR_SWS_Msk (WHAL_BITMASK(3) << RCC_CFGR_SWS_Pos) - -whal_Error whal_Stm32c0_Rcc_EnableHsi(whal_Clock *clkDev, - whal_Stm32c0_Rcc_HsiDiv hsidiv) -{ - size_t rdy; - - if (!clkDev) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_HSION_Msk, - RCC_CR_HSION_Msk); - do { - whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_HSIRDY_Msk, - RCC_CR_HSIRDY_Pos, &rdy); - } while (!rdy); - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_HSIDIV_Msk, - whal_SetBits(RCC_CR_HSIDIV_Msk, RCC_CR_HSIDIV_Pos, hsidiv)); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32c0_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32c0_Rcc_SysClockSrc src) -{ - size_t sws; - - if (!clkDev) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, - whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, src)); - do { - whal_Reg_Get(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, - RCC_CFGR_SWS_Pos, &sws); - } while (sws != (size_t)src); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32c0_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32c0_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32c0_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32c0_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); - return WHAL_SUCCESS; -} diff --git a/src/clock/stm32f0_rcc.c b/src/clock/stm32f0_rcc.c deleted file mode 100644 index cbf2371..0000000 --- a/src/clock/stm32f0_rcc.c +++ /dev/null @@ -1,131 +0,0 @@ -#include -#include -#include -#include -#include - -#define RCC_CR_REG 0x00 -#define RCC_CR_PLLON_Msk (1UL << 24) -#define RCC_CR_PLLRDY_Msk (1UL << 25) -#define RCC_CR_PLLRDY_Pos 25 - -#define RCC_CFGR_REG 0x04 -#define RCC_CFGR_SW_Pos 0 -#define RCC_CFGR_SW_Msk (WHAL_BITMASK(2) << RCC_CFGR_SW_Pos) -#define RCC_CFGR_SWS_Pos 2 -#define RCC_CFGR_SWS_Msk (WHAL_BITMASK(2) << RCC_CFGR_SWS_Pos) -#define RCC_CFGR_PLLSRC_Pos 16 -#define RCC_CFGR_PLLSRC_Msk (1UL << RCC_CFGR_PLLSRC_Pos) -#define RCC_CFGR_PLLMUL_Pos 18 -#define RCC_CFGR_PLLMUL_Msk (WHAL_BITMASK(4) << RCC_CFGR_PLLMUL_Pos) - -#define RCC_CFGR2_REG 0x2C -#define RCC_CFGR2_PREDIV_Pos 0 -#define RCC_CFGR2_PREDIV_Msk (WHAL_BITMASK(4) << RCC_CFGR2_PREDIV_Pos) - -whal_Error whal_Stm32f0_Rcc_EnableOsc(whal_Clock *clkDev, - const whal_Stm32f0_Rcc_OscCfg *cfg) -{ - size_t rdy; - - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); - do { - whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, - cfg->rdyPos, &rdy); - } while (!rdy); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f0_Rcc_DisableOsc(whal_Clock *clkDev, - const whal_Stm32f0_Rcc_OscCfg *cfg) -{ - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f0_Rcc_EnablePll(whal_Clock *clkDev, - const whal_Stm32f0_Rcc_PllCfg *cfg) -{ - size_t rdy; - uint32_t pllsrc; - - if (!clkDev || !cfg || - cfg->prediv < 1 || cfg->prediv > 16 || - cfg->pllmul < 2 || cfg->pllmul > 16) - return WHAL_EINVAL; - - /* Disable PLL before reconfiguring. */ - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); - - whal_Reg_Update(clkDev->base, RCC_CFGR2_REG, RCC_CFGR2_PREDIV_Msk, - whal_SetBits(RCC_CFGR2_PREDIV_Msk, RCC_CFGR2_PREDIV_Pos, - cfg->prediv - 1)); - whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_PLLMUL_Msk, - whal_SetBits(RCC_CFGR_PLLMUL_Msk, RCC_CFGR_PLLMUL_Pos, - cfg->pllmul - 2)); - - pllsrc = (cfg->clkSrc == WHAL_STM32F0_RCC_PLLSRC_HSE_PREDIV || - cfg->clkSrc == WHAL_STM32F0_RCC_PLLSRC_HSI48_PREDIV) ? 1 : 0; - whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_PLLSRC_Msk, - whal_SetBits(RCC_CFGR_PLLSRC_Msk, RCC_CFGR_PLLSRC_Pos, - pllsrc)); - - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, - RCC_CR_PLLON_Msk); - do { - whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, - RCC_CR_PLLRDY_Pos, &rdy); - } while (!rdy); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f0_Rcc_DisablePll(whal_Clock *clkDev) -{ - if (!clkDev) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f0_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32f0_Rcc_SysClockSrc src) -{ - size_t sws; - - if (!clkDev) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, - whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, src)); - do { - whal_Reg_Get(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, - RCC_CFGR_SWS_Pos, &sws); - } while (sws != (size_t)src); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f0_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32f0_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f0_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32f0_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); - return WHAL_SUCCESS; -} diff --git a/src/clock/stm32f3_rcc.c b/src/clock/stm32f3_rcc.c deleted file mode 100644 index d4247af..0000000 --- a/src/clock/stm32f3_rcc.c +++ /dev/null @@ -1,146 +0,0 @@ -#include -#include -#include -#include -#include - -#define RCC_CR_REG 0x00 -#define RCC_CR_PLLON_Msk (1UL << 24) -#define RCC_CR_PLLRDY_Msk (1UL << 25) -#define RCC_CR_PLLRDY_Pos 25 - -#define RCC_CFGR_REG 0x04 -#define RCC_CFGR_SW_Pos 0 -#define RCC_CFGR_SW_Msk (WHAL_BITMASK(2) << RCC_CFGR_SW_Pos) -#define RCC_CFGR_SWS_Pos 2 -#define RCC_CFGR_SWS_Msk (WHAL_BITMASK(2) << RCC_CFGR_SWS_Pos) -#define RCC_CFGR_PLLSRC_Pos 16 -#define RCC_CFGR_PLLSRC_Msk (1UL << RCC_CFGR_PLLSRC_Pos) -#define RCC_CFGR_PLLMUL_Pos 18 -#define RCC_CFGR_PLLMUL_Msk (WHAL_BITMASK(4) << RCC_CFGR_PLLMUL_Pos) - -#define RCC_CFGR2_REG 0x2C -#define RCC_CFGR2_PREDIV_Pos 0 -#define RCC_CFGR2_PREDIV_Msk (WHAL_BITMASK(4) << RCC_CFGR2_PREDIV_Pos) - -#define RCC_CFGR3_REG 0x30 -#define RCC_CFGR3_I2C1SW_Pos 4 -#define RCC_CFGR3_I2C1SW_Msk (1UL << RCC_CFGR3_I2C1SW_Pos) - -whal_Error whal_Stm32f3_Rcc_EnableOsc(whal_Clock *clkDev, - const whal_Stm32f3_Rcc_OscCfg *cfg) -{ - size_t rdy; - - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); - do { - whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, - cfg->rdyPos, &rdy); - } while (!rdy); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f3_Rcc_DisableOsc(whal_Clock *clkDev, - const whal_Stm32f3_Rcc_OscCfg *cfg) -{ - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f3_Rcc_EnablePll(whal_Clock *clkDev, - const whal_Stm32f3_Rcc_PllCfg *cfg) -{ - size_t rdy; - uint32_t pllsrc; - - if (!clkDev || !cfg || - cfg->prediv < 1 || cfg->prediv > 16 || - cfg->pllmul < 2 || cfg->pllmul > 16) - return WHAL_EINVAL; - - /* Disable PLL before reconfiguring. */ - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); - - whal_Reg_Update(clkDev->base, RCC_CFGR2_REG, RCC_CFGR2_PREDIV_Msk, - whal_SetBits(RCC_CFGR2_PREDIV_Msk, RCC_CFGR2_PREDIV_Pos, - cfg->prediv - 1)); - whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_PLLMUL_Msk, - whal_SetBits(RCC_CFGR_PLLMUL_Msk, RCC_CFGR_PLLMUL_Pos, - cfg->pllmul - 2)); - - pllsrc = (cfg->clkSrc == WHAL_STM32F3_RCC_PLLSRC_HSE_PREDIV) ? 1 : 0; - whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_PLLSRC_Msk, - whal_SetBits(RCC_CFGR_PLLSRC_Msk, RCC_CFGR_PLLSRC_Pos, - pllsrc)); - - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, - RCC_CR_PLLON_Msk); - do { - whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, - RCC_CR_PLLRDY_Pos, &rdy); - } while (!rdy); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f3_Rcc_DisablePll(whal_Clock *clkDev) -{ - if (!clkDev) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f3_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32f3_Rcc_SysClockSrc src) -{ - size_t sws; - - if (!clkDev) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, - whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, src)); - do { - whal_Reg_Get(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, - RCC_CFGR_SWS_Pos, &sws); - } while (sws != (size_t)src); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f3_Rcc_SetI2c1ClkSrc(whal_Clock *clkDev, - whal_Stm32f3_Rcc_I2c1ClkSrc src) -{ - if (!clkDev) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, RCC_CFGR3_REG, RCC_CFGR3_I2C1SW_Msk, - whal_SetBits(RCC_CFGR3_I2C1SW_Msk, RCC_CFGR3_I2C1SW_Pos, - src)); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f3_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32f3_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f3_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32f3_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); - return WHAL_SUCCESS; -} diff --git a/src/clock/stm32f4_rcc.c b/src/clock/stm32f4_rcc.c deleted file mode 100644 index 84fc352..0000000 --- a/src/clock/stm32f4_rcc.c +++ /dev/null @@ -1,147 +0,0 @@ -#include -#include -#include -#include -#include - -#define RCC_CR_REG 0x000 -#define RCC_CR_PLLON_Msk (1UL << 24) -#define RCC_CR_PLLRDY_Msk (1UL << 25) -#define RCC_CR_PLLRDY_Pos 25 - -#define RCC_PLLCFGR_REG 0x004 -#define RCC_PLLCFGR_PLLM_Pos 0 -#define RCC_PLLCFGR_PLLM_Msk (WHAL_BITMASK(6) << RCC_PLLCFGR_PLLM_Pos) -#define RCC_PLLCFGR_PLLN_Pos 6 -#define RCC_PLLCFGR_PLLN_Msk (WHAL_BITMASK(9) << RCC_PLLCFGR_PLLN_Pos) -#define RCC_PLLCFGR_PLLP_Pos 16 -#define RCC_PLLCFGR_PLLP_Msk (WHAL_BITMASK(2) << RCC_PLLCFGR_PLLP_Pos) -#define RCC_PLLCFGR_PLLSRC_Pos 22 -#define RCC_PLLCFGR_PLLSRC_Msk (1UL << RCC_PLLCFGR_PLLSRC_Pos) -#define RCC_PLLCFGR_PLLQ_Pos 24 -#define RCC_PLLCFGR_PLLQ_Msk (WHAL_BITMASK(4) << RCC_PLLCFGR_PLLQ_Pos) -#define RCC_PLLCFGR_Msk \ - (RCC_PLLCFGR_PLLM_Msk | RCC_PLLCFGR_PLLN_Msk | \ - RCC_PLLCFGR_PLLP_Msk | RCC_PLLCFGR_PLLSRC_Msk | \ - RCC_PLLCFGR_PLLQ_Msk) - -#define RCC_CFGR_REG 0x008 -#define RCC_CFGR_SW_Pos 0 -#define RCC_CFGR_SW_Msk (WHAL_BITMASK(2) << RCC_CFGR_SW_Pos) -#define RCC_CFGR_SWS_Pos 2 -#define RCC_CFGR_SWS_Msk (WHAL_BITMASK(2) << RCC_CFGR_SWS_Pos) -#define RCC_CFGR_PPRE1_Pos 10 -#define RCC_CFGR_PPRE1_Msk (WHAL_BITMASK(3) << RCC_CFGR_PPRE1_Pos) -#define RCC_CFGR_PPRE2_Pos 13 -#define RCC_CFGR_PPRE2_Msk (WHAL_BITMASK(3) << RCC_CFGR_PPRE2_Pos) - -whal_Error whal_Stm32f4_Rcc_EnableOsc(whal_Clock *clkDev, - const whal_Stm32f4_Rcc_OscCfg *cfg) -{ - size_t rdy; - - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); - do { - whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, - cfg->rdyPos, &rdy); - } while (!rdy); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f4_Rcc_DisableOsc(whal_Clock *clkDev, - const whal_Stm32f4_Rcc_OscCfg *cfg) -{ - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f4_Rcc_EnablePll(whal_Clock *clkDev, - const whal_Stm32f4_Rcc_PllCfg *cfg) -{ - size_t rdy; - - if (!clkDev || !cfg) - return WHAL_EINVAL; - - /* Disable PLL before reconfiguring. */ - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); - - whal_Reg_Update(clkDev->base, RCC_PLLCFGR_REG, RCC_PLLCFGR_Msk, - whal_SetBits(RCC_PLLCFGR_PLLM_Msk, RCC_PLLCFGR_PLLM_Pos, cfg->m) | - whal_SetBits(RCC_PLLCFGR_PLLN_Msk, RCC_PLLCFGR_PLLN_Pos, cfg->n) | - whal_SetBits(RCC_PLLCFGR_PLLP_Msk, RCC_PLLCFGR_PLLP_Pos, cfg->p) | - whal_SetBits(RCC_PLLCFGR_PLLSRC_Msk, RCC_PLLCFGR_PLLSRC_Pos, cfg->clkSrc) | - whal_SetBits(RCC_PLLCFGR_PLLQ_Msk, RCC_PLLCFGR_PLLQ_Pos, cfg->q)); - - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, - RCC_CR_PLLON_Msk); - do { - whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, - RCC_CR_PLLRDY_Pos, &rdy); - } while (!rdy); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f4_Rcc_DisablePll(whal_Clock *clkDev) -{ - if (!clkDev) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f4_Rcc_SetBusPrescalers(whal_Clock *clkDev, - const whal_Stm32f4_Rcc_BusCfg *cfg) -{ - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, RCC_CFGR_REG, - RCC_CFGR_PPRE1_Msk | RCC_CFGR_PPRE2_Msk, - whal_SetBits(RCC_CFGR_PPRE1_Msk, RCC_CFGR_PPRE1_Pos, cfg->ppre1) | - whal_SetBits(RCC_CFGR_PPRE2_Msk, RCC_CFGR_PPRE2_Pos, cfg->ppre2)); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f4_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32f4_Rcc_SysClockSrc src) -{ - size_t sws; - - if (!clkDev) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, - whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, src)); - do { - whal_Reg_Get(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, - RCC_CFGR_SWS_Pos, &sws); - } while (sws != (size_t)src); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f4_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32f4_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32f4_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32f4_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); - return WHAL_SUCCESS; -} diff --git a/src/clock/stm32l1_rcc.c b/src/clock/stm32l1_rcc.c deleted file mode 100644 index 904fc93..0000000 --- a/src/clock/stm32l1_rcc.c +++ /dev/null @@ -1,129 +0,0 @@ -#include -#include -#include -#include -#include - -#define RCC_CR_REG 0x00 -#define RCC_CR_PLLON_Msk (1UL << 24) -#define RCC_CR_PLLRDY_Msk (1UL << 25) -#define RCC_CR_PLLRDY_Pos 25 - -#define RCC_CFGR_REG 0x08 -#define RCC_CFGR_SW_Pos 0 -#define RCC_CFGR_SW_Msk (WHAL_BITMASK(2) << RCC_CFGR_SW_Pos) -#define RCC_CFGR_SWS_Pos 2 -#define RCC_CFGR_SWS_Msk (WHAL_BITMASK(2) << RCC_CFGR_SWS_Pos) -#define RCC_CFGR_PLLSRC_Pos 16 -#define RCC_CFGR_PLLSRC_Msk (1UL << RCC_CFGR_PLLSRC_Pos) -#define RCC_CFGR_PLLMUL_Pos 18 -#define RCC_CFGR_PLLMUL_Msk (WHAL_BITMASK(4) << RCC_CFGR_PLLMUL_Pos) -#define RCC_CFGR_PLLDIV_Pos 22 -#define RCC_CFGR_PLLDIV_Msk (WHAL_BITMASK(2) << RCC_CFGR_PLLDIV_Pos) - -whal_Error whal_Stm32l1_Rcc_EnableOsc(whal_Clock *clkDev, - const whal_Stm32l1_Rcc_OscCfg *cfg) -{ - size_t rdy; - - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); - do { - whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, - cfg->rdyPos, &rdy); - } while (!rdy); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32l1_Rcc_DisableOsc(whal_Clock *clkDev, - const whal_Stm32l1_Rcc_OscCfg *cfg) -{ - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32l1_Rcc_EnablePll(whal_Clock *clkDev, - const whal_Stm32l1_Rcc_PllCfg *cfg) -{ - size_t rdy; - uint32_t pllsrc; - - if (!clkDev || !cfg) - return WHAL_EINVAL; - - /* Disable PLL before reconfiguring; wait until it's actually off. */ - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); - do { - whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, - RCC_CR_PLLRDY_Pos, &rdy); - } while (rdy); - - pllsrc = (cfg->clkSrc == WHAL_STM32L1_RCC_PLLSRC_HSE) ? 1 : 0; - whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_PLLSRC_Msk, - whal_SetBits(RCC_CFGR_PLLSRC_Msk, RCC_CFGR_PLLSRC_Pos, - pllsrc)); - whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_PLLMUL_Msk, - whal_SetBits(RCC_CFGR_PLLMUL_Msk, RCC_CFGR_PLLMUL_Pos, - cfg->pllmul)); - whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_PLLDIV_Msk, - whal_SetBits(RCC_CFGR_PLLDIV_Msk, RCC_CFGR_PLLDIV_Pos, - cfg->plldiv)); - - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, - RCC_CR_PLLON_Msk); - do { - whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLLRDY_Msk, - RCC_CR_PLLRDY_Pos, &rdy); - } while (!rdy); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32l1_Rcc_DisablePll(whal_Clock *clkDev) -{ - if (!clkDev) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLLON_Msk, 0); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32l1_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32l1_Rcc_SysClockSrc src) -{ - size_t sws; - - if (!clkDev) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SW_Msk, - whal_SetBits(RCC_CFGR_SW_Msk, RCC_CFGR_SW_Pos, src)); - do { - whal_Reg_Get(clkDev->base, RCC_CFGR_REG, RCC_CFGR_SWS_Msk, - RCC_CFGR_SWS_Pos, &sws); - } while (sws != (size_t)src); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32l1_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32l1_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32l1_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32l1_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); - return WHAL_SUCCESS; -} diff --git a/src/clock/stm32n6_rcc.c b/src/clock/stm32n6_rcc.c deleted file mode 100644 index 15a44e8..0000000 --- a/src/clock/stm32n6_rcc.c +++ /dev/null @@ -1,176 +0,0 @@ -#include -#include -#include -#include -#include - -#define RCC_CR_REG 0x000 -#define RCC_CR_PLL1ON_Msk (1UL << 8) - -#define RCC_SR_REG 0x004 -#define RCC_SR_PLL1RDY_Msk (1UL << 8) -#define RCC_SR_PLL1RDY_Pos 8 - -#define RCC_CFGR1_REG 0x020 -#define RCC_CFGR1_CPUSW_Pos 16 -#define RCC_CFGR1_CPUSW_Msk (3UL << RCC_CFGR1_CPUSW_Pos) -#define RCC_CFGR1_CPUSWS_Pos 20 -#define RCC_CFGR1_CPUSWS_Msk (3UL << RCC_CFGR1_CPUSWS_Pos) -#define RCC_CFGR1_SYSSW_Pos 24 -#define RCC_CFGR1_SYSSW_Msk (3UL << RCC_CFGR1_SYSSW_Pos) -#define RCC_CFGR1_SYSSWS_Pos 28 -#define RCC_CFGR1_SYSSWS_Msk (3UL << RCC_CFGR1_SYSSWS_Pos) - -#define RCC_PLL1CFGR1_REG 0x080 -#define RCC_PLL1CFGR1_PLL1SEL_Pos 28 -#define RCC_PLL1CFGR1_PLL1SEL_Msk (7UL << RCC_PLL1CFGR1_PLL1SEL_Pos) -#define RCC_PLL1CFGR1_PLL1DIVM_Pos 20 -#define RCC_PLL1CFGR1_PLL1DIVM_Msk (0x3FUL << RCC_PLL1CFGR1_PLL1DIVM_Pos) -#define RCC_PLL1CFGR1_PLL1DIVN_Pos 0 -#define RCC_PLL1CFGR1_PLL1DIVN_Msk (0xFFFUL << RCC_PLL1CFGR1_PLL1DIVN_Pos) - -#define RCC_PLL1CFGR3_REG 0x088 -#define RCC_PLL1CFGR3_PLL1PDIVEN_Msk (1UL << 30) -#define RCC_PLL1CFGR3_PLL1PDIV1_Pos 27 -#define RCC_PLL1CFGR3_PLL1PDIV1_Msk (7UL << RCC_PLL1CFGR3_PLL1PDIV1_Pos) -#define RCC_PLL1CFGR3_PLL1PDIV2_Pos 24 -#define RCC_PLL1CFGR3_PLL1PDIV2_Msk (7UL << RCC_PLL1CFGR3_PLL1PDIV2_Pos) - -#define RCC_CCIPR2_REG 0x148 -#define RCC_CCIPR2_ETH1SEL_Pos 16 -#define RCC_CCIPR2_ETH1SEL_Msk (7UL << RCC_CCIPR2_ETH1SEL_Pos) - -whal_Error whal_Stm32n6_Rcc_EnableOsc(whal_Clock *clkDev, - const whal_Stm32n6_Rcc_OscCfg *cfg) -{ - size_t rdy; - - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); - do { - whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, - cfg->rdyPos, &rdy); - } while (!rdy); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32n6_Rcc_DisableOsc(whal_Clock *clkDev, - const whal_Stm32n6_Rcc_OscCfg *cfg) -{ - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32n6_Rcc_EnablePll1(whal_Clock *clkDev, - const whal_Stm32n6_Rcc_Pll1Cfg *cfg) -{ - size_t rdy; - - if (!clkDev || !cfg) - return WHAL_EINVAL; - - /* Disable PLL1 before reconfiguring; wait until off. */ - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); - do { - whal_Reg_Get(clkDev->base, RCC_SR_REG, RCC_SR_PLL1RDY_Msk, - RCC_SR_PLL1RDY_Pos, &rdy); - } while (rdy); - - whal_Reg_Write(clkDev->base, RCC_PLL1CFGR1_REG, - whal_SetBits(RCC_PLL1CFGR1_PLL1SEL_Msk, RCC_PLL1CFGR1_PLL1SEL_Pos, cfg->clkSrc) | - whal_SetBits(RCC_PLL1CFGR1_PLL1DIVM_Msk, RCC_PLL1CFGR1_PLL1DIVM_Pos, cfg->m) | - whal_SetBits(RCC_PLL1CFGR1_PLL1DIVN_Msk, RCC_PLL1CFGR1_PLL1DIVN_Pos, cfg->n)); - whal_Reg_Update(clkDev->base, RCC_PLL1CFGR3_REG, - RCC_PLL1CFGR3_PLL1PDIVEN_Msk | - RCC_PLL1CFGR3_PLL1PDIV1_Msk | - RCC_PLL1CFGR3_PLL1PDIV2_Msk, - RCC_PLL1CFGR3_PLL1PDIVEN_Msk | - whal_SetBits(RCC_PLL1CFGR3_PLL1PDIV1_Msk, RCC_PLL1CFGR3_PLL1PDIV1_Pos, cfg->pdiv1) | - whal_SetBits(RCC_PLL1CFGR3_PLL1PDIV2_Msk, RCC_PLL1CFGR3_PLL1PDIV2_Pos, cfg->pdiv2)); - - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, - RCC_CR_PLL1ON_Msk); - do { - whal_Reg_Get(clkDev->base, RCC_SR_REG, RCC_SR_PLL1RDY_Msk, - RCC_SR_PLL1RDY_Pos, &rdy); - } while (!rdy); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32n6_Rcc_DisablePll1(whal_Clock *clkDev) -{ - if (!clkDev) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32n6_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32n6_Rcc_SysClockSrc src) -{ - size_t sws; - - if (!clkDev) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, RCC_CFGR1_REG, RCC_CFGR1_SYSSW_Msk, - whal_SetBits(RCC_CFGR1_SYSSW_Msk, RCC_CFGR1_SYSSW_Pos, src)); - do { - whal_Reg_Get(clkDev->base, RCC_CFGR1_REG, RCC_CFGR1_SYSSWS_Msk, - RCC_CFGR1_SYSSWS_Pos, &sws); - } while (sws != (size_t)src); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32n6_Rcc_SetCpuClock(whal_Clock *clkDev, - whal_Stm32n6_Rcc_CpuClockSrc src) -{ - size_t sws; - - if (!clkDev) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, RCC_CFGR1_REG, RCC_CFGR1_CPUSW_Msk, - whal_SetBits(RCC_CFGR1_CPUSW_Msk, RCC_CFGR1_CPUSW_Pos, src)); - do { - whal_Reg_Get(clkDev->base, RCC_CFGR1_REG, RCC_CFGR1_CPUSWS_Msk, - RCC_CFGR1_CPUSWS_Pos, &sws); - } while (sws != (size_t)src); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32n6_Rcc_SetEth1If(whal_Clock *clkDev, - whal_Stm32n6_Rcc_Eth1If mode) -{ - if (!clkDev) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, RCC_CCIPR2_REG, RCC_CCIPR2_ETH1SEL_Msk, - whal_SetBits(RCC_CCIPR2_ETH1SEL_Msk, RCC_CCIPR2_ETH1SEL_Pos, - mode)); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32n6_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32n6_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32n6_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32n6_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); - return WHAL_SUCCESS; -} diff --git a/src/clock/stm32wba_rcc.c b/src/clock/stm32wba_rcc.c deleted file mode 100644 index c5ddac2..0000000 --- a/src/clock/stm32wba_rcc.c +++ /dev/null @@ -1,199 +0,0 @@ -#include -#include -#include -#include -#include - -#define RCC_CR_REG 0x000 -#define RCC_CR_PLL1ON_Msk (1UL << 24) -#define RCC_CR_PLL1RDY_Msk (1UL << 25) -#define RCC_CR_PLL1RDY_Pos 25 - -#define RCC_CFGR1_REG 0x01C -#define RCC_CFGR1_SW_Pos 0 -#define RCC_CFGR1_SW_Msk (3UL << RCC_CFGR1_SW_Pos) -#define RCC_CFGR1_SWS_Pos 2 -#define RCC_CFGR1_SWS_Msk (3UL << RCC_CFGR1_SWS_Pos) - -#define RCC_PLL1CFGR_REG 0x028 -#define RCC_PLL1CFGR_SRC_Pos 0 -#define RCC_PLL1CFGR_SRC_Msk (3UL << RCC_PLL1CFGR_SRC_Pos) -#define RCC_PLL1CFGR_RGE_Pos 2 -#define RCC_PLL1CFGR_RGE_Msk (3UL << RCC_PLL1CFGR_RGE_Pos) -#define RCC_PLL1CFGR_M_Pos 8 -#define RCC_PLL1CFGR_M_Msk (7UL << RCC_PLL1CFGR_M_Pos) -#define RCC_PLL1CFGR_REN_Pos 18 -#define RCC_PLL1CFGR_REN_Msk (1UL << RCC_PLL1CFGR_REN_Pos) - -#define RCC_PLL1DIVR_REG 0x034 -#define RCC_PLL1DIVR_N_Pos 0 -#define RCC_PLL1DIVR_N_Msk (0x1FFUL << RCC_PLL1DIVR_N_Pos) -#define RCC_PLL1DIVR_P_Pos 9 -#define RCC_PLL1DIVR_P_Msk (0x7FUL << RCC_PLL1DIVR_P_Pos) -#define RCC_PLL1DIVR_Q_Pos 16 -#define RCC_PLL1DIVR_Q_Msk (0x7FUL << RCC_PLL1DIVR_Q_Pos) -#define RCC_PLL1DIVR_R_Pos 24 -#define RCC_PLL1DIVR_R_Msk (0x7FUL << RCC_PLL1DIVR_R_Pos) - -#define RCC_BDCR1_REG 0x0C8 -#define RCC_BDCR1_LSI1ON_Msk (1UL << 2) -#define RCC_BDCR1_LSI1RDY_Msk (1UL << 3) -#define RCC_BDCR1_LSI1RDY_Pos 3 - -#define RCC_CFGR4_REG 0x080 -#define RCC_CFGR4_HPRE5_Pos 0 -#define RCC_CFGR4_HPRE5_Msk (7UL << RCC_CFGR4_HPRE5_Pos) - -#define RCC_CCIPR2_REG 0x0E4 -#define RCC_CCIPR2_RNGSEL_Pos 12 -#define RCC_CCIPR2_RNGSEL_Msk (3UL << RCC_CCIPR2_RNGSEL_Pos) - -whal_Error whal_Stm32wba_Rcc_EnableOsc(whal_Clock *clkDev, - const whal_Stm32wba_Rcc_OscCfg *cfg) -{ - size_t rdy; - - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); - do { - whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, - cfg->rdyPos, &rdy); - } while (!rdy); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32wba_Rcc_DisableOsc(whal_Clock *clkDev, - const whal_Stm32wba_Rcc_OscCfg *cfg) -{ - if (!clkDev || !cfg) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32wba_Rcc_EnablePll1(whal_Clock *clkDev, - const whal_Stm32wba_Rcc_Pll1Cfg *cfg) -{ - size_t rdy; - - if (!clkDev || !cfg) - return WHAL_EINVAL; - - /* Disable PLL1 before reconfiguring; wait until off. */ - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); - do { - whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLL1RDY_Msk, - RCC_CR_PLL1RDY_Pos, &rdy); - } while (rdy); - - whal_Reg_Write(clkDev->base, RCC_PLL1CFGR_REG, - whal_SetBits(RCC_PLL1CFGR_SRC_Msk, RCC_PLL1CFGR_SRC_Pos, cfg->clkSrc) | - whal_SetBits(RCC_PLL1CFGR_RGE_Msk, RCC_PLL1CFGR_RGE_Pos, cfg->rge) | - whal_SetBits(RCC_PLL1CFGR_M_Msk, RCC_PLL1CFGR_M_Pos, cfg->m) | - whal_SetBits(RCC_PLL1CFGR_REN_Msk, RCC_PLL1CFGR_REN_Pos, 1)); - whal_Reg_Write(clkDev->base, RCC_PLL1DIVR_REG, - whal_SetBits(RCC_PLL1DIVR_N_Msk, RCC_PLL1DIVR_N_Pos, cfg->n) | - whal_SetBits(RCC_PLL1DIVR_P_Msk, RCC_PLL1DIVR_P_Pos, cfg->p) | - whal_SetBits(RCC_PLL1DIVR_Q_Msk, RCC_PLL1DIVR_Q_Pos, cfg->q) | - whal_SetBits(RCC_PLL1DIVR_R_Msk, RCC_PLL1DIVR_R_Pos, cfg->r)); - - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, - RCC_CR_PLL1ON_Msk); - do { - whal_Reg_Get(clkDev->base, RCC_CR_REG, RCC_CR_PLL1RDY_Msk, - RCC_CR_PLL1RDY_Pos, &rdy); - } while (!rdy); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32wba_Rcc_DisablePll1(whal_Clock *clkDev) -{ - if (!clkDev) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, RCC_CR_REG, RCC_CR_PLL1ON_Msk, 0); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32wba_Rcc_EnableLsi(whal_Clock *clkDev) -{ - size_t rdy; - - if (!clkDev) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, RCC_BDCR1_REG, RCC_BDCR1_LSI1ON_Msk, - RCC_BDCR1_LSI1ON_Msk); - do { - whal_Reg_Get(clkDev->base, RCC_BDCR1_REG, RCC_BDCR1_LSI1RDY_Msk, - RCC_BDCR1_LSI1RDY_Pos, &rdy); - } while (!rdy); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32wba_Rcc_DisableLsi(whal_Clock *clkDev) -{ - if (!clkDev) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, RCC_BDCR1_REG, RCC_BDCR1_LSI1ON_Msk, 0); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32wba_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32wba_Rcc_SysClockSrc src) -{ - size_t sws; - - if (!clkDev) - return WHAL_EINVAL; - - whal_Reg_Update(clkDev->base, RCC_CFGR1_REG, RCC_CFGR1_SW_Msk, - whal_SetBits(RCC_CFGR1_SW_Msk, RCC_CFGR1_SW_Pos, src)); - do { - whal_Reg_Get(clkDev->base, RCC_CFGR1_REG, RCC_CFGR1_SWS_Msk, - RCC_CFGR1_SWS_Pos, &sws); - } while (sws != (size_t)src); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32wba_Rcc_SetRngClockSrc(whal_Clock *clkDev, - whal_Stm32wba_Rcc_RngSrc src) -{ - if (!clkDev) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, RCC_CCIPR2_REG, RCC_CCIPR2_RNGSEL_Msk, - whal_SetBits(RCC_CCIPR2_RNGSEL_Msk, RCC_CCIPR2_RNGSEL_Pos, - src)); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32wba_Rcc_SetHpre5(whal_Clock *clkDev, uint8_t hpre5) -{ - if (!clkDev) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, RCC_CFGR4_REG, RCC_CFGR4_HPRE5_Msk, - whal_SetBits(RCC_CFGR4_HPRE5_Msk, RCC_CFGR4_HPRE5_Pos, hpre5)); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32wba_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32wba_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 1)); - return WHAL_SUCCESS; -} - -whal_Error whal_Stm32wba_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32wba_Rcc_PeriphClk *clk) -{ - if (!clkDev || !clk) - return WHAL_EINVAL; - whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, - whal_SetBits(clk->enableMask, clk->enablePos, 0)); - return WHAL_SUCCESS; -} diff --git a/src/crypto/stm32n6_cryp.c b/src/crypto/stm32n6_cryp.c index 18364d8..2dab056 100644 --- a/src/crypto/stm32n6_cryp.c +++ b/src/crypto/stm32n6_cryp.c @@ -1,4 +1,5 @@ #include +#include "board.h" /* provides whal_Stm32n6_Cryp*_Dev singletons */ #include #include #include @@ -89,6 +90,10 @@ #define CRYP_IV1LR_REG 0x48 #define CRYP_IV1RR_REG 0x4C +/* Per-driver state surviving Start→Finalize. Singleton drivers so static. */ +static whal_Stm32n6_AesGcm_State g_aesGcmState; +static whal_Stm32n6_AesCcm_State g_aesCcmState; + static whal_Error WaitKeyValid(size_t base, whal_Timeout *timeout) { return whal_Reg_ReadPoll(base, CRYP_SR_REG, CRYP_SR_KEYVALID_Msk, @@ -239,13 +244,11 @@ static whal_Error PrepareDecryptionKey(size_t base, const uint8_t *key, return WaitCrypEnClear(base, timeout); } -static whal_Error Process_BlockCipher(whal_Crypto *cryptoDev, - const uint8_t *in, uint8_t *out, - size_t sz) +static whal_Error Process_BlockCipher(const uint8_t *in, uint8_t *out, size_t sz) { const whal_Stm32n6_Cryp_Cfg *cfg = - (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; + (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; + size_t base = whal_Stm32n6_Cryp_Dev.base; whal_Error err; size_t i; @@ -311,16 +314,14 @@ static whal_Error Process_BlockCipher(whal_Crypto *cryptoDev, whal_Error whal_Stm32n6_Cryp_Init(whal_Crypto *dev) { - if (!dev) - return WHAL_EINVAL; + (void)dev; return WHAL_SUCCESS; } whal_Error whal_Stm32n6_Cryp_Deinit(whal_Crypto *dev) { - if (!dev) - return WHAL_EINVAL; - Disable(dev->base); + (void)dev; + Disable(whal_Stm32n6_Cryp_Dev.base); return WHAL_SUCCESS; } @@ -338,19 +339,16 @@ whal_Error whal_Stm32n6_CrypAesEcb_Oneshot(whal_AesEcb *dev, const void *in, void *out, size_t sz) { - whal_Crypto *crypto; - const whal_Stm32n6_Cryp_Cfg *cfg; - size_t base; + const whal_Stm32n6_Cryp_Cfg *cfg = + (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; + size_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key) + if (!key) return WHAL_EINVAL; - crypto = dev->crypto; - cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; - base = crypto->base; - err = KeySizeBits(keySz, &keySizeBits); if (err) return err; @@ -374,7 +372,7 @@ whal_Error whal_Stm32n6_CrypAesEcb_Oneshot(whal_AesEcb *dev, Enable(base); } - err = Process_BlockCipher(crypto, in, out, sz); + err = Process_BlockCipher(in, out, sz); Disable(base); return err; } @@ -383,19 +381,16 @@ whal_Error whal_Stm32n6_CrypAesEcb_Start(whal_AesEcb *dev, whal_Crypto_Dir dir, const void *key, size_t keySz) { - whal_Crypto *crypto; - const whal_Stm32n6_Cryp_Cfg *cfg; - size_t base; + const whal_Stm32n6_Cryp_Cfg *cfg = + (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; + size_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key) + if (!key) return WHAL_EINVAL; - crypto = dev->crypto; - cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; - base = crypto->base; - err = KeySizeBits(keySz, &keySizeBits); if (err) return err; @@ -426,7 +421,8 @@ whal_Error whal_Stm32n6_CrypAesEcb_Process(whal_AesEcb *dev, const void *in, void *out, size_t sz) { - return Process_BlockCipher(dev->crypto, in, out, sz); + (void)dev; + return Process_BlockCipher(in, out, sz); } const whal_AesEcbDriver whal_Stm32n6_Cryp_EcbDriver = { @@ -445,19 +441,16 @@ whal_Error whal_Stm32n6_CrypAesCbc_Oneshot(whal_AesCbc *dev, const void *in, void *out, size_t sz) { - whal_Crypto *crypto; - const whal_Stm32n6_Cryp_Cfg *cfg; - size_t base; + const whal_Stm32n6_Cryp_Cfg *cfg = + (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; + size_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) + if (!key || !iv) return WHAL_EINVAL; - crypto = dev->crypto; - cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; - base = crypto->base; - err = KeySizeBits(keySz, &keySizeBits); if (err) return err; @@ -483,7 +476,7 @@ whal_Error whal_Stm32n6_CrypAesCbc_Oneshot(whal_AesCbc *dev, Enable(base); } - err = Process_BlockCipher(crypto, in, out, sz); + err = Process_BlockCipher(in, out, sz); Disable(base); return err; } @@ -493,19 +486,16 @@ whal_Error whal_Stm32n6_CrypAesCbc_Start(whal_AesCbc *dev, const void *key, size_t keySz, const void *iv) { - whal_Crypto *crypto; - const whal_Stm32n6_Cryp_Cfg *cfg; - size_t base; + const whal_Stm32n6_Cryp_Cfg *cfg = + (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; + size_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) + if (!key || !iv) return WHAL_EINVAL; - crypto = dev->crypto; - cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; - base = crypto->base; - err = KeySizeBits(keySz, &keySizeBits); if (err) return err; @@ -538,7 +528,8 @@ whal_Error whal_Stm32n6_CrypAesCbc_Process(whal_AesCbc *dev, const void *in, void *out, size_t sz) { - return Process_BlockCipher(dev->crypto, in, out, sz); + (void)dev; + return Process_BlockCipher(in, out, sz); } const whal_AesCbcDriver whal_Stm32n6_Cryp_CbcDriver = { @@ -557,20 +548,17 @@ whal_Error whal_Stm32n6_CrypAesCtr_Oneshot(whal_AesCtr *dev, const void *in, void *out, size_t sz) { - whal_Crypto *crypto; - const whal_Stm32n6_Cryp_Cfg *cfg; - size_t base; + const whal_Stm32n6_Cryp_Cfg *cfg = + (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; + size_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; uint32_t algoDir; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) + if (!key || !iv) return WHAL_EINVAL; - crypto = dev->crypto; - cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; - base = crypto->base; - err = KeySizeBits(keySz, &keySizeBits); if (err) return err; @@ -587,7 +575,7 @@ whal_Error whal_Stm32n6_CrypAesCtr_Oneshot(whal_AesCtr *dev, return err; Enable(base); - err = Process_BlockCipher(crypto, in, out, sz); + err = Process_BlockCipher(in, out, sz); Disable(base); return err; } @@ -597,20 +585,17 @@ whal_Error whal_Stm32n6_CrypAesCtr_Start(whal_AesCtr *dev, const void *key, size_t keySz, const void *iv) { - whal_Crypto *crypto; - const whal_Stm32n6_Cryp_Cfg *cfg; - size_t base; + const whal_Stm32n6_Cryp_Cfg *cfg = + (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; + size_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; uint32_t algoDir; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) + if (!key || !iv) return WHAL_EINVAL; - crypto = dev->crypto; - cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; - base = crypto->base; - err = KeySizeBits(keySz, &keySizeBits); if (err) return err; @@ -634,7 +619,8 @@ whal_Error whal_Stm32n6_CrypAesCtr_Process(whal_AesCtr *dev, const void *in, void *out, size_t sz) { - return Process_BlockCipher(dev->crypto, in, out, sz); + (void)dev; + return Process_BlockCipher(in, out, sz); } const whal_AesCtrDriver whal_Stm32n6_Cryp_CtrDriver = { @@ -651,13 +637,13 @@ const whal_AesCtrDriver whal_Stm32n6_Cryp_CtrDriver = { * and key, then enable CRYP and wait for the hash subkey computation to * complete (CRYPEN auto-clears). */ -static whal_Error GcmInit(whal_Crypto *cryptoDev, const uint8_t *key, - size_t keySz, uint32_t keySizeBits, - uint32_t algoDir, const uint8_t *iv12) +static whal_Error GcmInit(const uint8_t *key, size_t keySz, + uint32_t keySizeBits, uint32_t algoDir, + const uint8_t *iv12) { const whal_Stm32n6_Cryp_Cfg *cfg = - (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; + (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; + size_t base = whal_Stm32n6_Cryp_Dev.base; whal_Error err; DisableAndFlush(base); @@ -679,12 +665,11 @@ static whal_Error GcmInit(whal_Crypto *cryptoDev, const uint8_t *key, * Feed AAD blocks during the header phase. The peripheral consumes header * data without producing output; the last partial block must be zero-padded. */ -static whal_Error GcmHeaderPhase(whal_Crypto *cryptoDev, const uint8_t *aad, - size_t aadSz) +static whal_Error GcmHeaderPhase(const uint8_t *aad, size_t aadSz) { const whal_Stm32n6_Cryp_Cfg *cfg = - (const whal_Stm32n6_Cryp_Cfg *)cryptoDev->cfg; - size_t base = cryptoDev->base; + (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; + size_t base = whal_Stm32n6_Cryp_Dev.base; whal_Error err; size_t i; @@ -728,9 +713,9 @@ whal_Error whal_Stm32n6_CrypAesGcm_Oneshot(whal_AesGcm *dev, size_t sz, void *tag, size_t tagSz) { - whal_Crypto *crypto; - const whal_Stm32n6_Cryp_Cfg *cfg; - size_t base; + const whal_Stm32n6_Cryp_Cfg *cfg = + (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; + size_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; uint32_t algoDir; uint8_t tagBuf[16]; @@ -738,8 +723,9 @@ whal_Error whal_Stm32n6_CrypAesGcm_Oneshot(whal_AesGcm *dev, uint64_t payloadBits; whal_Error err; size_t i; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) + if (!key || !iv) return WHAL_EINVAL; if (ivSz != 12) return WHAL_ENOTSUP; @@ -750,10 +736,6 @@ whal_Error whal_Stm32n6_CrypAesGcm_Oneshot(whal_AesGcm *dev, if (!tag || tagSz == 0 || tagSz > 16) return WHAL_EINVAL; - crypto = dev->crypto; - cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; - base = crypto->base; - err = KeySizeBits(keySz, &keySizeBits); if (err) return err; @@ -762,13 +744,13 @@ whal_Error whal_Stm32n6_CrypAesGcm_Oneshot(whal_AesGcm *dev, : CRYP_ALGODIR_DECRYPT; /* Init phase */ - err = GcmInit(crypto, (const uint8_t *)key, keySz, + err = GcmInit((const uint8_t *)key, keySz, keySizeBits, algoDir, (const uint8_t *)iv); if (err) return err; /* Header phase */ - err = GcmHeaderPhase(crypto, (const uint8_t *)aad, aadSz); + err = GcmHeaderPhase((const uint8_t *)aad, aadSz); if (err) return err; @@ -855,23 +837,19 @@ whal_Error whal_Stm32n6_CrypAesGcm_Start(whal_AesGcm *dev, const void *iv, size_t ivSz, const void *aad, size_t aadSz) { - whal_Crypto *crypto; - size_t base; + size_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; uint32_t algoDir; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state || !key || !iv) + if (!key || !iv) return WHAL_EINVAL; - - crypto = dev->crypto; if (ivSz != 12) return WHAL_ENOTSUP; if (aadSz > 0 && !aad) return WHAL_EINVAL; - base = crypto->base; - err = KeySizeBits(keySz, &keySizeBits); if (err) return err; @@ -880,13 +858,13 @@ whal_Error whal_Stm32n6_CrypAesGcm_Start(whal_AesGcm *dev, : CRYP_ALGODIR_DECRYPT; /* Init phase */ - err = GcmInit(crypto, (const uint8_t *)key, keySz, + err = GcmInit((const uint8_t *)key, keySz, keySizeBits, algoDir, (const uint8_t *)iv); if (err) return err; /* Header phase */ - err = GcmHeaderPhase(crypto, (const uint8_t *)aad, aadSz); + err = GcmHeaderPhase((const uint8_t *)aad, aadSz); if (err) return err; @@ -898,11 +876,8 @@ whal_Error whal_Stm32n6_CrypAesGcm_Start(whal_AesGcm *dev, CRYP_GCM_CCMPH_PAYLOAD)); Enable(base); - { - whal_Stm32n6_AesGcm_State *st = (whal_Stm32n6_AesGcm_State *)dev->state; - st->aadSz = aadSz; - st->dataSz = 0; - } + g_aesGcmState.aadSz = aadSz; + g_aesGcmState.dataSz = 0; return WHAL_SUCCESS; } @@ -911,20 +886,12 @@ whal_Error whal_Stm32n6_CrypAesGcm_Process(whal_AesGcm *dev, const void *in, void *out, size_t sz) { - whal_Crypto *crypto; - const whal_Stm32n6_Cryp_Cfg *cfg; - size_t base; - whal_Stm32n6_AesGcm_State *st; + const whal_Stm32n6_Cryp_Cfg *cfg = + (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; + size_t base = whal_Stm32n6_Cryp_Dev.base; size_t i; whal_Error err; - - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) - return WHAL_EINVAL; - - crypto = dev->crypto; - cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; - base = crypto->base; - st = (whal_Stm32n6_AesGcm_State *)dev->state; + (void)dev; if (sz == 0) return WHAL_SUCCESS; @@ -962,7 +929,7 @@ whal_Error whal_Stm32n6_CrypAesGcm_Process(whal_AesGcm *dev, } } - st->dataSz += sz; + g_aesGcmState.dataSz += sz; return WHAL_SUCCESS; } @@ -970,23 +937,15 @@ whal_Error whal_Stm32n6_CrypAesGcm_Process(whal_AesGcm *dev, whal_Error whal_Stm32n6_CrypAesGcm_Finalize(whal_AesGcm *dev, void *tag, size_t tagSz) { - whal_Crypto *crypto; - const whal_Stm32n6_Cryp_Cfg *cfg; - size_t base; - whal_Stm32n6_AesGcm_State *st; + const whal_Stm32n6_Cryp_Cfg *cfg = + (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; + size_t base = whal_Stm32n6_Cryp_Dev.base; uint8_t tagBuf[16]; uint64_t aadBits; uint64_t payloadBits; size_t i; whal_Error err; - - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) - return WHAL_EINVAL; - - crypto = dev->crypto; - cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; - base = crypto->base; - st = (whal_Stm32n6_AesGcm_State *)dev->state; + (void)dev; if (!tag || tagSz == 0 || tagSz > 16) return WHAL_EINVAL; @@ -1000,8 +959,8 @@ whal_Error whal_Stm32n6_CrypAesGcm_Finalize(whal_AesGcm *dev, CRYP_GCM_CCMPH_FINAL)); Enable(base); - aadBits = (uint64_t)st->aadSz * 8; - payloadBits = (uint64_t)st->dataSz * 8; + aadBits = (uint64_t)g_aesGcmState.aadSz * 8; + payloadBits = (uint64_t)g_aesGcmState.dataSz * 8; whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)(aadBits >> 32)); whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)aadBits); whal_Reg_Write(base, CRYP_DINR_REG, (uint32_t)(payloadBits >> 32)); @@ -1037,16 +996,17 @@ whal_Error whal_Stm32n6_CrypAesGmac_Oneshot(whal_AesGmac *dev, const void *aad, size_t aadSz, void *tag, size_t tagSz) { - whal_Crypto *crypto; - const whal_Stm32n6_Cryp_Cfg *cfg; - size_t base; + const whal_Stm32n6_Cryp_Cfg *cfg = + (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; + size_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; uint8_t tagBuf[16]; uint64_t aadBits; whal_Error err; size_t i; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !iv) + if (!key || !iv) return WHAL_EINVAL; if (ivSz != 12) return WHAL_ENOTSUP; @@ -1055,23 +1015,19 @@ whal_Error whal_Stm32n6_CrypAesGmac_Oneshot(whal_AesGmac *dev, if (!tag || tagSz == 0 || tagSz > 16) return WHAL_EINVAL; - crypto = dev->crypto; - cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; - base = crypto->base; - err = KeySizeBits(keySz, &keySizeBits); if (err) return err; /* Init phase */ - err = GcmInit(crypto, (const uint8_t *)key, keySz, + err = GcmInit((const uint8_t *)key, keySz, keySizeBits, CRYP_ALGODIR_ENCRYPT, (const uint8_t *)iv); if (err) return err; /* Header phase */ - err = GcmHeaderPhase(crypto, (const uint8_t *)aad, aadSz); + err = GcmHeaderPhase((const uint8_t *)aad, aadSz); if (err) return err; @@ -1142,9 +1098,9 @@ whal_Error whal_Stm32n6_CrypAesCcm_Oneshot(whal_AesCcm *dev, size_t sz, void *tag, size_t tagSz) { - whal_Crypto *crypto; - const whal_Stm32n6_Cryp_Cfg *cfg; - size_t base; + const whal_Stm32n6_Cryp_Cfg *cfg = + (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; + size_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; uint32_t algoDir; uint8_t b0[16]; @@ -1154,8 +1110,9 @@ whal_Error whal_Stm32n6_CrypAesCcm_Oneshot(whal_AesCcm *dev, size_t q; size_t i; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !key || !nonce) + if (!key || !nonce) return WHAL_EINVAL; if (nonceSz < 7 || nonceSz > 13) return WHAL_EINVAL; @@ -1168,10 +1125,6 @@ whal_Error whal_Stm32n6_CrypAesCcm_Oneshot(whal_AesCcm *dev, if (!tag) return WHAL_EINVAL; - crypto = dev->crypto; - cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; - base = crypto->base; - err = KeySizeBits(keySz, &keySizeBits); if (err) return err; @@ -1326,10 +1279,9 @@ whal_Error whal_Stm32n6_CrypAesCcm_Start(whal_AesCcm *dev, const void *aad, size_t aadSz, size_t tagSz, size_t sz) { - whal_Crypto *crypto; - const whal_Stm32n6_Cryp_Cfg *cfg; - whal_Stm32n6_AesCcm_State *st; - size_t base; + const whal_Stm32n6_Cryp_Cfg *cfg = + (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; + size_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t keySizeBits; uint32_t algoDir; uint8_t b0[16]; @@ -1337,8 +1289,9 @@ whal_Error whal_Stm32n6_CrypAesCcm_Start(whal_AesCcm *dev, size_t q; size_t i; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state || !key || !nonce) + if (!key || !nonce) return WHAL_EINVAL; if (nonceSz < 7 || nonceSz > 13) return WHAL_EINVAL; @@ -1347,11 +1300,6 @@ whal_Error whal_Stm32n6_CrypAesCcm_Start(whal_AesCcm *dev, if (aadSz > 0 && !aad) return WHAL_EINVAL; - crypto = dev->crypto; - cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; - st = (whal_Stm32n6_AesCcm_State *)dev->state; - base = crypto->base; - err = KeySizeBits(keySz, &keySizeBits); if (err) return err; @@ -1364,13 +1312,13 @@ whal_Error whal_Stm32n6_CrypAesCcm_Start(whal_AesCcm *dev, sz, aadSz > 0, b0); for (i = 0; i < 16; i++) - st->ccmCtr0[i] = b0[i]; - st->ccmCtr0[0] &= 0x07; + g_aesCcmState.ccmCtr0[i] = b0[i]; + g_aesCcmState.ccmCtr0[0] &= 0x07; for (i = 16 - q; i < 16; i++) - st->ccmCtr0[i] = 0; + g_aesCcmState.ccmCtr0[i] = 0; for (i = 0; i < 16; i++) - ctr1[i] = st->ccmCtr0[i]; + ctr1[i] = g_aesCcmState.ccmCtr0[i]; ctr1[15] |= 0x01; /* Init phase */ @@ -1430,8 +1378,8 @@ whal_Error whal_Stm32n6_CrypAesCcm_Start(whal_AesCcm *dev, CRYP_GCM_CCMPH_PAYLOAD)); Enable(base); - st->aadSz = aadSz; - st->dataSz = 0; + g_aesCcmState.aadSz = aadSz; + g_aesCcmState.dataSz = 0; return WHAL_SUCCESS; } @@ -1440,21 +1388,13 @@ whal_Error whal_Stm32n6_CrypAesCcm_Process(whal_AesCcm *dev, const void *in, void *out, size_t sz) { - whal_Crypto *crypto; - const whal_Stm32n6_Cryp_Cfg *cfg; - size_t base; - whal_Stm32n6_AesCcm_State *st; + const whal_Stm32n6_Cryp_Cfg *cfg = + (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; + size_t base = whal_Stm32n6_Cryp_Dev.base; uint32_t algoDir; size_t i; whal_Error err; - - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) - return WHAL_EINVAL; - - crypto = dev->crypto; - cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; - base = crypto->base; - st = (whal_Stm32n6_AesCcm_State *)dev->state; + (void)dev; if (sz == 0) return WHAL_SUCCESS; @@ -1502,7 +1442,7 @@ whal_Error whal_Stm32n6_CrypAesCcm_Process(whal_AesCcm *dev, } } - st->dataSz += sz; + g_aesCcmState.dataSz += sz; return WHAL_SUCCESS; } @@ -1510,23 +1450,17 @@ whal_Error whal_Stm32n6_CrypAesCcm_Process(whal_AesCcm *dev, whal_Error whal_Stm32n6_CrypAesCcm_Finalize(whal_AesCcm *dev, void *tag, size_t tagSz) { - whal_Crypto *crypto; - const whal_Stm32n6_Cryp_Cfg *cfg; - whal_Stm32n6_AesCcm_State *st; - size_t base; + const whal_Stm32n6_Cryp_Cfg *cfg = + (const whal_Stm32n6_Cryp_Cfg *)whal_Stm32n6_Cryp_Dev.cfg; + size_t base = whal_Stm32n6_Cryp_Dev.base; uint8_t tagBuf[16]; size_t i; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state || - !tag || tagSz < 4 || tagSz > 16 || (tagSz & 1) != 0) + if (!tag || tagSz < 4 || tagSz > 16 || (tagSz & 1) != 0) return WHAL_EINVAL; - crypto = dev->crypto; - cfg = (const whal_Stm32n6_Cryp_Cfg *)crypto->cfg; - st = (whal_Stm32n6_AesCcm_State *)dev->state; - base = crypto->base; - /* Final phase */ Disable(base); whal_Reg_Update(base, CRYP_CR_REG, @@ -1536,7 +1470,7 @@ whal_Error whal_Stm32n6_CrypAesCcm_Finalize(whal_AesCcm *dev, CRYP_GCM_CCMPH_FINAL)); Enable(base); - WriteBlock(base, st->ccmCtr0); + WriteBlock(base, g_aesCcmState.ccmCtr0); err = WaitOutputReady(base, cfg->timeout); if (err) { diff --git a/src/crypto/stm32wba_hash.c b/src/crypto/stm32wba_hash.c index c72e7b8..431b6f7 100644 --- a/src/crypto/stm32wba_hash.c +++ b/src/crypto/stm32wba_hash.c @@ -1,4 +1,5 @@ #include +#include "board.h" /* provides whal_Stm32wba_Hash*_Dev singletons */ #include #include #include @@ -53,6 +54,11 @@ #define HASH_MODE_HASH 0 #define HASH_MODE_HMAC 1 +/* Per-driver HMAC state surviving Start→Finalize. Singleton drivers so static. */ +static whal_Stm32wba_HmacSha1_State g_hmacSha1State; +static whal_Stm32wba_HmacSha224_State g_hmacSha224State; +static whal_Stm32wba_HmacSha256_State g_hmacSha256State; + static uint32_t AlgoBits(size_t algo) { return whal_SetBits(HASH_CR_ALGO_Msk, HASH_CR_ALGO_Pos, algo); @@ -152,15 +158,13 @@ static void ReadDigest(size_t base, uint8_t *digest, size_t digestSz) whal_Error whal_Stm32wba_Hash_Init(whal_Crypto *dev) { - if (!dev) - return WHAL_EINVAL; + (void)dev; return WHAL_SUCCESS; } whal_Error whal_Stm32wba_Hash_Deinit(whal_Crypto *dev) { - if (!dev) - return WHAL_EINVAL; + (void)dev; return WHAL_SUCCESS; } @@ -176,18 +180,15 @@ whal_Error whal_Stm32wba_Sha1_Oneshot(whal_Sha1 *dev, const void *in, size_t inSz, void *digest, size_t digestSz) { - const whal_Stm32wba_Hash_Cfg *cfg; - size_t base; + const whal_Stm32wba_Hash_Cfg *cfg = + (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; + size_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg) - return WHAL_EINVAL; if (!digest || digestSz != 20) return WHAL_EINVAL; - cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; - base = dev->crypto->base; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); whal_Reg_Update(base, HASH_CR_REG, @@ -214,12 +215,8 @@ whal_Error whal_Stm32wba_Sha1_Oneshot(whal_Sha1 *dev, whal_Error whal_Stm32wba_Sha1_Start(whal_Sha1 *dev) { - size_t base; - - if (!dev || !dev->crypto || !dev->crypto->cfg) - return WHAL_EINVAL; - - base = dev->crypto->base; + size_t base = whal_Stm32wba_Hash_Dev.base; + (void)dev; whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); @@ -234,12 +231,11 @@ whal_Error whal_Stm32wba_Sha1_Start(whal_Sha1 *dev) whal_Error whal_Stm32wba_Sha1_Process(whal_Sha1 *dev, const void *in, size_t inSz) { - if (!dev || !dev->crypto) - return WHAL_EINVAL; + (void)dev; if (inSz > 0) { if (!in) return WHAL_EINVAL; - WriteData(dev->crypto->base, (const uint8_t *)in, inSz); + WriteData(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); } return WHAL_SUCCESS; } @@ -247,18 +243,15 @@ whal_Error whal_Stm32wba_Sha1_Process(whal_Sha1 *dev, whal_Error whal_Stm32wba_Sha1_Finalize(whal_Sha1 *dev, void *digest, size_t digestSz) { - const whal_Stm32wba_Hash_Cfg *cfg; - size_t base; + const whal_Stm32wba_Hash_Cfg *cfg = + (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; + size_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg) - return WHAL_EINVAL; if (!digest || digestSz != 20) return WHAL_EINVAL; - cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; - base = dev->crypto->base; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -284,18 +277,15 @@ whal_Error whal_Stm32wba_Sha224_Oneshot(whal_Sha224 *dev, const void *in, size_t inSz, void *digest, size_t digestSz) { - const whal_Stm32wba_Hash_Cfg *cfg; - size_t base; + const whal_Stm32wba_Hash_Cfg *cfg = + (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; + size_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg) - return WHAL_EINVAL; if (!digest || digestSz != 28) return WHAL_EINVAL; - cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; - base = dev->crypto->base; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); whal_Reg_Update(base, HASH_CR_REG, @@ -322,12 +312,8 @@ whal_Error whal_Stm32wba_Sha224_Oneshot(whal_Sha224 *dev, whal_Error whal_Stm32wba_Sha224_Start(whal_Sha224 *dev) { - size_t base; - - if (!dev || !dev->crypto || !dev->crypto->cfg) - return WHAL_EINVAL; - - base = dev->crypto->base; + size_t base = whal_Stm32wba_Hash_Dev.base; + (void)dev; whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); @@ -342,12 +328,11 @@ whal_Error whal_Stm32wba_Sha224_Start(whal_Sha224 *dev) whal_Error whal_Stm32wba_Sha224_Process(whal_Sha224 *dev, const void *in, size_t inSz) { - if (!dev || !dev->crypto) - return WHAL_EINVAL; + (void)dev; if (inSz > 0) { if (!in) return WHAL_EINVAL; - WriteData(dev->crypto->base, (const uint8_t *)in, inSz); + WriteData(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); } return WHAL_SUCCESS; } @@ -355,18 +340,15 @@ whal_Error whal_Stm32wba_Sha224_Process(whal_Sha224 *dev, whal_Error whal_Stm32wba_Sha224_Finalize(whal_Sha224 *dev, void *digest, size_t digestSz) { - const whal_Stm32wba_Hash_Cfg *cfg; - size_t base; + const whal_Stm32wba_Hash_Cfg *cfg = + (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; + size_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg) - return WHAL_EINVAL; if (!digest || digestSz != 28) return WHAL_EINVAL; - cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; - base = dev->crypto->base; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -392,18 +374,15 @@ whal_Error whal_Stm32wba_Sha256_Oneshot(whal_Sha256 *dev, const void *in, size_t inSz, void *digest, size_t digestSz) { - const whal_Stm32wba_Hash_Cfg *cfg; - size_t base; + const whal_Stm32wba_Hash_Cfg *cfg = + (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; + size_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg) - return WHAL_EINVAL; if (!digest || digestSz != 32) return WHAL_EINVAL; - cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; - base = dev->crypto->base; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); whal_Reg_Update(base, HASH_CR_REG, @@ -430,12 +409,8 @@ whal_Error whal_Stm32wba_Sha256_Oneshot(whal_Sha256 *dev, whal_Error whal_Stm32wba_Sha256_Start(whal_Sha256 *dev) { - size_t base; - - if (!dev || !dev->crypto || !dev->crypto->cfg) - return WHAL_EINVAL; - - base = dev->crypto->base; + size_t base = whal_Stm32wba_Hash_Dev.base; + (void)dev; whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); @@ -450,12 +425,11 @@ whal_Error whal_Stm32wba_Sha256_Start(whal_Sha256 *dev) whal_Error whal_Stm32wba_Sha256_Process(whal_Sha256 *dev, const void *in, size_t inSz) { - if (!dev || !dev->crypto) - return WHAL_EINVAL; + (void)dev; if (inSz > 0) { if (!in) return WHAL_EINVAL; - WriteData(dev->crypto->base, (const uint8_t *)in, inSz); + WriteData(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); } return WHAL_SUCCESS; } @@ -463,18 +437,15 @@ whal_Error whal_Stm32wba_Sha256_Process(whal_Sha256 *dev, whal_Error whal_Stm32wba_Sha256_Finalize(whal_Sha256 *dev, void *digest, size_t digestSz) { - const whal_Stm32wba_Hash_Cfg *cfg; - size_t base; + const whal_Stm32wba_Hash_Cfg *cfg = + (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; + size_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg) - return WHAL_EINVAL; if (!digest || digestSz != 32) return WHAL_EINVAL; - cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; - base = dev->crypto->base; - whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -501,16 +472,13 @@ whal_Error whal_Stm32wba_HmacSha1_Oneshot(whal_HmacSha1 *dev, const void *in, size_t inSz, void *digest, size_t digestSz) { - const whal_Stm32wba_Hash_Cfg *cfg; - size_t base; + const whal_Stm32wba_Hash_Cfg *cfg = + (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; + size_t base = whal_Stm32wba_Hash_Dev.base; size_t lkey; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg) - return WHAL_EINVAL; - - cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; - base = dev->crypto->base; if (!key || !digest || digestSz != 20) return WHAL_EINVAL; @@ -569,18 +537,16 @@ whal_Error whal_Stm32wba_HmacSha1_Oneshot(whal_HmacSha1 *dev, whal_Error whal_Stm32wba_HmacSha1_Start(whal_HmacSha1 *dev, const void *key, size_t keySz) { - const whal_Stm32wba_Hash_Cfg *cfg; - size_t base; + const whal_Stm32wba_Hash_Cfg *cfg = + (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; + size_t base = whal_Stm32wba_Hash_Dev.base; size_t lkey; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) - return WHAL_EINVAL; if (!key) return WHAL_EINVAL; - cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; - base = dev->crypto->base; lkey = (keySz > 64) ? 1 : 0; whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); @@ -605,12 +571,8 @@ whal_Error whal_Stm32wba_HmacSha1_Start(whal_HmacSha1 *dev, return err; /* Store key for outer-key phase in Finalize */ - { - whal_Stm32wba_HmacSha1_State *st = - (whal_Stm32wba_HmacSha1_State *)dev->state; - st->key = key; - st->keySz = keySz; - } + g_hmacSha1State.key = key; + g_hmacSha1State.keySz = keySz; return WHAL_SUCCESS; } @@ -618,12 +580,11 @@ whal_Error whal_Stm32wba_HmacSha1_Start(whal_HmacSha1 *dev, whal_Error whal_Stm32wba_HmacSha1_Process(whal_HmacSha1 *dev, const void *in, size_t inSz) { - if (!dev || !dev->crypto) - return WHAL_EINVAL; + (void)dev; if (inSz > 0) { if (!in) return WHAL_EINVAL; - WriteData(dev->crypto->base, (const uint8_t *)in, inSz); + WriteData(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); } return WHAL_SUCCESS; } @@ -631,20 +592,15 @@ whal_Error whal_Stm32wba_HmacSha1_Process(whal_HmacSha1 *dev, whal_Error whal_Stm32wba_HmacSha1_Finalize(whal_HmacSha1 *dev, void *digest, size_t digestSz) { - const whal_Stm32wba_Hash_Cfg *cfg; - const whal_Stm32wba_HmacSha1_State *st; - size_t base; + const whal_Stm32wba_Hash_Cfg *cfg = + (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; + size_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) - return WHAL_EINVAL; if (!digest || digestSz != 20) return WHAL_EINVAL; - cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; - base = dev->crypto->base; - st = (const whal_Stm32wba_HmacSha1_State *)dev->state; - /* Message done */ whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -655,7 +611,7 @@ whal_Error whal_Stm32wba_HmacSha1_Finalize(whal_HmacSha1 *dev, /* Outer key */ whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - WriteData(base, (const uint8_t *)st->key, st->keySz); + WriteData(base, (const uint8_t *)g_hmacSha1State.key, g_hmacSha1State.keySz); whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -683,16 +639,13 @@ whal_Error whal_Stm32wba_HmacSha224_Oneshot(whal_HmacSha224 *dev, const void *in, size_t inSz, void *digest, size_t digestSz) { - const whal_Stm32wba_Hash_Cfg *cfg; - size_t base; + const whal_Stm32wba_Hash_Cfg *cfg = + (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; + size_t base = whal_Stm32wba_Hash_Dev.base; size_t lkey; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg) - return WHAL_EINVAL; - - cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; - base = dev->crypto->base; if (!key || !digest || digestSz != 28) return WHAL_EINVAL; @@ -751,18 +704,16 @@ whal_Error whal_Stm32wba_HmacSha224_Oneshot(whal_HmacSha224 *dev, whal_Error whal_Stm32wba_HmacSha224_Start(whal_HmacSha224 *dev, const void *key, size_t keySz) { - const whal_Stm32wba_Hash_Cfg *cfg; - size_t base; + const whal_Stm32wba_Hash_Cfg *cfg = + (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; + size_t base = whal_Stm32wba_Hash_Dev.base; size_t lkey; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) - return WHAL_EINVAL; if (!key) return WHAL_EINVAL; - cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; - base = dev->crypto->base; lkey = (keySz > 64) ? 1 : 0; whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); @@ -787,12 +738,8 @@ whal_Error whal_Stm32wba_HmacSha224_Start(whal_HmacSha224 *dev, return err; /* Store key for outer-key phase in Finalize */ - { - whal_Stm32wba_HmacSha224_State *st = - (whal_Stm32wba_HmacSha224_State *)dev->state; - st->key = key; - st->keySz = keySz; - } + g_hmacSha224State.key = key; + g_hmacSha224State.keySz = keySz; return WHAL_SUCCESS; } @@ -800,12 +747,11 @@ whal_Error whal_Stm32wba_HmacSha224_Start(whal_HmacSha224 *dev, whal_Error whal_Stm32wba_HmacSha224_Process(whal_HmacSha224 *dev, const void *in, size_t inSz) { - if (!dev || !dev->crypto) - return WHAL_EINVAL; + (void)dev; if (inSz > 0) { if (!in) return WHAL_EINVAL; - WriteData(dev->crypto->base, (const uint8_t *)in, inSz); + WriteData(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); } return WHAL_SUCCESS; } @@ -813,20 +759,15 @@ whal_Error whal_Stm32wba_HmacSha224_Process(whal_HmacSha224 *dev, whal_Error whal_Stm32wba_HmacSha224_Finalize(whal_HmacSha224 *dev, void *digest, size_t digestSz) { - const whal_Stm32wba_Hash_Cfg *cfg; - const whal_Stm32wba_HmacSha224_State *st; - size_t base; + const whal_Stm32wba_Hash_Cfg *cfg = + (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; + size_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) - return WHAL_EINVAL; if (!digest || digestSz != 28) return WHAL_EINVAL; - cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; - base = dev->crypto->base; - st = (const whal_Stm32wba_HmacSha224_State *)dev->state; - /* Message done */ whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -837,7 +778,7 @@ whal_Error whal_Stm32wba_HmacSha224_Finalize(whal_HmacSha224 *dev, /* Outer key */ whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - WriteData(base, (const uint8_t *)st->key, st->keySz); + WriteData(base, (const uint8_t *)g_hmacSha224State.key, g_hmacSha224State.keySz); whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -865,16 +806,13 @@ whal_Error whal_Stm32wba_HmacSha256_Oneshot(whal_HmacSha256 *dev, const void *in, size_t inSz, void *digest, size_t digestSz) { - const whal_Stm32wba_Hash_Cfg *cfg; - size_t base; + const whal_Stm32wba_Hash_Cfg *cfg = + (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; + size_t base = whal_Stm32wba_Hash_Dev.base; size_t lkey; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg) - return WHAL_EINVAL; - - cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; - base = dev->crypto->base; if (!key || !digest || digestSz != 32) return WHAL_EINVAL; @@ -933,18 +871,16 @@ whal_Error whal_Stm32wba_HmacSha256_Oneshot(whal_HmacSha256 *dev, whal_Error whal_Stm32wba_HmacSha256_Start(whal_HmacSha256 *dev, const void *key, size_t keySz) { - const whal_Stm32wba_Hash_Cfg *cfg; - size_t base; + const whal_Stm32wba_Hash_Cfg *cfg = + (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; + size_t base = whal_Stm32wba_Hash_Dev.base; size_t lkey; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) - return WHAL_EINVAL; if (!key) return WHAL_EINVAL; - cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; - base = dev->crypto->base; lkey = (keySz > 64) ? 1 : 0; whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); @@ -969,12 +905,8 @@ whal_Error whal_Stm32wba_HmacSha256_Start(whal_HmacSha256 *dev, return err; /* Store key for outer-key phase in Finalize */ - { - whal_Stm32wba_HmacSha256_State *st = - (whal_Stm32wba_HmacSha256_State *)dev->state; - st->key = key; - st->keySz = keySz; - } + g_hmacSha256State.key = key; + g_hmacSha256State.keySz = keySz; return WHAL_SUCCESS; } @@ -982,12 +914,11 @@ whal_Error whal_Stm32wba_HmacSha256_Start(whal_HmacSha256 *dev, whal_Error whal_Stm32wba_HmacSha256_Process(whal_HmacSha256 *dev, const void *in, size_t inSz) { - if (!dev || !dev->crypto) - return WHAL_EINVAL; + (void)dev; if (inSz > 0) { if (!in) return WHAL_EINVAL; - WriteData(dev->crypto->base, (const uint8_t *)in, inSz); + WriteData(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); } return WHAL_SUCCESS; } @@ -995,20 +926,15 @@ whal_Error whal_Stm32wba_HmacSha256_Process(whal_HmacSha256 *dev, whal_Error whal_Stm32wba_HmacSha256_Finalize(whal_HmacSha256 *dev, void *digest, size_t digestSz) { - const whal_Stm32wba_Hash_Cfg *cfg; - const whal_Stm32wba_HmacSha256_State *st; - size_t base; + const whal_Stm32wba_Hash_Cfg *cfg = + (const whal_Stm32wba_Hash_Cfg *)whal_Stm32wba_Hash_Dev.cfg; + size_t base = whal_Stm32wba_Hash_Dev.base; whal_Error err; + (void)dev; - if (!dev || !dev->crypto || !dev->crypto->cfg || !dev->state) - return WHAL_EINVAL; if (!digest || digestSz != 32) return WHAL_EINVAL; - cfg = (const whal_Stm32wba_Hash_Cfg *)dev->crypto->cfg; - base = dev->crypto->base; - st = (const whal_Stm32wba_HmacSha256_State *)dev->state; - /* Message done */ whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -1019,7 +945,7 @@ whal_Error whal_Stm32wba_HmacSha256_Finalize(whal_HmacSha256 *dev, /* Outer key */ whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - WriteData(base, (const uint8_t *)st->key, st->keySz); + WriteData(base, (const uint8_t *)g_hmacSha256State.key, g_hmacSha256State.keySz); whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); diff --git a/src/dma/stm32wba_gpdma.c b/src/dma/stm32wba_gpdma.c index 3fe04f7..da07782 100644 --- a/src/dma/stm32wba_gpdma.c +++ b/src/dma/stm32wba_gpdma.c @@ -1,5 +1,9 @@ #include #include +#if defined(WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_GPDMA_SINGLE_INSTANCE) +#include "board.h" /* provides whal_Stm32wba_Gpdma_Dev singleton (possibly via platform alias macro) */ +#endif #include #include #include @@ -115,24 +119,39 @@ whal_Error whal_Stm32wba_Gpdma_Init(whal_Dma *dmaDev) { +#if defined(WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_GPDMA_SINGLE_INSTANCE) + (void)dmaDev; +#else if (!dmaDev || !dmaDev->cfg) return WHAL_EINVAL; +#endif return WHAL_SUCCESS; } whal_Error whal_Stm32wba_Gpdma_Deinit(whal_Dma *dmaDev) { +#if defined(WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_GPDMA_SINGLE_INSTANCE) + const whal_Stm32wba_Gpdma_Cfg *cfg = + (const whal_Stm32wba_Gpdma_Cfg *)whal_Stm32wba_Gpdma_Dev.cfg; + size_t base = whal_Stm32wba_Gpdma_Dev.base; + (void)dmaDev; +#else const whal_Stm32wba_Gpdma_Cfg *cfg; + size_t base; if (!dmaDev || !dmaDev->cfg) return WHAL_EINVAL; cfg = (const whal_Stm32wba_Gpdma_Cfg *)dmaDev->cfg; + base = dmaDev->base; +#endif /* Reset all channels */ for (uint8_t ch = 0; ch < cfg->numChannels; ch++) { - whal_Reg_Write(dmaDev->base, GPDMA_CxCR(ch), + whal_Reg_Write(base, GPDMA_CxCR(ch), GPDMA_CxCR_RESET_Msk); } @@ -142,18 +161,29 @@ whal_Error whal_Stm32wba_Gpdma_Deinit(whal_Dma *dmaDev) whal_Error whal_Stm32wba_Gpdma_Configure(whal_Dma *dmaDev, size_t ch, const void *chCfg) { - const whal_Stm32wba_Gpdma_Cfg *cfg; const whal_Stm32wba_Gpdma_ChCfg *ccfg; - size_t base; size_t tr1, tr2; whal_Error err; +#if defined(WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_GPDMA_SINGLE_INSTANCE) + const whal_Stm32wba_Gpdma_Cfg *cfg = + (const whal_Stm32wba_Gpdma_Cfg *)whal_Stm32wba_Gpdma_Dev.cfg; + size_t base = whal_Stm32wba_Gpdma_Dev.base; + (void)dmaDev; + + if (!chCfg) + return WHAL_EINVAL; +#else + const whal_Stm32wba_Gpdma_Cfg *cfg; + size_t base; if (!dmaDev || !dmaDev->cfg || !chCfg) return WHAL_EINVAL; cfg = (const whal_Stm32wba_Gpdma_Cfg *)dmaDev->cfg; - ccfg = (const whal_Stm32wba_Gpdma_ChCfg *)chCfg; base = dmaDev->base; +#endif + ccfg = (const whal_Stm32wba_Gpdma_ChCfg *)chCfg; if (ch >= cfg->numChannels) return WHAL_EINVAL; @@ -219,21 +249,31 @@ whal_Error whal_Stm32wba_Gpdma_Configure(whal_Dma *dmaDev, size_t ch, whal_Error whal_Stm32wba_Gpdma_Start(whal_Dma *dmaDev, size_t ch) { +#if defined(WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_GPDMA_SINGLE_INSTANCE) + const whal_Stm32wba_Gpdma_Cfg *cfg = + (const whal_Stm32wba_Gpdma_Cfg *)whal_Stm32wba_Gpdma_Dev.cfg; + size_t base = whal_Stm32wba_Gpdma_Dev.base; + (void)dmaDev; +#else const whal_Stm32wba_Gpdma_Cfg *cfg; + size_t base; if (!dmaDev || !dmaDev->cfg) return WHAL_EINVAL; cfg = (const whal_Stm32wba_Gpdma_Cfg *)dmaDev->cfg; + base = dmaDev->base; +#endif if (ch >= cfg->numChannels) return WHAL_EINVAL; /* Clear any stale flags from the previous transfer before enabling */ - whal_Reg_Write(dmaDev->base, GPDMA_CxFCR(ch), GPDMA_CxFCR_ALL); + whal_Reg_Write(base, GPDMA_CxFCR(ch), GPDMA_CxFCR_ALL); /* Set EN bit without disturbing the already-configured interrupt enables */ - whal_Reg_Update(dmaDev->base, GPDMA_CxCR(ch), GPDMA_CxCR_EN_Msk, + whal_Reg_Update(base, GPDMA_CxCR(ch), GPDMA_CxCR_EN_Msk, GPDMA_CxCR_EN_Msk); return WHAL_SUCCESS; @@ -241,6 +281,13 @@ whal_Error whal_Stm32wba_Gpdma_Start(whal_Dma *dmaDev, size_t ch) whal_Error whal_Stm32wba_Gpdma_Stop(whal_Dma *dmaDev, size_t ch) { +#if defined(WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_GPDMA_SINGLE_INSTANCE) + const whal_Stm32wba_Gpdma_Cfg *cfg = + (const whal_Stm32wba_Gpdma_Cfg *)whal_Stm32wba_Gpdma_Dev.cfg; + size_t base = whal_Stm32wba_Gpdma_Dev.base; + (void)dmaDev; +#else const whal_Stm32wba_Gpdma_Cfg *cfg; size_t base; @@ -249,6 +296,7 @@ whal_Error whal_Stm32wba_Gpdma_Stop(whal_Dma *dmaDev, size_t ch) cfg = (const whal_Stm32wba_Gpdma_Cfg *)dmaDev->cfg; base = dmaDev->base; +#endif if (ch >= cfg->numChannels) return WHAL_EINVAL; @@ -263,13 +311,19 @@ whal_Error whal_Stm32wba_Gpdma_Stop(whal_Dma *dmaDev, size_t ch) void whal_Stm32wba_Gpdma_IRQHandler(whal_Dma *dmaDev, size_t ch, whal_Stm32wba_Gpdma_Callback cb, void *ctx) { - size_t base; size_t sr; +#if defined(WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_GPDMA_SINGLE_INSTANCE) + size_t base = whal_Stm32wba_Gpdma_Dev.base; + (void)dmaDev; +#else + size_t base; if (!dmaDev) return; base = dmaDev->base; +#endif sr = whal_Reg_Read(base, GPDMA_CxSR(ch)); if (sr & GPDMA_CxSR_ALL_ERR) { diff --git a/src/eth/stm32n6_eth.c b/src/eth/stm32n6_eth.c index cab19b0..f134562 100644 --- a/src/eth/stm32n6_eth.c +++ b/src/eth/stm32n6_eth.c @@ -1,4 +1,5 @@ #include +#include "board.h" /* provides whal_Stm32n6_Eth_Dev singleton */ #include #include #include @@ -153,15 +154,11 @@ static whal_Error MdioPoll(size_t base, whal_Timeout *timeout) whal_Error whal_Stm32n6_Eth_Init(whal_Eth *ethDev) { - whal_Stm32n6_Eth_Cfg *cfg; - size_t base; + whal_Stm32n6_Eth_Cfg *cfg = + (whal_Stm32n6_Eth_Cfg *)whal_Stm32n6_Eth_Dev.cfg; + size_t base = whal_Stm32n6_Eth_Dev.base; whal_Error err; - - if (!ethDev || !ethDev->cfg) - return WHAL_EINVAL; - - cfg = (whal_Stm32n6_Eth_Cfg *)ethDev->cfg; - base = ethDev->base; + (void)ethDev; if (!cfg->txDescs || !cfg->txBufs || cfg->txDescCount == 0 || !cfg->rxDescs || !cfg->rxBufs || cfg->rxDescCount == 0 || @@ -241,13 +238,13 @@ whal_Error whal_Stm32n6_Eth_Init(whal_Eth *ethDev) /* MAC address */ whal_Reg_Write(base, ETH_MACA0LR_REG, - ((uint32_t)ethDev->macAddr[3] << 24) | - ((uint32_t)ethDev->macAddr[2] << 16) | - ((uint32_t)ethDev->macAddr[1] << 8) | - ((uint32_t)ethDev->macAddr[0])); + ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[3] << 24) | + ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[2] << 16) | + ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[1] << 8) | + ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[0])); whal_Reg_Write(base, ETH_MACA0HR_REG, - ((uint32_t)ethDev->macAddr[5] << 8) | - ((uint32_t)ethDev->macAddr[4])); + ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[5] << 8) | + ((uint32_t)whal_Stm32n6_Eth_Dev.macAddr[4])); /* Reset ring tracking state */ cfg->txHead = 0; @@ -262,10 +259,9 @@ whal_Error whal_Stm32n6_Eth_Init(whal_Eth *ethDev) whal_Error whal_Stm32n6_Eth_Deinit(whal_Eth *ethDev) { - if (!ethDev) - return WHAL_EINVAL; + (void)ethDev; - whal_Reg_Update(ethDev->base, ETH_DMAMR_REG, + whal_Reg_Update(whal_Stm32n6_Eth_Dev.base, ETH_DMAMR_REG, ETH_DMAMR_SWR_Msk, ETH_DMAMR_SWR_Msk); return WHAL_SUCCESS; @@ -274,14 +270,10 @@ whal_Error whal_Stm32n6_Eth_Deinit(whal_Eth *ethDev) whal_Error whal_Stm32n6_Eth_Start(whal_Eth *ethDev, uint8_t speed, uint8_t duplex) { - whal_Stm32n6_Eth_Cfg *cfg; - size_t base; - - if (!ethDev || !ethDev->cfg) - return WHAL_EINVAL; - - cfg = (whal_Stm32n6_Eth_Cfg *)ethDev->cfg; - base = ethDev->base; + whal_Stm32n6_Eth_Cfg *cfg = + (whal_Stm32n6_Eth_Cfg *)whal_Stm32n6_Eth_Dev.cfg; + size_t base = whal_Stm32n6_Eth_Dev.base; + (void)ethDev; /* Configure MAC speed and duplex to match PHY. PS=1 selects the * MII/RMII data path; required because the EQOS MAC defaults to GMII @@ -314,12 +306,8 @@ whal_Error whal_Stm32n6_Eth_Start(whal_Eth *ethDev, uint8_t speed, whal_Error whal_Stm32n6_Eth_Stop(whal_Eth *ethDev) { - size_t base; - - if (!ethDev) - return WHAL_EINVAL; - - base = ethDev->base; + size_t base = whal_Stm32n6_Eth_Dev.base; + (void)ethDev; /* Stop DMA TX */ whal_Reg_Update(base, ETH_DMAC0TXCR_REG, ETH_DMAC0TXCR_ST_Msk, 0); @@ -338,19 +326,18 @@ whal_Error whal_Stm32n6_Eth_Send(whal_Eth *ethDev, const void *frame, size_t len) { const uint8_t *frameBuf = (const uint8_t *)frame; - whal_Stm32n6_Eth_Cfg *cfg; + whal_Stm32n6_Eth_Cfg *cfg = + (whal_Stm32n6_Eth_Cfg *)whal_Stm32n6_Eth_Dev.cfg; + size_t base = whal_Stm32n6_Eth_Dev.base; whal_Stm32n6_Eth_TxDesc *desc; - size_t base; size_t idx; + (void)ethDev; - if (!ethDev || !ethDev->cfg || !frame || len == 0) + if (!frame || len == 0) return WHAL_EINVAL; - cfg = (whal_Stm32n6_Eth_Cfg *)ethDev->cfg; - if (len > cfg->txBufSize) return WHAL_EINVAL; - base = ethDev->base; idx = cfg->txHead; desc = &cfg->txDescs[idx]; @@ -388,18 +375,18 @@ whal_Error whal_Stm32n6_Eth_Recv(whal_Eth *ethDev, void *frame, size_t *len) { uint8_t *frameBuf = (uint8_t *)frame; - whal_Stm32n6_Eth_Cfg *cfg; + whal_Stm32n6_Eth_Cfg *cfg = + (whal_Stm32n6_Eth_Cfg *)whal_Stm32n6_Eth_Dev.cfg; + size_t base = whal_Stm32n6_Eth_Dev.base; whal_Stm32n6_Eth_RxDesc *desc; - size_t base; size_t idx; uint32_t rdes3; size_t pktLen; + (void)ethDev; - if (!ethDev || !ethDev->cfg || !frame || !len) + if (!frame || !len) return WHAL_EINVAL; - cfg = (whal_Stm32n6_Eth_Cfg *)ethDev->cfg; - base = ethDev->base; idx = cfg->rxHead; desc = &cfg->rxDescs[idx]; @@ -452,16 +439,15 @@ whal_Error whal_Stm32n6_Eth_Recv(whal_Eth *ethDev, void *frame, whal_Error whal_Stm32n6_Eth_MdioRead(whal_Eth *ethDev, uint8_t phyAddr, uint8_t reg, uint16_t *val) { - whal_Stm32n6_Eth_Cfg *cfg; - size_t base; + const whal_Stm32n6_Eth_Cfg *cfg = + (const whal_Stm32n6_Eth_Cfg *)whal_Stm32n6_Eth_Dev.cfg; + size_t base = whal_Stm32n6_Eth_Dev.base; whal_Error err; + (void)ethDev; - if (!ethDev || !ethDev->cfg || !val) + if (!val) return WHAL_EINVAL; - cfg = (whal_Stm32n6_Eth_Cfg *)ethDev->cfg; - base = ethDev->base; - err = MdioPoll(base, cfg->timeout); if (err) return err; @@ -490,15 +476,11 @@ whal_Error whal_Stm32n6_Eth_MdioRead(whal_Eth *ethDev, uint8_t phyAddr, whal_Error whal_Stm32n6_Eth_MdioWrite(whal_Eth *ethDev, uint8_t phyAddr, uint8_t reg, uint16_t val) { - whal_Stm32n6_Eth_Cfg *cfg; - size_t base; + const whal_Stm32n6_Eth_Cfg *cfg = + (const whal_Stm32n6_Eth_Cfg *)whal_Stm32n6_Eth_Dev.cfg; + size_t base = whal_Stm32n6_Eth_Dev.base; whal_Error err; - - if (!ethDev || !ethDev->cfg) - return WHAL_EINVAL; - - cfg = (whal_Stm32n6_Eth_Cfg *)ethDev->cfg; - base = ethDev->base; + (void)ethDev; err = MdioPoll(base, cfg->timeout); if (err) @@ -530,10 +512,9 @@ whal_Error whal_Stm32n6_Eth_MdioWrite(whal_Eth *ethDev, uint8_t phyAddr, whal_Error whal_Stm32n6_Eth_Ext_EnableLoopback(whal_Eth *ethDev, uint8_t enable) { - if (!ethDev) - return WHAL_EINVAL; + (void)ethDev; - whal_Reg_Update(ethDev->base, ETH_MACCR_REG, ETH_MACCR_LM_Msk, + whal_Reg_Update(whal_Stm32n6_Eth_Dev.base, ETH_MACCR_REG, ETH_MACCR_LM_Msk, whal_SetBits(ETH_MACCR_LM_Msk, ETH_MACCR_LM_Pos, enable ? 1 : 0)); diff --git a/src/flash/pic32cz_flash.c b/src/flash/pic32cz_flash.c index 79f9e2f..c8e270f 100644 --- a/src/flash/pic32cz_flash.c +++ b/src/flash/pic32cz_flash.c @@ -1,4 +1,5 @@ #include +#include "board.h" /* provides whal_Pic32cz_Flash_Dev singleton */ #include #include #include @@ -181,13 +182,8 @@ static whal_Error whal_Pic32cz_Flash_ExecCmd(size_t base, size_t cmd, whal_Error whal_Pic32cz_Flash_Init(whal_Flash *flashDev) { - size_t base; - - if (!flashDev) { - return WHAL_EINVAL; - } - - base = flashDev->base; + size_t base = whal_Pic32cz_Flash_Dev.base; + (void)flashDev; whal_Pic32cz_Flash_MutexUnlock(base); whal_Reg_Update(base, FCW_KEY_REG, 0xFFFFFFFF, 0); @@ -203,13 +199,8 @@ whal_Error whal_Pic32cz_Flash_Init(whal_Flash *flashDev) whal_Error whal_Pic32cz_Flash_Deinit(whal_Flash *flashDev) { - size_t base; - - if (!flashDev) { - return WHAL_EINVAL; - } - - base = flashDev->base; + size_t base = whal_Pic32cz_Flash_Dev.base; + (void)flashDev; whal_Pic32cz_Flash_MutexUnlock(base); whal_Reg_Update(base, FCW_KEY_REG, 0xFFFFFFFF, 0); @@ -230,46 +221,38 @@ whal_Error whal_Pic32cz_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len * Each FCW operation already requires the unlock key, providing * inherent per-operation protection. */ + (void)flashDev; (void)addr; (void)len; - if (!flashDev) { - return WHAL_EINVAL; - } - return WHAL_SUCCESS; } whal_Error whal_Pic32cz_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { + (void)flashDev; (void)addr; (void)len; - if (!flashDev) { - return WHAL_EINVAL; - } - return WHAL_SUCCESS; } whal_Error whal_Pic32cz_Flash_Read(whal_Flash *flashDev, size_t addr, void *data, size_t dataSz) { + const whal_Pic32cz_Flash_Cfg *cfg = + (const whal_Pic32cz_Flash_Cfg *)whal_Pic32cz_Flash_Dev.cfg; + size_t base = whal_Pic32cz_Flash_Dev.base; uint8_t *dataBuf = (uint8_t *)data; - size_t base; - whal_Pic32cz_Flash_Cfg *cfg; uint8_t *flashAddr = (uint8_t *)addr; whal_Error err; size_t i; + (void)flashDev; - if (!flashDev || !flashDev->cfg || !data) { + if (!data) { return WHAL_EINVAL; } - base = flashDev->base; - cfg = flashDev->cfg; - - err = whal_Pic32cz_Flash_MutexLock(base, cfg->timeout); if (err) return err; @@ -287,25 +270,24 @@ whal_Error whal_Pic32cz_Flash_Read(whal_Flash *flashDev, size_t addr, void *data whal_Error whal_Pic32cz_Flash_Write(whal_Flash *flashDev, size_t addr, const void *data, size_t dataSz) { + const whal_Pic32cz_Flash_Cfg *cfg = + (const whal_Pic32cz_Flash_Cfg *)whal_Pic32cz_Flash_Dev.cfg; + size_t base = whal_Pic32cz_Flash_Dev.base; const uint8_t *dataBuf = (const uint8_t *)data; - size_t base; - whal_Pic32cz_Flash_Cfg *cfg; const uint32_t *src; whal_Error err; size_t offset = 0; + (void)flashDev; - if (!flashDev || !flashDev->cfg || !data) { + if (!data) { return WHAL_EINVAL; } - cfg = flashDev->cfg; - /* Require double-word alignment */ if ((addr & 0x7) || (dataSz & 0x7)) { return WHAL_EINVAL; } - base = flashDev->base; src = (const uint32_t *)dataBuf; @@ -367,18 +349,13 @@ whal_Error whal_Pic32cz_Flash_Write(whal_Flash *flashDev, size_t addr, const voi whal_Error whal_Pic32cz_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t dataSz) { - size_t base; - whal_Pic32cz_Flash_Cfg *cfg; + const whal_Pic32cz_Flash_Cfg *cfg = + (const whal_Pic32cz_Flash_Cfg *)whal_Pic32cz_Flash_Dev.cfg; + size_t base = whal_Pic32cz_Flash_Dev.base; whal_Error err; size_t pageAddr; size_t endAddr; - - if (!flashDev || !flashDev->cfg) { - return WHAL_EINVAL; - } - - cfg = flashDev->cfg; - base = flashDev->base; + (void)flashDev; /* Align down to page boundary */ pageAddr = addr & ~(FCW_PAGE_SIZE - 1); diff --git a/src/flash/spi_nor_flash.c b/src/flash/spi_nor_flash.c index bfe50c5..f305411 100644 --- a/src/flash/spi_nor_flash.c +++ b/src/flash/spi_nor_flash.c @@ -1,4 +1,7 @@ #include +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE +#include "board.h" /* provides whal_SpiNor_Dev singleton */ +#endif #include #include #include @@ -151,10 +154,15 @@ whal_Error whal_SpiNor_Init(whal_Flash *flashDev) uint8_t cmd; whal_Error err; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; +#else if (!flashDev || !flashDev->cfg) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (!cfg->spiDev || !cfg->spiComCfg || !cfg->gpioDev) return WHAL_EINVAL; @@ -205,10 +213,19 @@ whal_Error whal_SpiNor_Init(whal_Flash *flashDev) whal_Error whal_SpiNor_Deinit(whal_Flash *flashDev) { + whal_SpiNor_Cfg *cfg; + +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; +#else if (!flashDev || !flashDev->cfg) return WHAL_EINVAL; - return SpiNor_CsDeassert((whal_SpiNor_Cfg *)flashDev->cfg); + cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif + + return SpiNor_CsDeassert(cfg); } whal_Error whal_SpiNor_Lock(whal_Flash *flashDev, size_t addr, size_t len) @@ -220,10 +237,15 @@ whal_Error whal_SpiNor_Lock(whal_Flash *flashDev, size_t addr, size_t len) (void)addr; (void)len; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; +#else if (!flashDev || !flashDev->cfg) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif err = whal_Spi_StartCom(cfg->spiDev, cfg->spiComCfg); if (err) @@ -262,10 +284,15 @@ whal_Error whal_SpiNor_Unlock(whal_Flash *flashDev, size_t addr, size_t len) (void)addr; (void)len; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; +#else if (!flashDev || !flashDev->cfg) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif err = whal_Spi_StartCom(cfg->spiDev, cfg->spiComCfg); if (err) @@ -303,10 +330,18 @@ whal_Error whal_SpiNor3b_Read(whal_Flash *flashDev, size_t addr, void *data, uint8_t frame[4]; whal_Error err; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (!data || dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || !data || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr & ~0xFFFFFF || addr >= cfg->capacity || dataSz > cfg->capacity - addr) @@ -345,10 +380,18 @@ whal_Error whal_SpiNor3b_Write(whal_Flash *flashDev, size_t addr, size_t offset; size_t pageRemaining; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (!data || dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || !data || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr & ~0xFFFFFF || addr >= cfg->capacity || dataSz > cfg->capacity - addr) @@ -409,10 +452,18 @@ whal_Error whal_SpiNor3b_Erase4k(whal_Flash *flashDev, size_t addr, size_t end; size_t cur; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr & ~0xFFFFFF || addr >= cfg->capacity || dataSz > cfg->capacity - addr) @@ -465,10 +516,18 @@ whal_Error whal_SpiNor3b_Erase32k(whal_Flash *flashDev, size_t addr, size_t end; size_t cur; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr & ~0xFFFFFF || addr >= cfg->capacity || dataSz > cfg->capacity - addr) @@ -521,10 +580,18 @@ whal_Error whal_SpiNor3b_Erase64k(whal_Flash *flashDev, size_t addr, size_t end; size_t cur; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr & ~0xFFFFFF || addr >= cfg->capacity || dataSz > cfg->capacity - addr) @@ -577,10 +644,15 @@ whal_Error whal_SpiNor_EraseChip(whal_Flash *flashDev, size_t addr, (void)addr; (void)dataSz; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; +#else if (!flashDev || !flashDev->cfg) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif err = whal_Spi_StartCom(cfg->spiDev, cfg->spiComCfg); if (err) @@ -608,10 +680,18 @@ whal_Error whal_SpiNor3b_ReadFast(whal_Flash *flashDev, size_t addr, uint8_t frame[5]; whal_Error err; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (!data || dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || !data || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr & ~0xFFFFFF || addr >= cfg->capacity || dataSz > cfg->capacity - addr) @@ -651,7 +731,12 @@ whal_Error whal_SpiNor4bMode_Init(whal_Flash *flashDev) if (err) return err; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; +#else cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif err = whal_Spi_StartCom(cfg->spiDev, cfg->spiComCfg); if (err) @@ -671,10 +756,18 @@ whal_Error whal_SpiNor4b_Read(whal_Flash *flashDev, size_t addr, uint8_t frame[5]; whal_Error err; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (!data || dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || !data || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr >= cfg->capacity || dataSz > cfg->capacity - addr) return WHAL_EINVAL; @@ -709,10 +802,18 @@ whal_Error whal_SpiNor4b_ReadFast(whal_Flash *flashDev, size_t addr, uint8_t frame[6]; whal_Error err; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (!data || dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || !data || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr >= cfg->capacity || dataSz > cfg->capacity - addr) return WHAL_EINVAL; @@ -751,10 +852,18 @@ whal_Error whal_SpiNor4b_Write(whal_Flash *flashDev, size_t addr, size_t offset; size_t pageRemaining; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (!data || dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || !data || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr >= cfg->capacity || dataSz > cfg->capacity - addr) return WHAL_EINVAL; @@ -809,10 +918,18 @@ whal_Error whal_SpiNor4b_Erase4k(whal_Flash *flashDev, size_t addr, size_t end; size_t cur; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr >= cfg->capacity || dataSz > cfg->capacity - addr) return WHAL_EINVAL; @@ -864,10 +981,18 @@ whal_Error whal_SpiNor4b_Erase64k(whal_Flash *flashDev, size_t addr, size_t end; size_t cur; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr >= cfg->capacity || dataSz > cfg->capacity - addr) return WHAL_EINVAL; @@ -920,10 +1045,18 @@ whal_Error whal_SpiNor4bMode_Read(whal_Flash *flashDev, size_t addr, uint8_t frame[5]; whal_Error err; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (!data || dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || !data || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr >= cfg->capacity || dataSz > cfg->capacity - addr) return WHAL_EINVAL; @@ -958,10 +1091,18 @@ whal_Error whal_SpiNor4bMode_ReadFast(whal_Flash *flashDev, size_t addr, uint8_t frame[6]; whal_Error err; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (!data || dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || !data || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr >= cfg->capacity || dataSz > cfg->capacity - addr) return WHAL_EINVAL; @@ -1000,10 +1141,18 @@ whal_Error whal_SpiNor4bMode_Write(whal_Flash *flashDev, size_t addr, size_t offset; size_t pageRemaining; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (!data || dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || !data || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr >= cfg->capacity || dataSz > cfg->capacity - addr) return WHAL_EINVAL; @@ -1058,10 +1207,18 @@ whal_Error whal_SpiNor4bMode_Erase4k(whal_Flash *flashDev, size_t addr, size_t end; size_t cur; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr >= cfg->capacity || dataSz > cfg->capacity - addr) return WHAL_EINVAL; @@ -1113,10 +1270,18 @@ whal_Error whal_SpiNor4bMode_Erase32k(whal_Flash *flashDev, size_t addr, size_t end; size_t cur; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr >= cfg->capacity || dataSz > cfg->capacity - addr) return WHAL_EINVAL; @@ -1168,10 +1333,18 @@ whal_Error whal_SpiNor4bMode_Erase64k(whal_Flash *flashDev, size_t addr, size_t end; size_t cur; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr >= cfg->capacity || dataSz > cfg->capacity - addr) return WHAL_EINVAL; @@ -1250,10 +1423,18 @@ whal_Error whal_SpiNor4bExReg_Read(whal_Flash *flashDev, size_t addr, size_t chunk; size_t bankRemaining; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (!data || dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || !data || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr >= cfg->capacity || dataSz > cfg->capacity - addr) return WHAL_EINVAL; @@ -1308,10 +1489,18 @@ whal_Error whal_SpiNor4bExReg_ReadFast(whal_Flash *flashDev, size_t addr, size_t chunk; size_t bankRemaining; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (!data || dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || !data || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr >= cfg->capacity || dataSz > cfg->capacity - addr) return WHAL_EINVAL; @@ -1367,10 +1556,18 @@ whal_Error whal_SpiNor4bExReg_Write(whal_Flash *flashDev, size_t addr, size_t offset; size_t pageRemaining; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (!data || dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || !data || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr >= cfg->capacity || dataSz > cfg->capacity - addr) return WHAL_EINVAL; @@ -1429,10 +1626,18 @@ whal_Error whal_SpiNor4bExReg_Erase4k(whal_Flash *flashDev, size_t addr, size_t end; size_t cur; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr >= cfg->capacity || dataSz > cfg->capacity - addr) return WHAL_EINVAL; @@ -1488,10 +1693,18 @@ whal_Error whal_SpiNor4bExReg_Erase32k(whal_Flash *flashDev, size_t addr, size_t end; size_t cur; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr >= cfg->capacity || dataSz > cfg->capacity - addr) return WHAL_EINVAL; @@ -1547,10 +1760,18 @@ whal_Error whal_SpiNor4bExReg_Erase64k(whal_Flash *flashDev, size_t addr, size_t end; size_t cur; +#ifdef WHAL_CFG_SPI_NOR_SINGLE_INSTANCE + cfg = (whal_SpiNor_Cfg *)whal_SpiNor_Dev.cfg; + (void)flashDev; + + if (dataSz == 0) + return WHAL_EINVAL; +#else if (!flashDev || !flashDev->cfg || dataSz == 0) return WHAL_EINVAL; cfg = (whal_SpiNor_Cfg *)flashDev->cfg; +#endif if (addr >= cfg->capacity || dataSz > cfg->capacity - addr) return WHAL_EINVAL; diff --git a/src/flash/stm32c0_flash.c b/src/flash/stm32c0_flash.c index c027761..0b4c14d 100644 --- a/src/flash/stm32c0_flash.c +++ b/src/flash/stm32c0_flash.c @@ -1,4 +1,5 @@ #include +#include "board.h" /* provides whal_Stm32c0_Flash_Dev singleton */ #include #include #include @@ -112,17 +113,11 @@ whal_Error whal_Stm32c0_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32c0_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base; - + size_t base = whal_Stm32c0_Flash_Dev.base; + (void)flashDev; (void)addr; (void)len; - if (!flashDev) { - return WHAL_EINVAL; - } - - base = flashDev->base; - /* Setting LOCK bit prevents further flash modifications until next unlock */ whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, whal_SetBits(FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, 1)); @@ -132,17 +127,11 @@ whal_Error whal_Stm32c0_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len whal_Error whal_Stm32c0_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base; - + size_t base = whal_Stm32c0_Flash_Dev.base; + (void)flashDev; (void)addr; (void)len; - if (!flashDev) { - return WHAL_EINVAL; - } - - base = flashDev->base; - /* * Unlock sequence: write KEY1 then KEY2 to KEYR register. * Incorrect sequence or order will trigger a bus error. @@ -156,17 +145,17 @@ whal_Error whal_Stm32c0_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t l whal_Error whal_Stm32c0_Flash_Read(whal_Flash *flashDev, size_t addr, void *data, size_t dataSz) { - whal_Stm32c0_Flash_Cfg *cfg; + const whal_Stm32c0_Flash_Cfg *cfg = + (const whal_Stm32c0_Flash_Cfg *)whal_Stm32c0_Flash_Dev.cfg; uint8_t *dataBuf = (uint8_t *)data; + (void)flashDev; - if (!flashDev || !flashDev->cfg || !data) + if (!data) return WHAL_EINVAL; if (dataSz == 0) return WHAL_SUCCESS; - cfg = flashDev->cfg; - if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) return WHAL_EINVAL; @@ -187,16 +176,11 @@ whal_Error whal_Stm32c0_Flash_Read(whal_Flash *flashDev, size_t addr, void *data static whal_Error whal_Stm32c0_Flash_WriteOrErase(whal_Flash *flashDev, size_t addr, const uint8_t *data, size_t dataSz, uint8_t write) { - whal_Stm32c0_Flash_Cfg *cfg; - size_t base; + const whal_Stm32c0_Flash_Cfg *cfg = + (const whal_Stm32c0_Flash_Cfg *)whal_Stm32c0_Flash_Dev.cfg; + size_t base = whal_Stm32c0_Flash_Dev.base; size_t bsy; - - if (!flashDev || !flashDev->cfg) { - return WHAL_EINVAL; - } - - cfg = flashDev->cfg; - base = flashDev->base; + (void)flashDev; if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) return WHAL_EINVAL; @@ -294,11 +278,9 @@ whal_Error whal_Stm32c0_Flash_Erase(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32c0_Flash_Ext_SetLatency(whal_Flash *flashDev, enum whal_Stm32c0_Flash_Latency latency) { - if (!flashDev) { - return WHAL_EINVAL; - } + size_t base = whal_Stm32c0_Flash_Dev.base; + (void)flashDev; - size_t base = flashDev->base; whal_Reg_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); return WHAL_SUCCESS; } diff --git a/src/flash/stm32f0_flash.c b/src/flash/stm32f0_flash.c index becfc99..7e6af3a 100644 --- a/src/flash/stm32f0_flash.c +++ b/src/flash/stm32f0_flash.c @@ -1,4 +1,5 @@ #include +#include "board.h" /* provides whal_Stm32f0_Flash_Dev singleton */ #include #include #include @@ -62,13 +63,12 @@ whal_Error whal_Stm32f0_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32f0_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { + size_t base = whal_Stm32f0_Flash_Dev.base; + (void)flashDev; (void)addr; (void)len; - if (!flashDev) - return WHAL_EINVAL; - - whal_Reg_Update(flashDev->base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, + whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, whal_SetBits(FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, 1)); return WHAL_SUCCESS; @@ -76,15 +76,14 @@ whal_Error whal_Stm32f0_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len whal_Error whal_Stm32f0_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { + size_t base = whal_Stm32f0_Flash_Dev.base; + (void)flashDev; (void)addr; (void)len; - if (!flashDev) - return WHAL_EINVAL; - - whal_Reg_Update(flashDev->base, FLASH_KEYR_REG, + whal_Reg_Update(base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0x45670123); - whal_Reg_Update(flashDev->base, FLASH_KEYR_REG, + whal_Reg_Update(base, FLASH_KEYR_REG, FLASH_KEYR_KEY_Msk, 0xCDEF89AB); return WHAL_SUCCESS; @@ -93,17 +92,17 @@ whal_Error whal_Stm32f0_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t l whal_Error whal_Stm32f0_Flash_Read(whal_Flash *flashDev, size_t addr, void *data, size_t dataSz) { - whal_Stm32f0_Flash_Cfg *cfg; + const whal_Stm32f0_Flash_Cfg *cfg = + (const whal_Stm32f0_Flash_Cfg *)whal_Stm32f0_Flash_Dev.cfg; uint8_t *dataBuf = (uint8_t *)data; + (void)flashDev; - if (!flashDev || !flashDev->cfg || !data) + if (!data) return WHAL_EINVAL; if (dataSz == 0) return WHAL_SUCCESS; - cfg = flashDev->cfg; - if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) return WHAL_EINVAL; @@ -119,15 +118,11 @@ static whal_Error whal_Stm32f0_Flash_WriteOrErase(whal_Flash *flashDev, const uint8_t *data, size_t dataSz, uint8_t write) { - whal_Stm32f0_Flash_Cfg *cfg; - size_t base; + const whal_Stm32f0_Flash_Cfg *cfg = + (const whal_Stm32f0_Flash_Cfg *)whal_Stm32f0_Flash_Dev.cfg; + size_t base = whal_Stm32f0_Flash_Dev.base; size_t bsy; - - if (!flashDev || !flashDev->cfg) - return WHAL_EINVAL; - - cfg = flashDev->cfg; - base = flashDev->base; + (void)flashDev; if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) return WHAL_EINVAL; @@ -218,10 +213,10 @@ whal_Error whal_Stm32f0_Flash_Erase(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32f0_Flash_Ext_SetLatency(whal_Flash *flashDev, enum whal_Stm32f0_Flash_Latency latency) { - if (!flashDev) - return WHAL_EINVAL; + size_t base = whal_Stm32f0_Flash_Dev.base; + (void)flashDev; - whal_Reg_Update(flashDev->base, FLASH_ACR_REG, + whal_Reg_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); return WHAL_SUCCESS; } diff --git a/src/flash/stm32f4_flash.c b/src/flash/stm32f4_flash.c index fd0b3ca..c133218 100644 --- a/src/flash/stm32f4_flash.c +++ b/src/flash/stm32f4_flash.c @@ -1,4 +1,5 @@ #include +#include "board.h" /* provides whal_Stm32f4_Flash_Dev singleton */ #include #include #include @@ -104,16 +105,11 @@ whal_Error whal_Stm32f4_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32f4_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base; - + size_t base = whal_Stm32f4_Flash_Dev.base; + (void)flashDev; (void)addr; (void)len; - if (!flashDev) - return WHAL_EINVAL; - - base = flashDev->base; - whal_Reg_Update(base, FLASH_CR_REG, FLASH_CR_LOCK_Msk, whal_SetBits(FLASH_CR_LOCK_Msk, FLASH_CR_LOCK_Pos, 1)); @@ -122,16 +118,11 @@ whal_Error whal_Stm32f4_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len whal_Error whal_Stm32f4_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base; - + size_t base = whal_Stm32f4_Flash_Dev.base; + (void)flashDev; (void)addr; (void)len; - if (!flashDev) - return WHAL_EINVAL; - - base = flashDev->base; - whal_Reg_Write(base, FLASH_KEYR_REG, FLASH_KEY1); whal_Reg_Write(base, FLASH_KEYR_REG, FLASH_KEY2); @@ -141,14 +132,14 @@ whal_Error whal_Stm32f4_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t l whal_Error whal_Stm32f4_Flash_Read(whal_Flash *flashDev, size_t addr, void *data, size_t dataSz) { + const whal_Stm32f4_Flash_Cfg *cfg = + (const whal_Stm32f4_Flash_Cfg *)whal_Stm32f4_Flash_Dev.cfg; uint8_t *dataBuf = (uint8_t *)data; - whal_Stm32f4_Flash_Cfg *cfg; + (void)flashDev; - if (!flashDev || !flashDev->cfg || !data) + if (!data) return WHAL_EINVAL; - cfg = flashDev->cfg; - if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) return WHAL_EINVAL; @@ -162,17 +153,16 @@ whal_Error whal_Stm32f4_Flash_Read(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32f4_Flash_Write(whal_Flash *flashDev, size_t addr, const void *data, size_t dataSz) { + const whal_Stm32f4_Flash_Cfg *cfg = + (const whal_Stm32f4_Flash_Cfg *)whal_Stm32f4_Flash_Dev.cfg; + size_t base = whal_Stm32f4_Flash_Dev.base; const uint8_t *dataBuf = (const uint8_t *)data; - whal_Stm32f4_Flash_Cfg *cfg; - size_t base; whal_Error err = WHAL_SUCCESS; + (void)flashDev; - if (!flashDev || !flashDev->cfg || !data) + if (!data) return WHAL_EINVAL; - cfg = flashDev->cfg; - base = flashDev->base; - /* Address and size must be 4-byte aligned for word programming */ if ((addr & 0x3) || (dataSz & 0x3)) return WHAL_EINVAL; @@ -226,15 +216,11 @@ whal_Error whal_Stm32f4_Flash_Write(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32f4_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t dataSz) { - whal_Stm32f4_Flash_Cfg *cfg; - size_t base; + const whal_Stm32f4_Flash_Cfg *cfg = + (const whal_Stm32f4_Flash_Cfg *)whal_Stm32f4_Flash_Dev.cfg; + size_t base = whal_Stm32f4_Flash_Dev.base; whal_Error err = WHAL_SUCCESS; - - if (!flashDev || !flashDev->cfg) - return WHAL_EINVAL; - - cfg = flashDev->cfg; - base = flashDev->base; + (void)flashDev; if (dataSz == 0) return WHAL_SUCCESS; @@ -295,10 +281,9 @@ whal_Error whal_Stm32f4_Flash_Erase(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32f4_Flash_Ext_SetLatency(whal_Flash *flashDev, enum whal_Stm32f4_Flash_Latency latency) { - if (!flashDev) - return WHAL_EINVAL; + size_t base = whal_Stm32f4_Flash_Dev.base; + (void)flashDev; - size_t base = flashDev->base; whal_Reg_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, whal_SetBits(FLASH_ACR_LATENCY_Msk, FLASH_ACR_LATENCY_Pos, latency)); return WHAL_SUCCESS; diff --git a/src/flash/stm32h5_flash.c b/src/flash/stm32h5_flash.c index 6f1da8e..c38aff8 100644 --- a/src/flash/stm32h5_flash.c +++ b/src/flash/stm32h5_flash.c @@ -1,4 +1,5 @@ #include +#include "board.h" /* provides whal_Stm32h5_Flash_Dev singleton */ #include #include #include @@ -134,16 +135,11 @@ whal_Error whal_Stm32h5_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32h5_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base; - + size_t base = whal_Stm32h5_Flash_Dev.base; + (void)flashDev; (void)addr; (void)len; - if (!flashDev) - return WHAL_EINVAL; - - base = flashDev->base; - whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_LOCK_Msk, whal_SetBits(FLASH_NSCR_LOCK_Msk, FLASH_NSCR_LOCK_Pos, 1)); @@ -153,16 +149,11 @@ whal_Error whal_Stm32h5_Flash_Lock(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32h5_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { - size_t base; - + size_t base = whal_Stm32h5_Flash_Dev.base; + (void)flashDev; (void)addr; (void)len; - if (!flashDev) - return WHAL_EINVAL; - - base = flashDev->base; - whal_Reg_Write(base, FLASH_NSKEYR_REG, FLASH_KEY1); whal_Reg_Write(base, FLASH_NSKEYR_REG, FLASH_KEY2); @@ -172,14 +163,14 @@ whal_Error whal_Stm32h5_Flash_Unlock(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32h5_Flash_Read(whal_Flash *flashDev, size_t addr, void *data, size_t dataSz) { + const whal_Stm32h5_Flash_Cfg *cfg = + (const whal_Stm32h5_Flash_Cfg *)whal_Stm32h5_Flash_Dev.cfg; uint8_t *dataBuf = (uint8_t *)data; - whal_Stm32h5_Flash_Cfg *cfg; + (void)flashDev; - if (!flashDev || !flashDev->cfg || !data) + if (!data) return WHAL_EINVAL; - cfg = flashDev->cfg; - if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) return WHAL_EINVAL; @@ -210,17 +201,16 @@ static whal_Error CheckErrors(size_t base) whal_Error whal_Stm32h5_Flash_Write(whal_Flash *flashDev, size_t addr, const void *data, size_t dataSz) { + const whal_Stm32h5_Flash_Cfg *cfg = + (const whal_Stm32h5_Flash_Cfg *)whal_Stm32h5_Flash_Dev.cfg; + size_t base = whal_Stm32h5_Flash_Dev.base; const uint8_t *dataBuf = (const uint8_t *)data; - whal_Stm32h5_Flash_Cfg *cfg; - size_t base; whal_Error err; + (void)flashDev; - if (!flashDev || !flashDev->cfg || !data) + if (!data) return WHAL_EINVAL; - cfg = flashDev->cfg; - base = flashDev->base; - /* Address and size must be 16-byte aligned (128-bit flash-word) */ if ((addr & 0xF) || (dataSz & 0xF)) return WHAL_EINVAL; @@ -269,17 +259,13 @@ whal_Error whal_Stm32h5_Flash_Write(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32h5_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t dataSz) { - whal_Stm32h5_Flash_Cfg *cfg; - size_t base; + const whal_Stm32h5_Flash_Cfg *cfg = + (const whal_Stm32h5_Flash_Cfg *)whal_Stm32h5_Flash_Dev.cfg; + size_t base = whal_Stm32h5_Flash_Dev.base; whal_Error err; size_t offset; size_t startSector, endSector; - - if (!flashDev || !flashDev->cfg) - return WHAL_EINVAL; - - cfg = flashDev->cfg; - base = flashDev->base; + (void)flashDev; if (dataSz == 0) return WHAL_SUCCESS; @@ -335,10 +321,10 @@ whal_Error whal_Stm32h5_Flash_Erase(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32h5_Flash_Ext_SetLatency(whal_Flash *flashDev, uint8_t latency) { - if (!flashDev) - return WHAL_EINVAL; + size_t base = whal_Stm32h5_Flash_Dev.base; + (void)flashDev; - whal_Reg_Update(flashDev->base, FLASH_ACR_REG, + whal_Reg_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_WRHIGHFREQ_Msk, latency); return WHAL_SUCCESS; diff --git a/src/flash/stm32l1_flash.c b/src/flash/stm32l1_flash.c index 2c14873..093fef6 100644 --- a/src/flash/stm32l1_flash.c +++ b/src/flash/stm32l1_flash.c @@ -1,4 +1,5 @@ #include +#include "board.h" /* provides whal_Stm32l1_Flash_Dev singleton */ #include #include #include @@ -119,14 +120,13 @@ whal_Error whal_Stm32l1_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32l1_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { + size_t base = whal_Stm32l1_Flash_Dev.base; + (void)flashDev; (void)addr; (void)len; - if (!flashDev) - return WHAL_EINVAL; - /* Set PELOCK to lock everything */ - whal_Reg_Update(flashDev->base, FLASH_PECR_REG, + whal_Reg_Update(base, FLASH_PECR_REG, FLASH_PECR_PELOCK_Msk, whal_SetBits(FLASH_PECR_PELOCK_Msk, FLASH_PECR_PELOCK_Pos, 1)); @@ -136,14 +136,11 @@ whal_Error whal_Stm32l1_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len whal_Error whal_Stm32l1_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { + size_t base = whal_Stm32l1_Flash_Dev.base; + (void)flashDev; (void)addr; (void)len; - if (!flashDev) - return WHAL_EINVAL; - - size_t base = flashDev->base; - /* Unlock PECR then program memory */ UnlockPecr(base); UnlockProgram(base); @@ -154,17 +151,17 @@ whal_Error whal_Stm32l1_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t l whal_Error whal_Stm32l1_Flash_Read(whal_Flash *flashDev, size_t addr, void *data, size_t dataSz) { - whal_Stm32l1_Flash_Cfg *cfg; + const whal_Stm32l1_Flash_Cfg *cfg = + (const whal_Stm32l1_Flash_Cfg *)whal_Stm32l1_Flash_Dev.cfg; uint8_t *dataBuf = (uint8_t *)data; + (void)flashDev; - if (!flashDev || !flashDev->cfg || !data) + if (!data) return WHAL_EINVAL; if (dataSz == 0) return WHAL_SUCCESS; - cfg = flashDev->cfg; - if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) return WHAL_EINVAL; @@ -179,12 +176,14 @@ whal_Error whal_Stm32l1_Flash_Read(whal_Flash *flashDev, size_t addr, void *data whal_Error whal_Stm32l1_Flash_Write(whal_Flash *flashDev, size_t addr, const void *data, size_t dataSz) { - whal_Stm32l1_Flash_Cfg *cfg; + const whal_Stm32l1_Flash_Cfg *cfg = + (const whal_Stm32l1_Flash_Cfg *)whal_Stm32l1_Flash_Dev.cfg; + size_t base = whal_Stm32l1_Flash_Dev.base; const uint8_t *buf = (const uint8_t *)data; - size_t base; whal_Error err = WHAL_SUCCESS; + (void)flashDev; - if (!flashDev || !flashDev->cfg || !data) + if (!data) return WHAL_EINVAL; if (dataSz == 0) @@ -194,9 +193,6 @@ whal_Error whal_Stm32l1_Flash_Write(whal_Flash *flashDev, size_t addr, if ((addr & 0x3) || (dataSz & 0x3)) return WHAL_EINVAL; - cfg = flashDev->cfg; - base = flashDev->base; - if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) return WHAL_EINVAL; @@ -232,19 +228,15 @@ whal_Error whal_Stm32l1_Flash_Write(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32l1_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t dataSz) { - whal_Stm32l1_Flash_Cfg *cfg; - size_t base; + const whal_Stm32l1_Flash_Cfg *cfg = + (const whal_Stm32l1_Flash_Cfg *)whal_Stm32l1_Flash_Dev.cfg; + size_t base = whal_Stm32l1_Flash_Dev.base; whal_Error err = WHAL_SUCCESS; - - if (!flashDev || !flashDev->cfg) - return WHAL_EINVAL; + (void)flashDev; if (dataSz == 0) return WHAL_SUCCESS; - cfg = flashDev->cfg; - base = flashDev->base; - if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) return WHAL_EINVAL; diff --git a/src/flash/stm32wba_flash.c b/src/flash/stm32wba_flash.c index c87f410..7d82f30 100644 --- a/src/flash/stm32wba_flash.c +++ b/src/flash/stm32wba_flash.c @@ -1,4 +1,5 @@ #include +#include "board.h" /* provides whal_Stm32wba_Flash_Dev singleton */ #include #include #include @@ -6,6 +7,16 @@ #include #include +#ifdef WHAL_CFG_STM32WBA_FLASH_DIRECT_API_MAPPING +#define whal_Stm32wba_Flash_Init whal_Flash_Init +#define whal_Stm32wba_Flash_Deinit whal_Flash_Deinit +#define whal_Stm32wba_Flash_Lock whal_Flash_Lock +#define whal_Stm32wba_Flash_Unlock whal_Flash_Unlock +#define whal_Stm32wba_Flash_Read whal_Flash_Read +#define whal_Stm32wba_Flash_Write whal_Flash_Write +#define whal_Stm32wba_Flash_Erase whal_Flash_Erase +#endif /* WHAL_CFG_STM32WBA_FLASH_DIRECT_API_MAPPING */ + /* * STM32WBA Flash Register Definitions (RM0493) * @@ -86,13 +97,12 @@ whal_Error whal_Stm32wba_Flash_Deinit(whal_Flash *flashDev) whal_Error whal_Stm32wba_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) { + size_t base = whal_Stm32wba_Flash_Dev.base; + (void)flashDev; (void)addr; (void)len; - if (!flashDev) - return WHAL_EINVAL; - - whal_Reg_Update(flashDev->base, FLASH_NSCR1_REG, FLASH_NSCR1_LOCK_Msk, + whal_Reg_Update(base, FLASH_NSCR1_REG, FLASH_NSCR1_LOCK_Msk, whal_SetBits(FLASH_NSCR1_LOCK_Msk, FLASH_NSCR1_LOCK_Pos, 1)); return WHAL_SUCCESS; @@ -100,16 +110,15 @@ whal_Error whal_Stm32wba_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t le whal_Error whal_Stm32wba_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) { + size_t base = whal_Stm32wba_Flash_Dev.base; + (void)flashDev; (void)addr; (void)len; - if (!flashDev) - return WHAL_EINVAL; - /* Only write the unlock sequence if LOCK bit is set */ - if (whal_Reg_Read(flashDev->base, FLASH_NSCR1_REG) & FLASH_NSCR1_LOCK_Msk) { - whal_Reg_Write(flashDev->base, FLASH_NSKEYR_REG, FLASH_KEY1); - whal_Reg_Write(flashDev->base, FLASH_NSKEYR_REG, FLASH_KEY2); + if (whal_Reg_Read(base, FLASH_NSCR1_REG) & FLASH_NSCR1_LOCK_Msk) { + whal_Reg_Write(base, FLASH_NSKEYR_REG, FLASH_KEY1); + whal_Reg_Write(base, FLASH_NSKEYR_REG, FLASH_KEY2); } return WHAL_SUCCESS; @@ -117,14 +126,14 @@ whal_Error whal_Stm32wba_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t whal_Error whal_Stm32wba_Flash_Read(whal_Flash *flashDev, size_t addr, void *data, size_t dataSz) { + const whal_Stm32wba_Flash_Cfg *cfg = + (const whal_Stm32wba_Flash_Cfg *)whal_Stm32wba_Flash_Dev.cfg; uint8_t *dataBuf = (uint8_t *)data; - whal_Stm32wba_Flash_Cfg *cfg; + (void)flashDev; - if (!flashDev || !flashDev->cfg || !data) + if (!data) return WHAL_EINVAL; - cfg = flashDev->cfg; - if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) return WHAL_EINVAL; @@ -154,17 +163,16 @@ static whal_Error CheckAndClearErrors(size_t base) whal_Error whal_Stm32wba_Flash_Write(whal_Flash *flashDev, size_t addr, const void *data, size_t dataSz) { + const whal_Stm32wba_Flash_Cfg *cfg = + (const whal_Stm32wba_Flash_Cfg *)whal_Stm32wba_Flash_Dev.cfg; + size_t base = whal_Stm32wba_Flash_Dev.base; const uint8_t *dataBuf = (const uint8_t *)data; - whal_Stm32wba_Flash_Cfg *cfg; - size_t base; whal_Error err; + (void)flashDev; - if (!flashDev || !flashDev->cfg || !data) + if (!data) return WHAL_EINVAL; - cfg = flashDev->cfg; - base = flashDev->base; - /* Address and size must be 16-byte aligned (128-bit flash-word) */ if ((addr & 0xF) || (dataSz & 0xF)) return WHAL_EINVAL; @@ -210,16 +218,12 @@ whal_Error whal_Stm32wba_Flash_Write(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32wba_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t dataSz) { - whal_Stm32wba_Flash_Cfg *cfg; - size_t base; + const whal_Stm32wba_Flash_Cfg *cfg = + (const whal_Stm32wba_Flash_Cfg *)whal_Stm32wba_Flash_Dev.cfg; + size_t base = whal_Stm32wba_Flash_Dev.base; whal_Error err; size_t offset, startPage, endPage; - - if (!flashDev || !flashDev->cfg) - return WHAL_EINVAL; - - cfg = flashDev->cfg; - base = flashDev->base; + (void)flashDev; if (dataSz == 0) return WHAL_SUCCESS; @@ -263,13 +267,14 @@ whal_Error whal_Stm32wba_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t d whal_Error whal_Stm32wba_Flash_Ext_SetLatency(whal_Flash *flashDev, uint8_t latency) { - if (!flashDev) - return WHAL_EINVAL; + size_t base = whal_Stm32wba_Flash_Dev.base; + (void)flashDev; - whal_Reg_Update(flashDev->base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); + whal_Reg_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); return WHAL_SUCCESS; } +#ifndef WHAL_CFG_STM32WBA_FLASH_DIRECT_API_MAPPING const whal_FlashDriver whal_Stm32wba_Flash_Driver = { .Init = whal_Stm32wba_Flash_Init, .Deinit = whal_Stm32wba_Flash_Deinit, @@ -279,3 +284,4 @@ const whal_FlashDriver whal_Stm32wba_Flash_Driver = { .Write = whal_Stm32wba_Flash_Write, .Erase = whal_Stm32wba_Flash_Erase, }; +#endif /* !WHAL_CFG_STM32WBA_FLASH_DIRECT_API_MAPPING */ diff --git a/src/gpio/pic32cz_gpio.c b/src/gpio/pic32cz_gpio.c index c52d07c..4bba404 100644 --- a/src/gpio/pic32cz_gpio.c +++ b/src/gpio/pic32cz_gpio.c @@ -1,3 +1,4 @@ +#include "board.h" /* provides whal_Pic32cz_Gpio_Dev singleton */ #include #include #include @@ -61,11 +62,10 @@ whal_Error whal_Pic32cz_Gpio_Init(whal_Gpio *gpioDev) { - if (!gpioDev || !gpioDev->cfg) { - return WHAL_EINVAL; - } - - const whal_Pic32cz_Gpio_Cfg *cfg = gpioDev->cfg; + const whal_Pic32cz_Gpio_Cfg *cfg = + (const whal_Pic32cz_Gpio_Cfg *)whal_Pic32cz_Gpio_Dev.cfg; + size_t base = whal_Pic32cz_Gpio_Dev.base; + (void)gpioDev; for (size_t i = 0; i < cfg->pinCfgCount; ++i) { whal_Pic32cz_Gpio_PinCfg *pinCfg = &cfg->pinCfg[i]; @@ -82,12 +82,12 @@ whal_Error whal_Pic32cz_Gpio_Init(whal_Gpio *gpioDev) size_t pmuxenMask = PINCFGx_PMUXEN_Msk(pinCfg->pin); size_t pmuxenPos = PINCFGx_PMUXEN_Pos(pinCfg->pin); - whal_Reg_Update(gpioDev->base, + whal_Reg_Update(base, PMUXx_REG(pinCfg->port, pinCfg->pin), pmuxMask, whal_SetBits(pmuxMask, pmuxPos, pinCfg->pmux)); - whal_Reg_Update(gpioDev->base, + whal_Reg_Update(base, PINCFGx_REG(pinCfg->port, pinCfg->pin), pmuxenMask, whal_SetBits(pmuxenMask, pmuxenPos, 1)); @@ -103,12 +103,12 @@ whal_Error whal_Pic32cz_Gpio_Init(whal_Gpio *gpioDev) */ /* Set pin direction */ - whal_Reg_Update(gpioDev->base, DIR_REG(pinCfg->port), + whal_Reg_Update(base, DIR_REG(pinCfg->port), pinMask, whal_SetBits(pinMask, pinCfg->pin, pinCfg->dir)); /* Set initial output value */ - whal_Reg_Update(gpioDev->base, OUT_REG(pinCfg->port), + whal_Reg_Update(base, OUT_REG(pinCfg->port), pinMask, whal_SetBits(pinMask, pinCfg->pin, pinCfg->out)); @@ -119,7 +119,7 @@ whal_Error whal_Pic32cz_Gpio_Init(whal_Gpio *gpioDev) size_t pullenMask = PINCFGx_PULLEN_Msk(pinCfg->pin); size_t pullenPos = PINCFGx_PULLEN_Pos(pinCfg->pin); - whal_Reg_Update(gpioDev->base, + whal_Reg_Update(base, PINCFGx_REG(pinCfg->port, pinCfg->pin), inenMask | pullenMask, whal_SetBits(inenMask, inenPos, pinCfg->inEn) | @@ -132,28 +132,25 @@ whal_Error whal_Pic32cz_Gpio_Init(whal_Gpio *gpioDev) whal_Error whal_Pic32cz_Gpio_Deinit(whal_Gpio *gpioDev) { - if (!gpioDev) { - return WHAL_EINVAL; - } - + (void)gpioDev; return WHAL_SUCCESS; } whal_Error whal_Pic32cz_Gpio_Get(whal_Gpio *gpioDev, size_t pin, size_t *value) { - if (!gpioDev || !gpioDev->cfg || !value) { - return WHAL_EINVAL; - } - - const whal_Pic32cz_Gpio_Cfg *cfg = gpioDev->cfg; + const whal_Pic32cz_Gpio_Cfg *cfg = + (const whal_Pic32cz_Gpio_Cfg *)whal_Pic32cz_Gpio_Dev.cfg; + size_t base = whal_Pic32cz_Gpio_Dev.base; + whal_Pic32cz_Gpio_PinCfg *pinCfg; + size_t pinMask; + size_t reg; + (void)gpioDev; - if (pin >= cfg->pinCfgCount) { + if (!value || pin >= cfg->pinCfgCount) return WHAL_EINVAL; - } - whal_Pic32cz_Gpio_PinCfg *pinCfg = &cfg->pinCfg[pin]; - size_t pinMask = (1UL << (pinCfg->pin)); - size_t reg; + pinCfg = &cfg->pinCfg[pin]; + pinMask = (1UL << (pinCfg->pin)); /* * Read from appropriate register based on pin direction: @@ -167,28 +164,28 @@ whal_Error whal_Pic32cz_Gpio_Get(whal_Gpio *gpioDev, size_t pin, size_t *value) reg = IN_REG(pinCfg->port); } - whal_Reg_Get(gpioDev->base, reg, pinMask, pinCfg->pin, value); + whal_Reg_Get(base, reg, pinMask, pinCfg->pin, value); return WHAL_SUCCESS; } whal_Error whal_Pic32cz_Gpio_Set(whal_Gpio *gpioDev, size_t pin, size_t value) { - if (!gpioDev || !gpioDev->cfg) { - return WHAL_EINVAL; - } - - const whal_Pic32cz_Gpio_Cfg *cfg = gpioDev->cfg; - - if (pin >= cfg->pinCfgCount) { + const whal_Pic32cz_Gpio_Cfg *cfg = + (const whal_Pic32cz_Gpio_Cfg *)whal_Pic32cz_Gpio_Dev.cfg; + size_t base = whal_Pic32cz_Gpio_Dev.base; + whal_Pic32cz_Gpio_PinCfg *pinCfg; + size_t pinMask; + (void)gpioDev; + + if (pin >= cfg->pinCfgCount) return WHAL_EINVAL; - } - whal_Pic32cz_Gpio_PinCfg *pinCfg = &cfg->pinCfg[pin]; - size_t pinMask = (1UL << (pinCfg->pin)); + pinCfg = &cfg->pinCfg[pin]; + pinMask = (1UL << (pinCfg->pin)); /* Update the output register to drive the new value */ - whal_Reg_Update(gpioDev->base, OUT_REG(pinCfg->port), + whal_Reg_Update(base, OUT_REG(pinCfg->port), pinMask, whal_SetBits(pinMask, pinCfg->pin, value)); diff --git a/src/i2c/stm32l1_i2c.c b/src/i2c/stm32l1_i2c.c index 53d1fe3..75f70db 100644 --- a/src/i2c/stm32l1_i2c.c +++ b/src/i2c/stm32l1_i2c.c @@ -1,4 +1,7 @@ #include +#ifdef WHAL_CFG_STM32L1_I2C_SINGLE_INSTANCE +#include "board.h" /* provides whal_Stm32l1_I2c_Dev singleton */ +#endif #include #include #include @@ -288,12 +291,17 @@ static uint32_t Stm32l1_I2c_CalcTrise(uint32_t pclk, uint32_t freq) whal_Error whal_Stm32l1_I2c_Init(whal_I2c *i2cDev) { +#ifdef WHAL_CFG_STM32L1_I2C_SINGLE_INSTANCE + size_t base = whal_Stm32l1_I2c_Dev.base; + (void)i2cDev; +#else size_t base; if (!i2cDev || !i2cDev->cfg) return WHAL_EINVAL; base = i2cDev->base; +#endif whal_Reg_Update(base, I2C_CR1, CR1_PE_Msk, 0); whal_Reg_Update(base, I2C_CR1, CR1_SWRST_Msk, CR1_SWRST_Msk); @@ -305,28 +313,49 @@ whal_Error whal_Stm32l1_I2c_Init(whal_I2c *i2cDev) whal_Error whal_Stm32l1_I2c_Deinit(whal_I2c *i2cDev) { +#ifdef WHAL_CFG_STM32L1_I2C_SINGLE_INSTANCE + size_t base = whal_Stm32l1_I2c_Dev.base; + (void)i2cDev; +#else + size_t base; + if (!i2cDev || !i2cDev->cfg) return WHAL_EINVAL; - whal_Reg_Update(i2cDev->base, I2C_CR1, CR1_PE_Msk, 0); + base = i2cDev->base; +#endif + + whal_Reg_Update(base, I2C_CR1, CR1_PE_Msk, 0); return WHAL_SUCCESS; } whal_Error whal_Stm32l1_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) { + uint32_t freqMhz; +#ifdef WHAL_CFG_STM32L1_I2C_SINGLE_INSTANCE + whal_Stm32l1_I2c_Cfg *cfg = + (whal_Stm32l1_I2c_Cfg *)whal_Stm32l1_I2c_Dev.cfg; + size_t base = whal_Stm32l1_I2c_Dev.base; + (void)i2cDev; + + if (!comCfg) + return WHAL_EINVAL; +#else whal_Stm32l1_I2c_Cfg *cfg; size_t base; - uint32_t freqMhz; if (!i2cDev || !i2cDev->cfg || !comCfg) return WHAL_EINVAL; +#endif if ((comCfg->addrSz != 7 && comCfg->addrSz != 10) || comCfg->freq == 0) return WHAL_EINVAL; +#ifndef WHAL_CFG_STM32L1_I2C_SINGLE_INSTANCE cfg = (whal_Stm32l1_I2c_Cfg *)i2cDev->cfg; base = i2cDev->base; +#endif whal_Reg_Update(base, I2C_CR1, CR1_PE_Msk, 0); @@ -348,12 +377,18 @@ whal_Error whal_Stm32l1_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) whal_Error whal_Stm32l1_I2c_EndCom(whal_I2c *i2cDev) { +#ifdef WHAL_CFG_STM32L1_I2C_SINGLE_INSTANCE + whal_Stm32l1_I2c_Cfg *cfg = + (whal_Stm32l1_I2c_Cfg *)whal_Stm32l1_I2c_Dev.cfg; + (void)i2cDev; +#else whal_Stm32l1_I2c_Cfg *cfg; if (!i2cDev || !i2cDev->cfg) return WHAL_EINVAL; cfg = (whal_Stm32l1_I2c_Cfg *)i2cDev->cfg; +#endif cfg->_addr = 0; cfg->_addrSz = 0; @@ -363,15 +398,25 @@ whal_Error whal_Stm32l1_I2c_EndCom(whal_I2c *i2cDev) whal_Error whal_Stm32l1_I2c_Transfer(whal_I2c *i2cDev, whal_I2c_Msg *msgs, size_t numMsgs) { + whal_Error err; +#ifdef WHAL_CFG_STM32L1_I2C_SINGLE_INSTANCE + whal_Stm32l1_I2c_Cfg *cfg = + (whal_Stm32l1_I2c_Cfg *)whal_Stm32l1_I2c_Dev.cfg; + size_t base = whal_Stm32l1_I2c_Dev.base; + (void)i2cDev; + + if (!msgs || numMsgs == 0) + return WHAL_EINVAL; +#else whal_Stm32l1_I2c_Cfg *cfg; size_t base; - whal_Error err; if (!i2cDev || !i2cDev->cfg || !msgs || numMsgs == 0) return WHAL_EINVAL; cfg = (whal_Stm32l1_I2c_Cfg *)i2cDev->cfg; base = i2cDev->base; +#endif for (size_t i = 0; i < numMsgs; i++) { uint8_t isRead = (msgs[i].flags & WHAL_I2C_MSG_READ) ? 1 : 0; diff --git a/src/power/pic32cz_supc.c b/src/power/pic32cz_supc.c deleted file mode 100644 index aa2880a..0000000 --- a/src/power/pic32cz_supc.c +++ /dev/null @@ -1,30 +0,0 @@ -#include -#include -#include -#include - -#define VREGCTRL_REG 0x1C -#define VREGCTRL_AVREGEN_Pos 16 -#define VREGCTRL_AVREGEN_Msk (WHAL_BITMASK(3) << VREGCTRL_AVREGEN_Pos) - -whal_Error whal_Pic32cz_Supc_EnableSupply(whal_Power *powerDev, - const whal_Pic32cz_Supc_Supply *supply) -{ - if (!powerDev || !supply) - return WHAL_EINVAL; - - whal_Reg_Update(powerDev->base, VREGCTRL_REG, supply->enableMask, - whal_SetBits(supply->enableMask, supply->enablePos, 1)); - return WHAL_SUCCESS; -} - -whal_Error whal_Pic32cz_Supc_DisableSupply(whal_Power *powerDev, - const whal_Pic32cz_Supc_Supply *supply) -{ - if (!powerDev || !supply) - return WHAL_EINVAL; - - whal_Reg_Update(powerDev->base, VREGCTRL_REG, supply->enableMask, - whal_SetBits(supply->enableMask, supply->enablePos, 0)); - return WHAL_SUCCESS; -} diff --git a/src/power/stm32l1_pwr.c b/src/power/stm32l1_pwr.c deleted file mode 100644 index 607d08f..0000000 --- a/src/power/stm32l1_pwr.c +++ /dev/null @@ -1,33 +0,0 @@ -#include -#include -#include -#include - -#define PWR_CR_REG 0x00 -#define PWR_CR_VOS_Pos 11 -#define PWR_CR_VOS_Msk (WHAL_BITMASK(2) << PWR_CR_VOS_Pos) -#define PWR_CSR_REG 0x04 -#define PWR_CSR_VOSF_Pos 4 -#define PWR_CSR_VOSF_Msk (1UL << PWR_CSR_VOSF_Pos) - -whal_Error whal_Stm32l1_Pwr_SetVosRange(whal_Power *powerDev, - whal_Stm32l1_Pwr_VosRange range, - whal_Timeout *timeout) -{ - size_t base; - whal_Error err; - - if (!powerDev) - return WHAL_EINVAL; - - base = powerDev->base; - - err = whal_Reg_ReadPoll(base, PWR_CSR_REG, PWR_CSR_VOSF_Msk, 0, timeout); - if (err) - return err; - - whal_Reg_Update(base, PWR_CR_REG, PWR_CR_VOS_Msk, - whal_SetBits(PWR_CR_VOS_Msk, PWR_CR_VOS_Pos, range)); - - return whal_Reg_ReadPoll(base, PWR_CSR_REG, PWR_CSR_VOSF_Msk, 0, timeout); -} diff --git a/src/rng/stm32wba_rng.c b/src/rng/stm32wba_rng.c index e410080..16e5706 100644 --- a/src/rng/stm32wba_rng.c +++ b/src/rng/stm32wba_rng.c @@ -1,4 +1,5 @@ #include +#include "board.h" /* provides whal_Stm32wba_Rng_Dev singleton */ #include #include #include @@ -67,14 +68,10 @@ whal_Error whal_Stm32wba_Rng_Init(whal_Rng *rngDev) { - const whal_Stm32wba_Rng_Cfg *cfg; - size_t base; - - if (!rngDev || !rngDev->cfg) - return WHAL_EINVAL; - - cfg = (const whal_Stm32wba_Rng_Cfg *)rngDev->cfg; - base = rngDev->base; + const whal_Stm32wba_Rng_Cfg *cfg = + (const whal_Stm32wba_Rng_Cfg *)whal_Stm32wba_Rng_Dev.cfg; + size_t base = whal_Stm32wba_Rng_Dev.base; + (void)rngDev; /* Apply Configuration C with CONDRST=1 and RNGEN=1 */ whal_Reg_Write(base, RNG_CR_REG, @@ -91,11 +88,10 @@ whal_Error whal_Stm32wba_Rng_Init(whal_Rng *rngDev) whal_Error whal_Stm32wba_Rng_Deinit(whal_Rng *rngDev) { - if (!rngDev || !rngDev->cfg) - return WHAL_EINVAL; + (void)rngDev; /* Disable RNG */ - whal_Reg_Update(rngDev->base, RNG_CR_REG, RNG_CR_RNGEN_Msk, 0); + whal_Reg_Update(whal_Stm32wba_Rng_Dev.base, RNG_CR_REG, RNG_CR_RNGEN_Msk, 0); return WHAL_SUCCESS; } @@ -104,16 +100,15 @@ whal_Error whal_Stm32wba_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rn { uint8_t *rngBuf = (uint8_t *)rngData; whal_Error err = WHAL_SUCCESS; - whal_Stm32wba_Rng_Cfg *cfg; - size_t base; + const whal_Stm32wba_Rng_Cfg *cfg = + (const whal_Stm32wba_Rng_Cfg *)whal_Stm32wba_Rng_Dev.cfg; + size_t base = whal_Stm32wba_Rng_Dev.base; size_t sr; size_t offset = 0; + (void)rngDev; - if (!rngDev || !rngDev->cfg || !rngData) + if (!rngData) return WHAL_EINVAL; - - cfg = (whal_Stm32wba_Rng_Cfg *)rngDev->cfg; - base = rngDev->base; #ifdef WHAL_CFG_NO_TIMEOUT (void)(cfg); #endif diff --git a/src/sensor/imu/bmi270_sensor.c b/src/sensor/imu/bmi270_sensor.c index ae55f55..e0b2cca 100644 --- a/src/sensor/imu/bmi270_sensor.c +++ b/src/sensor/imu/bmi270_sensor.c @@ -1,4 +1,7 @@ #include +#ifdef WHAL_CFG_BMI270_SINGLE_INSTANCE +#include "board.h" /* provides whal_Bmi270_Dev singleton */ +#endif #include #include #include @@ -45,11 +48,16 @@ whal_Error whal_Bmi270_Init(whal_Sensor *dev) whal_Error err; uint8_t val; +#ifdef WHAL_CFG_BMI270_SINGLE_INSTANCE + cfg = (whal_Bmi270_Cfg *)whal_Bmi270_Dev.cfg; + (void)dev; +#else if (!dev || !dev->cfg) { return WHAL_EINVAL; } cfg = (whal_Bmi270_Cfg *)dev->cfg; +#endif if (!cfg->i2c || !cfg->comCfg || !cfg->configData || cfg->configDataSz == 0 || !cfg->DelayMs) { @@ -162,11 +170,16 @@ whal_Error whal_Bmi270_Deinit(whal_Sensor *dev) whal_Error err; uint8_t val = BMI270_CMD_SOFT_RESET; +#ifdef WHAL_CFG_BMI270_SINGLE_INSTANCE + cfg = (whal_Bmi270_Cfg *)whal_Bmi270_Dev.cfg; + (void)dev; +#else if (!dev || !dev->cfg) { return WHAL_EINVAL; } cfg = (whal_Bmi270_Cfg *)dev->cfg; +#endif err = whal_I2c_StartCom(cfg->i2c, cfg->comCfg); if (err) @@ -185,11 +198,20 @@ whal_Error whal_Bmi270_Read(whal_Sensor *dev, void *data) uint8_t raw[BMI270_DATA_LEN]; whal_Error err; +#ifdef WHAL_CFG_BMI270_SINGLE_INSTANCE + cfg = (whal_Bmi270_Cfg *)whal_Bmi270_Dev.cfg; + (void)dev; + + if (!data) { + return WHAL_EINVAL; + } +#else if (!dev || !dev->cfg || !data) { return WHAL_EINVAL; } cfg = (whal_Bmi270_Cfg *)dev->cfg; +#endif out = (whal_Bmi270_Data *)data; err = whal_I2c_StartCom(cfg->i2c, cfg->comCfg); diff --git a/src/spi/stm32f4_spi.c b/src/spi/stm32f4_spi.c index d651ee1..fb363a3 100644 --- a/src/spi/stm32f4_spi.c +++ b/src/spi/stm32f4_spi.c @@ -1,4 +1,8 @@ #include +#if defined(WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32L1_SPI_SINGLE_INSTANCE) +#include "board.h" /* provides whal_Stm32f4_Spi_Dev singleton (possibly via platform alias macro) */ +#endif #include #include #include @@ -87,12 +91,18 @@ static uint32_t whal_Stm32f4_Spi_CalcBr(size_t pclk, uint32_t targetBaud) whal_Error whal_Stm32f4_Spi_Init(whal_Spi *spiDev) { +#if defined(WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32L1_SPI_SINGLE_INSTANCE) + size_t base = whal_Stm32f4_Spi_Dev.base; + (void)spiDev; +#else size_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; base = spiDev->base; +#endif /* Master mode with software slave management */ whal_Reg_Update(base, SPI_CR1_REG, @@ -106,12 +116,18 @@ whal_Error whal_Stm32f4_Spi_Init(whal_Spi *spiDev) whal_Error whal_Stm32f4_Spi_Deinit(whal_Spi *spiDev) { +#if defined(WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32L1_SPI_SINGLE_INSTANCE) + size_t base = whal_Stm32f4_Spi_Dev.base; + (void)spiDev; +#else size_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; base = spiDev->base; +#endif /* Disable SPI */ whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, @@ -122,12 +138,23 @@ whal_Error whal_Stm32f4_Spi_Deinit(whal_Spi *spiDev) whal_Error whal_Stm32f4_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) { + uint32_t cpol, cpha, br; +#if defined(WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32L1_SPI_SINGLE_INSTANCE) + whal_Stm32f4_Spi_Cfg *cfg = + (whal_Stm32f4_Spi_Cfg *)whal_Stm32f4_Spi_Dev.cfg; + size_t base = whal_Stm32f4_Spi_Dev.base; + (void)spiDev; + + if (!comCfg) + return WHAL_EINVAL; +#else size_t base; whal_Stm32f4_Spi_Cfg *cfg; - uint32_t cpol, cpha, br; if (!spiDev || !spiDev->cfg || !comCfg) return WHAL_EINVAL; +#endif /* Only 8-bit frames supported */ if (comCfg->wordSz != 8) @@ -136,8 +163,11 @@ whal_Error whal_Stm32f4_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) if (comCfg->mode > 3 || comCfg->dataLines != 1 || comCfg->freq == 0) return WHAL_EINVAL; +#if !defined(WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE) && \ + !defined(WHAL_CFG_STM32L1_SPI_SINGLE_INSTANCE) base = spiDev->base; cfg = (whal_Stm32f4_Spi_Cfg *)spiDev->cfg; +#endif br = whal_Stm32f4_Spi_CalcBr(cfg->pclk, comCfg->freq); @@ -164,12 +194,18 @@ whal_Error whal_Stm32f4_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) whal_Error whal_Stm32f4_Spi_EndCom(whal_Spi *spiDev) { +#if defined(WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32L1_SPI_SINGLE_INSTANCE) + size_t base = whal_Stm32f4_Spi_Dev.base; + (void)spiDev; +#else size_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; base = spiDev->base; +#endif /* Disable SPE */ whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, @@ -184,17 +220,28 @@ whal_Error whal_Stm32f4_Spi_SendRecv(whal_Spi *spiDev, { const uint8_t *txBuf = (const uint8_t *)tx; uint8_t *rxBuf = (uint8_t *)rx; - size_t base; - whal_Stm32f4_Spi_Cfg *cfg; size_t totalLen; whal_Error err; uint8_t txByte; +#if defined(WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32L1_SPI_SINGLE_INSTANCE) + whal_Stm32f4_Spi_Cfg *cfg = + (whal_Stm32f4_Spi_Cfg *)whal_Stm32f4_Spi_Dev.cfg; + size_t base = whal_Stm32f4_Spi_Dev.base; + (void)spiDev; + + if ((!tx && txLen) || (!rx && rxLen)) + return WHAL_EINVAL; +#else + size_t base; + whal_Stm32f4_Spi_Cfg *cfg; if (!spiDev || !spiDev->cfg || (!tx && txLen) || (!rx && rxLen)) return WHAL_EINVAL; base = spiDev->base; cfg = (whal_Stm32f4_Spi_Cfg *)spiDev->cfg; +#endif totalLen = txLen > rxLen ? txLen : rxLen; for (size_t i = 0; i < totalLen; i++) { diff --git a/src/spi/stm32h5_spi.c b/src/spi/stm32h5_spi.c index d674bf2..ee354ef 100644 --- a/src/spi/stm32h5_spi.c +++ b/src/spi/stm32h5_spi.c @@ -1,4 +1,9 @@ #include +#if defined(WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32WBA_SPI_SINGLE_INSTANCE) +#include "board.h" /* provides whal_Stm32h5_Spi_Dev singleton (possibly via platform alias macro) */ +#endif #include #include #include @@ -117,12 +122,19 @@ static uint32_t Stm32h5_Spi_CalcMbr(size_t pclk, uint32_t targetBaud) whal_Error whal_Stm32h5_Spi_Init(whal_Spi *spiDev) { +#if defined(WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32WBA_SPI_SINGLE_INSTANCE) + size_t base = whal_Stm32h5_Spi_Dev.base; + (void)spiDev; +#else size_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; base = spiDev->base; +#endif /* Disable SPI before configuring */ whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, @@ -142,12 +154,19 @@ whal_Error whal_Stm32h5_Spi_Init(whal_Spi *spiDev) whal_Error whal_Stm32h5_Spi_Deinit(whal_Spi *spiDev) { +#if defined(WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32WBA_SPI_SINGLE_INSTANCE) + size_t base = whal_Stm32h5_Spi_Dev.base; + (void)spiDev; +#else size_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; base = spiDev->base; +#endif whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, whal_SetBits(SPI_CR1_SPE_Msk, SPI_CR1_SPE_Pos, 0)); @@ -157,12 +176,24 @@ whal_Error whal_Stm32h5_Spi_Deinit(whal_Spi *spiDev) whal_Error whal_Stm32h5_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) { + uint32_t cpol, cpha, mbr, dsize, fthlv; +#if defined(WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32WBA_SPI_SINGLE_INSTANCE) + whal_Stm32h5_Spi_Cfg *cfg = + (whal_Stm32h5_Spi_Cfg *)whal_Stm32h5_Spi_Dev.cfg; + size_t base = whal_Stm32h5_Spi_Dev.base; + (void)spiDev; + + if (!comCfg) + return WHAL_EINVAL; +#else size_t base; whal_Stm32h5_Spi_Cfg *cfg; - uint32_t cpol, cpha, mbr, dsize, fthlv; if (!spiDev || !spiDev->cfg || !comCfg) return WHAL_EINVAL; +#endif if (comCfg->wordSz < 4 || comCfg->wordSz > 32) return WHAL_EINVAL; @@ -170,8 +201,12 @@ whal_Error whal_Stm32h5_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) if (comCfg->mode > 3 || comCfg->dataLines != 1 || comCfg->freq == 0) return WHAL_EINVAL; +#if !defined(WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE) && \ + !defined(WHAL_CFG_STM32N6_SPI_SINGLE_INSTANCE) && \ + !defined(WHAL_CFG_STM32WBA_SPI_SINGLE_INSTANCE) base = spiDev->base; cfg = (whal_Stm32h5_Spi_Cfg *)spiDev->cfg; +#endif /* Disable SPE before reconfiguring */ whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, @@ -212,12 +247,19 @@ whal_Error whal_Stm32h5_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) whal_Error whal_Stm32h5_Spi_EndCom(whal_Spi *spiDev) { +#if defined(WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32WBA_SPI_SINGLE_INSTANCE) + size_t base = whal_Stm32h5_Spi_Dev.base; + (void)spiDev; +#else size_t base; if (!spiDev || !spiDev->cfg) return WHAL_EINVAL; base = spiDev->base; +#endif /* Disable SPI */ whal_Reg_Update(base, SPI_CR1_REG, SPI_CR1_SPE_Msk, @@ -236,17 +278,29 @@ whal_Error whal_Stm32h5_Spi_SendRecv(whal_Spi *spiDev, { const uint8_t *txBuf = (const uint8_t *)tx; uint8_t *rxBuf = (uint8_t *)rx; - size_t base; - whal_Stm32h5_Spi_Cfg *cfg; size_t totalLen; whal_Error err; uint8_t txByte; +#if defined(WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32N6_SPI_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32WBA_SPI_SINGLE_INSTANCE) + whal_Stm32h5_Spi_Cfg *cfg = + (whal_Stm32h5_Spi_Cfg *)whal_Stm32h5_Spi_Dev.cfg; + size_t base = whal_Stm32h5_Spi_Dev.base; + (void)spiDev; + + if ((!tx && txLen) || (!rx && rxLen)) + return WHAL_EINVAL; +#else + size_t base; + whal_Stm32h5_Spi_Cfg *cfg; if (!spiDev || !spiDev->cfg || (!tx && txLen) || (!rx && rxLen)) return WHAL_EINVAL; base = spiDev->base; cfg = (whal_Stm32h5_Spi_Cfg *)spiDev->cfg; +#endif totalLen = txLen > rxLen ? txLen : rxLen; for (size_t i = 0; i < totalLen; i++) { diff --git a/src/uart/pic32cz_uart.c b/src/uart/pic32cz_uart.c index 6fee1ed..2a1447e 100644 --- a/src/uart/pic32cz_uart.c +++ b/src/uart/pic32cz_uart.c @@ -1,4 +1,7 @@ #include +#ifdef WHAL_CFG_PIC32CZ_UART_SINGLE_INSTANCE +#include "board.h" /* provides whal_Pic32cz_Uart_Dev singleton */ +#endif #include #include #include @@ -171,6 +174,12 @@ whal_Error whal_Pic32cz_Uart_Init(whal_Uart *uartDev) { whal_Error err; +#ifdef WHAL_CFG_PIC32CZ_UART_SINGLE_INSTANCE + whal_Pic32cz_Uart_Cfg *cfg = + (whal_Pic32cz_Uart_Cfg *)whal_Pic32cz_Uart_Dev.cfg; + size_t base = whal_Pic32cz_Uart_Dev.base; + (void)uartDev; +#else whal_Pic32cz_Uart_Cfg *cfg; size_t base; @@ -180,6 +189,7 @@ whal_Error whal_Pic32cz_Uart_Init(whal_Uart *uartDev) base = uartDev->base; cfg = (whal_Pic32cz_Uart_Cfg *)uartDev->cfg; +#endif /* Configure CTRLA: internal clock, async mode, LSB first, 16x sampling */ whal_Reg_Update(base, USART_CTRLA_REG, @@ -247,6 +257,12 @@ whal_Error whal_Pic32cz_Uart_Init(whal_Uart *uartDev) whal_Error whal_Pic32cz_Uart_Deinit(whal_Uart *uartDev) { whal_Error err; +#ifdef WHAL_CFG_PIC32CZ_UART_SINGLE_INSTANCE + whal_Pic32cz_Uart_Cfg *cfg = + (whal_Pic32cz_Uart_Cfg *)whal_Pic32cz_Uart_Dev.cfg; + size_t base = whal_Pic32cz_Uart_Dev.base; + (void)uartDev; +#else size_t base; whal_Pic32cz_Uart_Cfg *cfg; @@ -256,6 +272,7 @@ whal_Error whal_Pic32cz_Uart_Deinit(whal_Uart *uartDev) base = uartDev->base; cfg = (whal_Pic32cz_Uart_Cfg *)uartDev->cfg; +#endif /* Disable SERCOM USART */ whal_Reg_Update(base, USART_CTRLA_REG, @@ -285,10 +302,20 @@ whal_Error whal_Pic32cz_Uart_Deinit(whal_Uart *uartDev) whal_Error whal_Pic32cz_Uart_Send(whal_Uart *uartDev, const void *data, size_t dataSz) { - size_t base; - whal_Pic32cz_Uart_Cfg *cfg; const uint8_t *buf = data; whal_Error err; +#ifdef WHAL_CFG_PIC32CZ_UART_SINGLE_INSTANCE + whal_Pic32cz_Uart_Cfg *cfg = + (whal_Pic32cz_Uart_Cfg *)whal_Pic32cz_Uart_Dev.cfg; + size_t base = whal_Pic32cz_Uart_Dev.base; + (void)uartDev; + + if (!data) { + return WHAL_EINVAL; + } +#else + size_t base; + whal_Pic32cz_Uart_Cfg *cfg; if (!uartDev || !uartDev->cfg || !data) { return WHAL_EINVAL; @@ -296,6 +323,7 @@ whal_Error whal_Pic32cz_Uart_Send(whal_Uart *uartDev, const void *data, size_t d base = uartDev->base; cfg = (whal_Pic32cz_Uart_Cfg *)uartDev->cfg; +#endif for (size_t i = 0; i < dataSz; ++i) { /* Wait for data register to be empty */ @@ -328,9 +356,19 @@ whal_Error whal_Pic32cz_Uart_Send(whal_Uart *uartDev, const void *data, size_t d whal_Error whal_Pic32cz_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) { + uint8_t *buf = data; +#ifdef WHAL_CFG_PIC32CZ_UART_SINGLE_INSTANCE + whal_Pic32cz_Uart_Cfg *cfg = + (whal_Pic32cz_Uart_Cfg *)whal_Pic32cz_Uart_Dev.cfg; + size_t base = whal_Pic32cz_Uart_Dev.base; + (void)uartDev; + + if (!data) { + return WHAL_EINVAL; + } +#else size_t base; whal_Pic32cz_Uart_Cfg *cfg; - uint8_t *buf = data; if (!uartDev || !uartDev->cfg || !data) { return WHAL_EINVAL; @@ -338,6 +376,7 @@ whal_Error whal_Pic32cz_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) base = uartDev->base; cfg = (whal_Pic32cz_Uart_Cfg *)uartDev->cfg; +#endif for (size_t i = 0; i < dataSz; ++i) { size_t rxData; diff --git a/src/uart/stm32f0_uart.c b/src/uart/stm32f0_uart.c index 34b8a83..775ff82 100644 --- a/src/uart/stm32f0_uart.c +++ b/src/uart/stm32f0_uart.c @@ -1,4 +1,8 @@ #include +#if defined(WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F3_UART_SINGLE_INSTANCE) +#include "board.h" /* provides whal_Stm32f0_Uart_Dev singleton (possibly via platform alias macro) */ +#endif #include #include #include @@ -46,6 +50,13 @@ whal_Error whal_Stm32f0_Uart_Init(whal_Uart *uartDev) { +#if defined(WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F3_UART_SINGLE_INSTANCE) + const whal_Stm32f0_Uart_Cfg *cfg = + (const whal_Stm32f0_Uart_Cfg *)whal_Stm32f0_Uart_Dev.cfg; + size_t base = whal_Stm32f0_Uart_Dev.base; + (void)uartDev; +#else whal_Stm32f0_Uart_Cfg *cfg; size_t base; @@ -54,6 +65,7 @@ whal_Error whal_Stm32f0_Uart_Init(whal_Uart *uartDev) base = uartDev->base; cfg = (whal_Stm32f0_Uart_Cfg *)uartDev->cfg; +#endif whal_Reg_Update(base, UART_BRR_REG, UART_BRR_Msk, whal_SetBits(UART_BRR_Msk, UART_BRR_Pos, cfg->brr)); @@ -70,12 +82,18 @@ whal_Error whal_Stm32f0_Uart_Init(whal_Uart *uartDev) whal_Error whal_Stm32f0_Uart_Deinit(whal_Uart *uartDev) { +#if defined(WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F3_UART_SINGLE_INSTANCE) + size_t base = whal_Stm32f0_Uart_Dev.base; + (void)uartDev; +#else size_t base; if (!uartDev) return WHAL_EINVAL; base = uartDev->base; +#endif whal_Reg_Update(base, UART_CR1_REG, UART_CR1_UE_Msk | UART_CR1_RE_Msk | UART_CR1_TE_Msk, @@ -92,15 +110,26 @@ whal_Error whal_Stm32f0_Uart_Deinit(whal_Uart *uartDev) whal_Error whal_Stm32f0_Uart_Send(whal_Uart *uartDev, const void *data, size_t dataSz) { + const uint8_t *buf = data; +#if defined(WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F3_UART_SINGLE_INSTANCE) + const whal_Stm32f0_Uart_Cfg *cfg = + (const whal_Stm32f0_Uart_Cfg *)whal_Stm32f0_Uart_Dev.cfg; + size_t base = whal_Stm32f0_Uart_Dev.base; + (void)uartDev; + + if (!data) + return WHAL_EINVAL; +#else size_t base; whal_Stm32f0_Uart_Cfg *cfg; - const uint8_t *buf = data; if (!uartDev || !uartDev->cfg || !data) return WHAL_EINVAL; base = uartDev->base; cfg = (whal_Stm32f0_Uart_Cfg *)uartDev->cfg; +#endif for (size_t i = 0; i < dataSz; ++i) { whal_Error err; @@ -118,15 +147,26 @@ whal_Error whal_Stm32f0_Uart_Send(whal_Uart *uartDev, const void *data, whal_Error whal_Stm32f0_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) { + uint8_t *buf = data; +#if defined(WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32F3_UART_SINGLE_INSTANCE) + const whal_Stm32f0_Uart_Cfg *cfg = + (const whal_Stm32f0_Uart_Cfg *)whal_Stm32f0_Uart_Dev.cfg; + size_t base = whal_Stm32f0_Uart_Dev.base; + (void)uartDev; + + if (!data) + return WHAL_EINVAL; +#else size_t base; whal_Stm32f0_Uart_Cfg *cfg; - uint8_t *buf = data; if (!uartDev || !uartDev->cfg || !data) return WHAL_EINVAL; base = uartDev->base; cfg = (whal_Stm32f0_Uart_Cfg *)uartDev->cfg; +#endif for (size_t i = 0; i < dataSz; ++i) { size_t d; diff --git a/src/uart/stm32f4_uart.c b/src/uart/stm32f4_uart.c index 4f496e1..4602921 100644 --- a/src/uart/stm32f4_uart.c +++ b/src/uart/stm32f4_uart.c @@ -1,4 +1,8 @@ #include +#if defined(WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32L1_UART_SINGLE_INSTANCE) +#include "board.h" /* provides whal_Stm32f4_Uart_Dev singleton (possibly via platform alias macro) */ +#endif #include #include #include @@ -57,15 +61,23 @@ whal_Error whal_Stm32f4_Uart_Init(whal_Uart *uartDev) { + uint32_t brr; +#if defined(WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32L1_UART_SINGLE_INSTANCE) + const whal_Stm32f4_Uart_Cfg *cfg = + (const whal_Stm32f4_Uart_Cfg *)whal_Stm32f4_Uart_Dev.cfg; + size_t base = whal_Stm32f4_Uart_Dev.base; + (void)uartDev; +#else whal_Stm32f4_Uart_Cfg *cfg; size_t base; - uint32_t brr; if (!uartDev || !uartDev->cfg) return WHAL_EINVAL; base = uartDev->base; cfg = (whal_Stm32f4_Uart_Cfg *)uartDev->cfg; +#endif brr = cfg->brr; @@ -86,12 +98,18 @@ whal_Error whal_Stm32f4_Uart_Init(whal_Uart *uartDev) whal_Error whal_Stm32f4_Uart_Deinit(whal_Uart *uartDev) { +#if defined(WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32L1_UART_SINGLE_INSTANCE) + size_t base = whal_Stm32f4_Uart_Dev.base; + (void)uartDev; +#else size_t base; if (!uartDev) return WHAL_EINVAL; base = uartDev->base; +#endif /* Disable USART, transmitter, and receiver */ whal_Reg_Update(base, UART_CR1_REG, @@ -110,15 +128,26 @@ whal_Error whal_Stm32f4_Uart_Deinit(whal_Uart *uartDev) whal_Error whal_Stm32f4_Uart_Send(whal_Uart *uartDev, const void *data, size_t dataSz) { + const uint8_t *buf = data; +#if defined(WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32L1_UART_SINGLE_INSTANCE) + const whal_Stm32f4_Uart_Cfg *cfg = + (const whal_Stm32f4_Uart_Cfg *)whal_Stm32f4_Uart_Dev.cfg; + size_t base = whal_Stm32f4_Uart_Dev.base; + (void)uartDev; + + if (!data) + return WHAL_EINVAL; +#else size_t base; whal_Stm32f4_Uart_Cfg *cfg; - const uint8_t *buf = data; if (!uartDev || !uartDev->cfg || !data) return WHAL_EINVAL; base = uartDev->base; cfg = (whal_Stm32f4_Uart_Cfg *)uartDev->cfg; +#endif for (size_t i = 0; i < dataSz; ++i) { whal_Error err; @@ -138,16 +167,27 @@ whal_Error whal_Stm32f4_Uart_Send(whal_Uart *uartDev, const void *data, size_t d whal_Error whal_Stm32f4_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) { + uint8_t *buf = data; + size_t d; +#if defined(WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE) || \ + defined(WHAL_CFG_STM32L1_UART_SINGLE_INSTANCE) + const whal_Stm32f4_Uart_Cfg *cfg = + (const whal_Stm32f4_Uart_Cfg *)whal_Stm32f4_Uart_Dev.cfg; + size_t base = whal_Stm32f4_Uart_Dev.base; + (void)uartDev; + + if (!data) + return WHAL_EINVAL; +#else size_t base; whal_Stm32f4_Uart_Cfg *cfg; - uint8_t *buf = data; if (!uartDev || !uartDev->cfg || !data) return WHAL_EINVAL; base = uartDev->base; cfg = (whal_Stm32f4_Uart_Cfg *)uartDev->cfg; - size_t d; +#endif for (size_t i = 0; i < dataSz; ++i) { /* Wait for receive data register not empty */ diff --git a/src/uart/stm32wba_uart_dma.c b/src/uart/stm32wba_uart_dma.c index d73616e..1e438e7 100644 --- a/src/uart/stm32wba_uart_dma.c +++ b/src/uart/stm32wba_uart_dma.c @@ -1,4 +1,7 @@ #include +#ifdef WHAL_CFG_STM32WBA_UART_DMA_SINGLE_INSTANCE +#include "board.h" /* provides whal_Stm32wba_UartDma_Dev singleton */ +#endif #include #include #include @@ -27,22 +30,36 @@ whal_Error whal_Stm32wba_UartDma_SendAsync(whal_Uart *uartDev, const void *data, size_t dataSz) { + whal_Error err; +#ifdef WHAL_CFG_STM32WBA_UART_DMA_SINGLE_INSTANCE + whal_Stm32wba_UartDma_Cfg *cfg = + (whal_Stm32wba_UartDma_Cfg *)whal_Stm32wba_UartDma_Dev.cfg; + size_t base = whal_Stm32wba_UartDma_Dev.base; + (void)uartDev; + + if (!data || dataSz > 0xFFFF) + return WHAL_EINVAL; +#else whal_Stm32wba_UartDma_Cfg *cfg; size_t base; - whal_Error err; if (!uartDev || !uartDev->cfg || !data || dataSz > 0xFFFF) return WHAL_EINVAL; +#endif if (dataSz == 0) return WHAL_SUCCESS; +#ifndef WHAL_CFG_STM32WBA_UART_DMA_SINGLE_INSTANCE cfg = (whal_Stm32wba_UartDma_Cfg *)uartDev->cfg; +#endif if (cfg->txResult == WHAL_ENOTREADY) return WHAL_ENOTREADY; +#ifndef WHAL_CFG_STM32WBA_UART_DMA_SINGLE_INSTANCE base = uartDev->base; +#endif /* Single-byte DMA from flash fails on GPDMA — bounce through SRAM */ static volatile uint8_t txBounce; @@ -80,22 +97,36 @@ whal_Error whal_Stm32wba_UartDma_SendAsync(whal_Uart *uartDev, const void *data, whal_Error whal_Stm32wba_UartDma_RecvAsync(whal_Uart *uartDev, void *data, size_t dataSz) { + whal_Error err; +#ifdef WHAL_CFG_STM32WBA_UART_DMA_SINGLE_INSTANCE + whal_Stm32wba_UartDma_Cfg *cfg = + (whal_Stm32wba_UartDma_Cfg *)whal_Stm32wba_UartDma_Dev.cfg; + size_t base = whal_Stm32wba_UartDma_Dev.base; + (void)uartDev; + + if (!data || dataSz > 0xFFFF) + return WHAL_EINVAL; +#else whal_Stm32wba_UartDma_Cfg *cfg; size_t base; - whal_Error err; if (!uartDev || !uartDev->cfg || !data || dataSz > 0xFFFF) return WHAL_EINVAL; +#endif if (dataSz == 0) return WHAL_SUCCESS; +#ifndef WHAL_CFG_STM32WBA_UART_DMA_SINGLE_INSTANCE cfg = (whal_Stm32wba_UartDma_Cfg *)uartDev->cfg; +#endif if (cfg->rxResult == WHAL_ENOTREADY) return WHAL_ENOTREADY; +#ifndef WHAL_CFG_STM32WBA_UART_DMA_SINGLE_INSTANCE base = uartDev->base; +#endif cfg->rxChCfg->srcAddr = base + UART_RDR_REG; cfg->rxChCfg->dstAddr = (size_t)data; @@ -126,13 +157,20 @@ whal_Error whal_Stm32wba_UartDma_Send(whal_Uart *uartDev, const void *data, size_t dataSz) { whal_Stm32wba_UartDma_Cfg *cfg; + size_t base; whal_Error err; err = whal_Stm32wba_UartDma_SendAsync(uartDev, data, dataSz); if (err) return err; +#ifdef WHAL_CFG_STM32WBA_UART_DMA_SINGLE_INSTANCE + cfg = (whal_Stm32wba_UartDma_Cfg *)whal_Stm32wba_UartDma_Dev.cfg; + base = whal_Stm32wba_UartDma_Dev.base; +#else cfg = (whal_Stm32wba_UartDma_Cfg *)uartDev->cfg; + base = uartDev->base; +#endif WHAL_TIMEOUT_START(cfg->base.timeout); while (cfg->txResult == WHAL_ENOTREADY) { @@ -149,13 +187,13 @@ whal_Error whal_Stm32wba_UartDma_Send(whal_Uart *uartDev, const void *data, /* Wait for TC (transmission complete) so the last byte has shifted out * before we tear down the DMA channel */ - err = whal_Reg_ReadPoll(uartDev->base, UART_ISR_REG, + err = whal_Reg_ReadPoll(base, UART_ISR_REG, UART_ISR_TC_Msk, UART_ISR_TC_Msk, cfg->base.timeout); cleanup: whal_Dma_Stop(cfg->dma, cfg->txCh); - whal_Reg_Update(uartDev->base, UART_CR3_REG, UART_CR3_DMAT_Msk, 0); + whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAT_Msk, 0); cfg->txResult = err; return err; @@ -165,13 +203,20 @@ whal_Error whal_Stm32wba_UartDma_Recv(whal_Uart *uartDev, void *data, size_t dataSz) { whal_Stm32wba_UartDma_Cfg *cfg; + size_t base; whal_Error err; err = whal_Stm32wba_UartDma_RecvAsync(uartDev, data, dataSz); if (err) return err; +#ifdef WHAL_CFG_STM32WBA_UART_DMA_SINGLE_INSTANCE + cfg = (whal_Stm32wba_UartDma_Cfg *)whal_Stm32wba_UartDma_Dev.cfg; + base = whal_Stm32wba_UartDma_Dev.base; +#else cfg = (whal_Stm32wba_UartDma_Cfg *)uartDev->cfg; + base = uartDev->base; +#endif WHAL_TIMEOUT_START(cfg->base.timeout); while (cfg->rxResult == WHAL_ENOTREADY) { @@ -185,7 +230,7 @@ whal_Error whal_Stm32wba_UartDma_Recv(whal_Uart *uartDev, void *data, cleanup: whal_Dma_Stop(cfg->dma, cfg->rxCh); - whal_Reg_Update(uartDev->base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); + whal_Reg_Update(base, UART_CR3_REG, UART_CR3_DMAR_Msk, 0); cfg->rxResult = err; return err; diff --git a/src/watchdog/stm32f0_wwdg.c b/src/watchdog/stm32f0_wwdg.c index 83f04b6..63b9196 100644 --- a/src/watchdog/stm32f0_wwdg.c +++ b/src/watchdog/stm32f0_wwdg.c @@ -1,3 +1,4 @@ +#include "board.h" /* provides whal_Stm32f0_Wwdg_Dev singleton */ #include #include #include @@ -28,14 +29,10 @@ whal_Error whal_Stm32f0_Wwdg_Init(whal_Watchdog *wdgDev) { - size_t base; - whal_Stm32f0_Wwdg_Cfg *cfg; - - if (!wdgDev || !wdgDev->cfg) - return WHAL_EINVAL; - - base = wdgDev->base; - cfg = wdgDev->cfg; + const whal_Stm32f0_Wwdg_Cfg *cfg = + (const whal_Stm32f0_Wwdg_Cfg *)whal_Stm32f0_Wwdg_Dev.cfg; + size_t base = whal_Stm32f0_Wwdg_Dev.base; + (void)wdgDev; if (cfg->prescaler > 3 || cfg->window > 0x7F || cfg->counter > 0x7F) return WHAL_EINVAL; @@ -51,22 +48,16 @@ whal_Error whal_Stm32f0_Wwdg_Init(whal_Watchdog *wdgDev) whal_Error whal_Stm32f0_Wwdg_Deinit(whal_Watchdog *wdgDev) { - if (!wdgDev) - return WHAL_EINVAL; - + (void)wdgDev; return WHAL_SUCCESS; } whal_Error whal_Stm32f0_Wwdg_Refresh(whal_Watchdog *wdgDev) { - size_t base; - whal_Stm32f0_Wwdg_Cfg *cfg; - - if (!wdgDev || !wdgDev->cfg) - return WHAL_EINVAL; - - base = wdgDev->base; - cfg = wdgDev->cfg; + const whal_Stm32f0_Wwdg_Cfg *cfg = + (const whal_Stm32f0_Wwdg_Cfg *)whal_Stm32f0_Wwdg_Dev.cfg; + size_t base = whal_Stm32f0_Wwdg_Dev.base; + (void)wdgDev; whal_Reg_Write(base, CR_REG, CR_WDGA_Msk | cfg->counter); diff --git a/tests/clock/test_pic32cz_clock.c b/tests/clock/test_pic32cz_clock.c index 8cf70fb..c6c0267 100644 --- a/tests/clock/test_pic32cz_clock.c +++ b/tests/clock/test_pic32cz_clock.c @@ -33,7 +33,7 @@ static void Test_Clock_EnableDisable(void) size_t val = 0; /* Enable and verify */ - WHAL_ASSERT_EQ(whal_Pic32cz_Clock_EnablePeriphClk(&g_whalClock, &testClk), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Pic32cz_Clock_EnablePeriphClk(BOARD_CLOCK_DEV, &testClk), WHAL_SUCCESS); whal_Reg_Get(g_whalClock.base, GCLK_PCHCTRL_OFFSET(25), GCLK_PCHCTRL_CHEN_Msk, GCLK_PCHCTRL_CHEN_Pos, &val); @@ -44,7 +44,7 @@ static void Test_Clock_EnableDisable(void) WHAL_ASSERT_EQ(val, 1); /* Disable and verify */ - WHAL_ASSERT_EQ(whal_Pic32cz_Clock_DisablePeriphClk(&g_whalClock, &testClk), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Pic32cz_Clock_DisablePeriphClk(BOARD_CLOCK_DEV, &testClk), WHAL_SUCCESS); whal_Reg_Get(g_whalClock.base, GCLK_PCHCTRL_OFFSET(25), GCLK_PCHCTRL_CHEN_Msk, GCLK_PCHCTRL_CHEN_Pos, &val); @@ -52,7 +52,7 @@ static void Test_Clock_EnableDisable(void) /* Restore original state */ if (origChen) - whal_Pic32cz_Clock_EnablePeriphClk(&g_whalClock, &testClk); + whal_Pic32cz_Clock_EnablePeriphClk(BOARD_CLOCK_DEV, &testClk); } void whal_Test_Clock_Platform(void) diff --git a/tests/clock/test_stm32wb_clock.c b/tests/clock/test_stm32wb_clock.c index 7ca8382..3e39c08 100644 --- a/tests/clock/test_stm32wb_clock.c +++ b/tests/clock/test_stm32wb_clock.c @@ -14,21 +14,21 @@ static void Test_Clock_EnableDisable(void) whal_Reg_Get(g_whalClock.base, 0x4C, (1 << 0), 0, &origVal); /* Enable and verify */ - WHAL_ASSERT_EQ(whal_Stm32wb_Rcc_EnablePeriphClk(&g_whalClock, &testClk), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Stm32wb_Rcc_EnablePeriphClk(BOARD_CLOCK_DEV, &testClk), WHAL_SUCCESS); size_t val = 0; whal_Reg_Get(g_whalClock.base, 0x4C, (1 << 0), 0, &val); WHAL_ASSERT_EQ(val, 1); /* Disable and verify */ - WHAL_ASSERT_EQ(whal_Stm32wb_Rcc_DisablePeriphClk(&g_whalClock, &testClk), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Stm32wb_Rcc_DisablePeriphClk(BOARD_CLOCK_DEV, &testClk), WHAL_SUCCESS); whal_Reg_Get(g_whalClock.base, 0x4C, (1 << 0), 0, &val); WHAL_ASSERT_EQ(val, 0); /* Restore original state */ if (origVal) - whal_Stm32wb_Rcc_EnablePeriphClk(&g_whalClock, &testClk); + whal_Stm32wb_Rcc_EnablePeriphClk(BOARD_CLOCK_DEV, &testClk); } void whal_Test_Clock_Platform(void) diff --git a/tests/crypto/test_aes_cbc.c b/tests/crypto/test_aes_cbc.c index af6501d..643256f 100644 --- a/tests/crypto/test_aes_cbc.c +++ b/tests/crypto/test_aes_cbc.c @@ -51,12 +51,12 @@ static void Test_AesCbc_Basic(void) uint8_t ct[32] = {0}; uint8_t pt[32] = {0}; - WHAL_ASSERT_EQ(whal_AesCbc_Oneshot(&g_whalAesCbc, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesCbc_Oneshot(BOARD_AES_CBC_DEV, WHAL_CRYPTO_ENCRYPT, key, 32, iv, plaintext, ct, sizeof(plaintext)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesCbc_Oneshot(&g_whalAesCbc, WHAL_CRYPTO_DECRYPT, + WHAL_ASSERT_EQ(whal_AesCbc_Oneshot(BOARD_AES_CBC_DEV, WHAL_CRYPTO_DECRYPT, key, 32, iv, ct, pt, sizeof(ct)), WHAL_SUCCESS); @@ -67,7 +67,7 @@ static void Test_AesCbc_KnownAnswer(void) { uint8_t ct[16] = {0}; - WHAL_ASSERT_EQ(whal_AesCbc_Oneshot(&g_whalAesCbc, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesCbc_Oneshot(BOARD_AES_CBC_DEV, WHAL_CRYPTO_ENCRYPT, nistKey, 32, nistCbcIv, nistPt, ct, sizeof(nistPt)), WHAL_SUCCESS); diff --git a/tests/crypto/test_aes_ccm.c b/tests/crypto/test_aes_ccm.c index c9cfcfd..25cbe11 100644 --- a/tests/crypto/test_aes_ccm.c +++ b/tests/crypto/test_aes_ccm.c @@ -71,7 +71,7 @@ static void Test_AesCcm_Basic(void) uint8_t encTag[16] = {0}; uint8_t decTag[16] = {0}; - WHAL_ASSERT_EQ(whal_AesCcm_Oneshot(&g_whalAesCcm, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesCcm_Oneshot(BOARD_AES_CCM_DEV, WHAL_CRYPTO_ENCRYPT, key, 32, nonce, sizeof(nonce), aad, sizeof(aad), @@ -79,7 +79,7 @@ static void Test_AesCcm_Basic(void) encTag, sizeof(encTag)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesCcm_Oneshot(&g_whalAesCcm, WHAL_CRYPTO_DECRYPT, + WHAL_ASSERT_EQ(whal_AesCcm_Oneshot(BOARD_AES_CCM_DEV, WHAL_CRYPTO_DECRYPT, key, 32, nonce, sizeof(nonce), aad, sizeof(aad), @@ -96,7 +96,7 @@ static void Test_AesCcm_KnownAnswer(void) uint8_t ct[24] = {0}; uint8_t tag[16] = {0}; - WHAL_ASSERT_EQ(whal_AesCcm_Oneshot(&g_whalAesCcm, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesCcm_Oneshot(BOARD_AES_CCM_DEV, WHAL_CRYPTO_ENCRYPT, ccmKey, 32, ccmNonce, sizeof(ccmNonce), ccmAad, sizeof(ccmAad), @@ -159,23 +159,23 @@ static void Test_AesCcm_Streaming(void) uint8_t tag[16] = {0}; const size_t split = 32; - WHAL_ASSERT_EQ(whal_AesCcm_Start(&g_whalAesCcm, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesCcm_Start(BOARD_AES_CCM_DEV, WHAL_CRYPTO_ENCRYPT, ccmKey, 32, ccmNonce, sizeof(ccmNonce), ccmStreamAad, sizeof(ccmStreamAad), sizeof(tag), sizeof(ccmStreamPt)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesCcm_Process(&g_whalAesCcm, + WHAL_ASSERT_EQ(whal_AesCcm_Process(BOARD_AES_CCM_DEV, ccmStreamPt, ct, split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesCcm_Process(&g_whalAesCcm, + WHAL_ASSERT_EQ(whal_AesCcm_Process(BOARD_AES_CCM_DEV, ccmStreamPt + split, ct + split, sizeof(ccmStreamPt) - split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesCcm_Finalize(&g_whalAesCcm, tag, sizeof(tag)), + WHAL_ASSERT_EQ(whal_AesCcm_Finalize(BOARD_AES_CCM_DEV, tag, sizeof(tag)), WHAL_SUCCESS); WHAL_ASSERT_MEM_EQ(ct, ccmStreamCt, sizeof(ccmStreamCt)); @@ -188,23 +188,23 @@ static void Test_AesCcm_Streaming_NoAad(void) uint8_t tag[16] = {0}; const size_t split = 32; - WHAL_ASSERT_EQ(whal_AesCcm_Start(&g_whalAesCcm, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesCcm_Start(BOARD_AES_CCM_DEV, WHAL_CRYPTO_ENCRYPT, ccmKey, 32, ccmNonce, sizeof(ccmNonce), NULL, 0, sizeof(tag), sizeof(ccmStreamPt)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesCcm_Process(&g_whalAesCcm, + WHAL_ASSERT_EQ(whal_AesCcm_Process(BOARD_AES_CCM_DEV, ccmStreamPt, ct, split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesCcm_Process(&g_whalAesCcm, + WHAL_ASSERT_EQ(whal_AesCcm_Process(BOARD_AES_CCM_DEV, ccmStreamPt + split, ct + split, sizeof(ccmStreamPt) - split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesCcm_Finalize(&g_whalAesCcm, tag, sizeof(tag)), + WHAL_ASSERT_EQ(whal_AesCcm_Finalize(BOARD_AES_CCM_DEV, tag, sizeof(tag)), WHAL_SUCCESS); WHAL_ASSERT_MEM_EQ(ct, ccmStreamCt, sizeof(ccmStreamCt)); @@ -215,14 +215,14 @@ static void Test_AesCcm_Streaming_NoPayload(void) { uint8_t tag[16] = {0}; - WHAL_ASSERT_EQ(whal_AesCcm_Start(&g_whalAesCcm, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesCcm_Start(BOARD_AES_CCM_DEV, WHAL_CRYPTO_ENCRYPT, ccmKey, 32, ccmNonce, sizeof(ccmNonce), ccmStreamAad, sizeof(ccmStreamAad), sizeof(tag), 0), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesCcm_Finalize(&g_whalAesCcm, tag, sizeof(tag)), + WHAL_ASSERT_EQ(whal_AesCcm_Finalize(BOARD_AES_CCM_DEV, tag, sizeof(tag)), WHAL_SUCCESS); WHAL_ASSERT_MEM_EQ(tag, ccmStreamNoPtTag, sizeof(ccmStreamNoPtTag)); @@ -233,25 +233,25 @@ static void Test_AesCcm_Streaming_ThreeCall(void) uint8_t ct[sizeof(ccmStreamPt)] = {0}; uint8_t tag[16] = {0}; - WHAL_ASSERT_EQ(whal_AesCcm_Start(&g_whalAesCcm, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesCcm_Start(BOARD_AES_CCM_DEV, WHAL_CRYPTO_ENCRYPT, ccmKey, 32, ccmNonce, sizeof(ccmNonce), ccmStreamAad, sizeof(ccmStreamAad), sizeof(tag), sizeof(ccmStreamPt)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesCcm_Process(&g_whalAesCcm, + WHAL_ASSERT_EQ(whal_AesCcm_Process(BOARD_AES_CCM_DEV, ccmStreamPt, ct, 16), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesCcm_Process(&g_whalAesCcm, + WHAL_ASSERT_EQ(whal_AesCcm_Process(BOARD_AES_CCM_DEV, ccmStreamPt + 16, ct + 16, 16), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesCcm_Process(&g_whalAesCcm, + WHAL_ASSERT_EQ(whal_AesCcm_Process(BOARD_AES_CCM_DEV, ccmStreamPt + 32, ct + 32, sizeof(ccmStreamPt) - 32), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesCcm_Finalize(&g_whalAesCcm, tag, sizeof(tag)), + WHAL_ASSERT_EQ(whal_AesCcm_Finalize(BOARD_AES_CCM_DEV, tag, sizeof(tag)), WHAL_SUCCESS); WHAL_ASSERT_MEM_EQ(ct, ccmStreamCt, sizeof(ccmStreamCt)); diff --git a/tests/crypto/test_aes_ctr.c b/tests/crypto/test_aes_ctr.c index 5b11564..7efc3ff 100644 --- a/tests/crypto/test_aes_ctr.c +++ b/tests/crypto/test_aes_ctr.c @@ -51,12 +51,12 @@ static void Test_AesCtr_Basic(void) uint8_t ct[32] = {0}; uint8_t pt[32] = {0}; - WHAL_ASSERT_EQ(whal_AesCtr_Oneshot(&g_whalAesCtr, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesCtr_Oneshot(BOARD_AES_CTR_DEV, WHAL_CRYPTO_ENCRYPT, key, 32, iv, plaintext, ct, sizeof(plaintext)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesCtr_Oneshot(&g_whalAesCtr, WHAL_CRYPTO_DECRYPT, + WHAL_ASSERT_EQ(whal_AesCtr_Oneshot(BOARD_AES_CTR_DEV, WHAL_CRYPTO_DECRYPT, key, 32, iv, ct, pt, sizeof(ct)), WHAL_SUCCESS); @@ -67,7 +67,7 @@ static void Test_AesCtr_KnownAnswer(void) { uint8_t ct[16] = {0}; - WHAL_ASSERT_EQ(whal_AesCtr_Oneshot(&g_whalAesCtr, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesCtr_Oneshot(BOARD_AES_CTR_DEV, WHAL_CRYPTO_ENCRYPT, nistKey, 32, nistCtrIv, nistPt, ct, sizeof(nistPt)), WHAL_SUCCESS); diff --git a/tests/crypto/test_aes_ecb.c b/tests/crypto/test_aes_ecb.c index 2896847..6f45c11 100644 --- a/tests/crypto/test_aes_ecb.c +++ b/tests/crypto/test_aes_ecb.c @@ -41,12 +41,12 @@ static void Test_AesEcb_Basic(void) uint8_t ct[32] = {0}; uint8_t pt[32] = {0}; - WHAL_ASSERT_EQ(whal_AesEcb_Oneshot(&g_whalAesEcb, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesEcb_Oneshot(BOARD_AES_ECB_DEV, WHAL_CRYPTO_ENCRYPT, key, 32, plaintext, ct, sizeof(plaintext)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesEcb_Oneshot(&g_whalAesEcb, WHAL_CRYPTO_DECRYPT, + WHAL_ASSERT_EQ(whal_AesEcb_Oneshot(BOARD_AES_ECB_DEV, WHAL_CRYPTO_DECRYPT, key, 32, ct, pt, sizeof(ct)), WHAL_SUCCESS); @@ -57,7 +57,7 @@ static void Test_AesEcb_KnownAnswer(void) { uint8_t ct[16] = {0}; - WHAL_ASSERT_EQ(whal_AesEcb_Oneshot(&g_whalAesEcb, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesEcb_Oneshot(BOARD_AES_ECB_DEV, WHAL_CRYPTO_ENCRYPT, nistKey, 32, nistPt, ct, sizeof(nistPt)), WHAL_SUCCESS); diff --git a/tests/crypto/test_aes_gcm.c b/tests/crypto/test_aes_gcm.c index d7cc6fb..2215ff0 100644 --- a/tests/crypto/test_aes_gcm.c +++ b/tests/crypto/test_aes_gcm.c @@ -109,7 +109,7 @@ static void Test_AesGcm_Basic(void) uint8_t encTag[16] = {0}; uint8_t decTag[16] = {0}; - WHAL_ASSERT_EQ(whal_AesGcm_Oneshot(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesGcm_Oneshot(BOARD_AES_GCM_DEV, WHAL_CRYPTO_ENCRYPT, key, 32, nonce, sizeof(nonce), aad, sizeof(aad), @@ -117,7 +117,7 @@ static void Test_AesGcm_Basic(void) encTag, sizeof(encTag)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesGcm_Oneshot(&g_whalAesGcm, WHAL_CRYPTO_DECRYPT, + WHAL_ASSERT_EQ(whal_AesGcm_Oneshot(BOARD_AES_GCM_DEV, WHAL_CRYPTO_DECRYPT, key, 32, nonce, sizeof(nonce), aad, sizeof(aad), @@ -134,7 +134,7 @@ static void Test_AesGcm_KnownAnswer(void) uint8_t ct[64] = {0}; uint8_t tag[16] = {0}; - WHAL_ASSERT_EQ(whal_AesGcm_Oneshot(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesGcm_Oneshot(BOARD_AES_GCM_DEV, WHAL_CRYPTO_ENCRYPT, gcmKey, 32, gcmIv, sizeof(gcmIv), NULL, 0, @@ -151,7 +151,7 @@ static void Test_AesGcm_KnownAnswer_PartialBlocks(void) uint8_t ct[sizeof(gcm16Pt)] = {0}; uint8_t tag[16] = {0}; - WHAL_ASSERT_EQ(whal_AesGcm_Oneshot(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesGcm_Oneshot(BOARD_AES_GCM_DEV, WHAL_CRYPTO_ENCRYPT, gcmKey, 32, gcmIv, sizeof(gcmIv), gcm16Aad, sizeof(gcm16Aad), @@ -214,22 +214,22 @@ static void Test_AesGcm_Streaming(void) uint8_t tag[16] = {0}; const size_t split = 32; - WHAL_ASSERT_EQ(whal_AesGcm_Start(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesGcm_Start(BOARD_AES_GCM_DEV, WHAL_CRYPTO_ENCRYPT, gcmKey, 32, gcmIv, sizeof(gcmIv), gcmStreamAad, sizeof(gcmStreamAad)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesGcm_Process(&g_whalAesGcm, + WHAL_ASSERT_EQ(whal_AesGcm_Process(BOARD_AES_GCM_DEV, gcmStreamPt, ct, split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesGcm_Process(&g_whalAesGcm, + WHAL_ASSERT_EQ(whal_AesGcm_Process(BOARD_AES_GCM_DEV, gcmStreamPt + split, ct + split, sizeof(gcmStreamPt) - split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesGcm_Finalize(&g_whalAesGcm, tag, sizeof(tag)), + WHAL_ASSERT_EQ(whal_AesGcm_Finalize(BOARD_AES_GCM_DEV, tag, sizeof(tag)), WHAL_SUCCESS); WHAL_ASSERT_MEM_EQ(ct, gcmStreamCt, sizeof(gcmStreamCt)); @@ -242,22 +242,22 @@ static void Test_AesGcm_Streaming_NoAad(void) uint8_t tag[16] = {0}; const size_t split = 32; - WHAL_ASSERT_EQ(whal_AesGcm_Start(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesGcm_Start(BOARD_AES_GCM_DEV, WHAL_CRYPTO_ENCRYPT, gcmKey, 32, gcmIv, sizeof(gcmIv), NULL, 0), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesGcm_Process(&g_whalAesGcm, + WHAL_ASSERT_EQ(whal_AesGcm_Process(BOARD_AES_GCM_DEV, gcmStreamPt, ct, split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesGcm_Process(&g_whalAesGcm, + WHAL_ASSERT_EQ(whal_AesGcm_Process(BOARD_AES_GCM_DEV, gcmStreamPt + split, ct + split, sizeof(gcmStreamPt) - split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesGcm_Finalize(&g_whalAesGcm, tag, sizeof(tag)), + WHAL_ASSERT_EQ(whal_AesGcm_Finalize(BOARD_AES_GCM_DEV, tag, sizeof(tag)), WHAL_SUCCESS); WHAL_ASSERT_MEM_EQ(ct, gcmStreamCt, sizeof(gcmStreamCt)); @@ -268,13 +268,13 @@ static void Test_AesGcm_Streaming_NoPayload(void) { uint8_t tag[16] = {0}; - WHAL_ASSERT_EQ(whal_AesGcm_Start(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesGcm_Start(BOARD_AES_GCM_DEV, WHAL_CRYPTO_ENCRYPT, gcmKey, 32, gcmIv, sizeof(gcmIv), gcmStreamAad, sizeof(gcmStreamAad)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesGcm_Finalize(&g_whalAesGcm, tag, sizeof(tag)), + WHAL_ASSERT_EQ(whal_AesGcm_Finalize(BOARD_AES_GCM_DEV, tag, sizeof(tag)), WHAL_SUCCESS); WHAL_ASSERT_MEM_EQ(tag, gcmStreamNoPtTag, sizeof(gcmStreamNoPtTag)); @@ -285,25 +285,25 @@ static void Test_AesGcm_Streaming_ThreeCall(void) uint8_t ct[sizeof(gcmStreamPt)] = {0}; uint8_t tag[16] = {0}; - WHAL_ASSERT_EQ(whal_AesGcm_Start(&g_whalAesGcm, WHAL_CRYPTO_ENCRYPT, + WHAL_ASSERT_EQ(whal_AesGcm_Start(BOARD_AES_GCM_DEV, WHAL_CRYPTO_ENCRYPT, gcmKey, 32, gcmIv, sizeof(gcmIv), gcmStreamAad, sizeof(gcmStreamAad)), WHAL_SUCCESS); /* 16 + 16 + 18: two full blocks then one block + 2 partial. */ - WHAL_ASSERT_EQ(whal_AesGcm_Process(&g_whalAesGcm, + WHAL_ASSERT_EQ(whal_AesGcm_Process(BOARD_AES_GCM_DEV, gcmStreamPt, ct, 16), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesGcm_Process(&g_whalAesGcm, + WHAL_ASSERT_EQ(whal_AesGcm_Process(BOARD_AES_GCM_DEV, gcmStreamPt + 16, ct + 16, 16), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesGcm_Process(&g_whalAesGcm, + WHAL_ASSERT_EQ(whal_AesGcm_Process(BOARD_AES_GCM_DEV, gcmStreamPt + 32, ct + 32, sizeof(gcmStreamPt) - 32), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesGcm_Finalize(&g_whalAesGcm, tag, sizeof(tag)), + WHAL_ASSERT_EQ(whal_AesGcm_Finalize(BOARD_AES_GCM_DEV, tag, sizeof(tag)), WHAL_SUCCESS); WHAL_ASSERT_MEM_EQ(ct, gcmStreamCt, sizeof(gcmStreamCt)); diff --git a/tests/crypto/test_aes_gmac.c b/tests/crypto/test_aes_gmac.c index b6437b0..8200b9b 100644 --- a/tests/crypto/test_aes_gmac.c +++ b/tests/crypto/test_aes_gmac.c @@ -48,14 +48,14 @@ static void Test_AesGmac_Basic(void) uint8_t tag1[16] = {0}; uint8_t tag2[16] = {0}; - WHAL_ASSERT_EQ(whal_AesGmac_Oneshot(&g_whalAesGmac, + WHAL_ASSERT_EQ(whal_AesGmac_Oneshot(BOARD_AES_GMAC_DEV, key, 32, nonce, sizeof(nonce), aad, sizeof(aad), tag1, sizeof(tag1)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_AesGmac_Oneshot(&g_whalAesGmac, + WHAL_ASSERT_EQ(whal_AesGmac_Oneshot(BOARD_AES_GMAC_DEV, key, 32, nonce, sizeof(nonce), aad, sizeof(aad), @@ -69,7 +69,7 @@ static void Test_AesGmac_KnownAnswer(void) { uint8_t tag[16] = {0}; - WHAL_ASSERT_EQ(whal_AesGmac_Oneshot(&g_whalAesGmac, + WHAL_ASSERT_EQ(whal_AesGmac_Oneshot(BOARD_AES_GMAC_DEV, gmacKey, 32, gmacIv, sizeof(gmacIv), gmacAad, sizeof(gmacAad), diff --git a/tests/crypto/test_hmac_sha1.c b/tests/crypto/test_hmac_sha1.c index 96656a5..707bec5 100644 --- a/tests/crypto/test_hmac_sha1.c +++ b/tests/crypto/test_hmac_sha1.c @@ -25,7 +25,7 @@ static void Test_HmacSha1_KnownAnswer(void) { uint8_t digest[20] = {0}; - WHAL_ASSERT_EQ(whal_HmacSha1_Oneshot(&g_whalHmacSha1, + WHAL_ASSERT_EQ(whal_HmacSha1_Oneshot(BOARD_HMAC_SHA1_DEV, hmacKey, sizeof(hmacKey), hmacInput, sizeof(hmacInput), digest, sizeof(digest)), @@ -63,17 +63,17 @@ static void Test_HmacSha1_Streaming(void) uint8_t digest[20] = {0}; const size_t split = 50; - WHAL_ASSERT_EQ(whal_HmacSha1_Start(&g_whalHmacSha1, + WHAL_ASSERT_EQ(whal_HmacSha1_Start(BOARD_HMAC_SHA1_DEV, hmacKey, sizeof(hmacKey)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_HmacSha1_Process(&g_whalHmacSha1, + WHAL_ASSERT_EQ(whal_HmacSha1_Process(BOARD_HMAC_SHA1_DEV, hmacStreamMsg, split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_HmacSha1_Process(&g_whalHmacSha1, + WHAL_ASSERT_EQ(whal_HmacSha1_Process(BOARD_HMAC_SHA1_DEV, hmacStreamMsg + split, sizeof(hmacStreamMsg) - split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_HmacSha1_Finalize(&g_whalHmacSha1, + WHAL_ASSERT_EQ(whal_HmacSha1_Finalize(BOARD_HMAC_SHA1_DEV, digest, sizeof(digest)), WHAL_SUCCESS); diff --git a/tests/crypto/test_hmac_sha224.c b/tests/crypto/test_hmac_sha224.c index 02ba8fb..7d60746 100644 --- a/tests/crypto/test_hmac_sha224.c +++ b/tests/crypto/test_hmac_sha224.c @@ -26,7 +26,7 @@ static void Test_HmacSha224_KnownAnswer(void) { uint8_t digest[28] = {0}; - WHAL_ASSERT_EQ(whal_HmacSha224_Oneshot(&g_whalHmacSha224, + WHAL_ASSERT_EQ(whal_HmacSha224_Oneshot(BOARD_HMAC_SHA224_DEV, hmacKey, sizeof(hmacKey), hmacInput, sizeof(hmacInput), digest, sizeof(digest)), @@ -65,17 +65,17 @@ static void Test_HmacSha224_Streaming(void) uint8_t digest[28] = {0}; const size_t split = 50; - WHAL_ASSERT_EQ(whal_HmacSha224_Start(&g_whalHmacSha224, + WHAL_ASSERT_EQ(whal_HmacSha224_Start(BOARD_HMAC_SHA224_DEV, hmacKey, sizeof(hmacKey)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_HmacSha224_Process(&g_whalHmacSha224, + WHAL_ASSERT_EQ(whal_HmacSha224_Process(BOARD_HMAC_SHA224_DEV, hmacStreamMsg, split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_HmacSha224_Process(&g_whalHmacSha224, + WHAL_ASSERT_EQ(whal_HmacSha224_Process(BOARD_HMAC_SHA224_DEV, hmacStreamMsg + split, sizeof(hmacStreamMsg) - split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_HmacSha224_Finalize(&g_whalHmacSha224, + WHAL_ASSERT_EQ(whal_HmacSha224_Finalize(BOARD_HMAC_SHA224_DEV, digest, sizeof(digest)), WHAL_SUCCESS); diff --git a/tests/crypto/test_hmac_sha256.c b/tests/crypto/test_hmac_sha256.c index ebd09ad..2df0426 100644 --- a/tests/crypto/test_hmac_sha256.c +++ b/tests/crypto/test_hmac_sha256.c @@ -26,7 +26,7 @@ static void Test_HmacSha256_KnownAnswer(void) { uint8_t digest[32] = {0}; - WHAL_ASSERT_EQ(whal_HmacSha256_Oneshot(&g_whalHmacSha256, + WHAL_ASSERT_EQ(whal_HmacSha256_Oneshot(BOARD_HMAC_SHA256_DEV, hmacKey, sizeof(hmacKey), hmacInput, sizeof(hmacInput), digest, sizeof(digest)), @@ -65,17 +65,17 @@ static void Test_HmacSha256_Streaming(void) uint8_t digest[32] = {0}; const size_t split = 50; - WHAL_ASSERT_EQ(whal_HmacSha256_Start(&g_whalHmacSha256, + WHAL_ASSERT_EQ(whal_HmacSha256_Start(BOARD_HMAC_SHA256_DEV, hmacKey, sizeof(hmacKey)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_HmacSha256_Process(&g_whalHmacSha256, + WHAL_ASSERT_EQ(whal_HmacSha256_Process(BOARD_HMAC_SHA256_DEV, hmacStreamMsg, split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_HmacSha256_Process(&g_whalHmacSha256, + WHAL_ASSERT_EQ(whal_HmacSha256_Process(BOARD_HMAC_SHA256_DEV, hmacStreamMsg + split, sizeof(hmacStreamMsg) - split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_HmacSha256_Finalize(&g_whalHmacSha256, + WHAL_ASSERT_EQ(whal_HmacSha256_Finalize(BOARD_HMAC_SHA256_DEV, digest, sizeof(digest)), WHAL_SUCCESS); diff --git a/tests/crypto/test_sha1.c b/tests/crypto/test_sha1.c index 5e90c3c..33aeef7 100644 --- a/tests/crypto/test_sha1.c +++ b/tests/crypto/test_sha1.c @@ -16,7 +16,7 @@ static void Test_Sha1_KnownAnswer(void) { uint8_t digest[20] = {0}; - WHAL_ASSERT_EQ(whal_Sha1_Oneshot(&g_whalSha1, + WHAL_ASSERT_EQ(whal_Sha1_Oneshot(BOARD_SHA1_DEV, hashInput, sizeof(hashInput), digest, sizeof(digest)), WHAL_SUCCESS); @@ -53,14 +53,14 @@ static void Test_Sha1_Streaming(void) uint8_t digest[20] = {0}; const size_t split = 50; - WHAL_ASSERT_EQ(whal_Sha1_Start(&g_whalSha1), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Sha1_Process(&g_whalSha1, streamMsg, split), + WHAL_ASSERT_EQ(whal_Sha1_Start(BOARD_SHA1_DEV), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Sha1_Process(BOARD_SHA1_DEV, streamMsg, split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Sha1_Process(&g_whalSha1, + WHAL_ASSERT_EQ(whal_Sha1_Process(BOARD_SHA1_DEV, streamMsg + split, sizeof(streamMsg) - split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Sha1_Finalize(&g_whalSha1, digest, sizeof(digest)), + WHAL_ASSERT_EQ(whal_Sha1_Finalize(BOARD_SHA1_DEV, digest, sizeof(digest)), WHAL_SUCCESS); WHAL_ASSERT_MEM_EQ(digest, sha1StreamDigest, sizeof(sha1StreamDigest)); diff --git a/tests/crypto/test_sha224.c b/tests/crypto/test_sha224.c index f46ec0f..0a93177 100644 --- a/tests/crypto/test_sha224.c +++ b/tests/crypto/test_sha224.c @@ -17,7 +17,7 @@ static void Test_Sha224_KnownAnswer(void) { uint8_t digest[28] = {0}; - WHAL_ASSERT_EQ(whal_Sha224_Oneshot(&g_whalSha224, + WHAL_ASSERT_EQ(whal_Sha224_Oneshot(BOARD_SHA224_DEV, hashInput, sizeof(hashInput), digest, sizeof(digest)), WHAL_SUCCESS); @@ -55,14 +55,14 @@ static void Test_Sha224_Streaming(void) uint8_t digest[28] = {0}; const size_t split = 50; - WHAL_ASSERT_EQ(whal_Sha224_Start(&g_whalSha224), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Sha224_Process(&g_whalSha224, streamMsg, split), + WHAL_ASSERT_EQ(whal_Sha224_Start(BOARD_SHA224_DEV), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Sha224_Process(BOARD_SHA224_DEV, streamMsg, split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Sha224_Process(&g_whalSha224, + WHAL_ASSERT_EQ(whal_Sha224_Process(BOARD_SHA224_DEV, streamMsg + split, sizeof(streamMsg) - split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Sha224_Finalize(&g_whalSha224, + WHAL_ASSERT_EQ(whal_Sha224_Finalize(BOARD_SHA224_DEV, digest, sizeof(digest)), WHAL_SUCCESS); diff --git a/tests/crypto/test_sha256.c b/tests/crypto/test_sha256.c index ee4a9fe..7e5af22 100644 --- a/tests/crypto/test_sha256.c +++ b/tests/crypto/test_sha256.c @@ -17,7 +17,7 @@ static void Test_Sha256_KnownAnswer(void) { uint8_t digest[32] = {0}; - WHAL_ASSERT_EQ(whal_Sha256_Oneshot(&g_whalSha256, + WHAL_ASSERT_EQ(whal_Sha256_Oneshot(BOARD_SHA256_DEV, hashInput, sizeof(hashInput), digest, sizeof(digest)), WHAL_SUCCESS); @@ -55,14 +55,14 @@ static void Test_Sha256_Streaming(void) uint8_t digest[32] = {0}; const size_t split = 50; - WHAL_ASSERT_EQ(whal_Sha256_Start(&g_whalSha256), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Sha256_Process(&g_whalSha256, streamMsg, split), + WHAL_ASSERT_EQ(whal_Sha256_Start(BOARD_SHA256_DEV), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Sha256_Process(BOARD_SHA256_DEV, streamMsg, split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Sha256_Process(&g_whalSha256, + WHAL_ASSERT_EQ(whal_Sha256_Process(BOARD_SHA256_DEV, streamMsg + split, sizeof(streamMsg) - split), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Sha256_Finalize(&g_whalSha256, + WHAL_ASSERT_EQ(whal_Sha256_Finalize(BOARD_SHA256_DEV, digest, sizeof(digest)), WHAL_SUCCESS); diff --git a/tests/eth/test_eth.c b/tests/eth/test_eth.c index e2c6a34..6bbb212 100644 --- a/tests/eth/test_eth.c +++ b/tests/eth/test_eth.c @@ -31,10 +31,10 @@ static void Test_Eth_Api(void) WHAL_ASSERT_EQ(whal_Eth_Recv(NULL, buf, &len), WHAL_EINVAL); WHAL_ASSERT_EQ(whal_Eth_MdioRead(NULL, 0, 0, &val), WHAL_EINVAL); WHAL_ASSERT_EQ(whal_Eth_MdioWrite(NULL, 0, 0, 0), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Eth_Send(&g_whalEth, NULL, 64), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Eth_Recv(&g_whalEth, NULL, &len), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Eth_Recv(&g_whalEth, buf, NULL), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Eth_MdioRead(&g_whalEth, 0, 0, NULL), WHAL_EINVAL); + WHAL_ASSERT_EQ(whal_Eth_Send(BOARD_ETH_DEV, NULL, 64), WHAL_EINVAL); + WHAL_ASSERT_EQ(whal_Eth_Recv(BOARD_ETH_DEV, NULL, &len), WHAL_EINVAL); + WHAL_ASSERT_EQ(whal_Eth_Recv(BOARD_ETH_DEV, buf, NULL), WHAL_EINVAL); + WHAL_ASSERT_EQ(whal_Eth_MdioRead(BOARD_ETH_DEV, 0, 0, NULL), WHAL_EINVAL); WHAL_ASSERT_EQ(whal_EthPhy_Init(NULL), WHAL_EINVAL); WHAL_ASSERT_EQ(whal_EthPhy_Deinit(NULL), WHAL_EINVAL); @@ -46,9 +46,9 @@ static void Test_Eth_MdioReadPhyId(void) uint16_t id1 = 0; uint16_t id2 = 0; - WHAL_ASSERT_EQ(whal_Eth_MdioRead(&g_whalEth, BOARD_ETH_PHY_ADDR, + WHAL_ASSERT_EQ(whal_Eth_MdioRead(BOARD_ETH_DEV, BOARD_ETH_PHY_ADDR, PHY_REG_PHYIDR1, &id1), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Eth_MdioRead(&g_whalEth, BOARD_ETH_PHY_ADDR, + WHAL_ASSERT_EQ(whal_Eth_MdioRead(BOARD_ETH_DEV, BOARD_ETH_PHY_ADDR, PHY_REG_PHYIDR2, &id2), WHAL_SUCCESS); /* PHY ID should not be 0x0000 or 0xFFFF (no PHY / bus error) */ @@ -69,7 +69,7 @@ static void Test_Eth_PhyGetLinkState(void) uint8_t speed = 0; uint8_t duplex = 0; - WHAL_ASSERT_EQ(whal_EthPhy_GetLinkState(&g_whalEthPhy, &up, &speed, + WHAL_ASSERT_EQ(whal_EthPhy_GetLinkState(BOARD_ETH_PHY_DEV, &up, &speed, &duplex), WHAL_SUCCESS); whal_Test_Printf(" link: %s, speed: %d, duplex: %s\n", diff --git a/tests/eth/test_stm32h5_eth.c b/tests/eth/test_stm32h5_eth.c index c4530db..226d907 100644 --- a/tests/eth/test_stm32h5_eth.c +++ b/tests/eth/test_stm32h5_eth.c @@ -30,18 +30,18 @@ static void Test_Eth_Loopback(void) size_t rxLen = sizeof(rxFrame); whal_Error err; - WHAL_ASSERT_EQ(whal_Stm32h5_Eth_Ext_EnableLoopback(&g_whalEth, 1), + WHAL_ASSERT_EQ(whal_Stm32h5_Eth_Ext_EnableLoopback(BOARD_ETH_DEV, 1), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Eth_Start(&g_whalEth, WHAL_ETH_SPEED_100, + WHAL_ASSERT_EQ(whal_Eth_Start(BOARD_ETH_DEV, WHAL_ETH_SPEED_100, WHAL_ETH_DUPLEX_FULL), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Eth_Send(&g_whalEth, txFrame, sizeof(txFrame)), + WHAL_ASSERT_EQ(whal_Eth_Send(BOARD_ETH_DEV, txFrame, sizeof(txFrame)), WHAL_SUCCESS); /* Poll for the looped-back frame */ uint32_t start = g_tick; do { - err = whal_Eth_Recv(&g_whalEth, rxFrame, &rxLen); + err = whal_Eth_Recv(BOARD_ETH_DEV, rxFrame, &rxLen); } while (err == WHAL_ENOTREADY && (g_tick - start) < 100); WHAL_ASSERT_EQ(err, WHAL_SUCCESS); @@ -49,9 +49,9 @@ static void Test_Eth_Loopback(void) /* Verify payload matches (skip MAC header) */ WHAL_ASSERT_MEM_EQ(rxFrame + 14, txFrame + 14, sizeof(txFrame) - 14); - WHAL_ASSERT_EQ(whal_Eth_Stop(&g_whalEth), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Eth_Stop(BOARD_ETH_DEV), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Stm32h5_Eth_Ext_EnableLoopback(&g_whalEth, 0), + WHAL_ASSERT_EQ(whal_Stm32h5_Eth_Ext_EnableLoopback(BOARD_ETH_DEV, 0), WHAL_SUCCESS); } diff --git a/tests/eth/test_stm32n6_eth.c b/tests/eth/test_stm32n6_eth.c index abe4bc0..711e241 100644 --- a/tests/eth/test_stm32n6_eth.c +++ b/tests/eth/test_stm32n6_eth.c @@ -44,13 +44,13 @@ static void Test_Eth_Loopback(void) }; uint8_t rxFrame[1536]; size_t rxLen = sizeof(rxFrame); - size_t base = g_whalEth.base; - whal_Stm32n6_Eth_Cfg *ethCfg = (whal_Stm32n6_Eth_Cfg *)g_whalEth.cfg; + size_t base = whal_Stm32n6_Eth_Dev.base; + whal_Stm32n6_Eth_Cfg *ethCfg = (whal_Stm32n6_Eth_Cfg *)whal_Stm32n6_Eth_Dev.cfg; whal_Error err; uint16_t bcr = 0; /* Verify the LAN8742A is alive and not in software power-down. */ - err = whal_Eth_MdioRead(&g_whalEth, BOARD_ETH_PHY_ADDR, 0x00, &bcr); + err = whal_Eth_MdioRead(BOARD_ETH_DEV, BOARD_ETH_PHY_ADDR, 0x00, &bcr); whal_Test_Printf(" PHY BCR read: err=%d val=%d (pwd=%d)\n", (int)err, (int)bcr, (int)((bcr >> 11) & 1)); @@ -72,15 +72,15 @@ static void Test_Eth_Loopback(void) DumpHex32("DMAC0TXDLAR", (uint32_t)whal_Reg_Read(base, 0x1114)); DumpHex32("DMAC0RXDLAR", (uint32_t)whal_Reg_Read(base, 0x111C)); - WHAL_ASSERT_EQ(whal_Stm32n6_Eth_Ext_EnableLoopback(&g_whalEth, 1), + WHAL_ASSERT_EQ(whal_Stm32n6_Eth_Ext_EnableLoopback(BOARD_ETH_DEV, 1), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Eth_Start(&g_whalEth, WHAL_ETH_SPEED_100, + WHAL_ASSERT_EQ(whal_Eth_Start(BOARD_ETH_DEV, WHAL_ETH_SPEED_100, WHAL_ETH_DUPLEX_FULL), WHAL_SUCCESS); DumpHex32("MACCR after Start", (uint32_t)whal_Reg_Read(base, DBG_MACCR_REG)); - WHAL_ASSERT_EQ(whal_Eth_Send(&g_whalEth, txFrame, sizeof(txFrame)), + WHAL_ASSERT_EQ(whal_Eth_Send(BOARD_ETH_DEV, txFrame, sizeof(txFrame)), WHAL_SUCCESS); /* Give the MAC a moment, then snapshot TX/RX descriptor state. */ @@ -95,7 +95,7 @@ static void Test_Eth_Loopback(void) /* Poll for the looped-back frame */ uint32_t start = g_tick; do { - err = whal_Eth_Recv(&g_whalEth, rxFrame, &rxLen); + err = whal_Eth_Recv(BOARD_ETH_DEV, rxFrame, &rxLen); } while (err == WHAL_ENOTREADY && (g_tick - start) < 100); if (err != WHAL_SUCCESS) { @@ -113,9 +113,9 @@ static void Test_Eth_Loopback(void) /* Verify payload matches (skip MAC header) */ WHAL_ASSERT_MEM_EQ(rxFrame + 14, txFrame + 14, sizeof(txFrame) - 14); - WHAL_ASSERT_EQ(whal_Eth_Stop(&g_whalEth), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Eth_Stop(BOARD_ETH_DEV), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Stm32n6_Eth_Ext_EnableLoopback(&g_whalEth, 0), + WHAL_ASSERT_EQ(whal_Stm32n6_Eth_Ext_EnableLoopback(BOARD_ETH_DEV, 0), WHAL_SUCCESS); } diff --git a/tests/flash/test_flash.c b/tests/flash/test_flash.c index f4044c1..79b3891 100644 --- a/tests/flash/test_flash.c +++ b/tests/flash/test_flash.c @@ -78,7 +78,7 @@ static void run_flash_tests(const char *name) void whal_Test_Flash(void) { /* Test on-chip flash */ - g_testFlashDev = &g_whalFlash; + g_testFlashDev = BOARD_FLASH_DEV; g_testFlashAddr = BOARD_FLASH_TEST_ADDR; g_testFlashSectorSz = BOARD_FLASH_SECTOR_SZ; run_flash_tests("on-chip"); diff --git a/tests/flash/test_stm32wb_flash.c b/tests/flash/test_stm32wb_flash.c index 0ef6e83..0040fe8 100644 --- a/tests/flash/test_stm32wb_flash.c +++ b/tests/flash/test_stm32wb_flash.c @@ -13,7 +13,7 @@ static void Test_Flash_LockReadback(void) { /* After locking, the CR.LOCK bit should be set */ - WHAL_ASSERT_EQ(whal_Flash_Lock(&g_whalFlash, 0, 0), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Flash_Lock(BOARD_FLASH_DEV, 0, 0), WHAL_SUCCESS); size_t val = 0; whal_Reg_Get(g_whalFlash.base, FLASH_CR_REG, diff --git a/tests/gpio/test_gpio.c b/tests/gpio/test_gpio.c index 839f497..36fd548 100644 --- a/tests/gpio/test_gpio.c +++ b/tests/gpio/test_gpio.c @@ -10,7 +10,7 @@ static void Test_Gpio_Api(void) WHAL_ASSERT_EQ(whal_Gpio_Deinit(NULL), WHAL_EINVAL); WHAL_ASSERT_EQ(whal_Gpio_Get(NULL, 0, &val), WHAL_EINVAL); WHAL_ASSERT_EQ(whal_Gpio_Set(NULL, 0, 0), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Gpio_Get(&g_whalGpio, 0, NULL), WHAL_EINVAL); + WHAL_ASSERT_EQ(whal_Gpio_Get(BOARD_GPIO_DEV, 0, NULL), WHAL_EINVAL); } static void Test_Gpio_SetGetHighLow(void) @@ -18,13 +18,13 @@ static void Test_Gpio_SetGetHighLow(void) size_t val = 0; /* Set high and verify */ - WHAL_ASSERT_EQ(whal_Gpio_Set(&g_whalGpio, BOARD_LED_PIN, 1), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Gpio_Get(&g_whalGpio, BOARD_LED_PIN, &val), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 1), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Gpio_Get(BOARD_GPIO_DEV, BOARD_LED_PIN, &val), WHAL_SUCCESS); WHAL_ASSERT_EQ(val, 1); /* Set low and verify */ - WHAL_ASSERT_EQ(whal_Gpio_Set(&g_whalGpio, BOARD_LED_PIN, 0), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Gpio_Get(&g_whalGpio, BOARD_LED_PIN, &val), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 0), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Gpio_Get(BOARD_GPIO_DEV, BOARD_LED_PIN, &val), WHAL_SUCCESS); WHAL_ASSERT_EQ(val, 0); } diff --git a/tests/gpio/test_pic32cz_gpio.c b/tests/gpio/test_pic32cz_gpio.c index 7a767b5..9157891 100644 --- a/tests/gpio/test_pic32cz_gpio.c +++ b/tests/gpio/test_pic32cz_gpio.c @@ -19,28 +19,28 @@ static void Test_Gpio_DirRegister(void) { /* PB21 should be configured as output (bit 21 set in DIR register) */ size_t val = 0; - whal_Reg_Get(g_whalGpio.base, PORT_DIR_REG(LED_PORT), + whal_Reg_Get(whal_Pic32cz_Gpio_Dev.base, PORT_DIR_REG(LED_PORT), (1UL << LED_HW_PIN), LED_HW_PIN, &val); WHAL_ASSERT_EQ(val, 1); } static void Test_Gpio_SetHighReg(void) { - WHAL_ASSERT_EQ(whal_Gpio_Set(&g_whalGpio, BOARD_LED_PIN, 1), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 1), WHAL_SUCCESS); /* Readback OUT register bit 21 */ size_t val = 0; - whal_Reg_Get(g_whalGpio.base, PORT_OUT_REG(LED_PORT), + whal_Reg_Get(whal_Pic32cz_Gpio_Dev.base, PORT_OUT_REG(LED_PORT), (1UL << LED_HW_PIN), LED_HW_PIN, &val); WHAL_ASSERT_EQ(val, 1); } static void Test_Gpio_SetLowReg(void) { - WHAL_ASSERT_EQ(whal_Gpio_Set(&g_whalGpio, BOARD_LED_PIN, 0), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 0), WHAL_SUCCESS); size_t val = 0; - whal_Reg_Get(g_whalGpio.base, PORT_OUT_REG(LED_PORT), + whal_Reg_Get(whal_Pic32cz_Gpio_Dev.base, PORT_OUT_REG(LED_PORT), (1UL << LED_HW_PIN), LED_HW_PIN, &val); WHAL_ASSERT_EQ(val, 0); } diff --git a/tests/gpio/test_stm32wb_gpio.c b/tests/gpio/test_stm32wb_gpio.c index fce5da2..1196615 100644 --- a/tests/gpio/test_stm32wb_gpio.c +++ b/tests/gpio/test_stm32wb_gpio.c @@ -6,7 +6,7 @@ /* * GPIO register offsets. Port and pin are derived from the LED entry in - * g_whalGpio.cfg->pinCfg[BOARD_LED_PIN]. Port stride is 0x400 on all + * whal_Stm32wb_Gpio_Dev.cfg->pinCfg[BOARD_LED_PIN]. Port stride is 0x400 on all * supported STM32 families. */ #define GPIOx_MODE_REG 0x00 @@ -15,14 +15,14 @@ static inline size_t Board_LedPortBase(void) { - whal_Stm32wb_Gpio_Cfg *cfg = (whal_Stm32wb_Gpio_Cfg *)g_whalGpio.cfg; + const whal_Stm32wb_Gpio_Cfg *cfg = (const whal_Stm32wb_Gpio_Cfg *)whal_Stm32wb_Gpio_Dev.cfg; whal_Stm32wb_Gpio_PinCfg led = cfg->pinCfg[BOARD_LED_PIN]; - return g_whalGpio.base + WHAL_STM32WB_GPIO_GET_PORT(led) * GPIOx_STRIDE; + return whal_Stm32wb_Gpio_Dev.base + WHAL_STM32WB_GPIO_GET_PORT(led) * GPIOx_STRIDE; } static inline size_t Board_LedPinNum(void) { - whal_Stm32wb_Gpio_Cfg *cfg = (whal_Stm32wb_Gpio_Cfg *)g_whalGpio.cfg; + const whal_Stm32wb_Gpio_Cfg *cfg = (const whal_Stm32wb_Gpio_Cfg *)whal_Stm32wb_Gpio_Dev.cfg; whal_Stm32wb_Gpio_PinCfg led = cfg->pinCfg[BOARD_LED_PIN]; return WHAL_STM32WB_GPIO_GET_PIN(led); } @@ -45,8 +45,8 @@ static void Test_Gpio_PinCfgRoundTrip(void) static void Test_Gpio_NoDuplicatePins(void) { - whal_Stm32wb_Gpio_Cfg *cfg = (whal_Stm32wb_Gpio_Cfg *)g_whalGpio.cfg; - whal_Stm32wb_Gpio_PinCfg *pins = cfg->pinCfg; + const whal_Stm32wb_Gpio_Cfg *cfg = (const whal_Stm32wb_Gpio_Cfg *)whal_Stm32wb_Gpio_Dev.cfg; + const whal_Stm32wb_Gpio_PinCfg *pins = cfg->pinCfg; for (size_t i = 0; i < cfg->pinCount; i++) { for (size_t j = i + 1; j < cfg->pinCount; j++) { @@ -72,7 +72,7 @@ static void Test_Gpio_ModeRegister(void) static void Test_Gpio_SetHighReg(void) { - WHAL_ASSERT_EQ(whal_Gpio_Set(&g_whalGpio, BOARD_LED_PIN, 1), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 1), WHAL_SUCCESS); size_t pinNum = Board_LedPinNum(); size_t val = 0; @@ -83,7 +83,7 @@ static void Test_Gpio_SetHighReg(void) static void Test_Gpio_SetLowReg(void) { - WHAL_ASSERT_EQ(whal_Gpio_Set(&g_whalGpio, BOARD_LED_PIN, 0), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 0), WHAL_SUCCESS); size_t pinNum = Board_LedPinNum(); size_t val = 0; diff --git a/tests/i2c/test_i2c.c b/tests/i2c/test_i2c.c index e05abb8..76b7ad6 100644 --- a/tests/i2c/test_i2c.c +++ b/tests/i2c/test_i2c.c @@ -12,8 +12,8 @@ static void Test_I2c_Api(void) WHAL_ASSERT_EQ(whal_I2c_StartCom(NULL, &comCfg), WHAL_EINVAL); WHAL_ASSERT_EQ(whal_I2c_EndCom(NULL), WHAL_EINVAL); WHAL_ASSERT_EQ(whal_I2c_Transfer(NULL, &msg, 1), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_I2c_StartCom(&g_whalI2c, NULL), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_I2c_Transfer(&g_whalI2c, NULL, 1), WHAL_EINVAL); + WHAL_ASSERT_EQ(whal_I2c_StartCom(BOARD_I2C_DEV, NULL), WHAL_EINVAL); + WHAL_ASSERT_EQ(whal_I2c_Transfer(BOARD_I2C_DEV, NULL, 1), WHAL_EINVAL); } void whal_Test_I2c(void) diff --git a/tests/ipc/test_ipc.c b/tests/ipc/test_ipc.c index edb365c..78fe099 100644 --- a/tests/ipc/test_ipc.c +++ b/tests/ipc/test_ipc.c @@ -4,9 +4,9 @@ static void Test_Ipc_InitDeinit(void) { - WHAL_ASSERT_EQ(whal_Ipc_Init(&g_whalIpc), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Ipc_Deinit(&g_whalIpc), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Ipc_Init(&g_whalIpc), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Ipc_Init(BOARD_IPC_DEV), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Ipc_Deinit(BOARD_IPC_DEV), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Ipc_Init(BOARD_IPC_DEV), WHAL_SUCCESS); } static void Test_Ipc_InitNull(void) @@ -16,12 +16,12 @@ static void Test_Ipc_InitNull(void) static void Test_Ipc_SendNull(void) { - WHAL_ASSERT_EQ(whal_Ipc_Send(&g_whalIpc, NULL, 0), WHAL_EINVAL); + WHAL_ASSERT_EQ(whal_Ipc_Send(BOARD_IPC_DEV, NULL, 0), WHAL_EINVAL); } static void Test_Ipc_RecvNull(void) { - WHAL_ASSERT_EQ(whal_Ipc_Recv(&g_whalIpc, NULL, 0), WHAL_EINVAL); + WHAL_ASSERT_EQ(whal_Ipc_Recv(BOARD_IPC_DEV, NULL, 0), WHAL_EINVAL); } void whal_Test_Ipc(void) diff --git a/tests/main.c b/tests/main.c index c55314b..55d9b85 100644 --- a/tests/main.c +++ b/tests/main.c @@ -176,10 +176,10 @@ void whal_Test_Puts(const char *s) if (len == 0) return; - whal_Uart_Send(&g_whalUart, s, len); + whal_Uart_Send(BOARD_UART_DEV, s, len); if (s[len - 1] == '\n') - whal_Uart_Send(&g_whalUart, "\r", 1); + whal_Uart_Send(BOARD_UART_DEV, "\r", 1); } void main(void) @@ -191,7 +191,7 @@ void main(void) if (Board_Init() != WHAL_SUCCESS) while (1); - whal_Gpio_Set(&g_whalGpio, BOARD_LED_PIN, 1); + whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 1); whal_Test_Printf("wolfHAL HW Test Suite\n"); whal_Test_Printf("=====================\n"); @@ -357,14 +357,14 @@ void main(void) WHAL_TEST_SUMMARY(); if (g_whalTestFailed == 0) { - whal_Gpio_Set(&g_whalGpio, BOARD_LED_PIN, 1); + whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 1); while (1); } while (1) { - whal_Gpio_Set(&g_whalGpio, BOARD_LED_PIN, 1); + whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 1); Board_WaitMs(100); - whal_Gpio_Set(&g_whalGpio, BOARD_LED_PIN, 0); + whal_Gpio_Set(BOARD_GPIO_DEV, BOARD_LED_PIN, 0); Board_WaitMs(100); } } diff --git a/tests/rng/test_rng.c b/tests/rng/test_rng.c index 64a2cbc..1e9ee5a 100644 --- a/tests/rng/test_rng.c +++ b/tests/rng/test_rng.c @@ -10,7 +10,7 @@ static void Test_Rng_Api(void) WHAL_ASSERT_EQ(whal_Rng_Init(NULL), WHAL_EINVAL); WHAL_ASSERT_EQ(whal_Rng_Deinit(NULL), WHAL_EINVAL); WHAL_ASSERT_EQ(whal_Rng_Generate(NULL, buf, sizeof(buf)), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Rng_Generate(&g_whalRng, NULL, 8), WHAL_EINVAL); + WHAL_ASSERT_EQ(whal_Rng_Generate(BOARD_RNG_DEV, NULL, 8), WHAL_EINVAL); } static void Test_Rng_GenerateNonzero(void) @@ -18,7 +18,7 @@ static void Test_Rng_GenerateNonzero(void) uint8_t buf[32] = {0}; int allZero = 1; - WHAL_ASSERT_EQ(whal_Rng_Generate(&g_whalRng, buf, sizeof(buf)), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Rng_Generate(BOARD_RNG_DEV, buf, sizeof(buf)), WHAL_SUCCESS); for (size_t i = 0; i < sizeof(buf); i++) { if (buf[i] != 0) { @@ -36,8 +36,8 @@ static void Test_Rng_GenerateUnique(void) uint8_t buf2[16] = {0}; int same = 1; - WHAL_ASSERT_EQ(whal_Rng_Generate(&g_whalRng, buf1, sizeof(buf1)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Rng_Generate(&g_whalRng, buf2, sizeof(buf2)), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Rng_Generate(BOARD_RNG_DEV, buf1, sizeof(buf1)), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Rng_Generate(BOARD_RNG_DEV, buf2, sizeof(buf2)), WHAL_SUCCESS); for (size_t i = 0; i < sizeof(buf1); i++) { if (buf1[i] != buf2[i]) { diff --git a/tests/spi/test_spi_loopback.c b/tests/spi/test_spi_loopback.c index 05754f6..1d40faf 100644 --- a/tests/spi/test_spi_loopback.c +++ b/tests/spi/test_spi_loopback.c @@ -21,12 +21,12 @@ static void Test_SpiLoopback_SendRecv(void) uint8_t tx[] = {0xDE, 0xAD, 0xBE, 0xEF}; uint8_t rx[4] = {0}; - WHAL_ASSERT_EQ(whal_Spi_StartCom(&g_whalSpi, &loopbackComCfg), + WHAL_ASSERT_EQ(whal_Spi_StartCom(BOARD_SPI_DEV, &loopbackComCfg), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Spi_SendRecv(&g_whalSpi, + WHAL_ASSERT_EQ(whal_Spi_SendRecv(BOARD_SPI_DEV, tx, sizeof(tx), rx, sizeof(rx)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Spi_EndCom(&g_whalSpi), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Spi_EndCom(BOARD_SPI_DEV), WHAL_SUCCESS); WHAL_ASSERT_MEM_EQ(rx, tx, sizeof(tx)); } @@ -34,18 +34,18 @@ static void Test_SpiLoopback_NullBufWithLen(void) { uint8_t buf[1] = {0}; - WHAL_ASSERT_EQ(whal_Spi_StartCom(&g_whalSpi, &loopbackComCfg), + WHAL_ASSERT_EQ(whal_Spi_StartCom(BOARD_SPI_DEV, &loopbackComCfg), WHAL_SUCCESS); /* NULL tx with nonzero txLen */ - WHAL_ASSERT_EQ(whal_Spi_SendRecv(&g_whalSpi, NULL, 1, buf, 1), + WHAL_ASSERT_EQ(whal_Spi_SendRecv(BOARD_SPI_DEV, NULL, 1, buf, 1), WHAL_EINVAL); /* NULL rx with nonzero rxLen */ - WHAL_ASSERT_EQ(whal_Spi_SendRecv(&g_whalSpi, buf, 1, NULL, 1), + WHAL_ASSERT_EQ(whal_Spi_SendRecv(BOARD_SPI_DEV, buf, 1, NULL, 1), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Spi_EndCom(&g_whalSpi), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Spi_EndCom(BOARD_SPI_DEV), WHAL_SUCCESS); } static void Test_SpiLoopback_SendRecvDrain(void) @@ -54,18 +54,18 @@ static void Test_SpiLoopback_SendRecvDrain(void) uint8_t rx[4] = {0}; uint8_t expected[4] = {0xFF, 0xFF, 0xFF, 0xFF}; - WHAL_ASSERT_EQ(whal_Spi_StartCom(&g_whalSpi, &loopbackComCfg), + WHAL_ASSERT_EQ(whal_Spi_StartCom(BOARD_SPI_DEV, &loopbackComCfg), WHAL_SUCCESS); /* Send-only: driver must drain RX FIFO internally */ - WHAL_ASSERT_EQ(whal_Spi_SendRecv(&g_whalSpi, tx, sizeof(tx), NULL, 0), + WHAL_ASSERT_EQ(whal_Spi_SendRecv(BOARD_SPI_DEV, tx, sizeof(tx), NULL, 0), WHAL_SUCCESS); /* Receive-only: loopback returns 0xFF (the dummy TX byte) */ - WHAL_ASSERT_EQ(whal_Spi_SendRecv(&g_whalSpi, NULL, 0, rx, sizeof(rx)), + WHAL_ASSERT_EQ(whal_Spi_SendRecv(BOARD_SPI_DEV, NULL, 0, rx, sizeof(rx)), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Spi_EndCom(&g_whalSpi), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Spi_EndCom(BOARD_SPI_DEV), WHAL_SUCCESS); /* If RX wasn't drained, stale 0xDE/0xAD/0xBE/0xEF leaks here */ WHAL_ASSERT_MEM_EQ(rx, expected, sizeof(expected)); @@ -81,7 +81,7 @@ static void Test_Spi_Api(void) WHAL_ASSERT_EQ(whal_Spi_StartCom(NULL, &cfg), WHAL_EINVAL); WHAL_ASSERT_EQ(whal_Spi_EndCom(NULL), WHAL_EINVAL); WHAL_ASSERT_EQ(whal_Spi_SendRecv(NULL, buf, 4, buf, 4), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Spi_StartCom(&g_whalSpi, NULL), WHAL_EINVAL); + WHAL_ASSERT_EQ(whal_Spi_StartCom(BOARD_SPI_DEV, NULL), WHAL_EINVAL); } void whal_Test_Spi_Loopback(void) diff --git a/tests/uart/test_uart.c b/tests/uart/test_uart.c index 2cd2eb7..990f9aa 100644 --- a/tests/uart/test_uart.c +++ b/tests/uart/test_uart.c @@ -12,8 +12,8 @@ static void Test_Uart_Api(void) WHAL_ASSERT_EQ(whal_Uart_Recv(NULL, buf, sizeof(buf)), WHAL_EINVAL); WHAL_ASSERT_EQ(whal_Uart_SendAsync(NULL, buf, sizeof(buf)), WHAL_EINVAL); WHAL_ASSERT_EQ(whal_Uart_RecvAsync(NULL, buf, sizeof(buf)), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Uart_Send(&g_whalUart, NULL, 8), WHAL_EINVAL); - WHAL_ASSERT_EQ(whal_Uart_Recv(&g_whalUart, NULL, 8), WHAL_EINVAL); + WHAL_ASSERT_EQ(whal_Uart_Send(BOARD_UART_DEV, NULL, 8), WHAL_EINVAL); + WHAL_ASSERT_EQ(whal_Uart_Recv(BOARD_UART_DEV, NULL, 8), WHAL_EINVAL); } void whal_Test_Uart(void) diff --git a/tests/watchdog/test_watchdog.c b/tests/watchdog/test_watchdog.c index f3f4b08..4e02108 100644 --- a/tests/watchdog/test_watchdog.c +++ b/tests/watchdog/test_watchdog.c @@ -38,7 +38,7 @@ static void Test_Watchdog(void) { wdg_test_state_t state; - WHAL_ASSERT_EQ(whal_Flash_Read(&g_whalFlash, BOARD_FLASH_TEST_ADDR, + WHAL_ASSERT_EQ(whal_Flash_Read(BOARD_FLASH_DEV, BOARD_FLASH_TEST_ADDR, &state, sizeof(state)), WHAL_SUCCESS); if (state.magic != WDG_TEST_MAGIC) { @@ -50,35 +50,35 @@ static void Test_Watchdog(void) state.pad[0] = 0; state.pad[1] = 0; - WHAL_ASSERT_EQ(whal_Flash_Unlock(&g_whalFlash, BOARD_FLASH_TEST_ADDR, + WHAL_ASSERT_EQ(whal_Flash_Unlock(BOARD_FLASH_DEV, BOARD_FLASH_TEST_ADDR, BOARD_FLASH_SECTOR_SZ), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Flash_Erase(&g_whalFlash, BOARD_FLASH_TEST_ADDR, + WHAL_ASSERT_EQ(whal_Flash_Erase(BOARD_FLASH_DEV, BOARD_FLASH_TEST_ADDR, BOARD_FLASH_SECTOR_SZ), WHAL_SUCCESS); do { - err = whal_Flash_Write(&g_whalFlash, BOARD_FLASH_TEST_ADDR, + err = whal_Flash_Write(BOARD_FLASH_DEV, BOARD_FLASH_TEST_ADDR, &state, sizeof(state)); } while (err == WHAL_ENOTREADY); WHAL_ASSERT_EQ(err, WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Watchdog_Init(&g_whalWatchdog), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Watchdog_Init(BOARD_WATCHDOG_DEV), WHAL_SUCCESS); /* Verify refresh keeps us alive */ for (int i = 0; i < 1000; i++) { Board_WaitMs(1); - WHAL_ASSERT_EQ(whal_Watchdog_Refresh(&g_whalWatchdog), + WHAL_ASSERT_EQ(whal_Watchdog_Refresh(BOARD_WATCHDOG_DEV), WHAL_SUCCESS); } /* Mark that refresh loop completed */ state.refreshOk = WDG_TEST_REFRESH_OK; - WHAL_ASSERT_EQ(whal_Flash_Erase(&g_whalFlash, BOARD_FLASH_TEST_ADDR, + WHAL_ASSERT_EQ(whal_Flash_Erase(BOARD_FLASH_DEV, BOARD_FLASH_TEST_ADDR, BOARD_FLASH_SECTOR_SZ), WHAL_SUCCESS); do { - err = whal_Flash_Write(&g_whalFlash, BOARD_FLASH_TEST_ADDR, + err = whal_Flash_Write(BOARD_FLASH_DEV, BOARD_FLASH_TEST_ADDR, &state, sizeof(state)); } while (err == WHAL_ENOTREADY); WHAL_ASSERT_EQ(err, WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Flash_Lock(&g_whalFlash, BOARD_FLASH_TEST_ADDR, + WHAL_ASSERT_EQ(whal_Flash_Lock(BOARD_FLASH_DEV, BOARD_FLASH_TEST_ADDR, BOARD_FLASH_SECTOR_SZ), WHAL_SUCCESS); /* Stop refreshing — watchdog should reset us */ @@ -87,11 +87,11 @@ static void Test_Watchdog(void) /* Phase 1: watchdog fired — clean up first, then verify */ uint32_t refreshOk = state.refreshOk; - WHAL_ASSERT_EQ(whal_Flash_Unlock(&g_whalFlash, BOARD_FLASH_TEST_ADDR, + WHAL_ASSERT_EQ(whal_Flash_Unlock(BOARD_FLASH_DEV, BOARD_FLASH_TEST_ADDR, BOARD_FLASH_SECTOR_SZ), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Flash_Erase(&g_whalFlash, BOARD_FLASH_TEST_ADDR, + WHAL_ASSERT_EQ(whal_Flash_Erase(BOARD_FLASH_DEV, BOARD_FLASH_TEST_ADDR, BOARD_FLASH_SECTOR_SZ), WHAL_SUCCESS); - WHAL_ASSERT_EQ(whal_Flash_Lock(&g_whalFlash, BOARD_FLASH_TEST_ADDR, + WHAL_ASSERT_EQ(whal_Flash_Lock(BOARD_FLASH_DEV, BOARD_FLASH_TEST_ADDR, BOARD_FLASH_SECTOR_SZ), WHAL_SUCCESS); WHAL_ASSERT_EQ(refreshOk, WDG_TEST_REFRESH_OK); } diff --git a/wolfHAL/clock/pic32cz_clock.h b/wolfHAL/clock/pic32cz_clock.h index 8141629..6ce1dc6 100644 --- a/wolfHAL/clock/pic32cz_clock.h +++ b/wolfHAL/clock/pic32cz_clock.h @@ -3,8 +3,10 @@ #include #include -#include #include +#include +#include +#include /* * @file pic32cz_clock.h @@ -21,6 +23,64 @@ * -> MCLK -> CPU/bus clocks */ +/* + * PIC32CZ Clock System Register Map. + * OSCCTRL @ 0x00000, GCLK @ 0x10000, MCLK @ 0x12000. + */ + +#define WHAL_PIC32CZ_CLOCK_OSCCTRL 0x00000 + +#define WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_REG(pllInst) (0x40 + ((pllInst) * 20)) +#define WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_ENABLE_Pos 1 +#define WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_ENABLE_Msk (1UL << WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_ENABLE_Pos) +#define WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_REFSEL_Pos 8 +#define WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_REFSEL_Msk (WHAL_BITMASK(3) << WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_REFSEL_Pos) +#define WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_BWSEL_Pos 11 +#define WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_BWSEL_Msk (WHAL_BITMASK(3) << WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_BWSEL_Pos) + +#define WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxFBDIV_REG(pllInst) (0x44 + ((pllInst) * 20)) +#define WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxFBDIV_Pos 0 +#define WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxFBDIV_Msk (WHAL_BITMASK(10) << WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxFBDIV_Pos) + +#define WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxREFDIV_REG(pllInst) (0x48 + ((pllInst) * 20)) +#define WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxREFDIV_Pos 0 +#define WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxREFDIV_Msk (WHAL_BITMASK(6) << WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxREFDIV_Pos) + +#define WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxPOSTDIVA_REG(pllInst) (0x4C + ((pllInst) * 20)) + +#define WHAL_PIC32CZ_CLOCK_OSCCTRL_STATUS_REG (WHAL_PIC32CZ_CLOCK_OSCCTRL + 0x10) +#define WHAL_PIC32CZ_CLOCK_OSCCTRL_STATUS_PLLxLOCK_Pos(pllInst) (24 + (pllInst)) +#define WHAL_PIC32CZ_CLOCK_OSCCTRL_STATUS_PLLxLOCK_Msk(pllInst) (1UL << WHAL_PIC32CZ_CLOCK_OSCCTRL_STATUS_PLLxLOCK_Pos(pllInst)) + +#define WHAL_PIC32CZ_CLOCK_GCLK 0x10000 + +#define WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_REG(gclkInst) ((WHAL_PIC32CZ_CLOCK_GCLK + 0x20 + ((gclkInst) * 0x4))) +#define WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_SRC_Pos 0 +#define WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_SRC_Msk (WHAL_BITMASK(5) << WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_SRC_Pos) +#define WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_GENEN_Pos 8 +#define WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_GENEN_Msk (1UL << WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_GENEN_Pos) +#define WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_DIV_Pos 16 +#define WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_DIV_Msk (WHAL_BITMASK(16) << WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_DIV_Pos) + +#define WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_REG(periphChannel) (WHAL_PIC32CZ_CLOCK_GCLK + 0x80 + ((periphChannel) * 0x4)) +#define WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_GEN_Pos 0 +#define WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_GEN_Msk (WHAL_BITMASK(4) << WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_GEN_Pos) +#define WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_CHEN_Pos 6 +#define WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_CHEN_Msk (1UL << WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_CHEN_Pos) + +#define WHAL_PIC32CZ_CLOCK_GCLK_SYNCBUSY_REG (WHAL_PIC32CZ_CLOCK_GCLK + 0x04) +#define WHAL_PIC32CZ_CLOCK_GCLK_SYNCBUSY_GENCTRLx_Pos(gclkInst) (2 + (gclkInst)) +#define WHAL_PIC32CZ_CLOCK_GCLK_SYNCBUSY_GENCTRLx_Msk(gclkInst) (1UL << WHAL_PIC32CZ_CLOCK_GCLK_SYNCBUSY_GENCTRLx_Pos(gclkInst)) + +#define WHAL_PIC32CZ_CLOCK_MCLK 0x12000 +#define WHAL_PIC32CZ_CLOCK_MCLK_INTFLAG_REG (WHAL_PIC32CZ_CLOCK_MCLK + 0x08) +#define WHAL_PIC32CZ_CLOCK_MCLK_INTFLAG_CKRDY_Pos 0 +#define WHAL_PIC32CZ_CLOCK_MCLK_INTFLAG_CKRDY_Msk (1UL << WHAL_PIC32CZ_CLOCK_MCLK_INTFLAG_CKRDY_Pos) +#define WHAL_PIC32CZ_CLOCK_MCLK_DIV1_REG (WHAL_PIC32CZ_CLOCK_MCLK + 0x10) +#define WHAL_PIC32CZ_CLOCK_MCLK_DIV1_Pos 0 +#define WHAL_PIC32CZ_CLOCK_MCLK_DIV1_Msk (WHAL_BITMASK(8) << WHAL_PIC32CZ_CLOCK_MCLK_DIV1_Pos) +#define WHAL_PIC32CZ_CLOCK_MCLK_CLKxMSK_REG(enableInst) (WHAL_PIC32CZ_CLOCK_MCLK + 0x3C + ((enableInst) * 0x4)) + /* * @brief PLL instance. */ @@ -127,32 +187,176 @@ typedef struct { } whal_Pic32cz_Clock_PeriphClk; /* - * @brief Configure and enable a PLL. Blocks until lock is detected. + * @brief Configure and enable a PLL, then wait for PLLxLOCK. + * + * Programs PLLxFBDIV, PLLxREFDIV, the requested output post-dividers / + * output-enable bits in PLLxPOSTDIVA, then enables the PLL by setting + * ENABLE/REFSEL/BWSEL in PLLxCTRL. Polls OSCCTRL.STATUS until the + * matching PLLxLOCK bit asserts. + * + * @param clkDev Clock device instance. + * @param cfg PLL configuration. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Pic32cz_Clock_EnablePll(whal_Clock *clkDev, - const whal_Pic32cz_Clock_PllCfg *cfg); +static inline whal_Error whal_Pic32cz_Clock_EnablePll( + const whal_Clock *clkDev, const whal_Pic32cz_Clock_PllCfg *cfg) +{ + size_t status; + uint8_t i; + size_t pllCtrlReg, pllFbdivReg, pllRefdivReg, pllPostdivaReg; + + pllCtrlReg = WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_REG(cfg->pllInst); + pllFbdivReg = WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxFBDIV_REG(cfg->pllInst); + pllRefdivReg = WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxREFDIV_REG(cfg->pllInst); + pllPostdivaReg = WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxPOSTDIVA_REG(cfg->pllInst); + + whal_Reg_Update(clkDev->base, pllFbdivReg, + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxFBDIV_Msk, + whal_SetBits(WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxFBDIV_Msk, + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxFBDIV_Pos, + cfg->fbDiv)); + whal_Reg_Update(clkDev->base, pllRefdivReg, + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxREFDIV_Msk, + whal_SetBits(WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxREFDIV_Msk, + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxREFDIV_Pos, + cfg->refDiv)); + for (i = 0; i < cfg->outCfgCount; i++) { + const whal_Pic32cz_Clock_PllOutCfg *out = &cfg->outCfg[i]; + whal_Reg_Update(clkDev->base, pllPostdivaReg, + out->outEnMask | out->postDivMask, + whal_SetBits(out->postDivMask, out->postDivPos, out->postDiv) | + whal_SetBits(out->outEnMask, out->outEnPos, 1)); + } + + whal_Reg_Update(clkDev->base, pllCtrlReg, + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_ENABLE_Msk | + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_REFSEL_Msk | + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_BWSEL_Msk, + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_ENABLE_Msk | + whal_SetBits(WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_REFSEL_Msk, + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_REFSEL_Pos, cfg->refSel) | + whal_SetBits(WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_BWSEL_Msk, + WHAL_PIC32CZ_CLOCK_OSCCTRL_PLLxCTRL_BWSEL_Pos, cfg->bwSel)); + + do { + whal_Reg_Get(clkDev->base, WHAL_PIC32CZ_CLOCK_OSCCTRL_STATUS_REG, + WHAL_PIC32CZ_CLOCK_OSCCTRL_STATUS_PLLxLOCK_Msk(cfg->pllInst), + WHAL_PIC32CZ_CLOCK_OSCCTRL_STATUS_PLLxLOCK_Pos(cfg->pllInst), + &status); + } while (!status); + return WHAL_SUCCESS; +} /* - * @brief Configure and enable a GCLK generator. Blocks until sync clears. + * @brief Enable a GCLK generator with the supplied source and divider. + * + * Programs GCLK_GENCTRLx (SRC/GENEN/DIV) and waits for the GCLK_SYNCBUSY + * bit for this generator to clear. + * + * @param clkDev Clock device instance. + * @param cfg Generator configuration. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Pic32cz_Clock_EnableGclkGen(whal_Clock *clkDev, - const whal_Pic32cz_Clock_GenCfg *cfg); +static inline whal_Error whal_Pic32cz_Clock_EnableGclkGen( + const whal_Clock *clkDev, const whal_Pic32cz_Clock_GenCfg *cfg) +{ + size_t status; + + whal_Reg_Update(clkDev->base, WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_REG(cfg->gen), + WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_SRC_Msk | + WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_GENEN_Msk | + WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_DIV_Msk, + whal_SetBits(WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_SRC_Msk, + WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_SRC_Pos, cfg->genSrc) | + WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_GENEN_Msk | + whal_SetBits(WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_DIV_Msk, + WHAL_PIC32CZ_CLOCK_GCLK_GENCTRLx_DIV_Pos, cfg->genDiv)); + do { + whal_Reg_Get(clkDev->base, WHAL_PIC32CZ_CLOCK_GCLK_SYNCBUSY_REG, + WHAL_PIC32CZ_CLOCK_GCLK_SYNCBUSY_GENCTRLx_Msk(cfg->gen), + WHAL_PIC32CZ_CLOCK_GCLK_SYNCBUSY_GENCTRLx_Pos(cfg->gen), + &status); + } while (status); + return WHAL_SUCCESS; +} /* - * @brief Set the MCLK CPU divider. Blocks until ready. + * @brief Program the main clock CPU divider (MCLK DIV1). + * + * Writes MCLK.DIV1 and polls MCLK.INTFLAG.CKRDY for the change to settle. + * + * @param clkDev Clock device instance. + * @param div Divider value to write into MCLK.DIV1. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Pic32cz_Clock_SetMclkDiv(whal_Clock *clkDev, uint8_t div); +static inline whal_Error whal_Pic32cz_Clock_SetMclkDiv( + const whal_Clock *clkDev, uint8_t div) +{ + size_t status; + + whal_Reg_Update(clkDev->base, WHAL_PIC32CZ_CLOCK_MCLK_DIV1_REG, + WHAL_PIC32CZ_CLOCK_MCLK_DIV1_Msk, + whal_SetBits(WHAL_PIC32CZ_CLOCK_MCLK_DIV1_Msk, + WHAL_PIC32CZ_CLOCK_MCLK_DIV1_Pos, div)); + do { + whal_Reg_Get(clkDev->base, WHAL_PIC32CZ_CLOCK_MCLK_INTFLAG_REG, + WHAL_PIC32CZ_CLOCK_MCLK_INTFLAG_CKRDY_Msk, + WHAL_PIC32CZ_CLOCK_MCLK_INTFLAG_CKRDY_Pos, &status); + } while (!status); + return WHAL_SUCCESS; +} /* - * @brief Enable a peripheral clock — connects GCLK channel to a generator - * and enables the peripheral's MCLK bus gate. + * @brief Route a GCLK generator to a peripheral channel and ungate the MCLK bit. + * + * Configures GCLK_PCHCTRLx with the requested generator + channel-enable + * bit, then sets the matching MCLK_CLKxMSK enable bit. + * + * @param clkDev Clock device instance. + * @param clk Peripheral clock descriptor (GCLK channel + MCLK enable bit). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Pic32cz_Clock_EnablePeriphClk(whal_Clock *clkDev, - const whal_Pic32cz_Clock_PeriphClk *clk); +static inline whal_Error whal_Pic32cz_Clock_EnablePeriphClk( + const whal_Clock *clkDev, const whal_Pic32cz_Clock_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, + WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_REG(clk->gclkPeriphChannel), + WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_GEN_Msk | + WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_CHEN_Msk, + whal_SetBits(WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_GEN_Msk, + WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_GEN_Pos, + clk->gclkPeriphSrc) | + WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_CHEN_Msk); + whal_Reg_Update(clkDev->base, + WHAL_PIC32CZ_CLOCK_MCLK_CLKxMSK_REG(clk->mclkEnableInst), + clk->mclkEnableMask, + whal_SetBits(clk->mclkEnableMask, clk->mclkEnablePos, 1)); + return WHAL_SUCCESS; +} + /* - * @brief Disable a peripheral clock. + * @brief Gate off a peripheral's MCLK bit and disable the GCLK channel. + * + * @param clkDev Clock device instance. + * @param clk Peripheral clock descriptor (GCLK channel + MCLK enable bit). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Pic32cz_Clock_DisablePeriphClk(whal_Clock *clkDev, - const whal_Pic32cz_Clock_PeriphClk *clk); +static inline whal_Error whal_Pic32cz_Clock_DisablePeriphClk( + const whal_Clock *clkDev, const whal_Pic32cz_Clock_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, + WHAL_PIC32CZ_CLOCK_MCLK_CLKxMSK_REG(clk->mclkEnableInst), + clk->mclkEnableMask, + whal_SetBits(clk->mclkEnableMask, clk->mclkEnablePos, 0)); + whal_Reg_Update(clkDev->base, + WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_REG(clk->gclkPeriphChannel), + WHAL_PIC32CZ_CLOCK_GCLK_PCHCTRLx_CHEN_Msk, 0); + return WHAL_SUCCESS; +} #endif /* WHAL_PIC32CZ_CLOCK_H */ diff --git a/wolfHAL/clock/stm32c0_rcc.h b/wolfHAL/clock/stm32c0_rcc.h index 79b6a5a..49e72fc 100644 --- a/wolfHAL/clock/stm32c0_rcc.h +++ b/wolfHAL/clock/stm32c0_rcc.h @@ -2,8 +2,11 @@ #define WHAL_STM32C0_RCC_H #include -#include #include +#include +#include +#include +#include /* * @file stm32c0_rcc.h @@ -15,6 +18,22 @@ * HSISYS. */ +/* Clock Control Register */ +#define WHAL_STM32C0_RCC_CR_REG 0x000 +#define WHAL_STM32C0_RCC_CR_HSION_Pos 8 +#define WHAL_STM32C0_RCC_CR_HSION_Msk (1UL << WHAL_STM32C0_RCC_CR_HSION_Pos) +#define WHAL_STM32C0_RCC_CR_HSIRDY_Pos 10 +#define WHAL_STM32C0_RCC_CR_HSIRDY_Msk (1UL << WHAL_STM32C0_RCC_CR_HSIRDY_Pos) +#define WHAL_STM32C0_RCC_CR_HSIDIV_Pos 11 +#define WHAL_STM32C0_RCC_CR_HSIDIV_Msk (WHAL_BITMASK(3) << WHAL_STM32C0_RCC_CR_HSIDIV_Pos) + +/* Clock Configuration Register */ +#define WHAL_STM32C0_RCC_CFGR_REG 0x008 +#define WHAL_STM32C0_RCC_CFGR_SW_Pos 0 +#define WHAL_STM32C0_RCC_CFGR_SW_Msk (WHAL_BITMASK(3) << WHAL_STM32C0_RCC_CFGR_SW_Pos) +#define WHAL_STM32C0_RCC_CFGR_SWS_Pos 3 +#define WHAL_STM32C0_RCC_CFGR_SWS_Msk (WHAL_BITMASK(3) << WHAL_STM32C0_RCC_CFGR_SWS_Pos) + /* * @brief HSI divider selection (RCC_CR.HSIDIV). */ @@ -49,27 +68,93 @@ typedef struct { } whal_Stm32c0_Rcc_PeriphClk; /* - * @brief Enable HSI, set the HSIDIV divider, and wait for ready. + * @brief Enable HSI16/HSI48, wait for it to be ready, then set HSIDIV. + * + * Sets RCC_CR.HSION, polls RCC_CR.HSIRDY, then writes HSIDIV. Leaves HSISYS + * = 48 MHz / 2^hsidiv. + * + * @param clkDev RCC device instance. + * @param hsidiv HSI divider selection. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32c0_Rcc_EnableHsi(whal_Clock *clkDev, - whal_Stm32c0_Rcc_HsiDiv hsidiv); +static inline whal_Error whal_Stm32c0_Rcc_EnableHsi( + const whal_Clock *clkDev, whal_Stm32c0_Rcc_HsiDiv hsidiv) +{ + size_t rdy; + + whal_Reg_Update(clkDev->base, WHAL_STM32C0_RCC_CR_REG, + WHAL_STM32C0_RCC_CR_HSION_Msk, + WHAL_STM32C0_RCC_CR_HSION_Msk); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32C0_RCC_CR_REG, + WHAL_STM32C0_RCC_CR_HSIRDY_Msk, + WHAL_STM32C0_RCC_CR_HSIRDY_Pos, &rdy); + } while (!rdy); + whal_Reg_Update(clkDev->base, WHAL_STM32C0_RCC_CR_REG, + WHAL_STM32C0_RCC_CR_HSIDIV_Msk, + whal_SetBits(WHAL_STM32C0_RCC_CR_HSIDIV_Msk, + WHAL_STM32C0_RCC_CR_HSIDIV_Pos, hsidiv)); + return WHAL_SUCCESS; +} /* - * @brief Switch SYSCLK to the given source. Blocks until RCC_CFGR.SWS - * reflects the new source. + * @brief Switch SYSCLK to the requested source and wait for the switch. + * + * Writes RCC_CFGR.SW and polls RCC_CFGR.SWS until it reports the new source. + * + * @param clkDev RCC device instance. + * @param src System clock source. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32c0_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32c0_Rcc_SysClockSrc src); +static inline whal_Error whal_Stm32c0_Rcc_SetSysClock( + const whal_Clock *clkDev, whal_Stm32c0_Rcc_SysClockSrc src) +{ + size_t sws; + + whal_Reg_Update(clkDev->base, WHAL_STM32C0_RCC_CFGR_REG, + WHAL_STM32C0_RCC_CFGR_SW_Msk, + whal_SetBits(WHAL_STM32C0_RCC_CFGR_SW_Msk, + WHAL_STM32C0_RCC_CFGR_SW_Pos, src)); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32C0_RCC_CFGR_REG, + WHAL_STM32C0_RCC_CFGR_SWS_Msk, + WHAL_STM32C0_RCC_CFGR_SWS_Pos, &sws); + } while (sws != (size_t)src); + return WHAL_SUCCESS; +} /* - * @brief Enable a peripheral clock. + * @brief Set the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32c0_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32c0_Rcc_PeriphClk *clk); +static inline whal_Error whal_Stm32c0_Rcc_EnablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32c0_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); + return WHAL_SUCCESS; +} + /* - * @brief Disable a peripheral clock. + * @brief Clear the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32c0_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32c0_Rcc_PeriphClk *clk); +static inline whal_Error whal_Stm32c0_Rcc_DisablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32c0_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); + return WHAL_SUCCESS; +} #endif /* WHAL_STM32C0_RCC_H */ diff --git a/wolfHAL/clock/stm32f0_rcc.h b/wolfHAL/clock/stm32f0_rcc.h index 1543519..21bd8f0 100644 --- a/wolfHAL/clock/stm32f0_rcc.h +++ b/wolfHAL/clock/stm32f0_rcc.h @@ -2,8 +2,11 @@ #define WHAL_STM32F0_RCC_H #include -#include #include +#include +#include +#include +#include /* * @file stm32f0_rcc.h @@ -18,6 +21,25 @@ * PLL = source/PREDIV * PLLMUL */ +#define WHAL_STM32F0_RCC_CR_REG 0x00 +#define WHAL_STM32F0_RCC_CR_PLLON_Msk (1UL << 24) +#define WHAL_STM32F0_RCC_CR_PLLRDY_Msk (1UL << 25) +#define WHAL_STM32F0_RCC_CR_PLLRDY_Pos 25 + +#define WHAL_STM32F0_RCC_CFGR_REG 0x04 +#define WHAL_STM32F0_RCC_CFGR_SW_Pos 0 +#define WHAL_STM32F0_RCC_CFGR_SW_Msk (WHAL_BITMASK(2) << WHAL_STM32F0_RCC_CFGR_SW_Pos) +#define WHAL_STM32F0_RCC_CFGR_SWS_Pos 2 +#define WHAL_STM32F0_RCC_CFGR_SWS_Msk (WHAL_BITMASK(2) << WHAL_STM32F0_RCC_CFGR_SWS_Pos) +#define WHAL_STM32F0_RCC_CFGR_PLLSRC_Pos 16 +#define WHAL_STM32F0_RCC_CFGR_PLLSRC_Msk (1UL << WHAL_STM32F0_RCC_CFGR_PLLSRC_Pos) +#define WHAL_STM32F0_RCC_CFGR_PLLMUL_Pos 18 +#define WHAL_STM32F0_RCC_CFGR_PLLMUL_Msk (WHAL_BITMASK(4) << WHAL_STM32F0_RCC_CFGR_PLLMUL_Pos) + +#define WHAL_STM32F0_RCC_CFGR2_REG 0x2C +#define WHAL_STM32F0_RCC_CFGR2_PREDIV_Pos 0 +#define WHAL_STM32F0_RCC_CFGR2_PREDIV_Msk (WHAL_BITMASK(4) << WHAL_STM32F0_RCC_CFGR2_PREDIV_Pos) + /* * @brief System clock source selection (RCC_CFGR.SW). */ @@ -80,43 +102,162 @@ typedef struct { .rdyReg = 0x034, .rdyMsk = (1UL << 17), .rdyPos = 17 /* - * @brief Enable an oscillator (HSI/HSE/HSI48). Blocks until ready. + * @brief Turn on an oscillator (HSI/HSE/HSI48) and wait for its ready bit. + * + * @param clkDev RCC device instance. + * @param cfg Oscillator on/ready bit descriptor (e.g. WHAL_STM32F0_RCC_HSI_CFG). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f0_Rcc_EnableOsc(whal_Clock *clkDev, - const whal_Stm32f0_Rcc_OscCfg *cfg); +static inline whal_Error whal_Stm32f0_Rcc_EnableOsc( + const whal_Clock *clkDev, const whal_Stm32f0_Rcc_OscCfg *cfg) +{ + size_t rdy; + + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); + do { + whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + /* - * @brief Disable an oscillator. + * @brief Turn off an oscillator (HSI/HSE/HSI48). + * + * @param clkDev RCC device instance. + * @param cfg Oscillator on/ready bit descriptor. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f0_Rcc_DisableOsc(whal_Clock *clkDev, - const whal_Stm32f0_Rcc_OscCfg *cfg); +static inline whal_Error whal_Stm32f0_Rcc_DisableOsc( + const whal_Clock *clkDev, const whal_Stm32f0_Rcc_OscCfg *cfg) +{ + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); + return WHAL_SUCCESS; +} /* - * @brief Configure the PLL (PREDIV, PLLMUL, source) and enable it. - * Caller must have the PLL source oscillator already enabled. - * Blocks until PLL is ready. + * @brief Configure and enable the PLL, waiting for lock. + * + * Turns the PLL off, programs PREDIV (CFGR2), PLLMUL and PLLSRC (CFGR), then + * sets PLLON and polls PLLRDY. Caller must have enabled the reference clock + * first. + * + * @param clkDev RCC device instance. + * @param cfg PLL configuration. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f0_Rcc_EnablePll(whal_Clock *clkDev, - const whal_Stm32f0_Rcc_PllCfg *cfg); +static inline whal_Error whal_Stm32f0_Rcc_EnablePll( + const whal_Clock *clkDev, const whal_Stm32f0_Rcc_PllCfg *cfg) +{ + size_t rdy; + uint32_t pllsrc; + + /* Disable PLL before reconfiguring. */ + whal_Reg_Update(clkDev->base, WHAL_STM32F0_RCC_CR_REG, + WHAL_STM32F0_RCC_CR_PLLON_Msk, 0); + + whal_Reg_Update(clkDev->base, WHAL_STM32F0_RCC_CFGR2_REG, + WHAL_STM32F0_RCC_CFGR2_PREDIV_Msk, + whal_SetBits(WHAL_STM32F0_RCC_CFGR2_PREDIV_Msk, + WHAL_STM32F0_RCC_CFGR2_PREDIV_Pos, + cfg->prediv - 1)); + whal_Reg_Update(clkDev->base, WHAL_STM32F0_RCC_CFGR_REG, + WHAL_STM32F0_RCC_CFGR_PLLMUL_Msk, + whal_SetBits(WHAL_STM32F0_RCC_CFGR_PLLMUL_Msk, + WHAL_STM32F0_RCC_CFGR_PLLMUL_Pos, + cfg->pllmul - 2)); + + pllsrc = (cfg->clkSrc == WHAL_STM32F0_RCC_PLLSRC_HSE_PREDIV || + cfg->clkSrc == WHAL_STM32F0_RCC_PLLSRC_HSI48_PREDIV) ? 1 : 0; + whal_Reg_Update(clkDev->base, WHAL_STM32F0_RCC_CFGR_REG, + WHAL_STM32F0_RCC_CFGR_PLLSRC_Msk, + whal_SetBits(WHAL_STM32F0_RCC_CFGR_PLLSRC_Msk, + WHAL_STM32F0_RCC_CFGR_PLLSRC_Pos, + pllsrc)); + + whal_Reg_Update(clkDev->base, WHAL_STM32F0_RCC_CR_REG, + WHAL_STM32F0_RCC_CR_PLLON_Msk, + WHAL_STM32F0_RCC_CR_PLLON_Msk); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32F0_RCC_CR_REG, + WHAL_STM32F0_RCC_CR_PLLRDY_Msk, + WHAL_STM32F0_RCC_CR_PLLRDY_Pos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + /* - * @brief Disable the PLL. + * @brief Turn the PLL off (clears RCC_CR.PLLON). + * + * @param clkDev RCC device instance. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f0_Rcc_DisablePll(whal_Clock *clkDev); +static inline whal_Error whal_Stm32f0_Rcc_DisablePll(const whal_Clock *clkDev) +{ + whal_Reg_Update(clkDev->base, WHAL_STM32F0_RCC_CR_REG, + WHAL_STM32F0_RCC_CR_PLLON_Msk, 0); + return WHAL_SUCCESS; +} /* - * @brief Switch SYSCLK to the given source. Blocks until SWS confirms. + * @brief Switch SYSCLK to the requested source and wait for the switch. + * + * @param clkDev RCC device instance. + * @param src System clock source. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f0_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32f0_Rcc_SysClockSrc src); +static inline whal_Error whal_Stm32f0_Rcc_SetSysClock( + const whal_Clock *clkDev, whal_Stm32f0_Rcc_SysClockSrc src) +{ + size_t sws; + + whal_Reg_Update(clkDev->base, WHAL_STM32F0_RCC_CFGR_REG, + WHAL_STM32F0_RCC_CFGR_SW_Msk, + whal_SetBits(WHAL_STM32F0_RCC_CFGR_SW_Msk, + WHAL_STM32F0_RCC_CFGR_SW_Pos, src)); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32F0_RCC_CFGR_REG, + WHAL_STM32F0_RCC_CFGR_SWS_Msk, + WHAL_STM32F0_RCC_CFGR_SWS_Pos, &sws); + } while (sws != (size_t)src); + return WHAL_SUCCESS; +} /* - * @brief Enable a peripheral clock. + * @brief Set the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f0_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32f0_Rcc_PeriphClk *clk); +static inline whal_Error whal_Stm32f0_Rcc_EnablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32f0_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); + return WHAL_SUCCESS; +} + /* - * @brief Disable a peripheral clock. + * @brief Clear the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f0_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32f0_Rcc_PeriphClk *clk); +static inline whal_Error whal_Stm32f0_Rcc_DisablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32f0_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); + return WHAL_SUCCESS; +} #endif /* WHAL_STM32F0_RCC_H */ diff --git a/wolfHAL/clock/stm32f3_rcc.h b/wolfHAL/clock/stm32f3_rcc.h index 545a1bf..911e3db 100644 --- a/wolfHAL/clock/stm32f3_rcc.h +++ b/wolfHAL/clock/stm32f3_rcc.h @@ -2,8 +2,11 @@ #define WHAL_STM32F3_RCC_H #include -#include #include +#include +#include +#include +#include /* * @file stm32f3_rcc.h @@ -17,6 +20,29 @@ * PLL = HSI/2 or HSE/PREDIV * PLLMUL (max 72 MHz) */ +#define WHAL_STM32F3_RCC_CR_REG 0x00 +#define WHAL_STM32F3_RCC_CR_PLLON_Msk (1UL << 24) +#define WHAL_STM32F3_RCC_CR_PLLRDY_Msk (1UL << 25) +#define WHAL_STM32F3_RCC_CR_PLLRDY_Pos 25 + +#define WHAL_STM32F3_RCC_CFGR_REG 0x04 +#define WHAL_STM32F3_RCC_CFGR_SW_Pos 0 +#define WHAL_STM32F3_RCC_CFGR_SW_Msk (WHAL_BITMASK(2) << WHAL_STM32F3_RCC_CFGR_SW_Pos) +#define WHAL_STM32F3_RCC_CFGR_SWS_Pos 2 +#define WHAL_STM32F3_RCC_CFGR_SWS_Msk (WHAL_BITMASK(2) << WHAL_STM32F3_RCC_CFGR_SWS_Pos) +#define WHAL_STM32F3_RCC_CFGR_PLLSRC_Pos 16 +#define WHAL_STM32F3_RCC_CFGR_PLLSRC_Msk (1UL << WHAL_STM32F3_RCC_CFGR_PLLSRC_Pos) +#define WHAL_STM32F3_RCC_CFGR_PLLMUL_Pos 18 +#define WHAL_STM32F3_RCC_CFGR_PLLMUL_Msk (WHAL_BITMASK(4) << WHAL_STM32F3_RCC_CFGR_PLLMUL_Pos) + +#define WHAL_STM32F3_RCC_CFGR2_REG 0x2C +#define WHAL_STM32F3_RCC_CFGR2_PREDIV_Pos 0 +#define WHAL_STM32F3_RCC_CFGR2_PREDIV_Msk (WHAL_BITMASK(4) << WHAL_STM32F3_RCC_CFGR2_PREDIV_Pos) + +#define WHAL_STM32F3_RCC_CFGR3_REG 0x30 +#define WHAL_STM32F3_RCC_CFGR3_I2C1SW_Pos 4 +#define WHAL_STM32F3_RCC_CFGR3_I2C1SW_Msk (1UL << WHAL_STM32F3_RCC_CFGR3_I2C1SW_Pos) + /* * @brief System clock source selection (RCC_CFGR.SW). */ @@ -81,48 +107,179 @@ typedef struct { .rdyReg = 0x000, .rdyMsk = (1UL << 17), .rdyPos = 17 /* - * @brief Enable an oscillator (HSI/HSE). Blocks until ready. + * @brief Turn on an oscillator (HSI/HSE) and wait for its ready bit. + * + * @param clkDev RCC device instance. + * @param cfg Oscillator on/ready bit descriptor. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f3_Rcc_EnableOsc(whal_Clock *clkDev, - const whal_Stm32f3_Rcc_OscCfg *cfg); +static inline whal_Error whal_Stm32f3_Rcc_EnableOsc( + const whal_Clock *clkDev, const whal_Stm32f3_Rcc_OscCfg *cfg) +{ + size_t rdy; + + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); + do { + whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + /* - * @brief Disable an oscillator. + * @brief Turn off an oscillator (HSI/HSE). + * + * @param clkDev RCC device instance. + * @param cfg Oscillator on/ready bit descriptor. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f3_Rcc_DisableOsc(whal_Clock *clkDev, - const whal_Stm32f3_Rcc_OscCfg *cfg); +static inline whal_Error whal_Stm32f3_Rcc_DisableOsc( + const whal_Clock *clkDev, const whal_Stm32f3_Rcc_OscCfg *cfg) +{ + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); + return WHAL_SUCCESS; +} /* - * @brief Configure the PLL and enable it. Caller must have the PLL source - * oscillator already enabled. Blocks until PLL is ready. + * @brief Configure and enable the PLL, waiting for lock. + * + * Turns the PLL off, programs PREDIV (CFGR2), PLLMUL and PLLSRC (CFGR), then + * sets PLLON and polls PLLRDY. Caller must have enabled the reference clock. + * + * @param clkDev RCC device instance. + * @param cfg PLL configuration. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f3_Rcc_EnablePll(whal_Clock *clkDev, - const whal_Stm32f3_Rcc_PllCfg *cfg); +static inline whal_Error whal_Stm32f3_Rcc_EnablePll( + const whal_Clock *clkDev, const whal_Stm32f3_Rcc_PllCfg *cfg) +{ + size_t rdy; + uint32_t pllsrc; + + /* Disable PLL before reconfiguring. */ + whal_Reg_Update(clkDev->base, WHAL_STM32F3_RCC_CR_REG, + WHAL_STM32F3_RCC_CR_PLLON_Msk, 0); + + whal_Reg_Update(clkDev->base, WHAL_STM32F3_RCC_CFGR2_REG, + WHAL_STM32F3_RCC_CFGR2_PREDIV_Msk, + whal_SetBits(WHAL_STM32F3_RCC_CFGR2_PREDIV_Msk, + WHAL_STM32F3_RCC_CFGR2_PREDIV_Pos, + cfg->prediv - 1)); + whal_Reg_Update(clkDev->base, WHAL_STM32F3_RCC_CFGR_REG, + WHAL_STM32F3_RCC_CFGR_PLLMUL_Msk, + whal_SetBits(WHAL_STM32F3_RCC_CFGR_PLLMUL_Msk, + WHAL_STM32F3_RCC_CFGR_PLLMUL_Pos, + cfg->pllmul - 2)); + + pllsrc = (cfg->clkSrc == WHAL_STM32F3_RCC_PLLSRC_HSE_PREDIV) ? 1 : 0; + whal_Reg_Update(clkDev->base, WHAL_STM32F3_RCC_CFGR_REG, + WHAL_STM32F3_RCC_CFGR_PLLSRC_Msk, + whal_SetBits(WHAL_STM32F3_RCC_CFGR_PLLSRC_Msk, + WHAL_STM32F3_RCC_CFGR_PLLSRC_Pos, + pllsrc)); + + whal_Reg_Update(clkDev->base, WHAL_STM32F3_RCC_CR_REG, + WHAL_STM32F3_RCC_CR_PLLON_Msk, + WHAL_STM32F3_RCC_CR_PLLON_Msk); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32F3_RCC_CR_REG, + WHAL_STM32F3_RCC_CR_PLLRDY_Msk, + WHAL_STM32F3_RCC_CR_PLLRDY_Pos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + /* - * @brief Disable the PLL. + * @brief Turn the PLL off (clears RCC_CR.PLLON). + * + * @param clkDev RCC device instance. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f3_Rcc_DisablePll(whal_Clock *clkDev); +static inline whal_Error whal_Stm32f3_Rcc_DisablePll(const whal_Clock *clkDev) +{ + whal_Reg_Update(clkDev->base, WHAL_STM32F3_RCC_CR_REG, + WHAL_STM32F3_RCC_CR_PLLON_Msk, 0); + return WHAL_SUCCESS; +} /* - * @brief Switch SYSCLK to the given source. Blocks until SWS confirms. + * @brief Switch SYSCLK to the requested source and wait for the switch. + * + * @param clkDev RCC device instance. + * @param src System clock source. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f3_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32f3_Rcc_SysClockSrc src); +static inline whal_Error whal_Stm32f3_Rcc_SetSysClock( + const whal_Clock *clkDev, whal_Stm32f3_Rcc_SysClockSrc src) +{ + size_t sws; + + whal_Reg_Update(clkDev->base, WHAL_STM32F3_RCC_CFGR_REG, + WHAL_STM32F3_RCC_CFGR_SW_Msk, + whal_SetBits(WHAL_STM32F3_RCC_CFGR_SW_Msk, + WHAL_STM32F3_RCC_CFGR_SW_Pos, src)); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32F3_RCC_CFGR_REG, + WHAL_STM32F3_RCC_CFGR_SWS_Msk, + WHAL_STM32F3_RCC_CFGR_SWS_Pos, &sws); + } while (sws != (size_t)src); + return WHAL_SUCCESS; +} /* - * @brief Select the I2C1 peripheral clock source (RCC_CFGR3.I2C1SW). + * @brief Select the kernel clock for the I2C1 peripheral. + * + * @param clkDev RCC device instance. + * @param src I2C1 kernel clock source. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f3_Rcc_SetI2c1ClkSrc(whal_Clock *clkDev, - whal_Stm32f3_Rcc_I2c1ClkSrc src); +static inline whal_Error whal_Stm32f3_Rcc_SetI2c1ClkSrc( + const whal_Clock *clkDev, whal_Stm32f3_Rcc_I2c1ClkSrc src) +{ + whal_Reg_Update(clkDev->base, WHAL_STM32F3_RCC_CFGR3_REG, + WHAL_STM32F3_RCC_CFGR3_I2C1SW_Msk, + whal_SetBits(WHAL_STM32F3_RCC_CFGR3_I2C1SW_Msk, + WHAL_STM32F3_RCC_CFGR3_I2C1SW_Pos, + src)); + return WHAL_SUCCESS; +} /* - * @brief Enable a peripheral clock. + * @brief Set the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f3_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32f3_Rcc_PeriphClk *clk); +static inline whal_Error whal_Stm32f3_Rcc_EnablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32f3_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); + return WHAL_SUCCESS; +} + /* - * @brief Disable a peripheral clock. + * @brief Clear the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f3_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32f3_Rcc_PeriphClk *clk); +static inline whal_Error whal_Stm32f3_Rcc_DisablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32f3_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); + return WHAL_SUCCESS; +} #endif /* WHAL_STM32F3_RCC_H */ diff --git a/wolfHAL/clock/stm32f4_rcc.h b/wolfHAL/clock/stm32f4_rcc.h index 39572c1..17a0425 100644 --- a/wolfHAL/clock/stm32f4_rcc.h +++ b/wolfHAL/clock/stm32f4_rcc.h @@ -2,8 +2,11 @@ #define WHAL_STM32F4_RCC_H #include -#include #include +#include +#include +#include +#include /* * @file stm32f4_rcc.h @@ -17,6 +20,37 @@ * f_pllq = f_vco / q (USB / SDIO) */ +#define WHAL_STM32F4_RCC_CR_REG 0x000 +#define WHAL_STM32F4_RCC_CR_PLLON_Msk (1UL << 24) +#define WHAL_STM32F4_RCC_CR_PLLRDY_Msk (1UL << 25) +#define WHAL_STM32F4_RCC_CR_PLLRDY_Pos 25 + +#define WHAL_STM32F4_RCC_PLLCFGR_REG 0x004 +#define WHAL_STM32F4_RCC_PLLCFGR_PLLM_Pos 0 +#define WHAL_STM32F4_RCC_PLLCFGR_PLLM_Msk (WHAL_BITMASK(6) << WHAL_STM32F4_RCC_PLLCFGR_PLLM_Pos) +#define WHAL_STM32F4_RCC_PLLCFGR_PLLN_Pos 6 +#define WHAL_STM32F4_RCC_PLLCFGR_PLLN_Msk (WHAL_BITMASK(9) << WHAL_STM32F4_RCC_PLLCFGR_PLLN_Pos) +#define WHAL_STM32F4_RCC_PLLCFGR_PLLP_Pos 16 +#define WHAL_STM32F4_RCC_PLLCFGR_PLLP_Msk (WHAL_BITMASK(2) << WHAL_STM32F4_RCC_PLLCFGR_PLLP_Pos) +#define WHAL_STM32F4_RCC_PLLCFGR_PLLSRC_Pos 22 +#define WHAL_STM32F4_RCC_PLLCFGR_PLLSRC_Msk (1UL << WHAL_STM32F4_RCC_PLLCFGR_PLLSRC_Pos) +#define WHAL_STM32F4_RCC_PLLCFGR_PLLQ_Pos 24 +#define WHAL_STM32F4_RCC_PLLCFGR_PLLQ_Msk (WHAL_BITMASK(4) << WHAL_STM32F4_RCC_PLLCFGR_PLLQ_Pos) +#define WHAL_STM32F4_RCC_PLLCFGR_Msk \ + (WHAL_STM32F4_RCC_PLLCFGR_PLLM_Msk | WHAL_STM32F4_RCC_PLLCFGR_PLLN_Msk | \ + WHAL_STM32F4_RCC_PLLCFGR_PLLP_Msk | WHAL_STM32F4_RCC_PLLCFGR_PLLSRC_Msk | \ + WHAL_STM32F4_RCC_PLLCFGR_PLLQ_Msk) + +#define WHAL_STM32F4_RCC_CFGR_REG 0x008 +#define WHAL_STM32F4_RCC_CFGR_SW_Pos 0 +#define WHAL_STM32F4_RCC_CFGR_SW_Msk (WHAL_BITMASK(2) << WHAL_STM32F4_RCC_CFGR_SW_Pos) +#define WHAL_STM32F4_RCC_CFGR_SWS_Pos 2 +#define WHAL_STM32F4_RCC_CFGR_SWS_Msk (WHAL_BITMASK(2) << WHAL_STM32F4_RCC_CFGR_SWS_Pos) +#define WHAL_STM32F4_RCC_CFGR_PPRE1_Pos 10 +#define WHAL_STM32F4_RCC_CFGR_PPRE1_Msk (WHAL_BITMASK(3) << WHAL_STM32F4_RCC_CFGR_PPRE1_Pos) +#define WHAL_STM32F4_RCC_CFGR_PPRE2_Pos 13 +#define WHAL_STM32F4_RCC_CFGR_PPRE2_Msk (WHAL_BITMASK(3) << WHAL_STM32F4_RCC_CFGR_PPRE2_Pos) + /* * @brief System clock source selection (RCC_CFGR.SW). */ @@ -86,47 +120,175 @@ typedef struct { .rdyReg = 0x000, .rdyMsk = (1UL << 17), .rdyPos = 17 /* - * @brief Enable an oscillator (HSI/HSE). Blocks until ready. + * @brief Turn on an oscillator (HSI/HSE) and wait for its ready bit. + * + * @param clkDev RCC device instance. + * @param cfg Oscillator on/ready bit descriptor. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f4_Rcc_EnableOsc(whal_Clock *clkDev, - const whal_Stm32f4_Rcc_OscCfg *cfg); +static inline whal_Error whal_Stm32f4_Rcc_EnableOsc( + const whal_Clock *clkDev, const whal_Stm32f4_Rcc_OscCfg *cfg) +{ + size_t rdy; + + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); + do { + whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + /* - * @brief Disable an oscillator. + * @brief Turn off an oscillator (HSI/HSE). + * + * @param clkDev RCC device instance. + * @param cfg Oscillator on/ready bit descriptor. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f4_Rcc_DisableOsc(whal_Clock *clkDev, - const whal_Stm32f4_Rcc_OscCfg *cfg); +static inline whal_Error whal_Stm32f4_Rcc_DisableOsc( + const whal_Clock *clkDev, const whal_Stm32f4_Rcc_OscCfg *cfg) +{ + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); + return WHAL_SUCCESS; +} /* - * @brief Configure and enable the PLL. Blocks until PLL is ready. + * @brief Configure and enable the PLL, waiting for lock. + * + * Turns the PLL off, programs PLLCFGR (M/N/P/Q + source), sets PLLON, and + * polls PLLRDY. Caller must have enabled the reference clock first. + * + * @param clkDev RCC device instance. + * @param cfg PLL configuration. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f4_Rcc_EnablePll(whal_Clock *clkDev, - const whal_Stm32f4_Rcc_PllCfg *cfg); +static inline whal_Error whal_Stm32f4_Rcc_EnablePll( + const whal_Clock *clkDev, const whal_Stm32f4_Rcc_PllCfg *cfg) +{ + size_t rdy; + + /* Disable PLL before reconfiguring. */ + whal_Reg_Update(clkDev->base, WHAL_STM32F4_RCC_CR_REG, + WHAL_STM32F4_RCC_CR_PLLON_Msk, 0); + + whal_Reg_Update(clkDev->base, WHAL_STM32F4_RCC_PLLCFGR_REG, + WHAL_STM32F4_RCC_PLLCFGR_Msk, + whal_SetBits(WHAL_STM32F4_RCC_PLLCFGR_PLLM_Msk, + WHAL_STM32F4_RCC_PLLCFGR_PLLM_Pos, cfg->m) | + whal_SetBits(WHAL_STM32F4_RCC_PLLCFGR_PLLN_Msk, + WHAL_STM32F4_RCC_PLLCFGR_PLLN_Pos, cfg->n) | + whal_SetBits(WHAL_STM32F4_RCC_PLLCFGR_PLLP_Msk, + WHAL_STM32F4_RCC_PLLCFGR_PLLP_Pos, cfg->p) | + whal_SetBits(WHAL_STM32F4_RCC_PLLCFGR_PLLSRC_Msk, + WHAL_STM32F4_RCC_PLLCFGR_PLLSRC_Pos, cfg->clkSrc) | + whal_SetBits(WHAL_STM32F4_RCC_PLLCFGR_PLLQ_Msk, + WHAL_STM32F4_RCC_PLLCFGR_PLLQ_Pos, cfg->q)); + + whal_Reg_Update(clkDev->base, WHAL_STM32F4_RCC_CR_REG, + WHAL_STM32F4_RCC_CR_PLLON_Msk, + WHAL_STM32F4_RCC_CR_PLLON_Msk); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32F4_RCC_CR_REG, + WHAL_STM32F4_RCC_CR_PLLRDY_Msk, + WHAL_STM32F4_RCC_CR_PLLRDY_Pos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + /* - * @brief Disable the PLL. + * @brief Turn the PLL off (clears RCC_CR.PLLON). + * + * @param clkDev RCC device instance. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f4_Rcc_DisablePll(whal_Clock *clkDev); +static inline whal_Error whal_Stm32f4_Rcc_DisablePll(const whal_Clock *clkDev) +{ + whal_Reg_Update(clkDev->base, WHAL_STM32F4_RCC_CR_REG, + WHAL_STM32F4_RCC_CR_PLLON_Msk, 0); + return WHAL_SUCCESS; +} /* - * @brief Set APB1 / APB2 bus prescalers. + * @brief Program APB1/APB2 bus prescalers (RCC_CFGR.PPRE1/PPRE2). + * + * @param clkDev RCC device instance. + * @param cfg Bus prescaler configuration. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f4_Rcc_SetBusPrescalers(whal_Clock *clkDev, - const whal_Stm32f4_Rcc_BusCfg *cfg); +static inline whal_Error whal_Stm32f4_Rcc_SetBusPrescalers( + const whal_Clock *clkDev, const whal_Stm32f4_Rcc_BusCfg *cfg) +{ + whal_Reg_Update(clkDev->base, WHAL_STM32F4_RCC_CFGR_REG, + WHAL_STM32F4_RCC_CFGR_PPRE1_Msk | + WHAL_STM32F4_RCC_CFGR_PPRE2_Msk, + whal_SetBits(WHAL_STM32F4_RCC_CFGR_PPRE1_Msk, + WHAL_STM32F4_RCC_CFGR_PPRE1_Pos, cfg->ppre1) | + whal_SetBits(WHAL_STM32F4_RCC_CFGR_PPRE2_Msk, + WHAL_STM32F4_RCC_CFGR_PPRE2_Pos, cfg->ppre2)); + return WHAL_SUCCESS; +} /* - * @brief Switch SYSCLK to the given source. Blocks until SWS confirms. + * @brief Switch SYSCLK to the requested source and wait for the switch. + * + * @param clkDev RCC device instance. + * @param src System clock source. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f4_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32f4_Rcc_SysClockSrc src); +static inline whal_Error whal_Stm32f4_Rcc_SetSysClock( + const whal_Clock *clkDev, whal_Stm32f4_Rcc_SysClockSrc src) +{ + size_t sws; + + whal_Reg_Update(clkDev->base, WHAL_STM32F4_RCC_CFGR_REG, + WHAL_STM32F4_RCC_CFGR_SW_Msk, + whal_SetBits(WHAL_STM32F4_RCC_CFGR_SW_Msk, + WHAL_STM32F4_RCC_CFGR_SW_Pos, src)); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32F4_RCC_CFGR_REG, + WHAL_STM32F4_RCC_CFGR_SWS_Msk, + WHAL_STM32F4_RCC_CFGR_SWS_Pos, &sws); + } while (sws != (size_t)src); + return WHAL_SUCCESS; +} /* - * @brief Enable a peripheral clock. + * @brief Set the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f4_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32f4_Rcc_PeriphClk *clk); +static inline whal_Error whal_Stm32f4_Rcc_EnablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32f4_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); + return WHAL_SUCCESS; +} + /* - * @brief Disable a peripheral clock. + * @brief Clear the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32f4_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32f4_Rcc_PeriphClk *clk); +static inline whal_Error whal_Stm32f4_Rcc_DisablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32f4_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); + return WHAL_SUCCESS; +} #endif /* WHAL_STM32F4_RCC_H */ diff --git a/wolfHAL/clock/stm32h5_rcc.h b/wolfHAL/clock/stm32h5_rcc.h index 7aaced6..1cc2118 100644 --- a/wolfHAL/clock/stm32h5_rcc.h +++ b/wolfHAL/clock/stm32h5_rcc.h @@ -50,6 +50,9 @@ #define WHAL_STM32H5_RCC_PLL1DIVR_PLL1R_Pos 24 #define WHAL_STM32H5_RCC_PLL1DIVR_PLL1R_Msk (WHAL_BITMASK(7) << WHAL_STM32H5_RCC_PLL1DIVR_PLL1R_Pos) +/* + * @brief System clock source selection (RCC_CFGR1.SW). + */ typedef enum { WHAL_STM32H5_RCC_SYSCLK_SRC_HSI, WHAL_STM32H5_RCC_SYSCLK_SRC_CSI, @@ -57,6 +60,9 @@ typedef enum { WHAL_STM32H5_RCC_SYSCLK_SRC_PLL1, } whal_Stm32h5_Rcc_SysClockSrc; +/* + * @brief PLL input clock source (RCC_PLL1CFGR.PLL1SRC). + */ typedef enum { WHAL_STM32H5_RCC_PLLCLK_SRC_NONE, WHAL_STM32H5_RCC_PLLCLK_SRC_HSI, @@ -64,6 +70,13 @@ typedef enum { WHAL_STM32H5_RCC_PLLCLK_SRC_HSE, } whal_Stm32h5_Rcc_PllClockSrc; +/* + * @brief PLL1 configuration parameters. + * VCO = (input / m) * n + * PLLP = VCO / p (SYSCLK domain) + * PLLQ = VCO / q + * PLLR = VCO / r + */ typedef struct { whal_Stm32h5_Rcc_PllClockSrc clkSrc; uint16_t n; @@ -73,12 +86,18 @@ typedef struct { uint8_t r; } whal_Stm32h5_Rcc_PllCfg; +/* + * @brief Peripheral clock descriptor (RCC *ENR enable bit). + */ typedef struct { size_t regOffset; size_t enableMask; size_t enablePos; } whal_Stm32h5_Rcc_PeriphClk; +/* + * @brief Cfg for EnableOsc/DisableOsc — on bit + ready bit. + */ typedef struct { size_t onReg; size_t onMsk; @@ -100,6 +119,14 @@ typedef struct { .onReg = 0x000, .onMsk = (1UL << 16), \ .rdyReg = 0x000, .rdyMsk = (1UL << 17), .rdyPos = 17 +/* + * @brief Turn on an oscillator and wait for its ready bit. + * + * @param clkDev RCC device instance. + * @param cfg Oscillator on/ready bit descriptor (e.g. WHAL_STM32H5_RCC_HSE_CFG). + * + * @retval WHAL_SUCCESS Always. + */ static inline whal_Error whal_Stm32h5_Rcc_EnableOsc( const whal_Clock *clkDev, const whal_Stm32h5_Rcc_OscCfg *cfg) { @@ -113,6 +140,14 @@ static inline whal_Error whal_Stm32h5_Rcc_EnableOsc( return WHAL_SUCCESS; } +/* + * @brief Turn off an oscillator. + * + * @param clkDev RCC device instance. + * @param cfg Oscillator on/ready bit descriptor. + * + * @retval WHAL_SUCCESS Always. + */ static inline whal_Error whal_Stm32h5_Rcc_DisableOsc( const whal_Clock *clkDev, const whal_Stm32h5_Rcc_OscCfg *cfg) { @@ -120,6 +155,17 @@ static inline whal_Error whal_Stm32h5_Rcc_DisableOsc( return WHAL_SUCCESS; } +/* + * @brief Configure and enable PLL1, waiting for lock. + * + * Turns PLL1 off, waits for !PLL1RDY, programs PLL1CFGR (SRC/M, output + * enables) and PLL1DIVR (N/P/Q/R), then sets PLL1ON and polls PLL1RDY. + * + * @param clkDev RCC device instance. + * @param cfg PLL1 configuration. + * + * @retval WHAL_SUCCESS Always. + */ static inline whal_Error whal_Stm32h5_Rcc_EnablePll1( const whal_Clock *clkDev, const whal_Stm32h5_Rcc_PllCfg *cfg) { @@ -174,6 +220,13 @@ static inline whal_Error whal_Stm32h5_Rcc_EnablePll1( return WHAL_SUCCESS; } +/* + * @brief Turn PLL1 off (clears RCC_CR.PLL1ON). + * + * @param clkDev RCC device instance. + * + * @retval WHAL_SUCCESS Always. + */ static inline whal_Error whal_Stm32h5_Rcc_DisablePll1(const whal_Clock *clkDev) { whal_Reg_Update(clkDev->base, WHAL_STM32H5_RCC_CR_REG, @@ -181,6 +234,14 @@ static inline whal_Error whal_Stm32h5_Rcc_DisablePll1(const whal_Clock *clkDev) return WHAL_SUCCESS; } +/* + * @brief Switch SYSCLK to the requested source and wait for the switch. + * + * @param clkDev RCC device instance. + * @param src System clock source. + * + * @retval WHAL_SUCCESS Always. + */ static inline whal_Error whal_Stm32h5_Rcc_SetSysClock( const whal_Clock *clkDev, whal_Stm32h5_Rcc_SysClockSrc src) { @@ -198,6 +259,16 @@ static inline whal_Error whal_Stm32h5_Rcc_SetSysClock( return WHAL_SUCCESS; } +/* + * @brief Program the HSI divider (RCC_CR.HSIDIV). + * + * HSI = 64 MHz / 2^div. Encoded as 0..3 for /1, /2, /4, /8. + * + * @param clkDev RCC device instance. + * @param div HSIDIV encoded value (0..3). + * + * @retval WHAL_SUCCESS Always. + */ static inline whal_Error whal_Stm32h5_Rcc_SetHsiDiv( const whal_Clock *clkDev, uint8_t div) { @@ -208,6 +279,14 @@ static inline whal_Error whal_Stm32h5_Rcc_SetHsiDiv( return WHAL_SUCCESS; } +/* + * @brief Set the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. + */ static inline whal_Error whal_Stm32h5_Rcc_EnablePeriphClk( const whal_Clock *clkDev, const whal_Stm32h5_Rcc_PeriphClk *clk) { @@ -216,6 +295,14 @@ static inline whal_Error whal_Stm32h5_Rcc_EnablePeriphClk( return WHAL_SUCCESS; } +/* + * @brief Clear the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. + */ static inline whal_Error whal_Stm32h5_Rcc_DisablePeriphClk( const whal_Clock *clkDev, const whal_Stm32h5_Rcc_PeriphClk *clk) { diff --git a/wolfHAL/clock/stm32l1_rcc.h b/wolfHAL/clock/stm32l1_rcc.h index f43d69b..00a844d 100644 --- a/wolfHAL/clock/stm32l1_rcc.h +++ b/wolfHAL/clock/stm32l1_rcc.h @@ -2,8 +2,11 @@ #define WHAL_STM32L1_RCC_H #include -#include #include +#include +#include +#include +#include /* * @file stm32l1_rcc.h @@ -18,6 +21,23 @@ * PLL = HSI or HSE * PLLMUL / PLLDIV (max 32 MHz) */ +#define WHAL_STM32L1_RCC_CR_REG 0x00 +#define WHAL_STM32L1_RCC_CR_PLLON_Msk (1UL << 24) +#define WHAL_STM32L1_RCC_CR_PLLRDY_Msk (1UL << 25) +#define WHAL_STM32L1_RCC_CR_PLLRDY_Pos 25 + +#define WHAL_STM32L1_RCC_CFGR_REG 0x08 +#define WHAL_STM32L1_RCC_CFGR_SW_Pos 0 +#define WHAL_STM32L1_RCC_CFGR_SW_Msk (WHAL_BITMASK(2) << WHAL_STM32L1_RCC_CFGR_SW_Pos) +#define WHAL_STM32L1_RCC_CFGR_SWS_Pos 2 +#define WHAL_STM32L1_RCC_CFGR_SWS_Msk (WHAL_BITMASK(2) << WHAL_STM32L1_RCC_CFGR_SWS_Pos) +#define WHAL_STM32L1_RCC_CFGR_PLLSRC_Pos 16 +#define WHAL_STM32L1_RCC_CFGR_PLLSRC_Msk (1UL << WHAL_STM32L1_RCC_CFGR_PLLSRC_Pos) +#define WHAL_STM32L1_RCC_CFGR_PLLMUL_Pos 18 +#define WHAL_STM32L1_RCC_CFGR_PLLMUL_Msk (WHAL_BITMASK(4) << WHAL_STM32L1_RCC_CFGR_PLLMUL_Pos) +#define WHAL_STM32L1_RCC_CFGR_PLLDIV_Pos 22 +#define WHAL_STM32L1_RCC_CFGR_PLLDIV_Msk (WHAL_BITMASK(2) << WHAL_STM32L1_RCC_CFGR_PLLDIV_Pos) + /* * @brief System clock source selection (RCC_CFGR.SW). */ @@ -97,42 +117,165 @@ typedef struct { .rdyReg = 0x000, .rdyMsk = (1UL << 17), .rdyPos = 17 /* - * @brief Enable an oscillator (HSI/HSE). Blocks until ready. + * @brief Turn on an oscillator (HSI/HSE) and wait for its ready bit. + * + * @param clkDev RCC device instance. + * @param cfg Oscillator on/ready bit descriptor. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32l1_Rcc_EnableOsc(whal_Clock *clkDev, - const whal_Stm32l1_Rcc_OscCfg *cfg); +static inline whal_Error whal_Stm32l1_Rcc_EnableOsc( + const whal_Clock *clkDev, const whal_Stm32l1_Rcc_OscCfg *cfg) +{ + size_t rdy; + + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); + do { + whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + /* - * @brief Disable an oscillator. + * @brief Turn off an oscillator (HSI/HSE). + * + * @param clkDev RCC device instance. + * @param cfg Oscillator on/ready bit descriptor. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32l1_Rcc_DisableOsc(whal_Clock *clkDev, - const whal_Stm32l1_Rcc_OscCfg *cfg); +static inline whal_Error whal_Stm32l1_Rcc_DisableOsc( + const whal_Clock *clkDev, const whal_Stm32l1_Rcc_OscCfg *cfg) +{ + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); + return WHAL_SUCCESS; +} /* - * @brief Configure and enable the PLL. Caller must have the PLL source - * oscillator already enabled. Blocks until PLL is ready. + * @brief Configure and enable the PLL, waiting for lock. + * + * Turns the PLL off (waits for !PLLRDY), programs PLLSRC, PLLMUL, PLLDIV, + * sets PLLON, and polls PLLRDY. Requires PWR VOS range high enough for the + * target frequency — see stm32l1_pwr.h. + * + * @param clkDev RCC device instance. + * @param cfg PLL configuration. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32l1_Rcc_EnablePll(whal_Clock *clkDev, - const whal_Stm32l1_Rcc_PllCfg *cfg); +static inline whal_Error whal_Stm32l1_Rcc_EnablePll( + const whal_Clock *clkDev, const whal_Stm32l1_Rcc_PllCfg *cfg) +{ + size_t rdy; + uint32_t pllsrc; + + /* Disable PLL before reconfiguring; wait until it's actually off. */ + whal_Reg_Update(clkDev->base, WHAL_STM32L1_RCC_CR_REG, + WHAL_STM32L1_RCC_CR_PLLON_Msk, 0); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32L1_RCC_CR_REG, + WHAL_STM32L1_RCC_CR_PLLRDY_Msk, + WHAL_STM32L1_RCC_CR_PLLRDY_Pos, &rdy); + } while (rdy); + + pllsrc = (cfg->clkSrc == WHAL_STM32L1_RCC_PLLSRC_HSE) ? 1 : 0; + whal_Reg_Update(clkDev->base, WHAL_STM32L1_RCC_CFGR_REG, + WHAL_STM32L1_RCC_CFGR_PLLSRC_Msk, + whal_SetBits(WHAL_STM32L1_RCC_CFGR_PLLSRC_Msk, + WHAL_STM32L1_RCC_CFGR_PLLSRC_Pos, + pllsrc)); + whal_Reg_Update(clkDev->base, WHAL_STM32L1_RCC_CFGR_REG, + WHAL_STM32L1_RCC_CFGR_PLLMUL_Msk, + whal_SetBits(WHAL_STM32L1_RCC_CFGR_PLLMUL_Msk, + WHAL_STM32L1_RCC_CFGR_PLLMUL_Pos, + cfg->pllmul)); + whal_Reg_Update(clkDev->base, WHAL_STM32L1_RCC_CFGR_REG, + WHAL_STM32L1_RCC_CFGR_PLLDIV_Msk, + whal_SetBits(WHAL_STM32L1_RCC_CFGR_PLLDIV_Msk, + WHAL_STM32L1_RCC_CFGR_PLLDIV_Pos, + cfg->plldiv)); + + whal_Reg_Update(clkDev->base, WHAL_STM32L1_RCC_CR_REG, + WHAL_STM32L1_RCC_CR_PLLON_Msk, + WHAL_STM32L1_RCC_CR_PLLON_Msk); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32L1_RCC_CR_REG, + WHAL_STM32L1_RCC_CR_PLLRDY_Msk, + WHAL_STM32L1_RCC_CR_PLLRDY_Pos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + /* - * @brief Disable the PLL. + * @brief Turn the PLL off (clears RCC_CR.PLLON). + * + * @param clkDev RCC device instance. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32l1_Rcc_DisablePll(whal_Clock *clkDev); +static inline whal_Error whal_Stm32l1_Rcc_DisablePll(const whal_Clock *clkDev) +{ + whal_Reg_Update(clkDev->base, WHAL_STM32L1_RCC_CR_REG, + WHAL_STM32L1_RCC_CR_PLLON_Msk, 0); + return WHAL_SUCCESS; +} /* - * @brief Switch SYSCLK to the given source. Blocks until SWS confirms. + * @brief Switch SYSCLK to the requested source and wait for the switch. + * + * @param clkDev RCC device instance. + * @param src System clock source. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32l1_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32l1_Rcc_SysClockSrc src); +static inline whal_Error whal_Stm32l1_Rcc_SetSysClock( + const whal_Clock *clkDev, whal_Stm32l1_Rcc_SysClockSrc src) +{ + size_t sws; + + whal_Reg_Update(clkDev->base, WHAL_STM32L1_RCC_CFGR_REG, + WHAL_STM32L1_RCC_CFGR_SW_Msk, + whal_SetBits(WHAL_STM32L1_RCC_CFGR_SW_Msk, + WHAL_STM32L1_RCC_CFGR_SW_Pos, src)); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32L1_RCC_CFGR_REG, + WHAL_STM32L1_RCC_CFGR_SWS_Msk, + WHAL_STM32L1_RCC_CFGR_SWS_Pos, &sws); + } while (sws != (size_t)src); + return WHAL_SUCCESS; +} /* - * @brief Enable a peripheral clock. + * @brief Set the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32l1_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32l1_Rcc_PeriphClk *clk); +static inline whal_Error whal_Stm32l1_Rcc_EnablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32l1_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); + return WHAL_SUCCESS; +} + /* - * @brief Disable a peripheral clock. + * @brief Clear the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32l1_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32l1_Rcc_PeriphClk *clk); +static inline whal_Error whal_Stm32l1_Rcc_DisablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32l1_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); + return WHAL_SUCCESS; +} #endif /* WHAL_STM32L1_RCC_H */ diff --git a/wolfHAL/clock/stm32n6_rcc.h b/wolfHAL/clock/stm32n6_rcc.h index ab1f149..420ddb4 100644 --- a/wolfHAL/clock/stm32n6_rcc.h +++ b/wolfHAL/clock/stm32n6_rcc.h @@ -1,6 +1,13 @@ #ifndef WHAL_STM32N6_RCC_H #define WHAL_STM32N6_RCC_H +#include +#include +#include +#include +#include +#include + /** * @file stm32n6_rcc.h * @brief STM32N6 RCC (Reset and Clock Control) driver. @@ -13,9 +20,41 @@ * - PLL1 configuration split across PLL1CFGR1/PLL1CFGR2/PLL1CFGR3 */ -#include -#include -#include +#define WHAL_STM32N6_RCC_CR_REG 0x000 +#define WHAL_STM32N6_RCC_CR_PLL1ON_Msk (1UL << 8) + +#define WHAL_STM32N6_RCC_SR_REG 0x004 +#define WHAL_STM32N6_RCC_SR_PLL1RDY_Msk (1UL << 8) +#define WHAL_STM32N6_RCC_SR_PLL1RDY_Pos 8 + +#define WHAL_STM32N6_RCC_CFGR1_REG 0x020 +#define WHAL_STM32N6_RCC_CFGR1_CPUSW_Pos 16 +#define WHAL_STM32N6_RCC_CFGR1_CPUSW_Msk (3UL << WHAL_STM32N6_RCC_CFGR1_CPUSW_Pos) +#define WHAL_STM32N6_RCC_CFGR1_CPUSWS_Pos 20 +#define WHAL_STM32N6_RCC_CFGR1_CPUSWS_Msk (3UL << WHAL_STM32N6_RCC_CFGR1_CPUSWS_Pos) +#define WHAL_STM32N6_RCC_CFGR1_SYSSW_Pos 24 +#define WHAL_STM32N6_RCC_CFGR1_SYSSW_Msk (3UL << WHAL_STM32N6_RCC_CFGR1_SYSSW_Pos) +#define WHAL_STM32N6_RCC_CFGR1_SYSSWS_Pos 28 +#define WHAL_STM32N6_RCC_CFGR1_SYSSWS_Msk (3UL << WHAL_STM32N6_RCC_CFGR1_SYSSWS_Pos) + +#define WHAL_STM32N6_RCC_PLL1CFGR1_REG 0x080 +#define WHAL_STM32N6_RCC_PLL1CFGR1_PLL1SEL_Pos 28 +#define WHAL_STM32N6_RCC_PLL1CFGR1_PLL1SEL_Msk (7UL << WHAL_STM32N6_RCC_PLL1CFGR1_PLL1SEL_Pos) +#define WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVM_Pos 20 +#define WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVM_Msk (0x3FUL << WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVM_Pos) +#define WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVN_Pos 0 +#define WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVN_Msk (0xFFFUL << WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVN_Pos) + +#define WHAL_STM32N6_RCC_PLL1CFGR3_REG 0x088 +#define WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIVEN_Msk (1UL << 30) +#define WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV1_Pos 27 +#define WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV1_Msk (7UL << WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV1_Pos) +#define WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV2_Pos 24 +#define WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV2_Msk (7UL << WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV2_Pos) + +#define WHAL_STM32N6_RCC_CCIPR2_REG 0x148 +#define WHAL_STM32N6_RCC_CCIPR2_ETH1SEL_Pos 16 +#define WHAL_STM32N6_RCC_CCIPR2_ETH1SEL_Msk (7UL << WHAL_STM32N6_RCC_CCIPR2_ETH1SEL_Pos) /** * @brief System clock switch selection (RCC_CFGR1.SYSSW). @@ -106,55 +145,211 @@ typedef struct { .rdyReg = 0x004, .rdyMsk = (1UL << 4), .rdyPos = 4 /** - * @brief Enable an oscillator (HSI/MSI/HSE/LSI/LSE). Blocks until ready. + * @brief Turn on an oscillator and wait for its ready bit. + * + * @param clkDev RCC device instance. + * @param cfg Oscillator on/ready bit descriptor (e.g. WHAL_STM32N6_RCC_HSE_CFG). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32n6_Rcc_EnableOsc(whal_Clock *clkDev, - const whal_Stm32n6_Rcc_OscCfg *cfg); +static inline whal_Error whal_Stm32n6_Rcc_EnableOsc( + const whal_Clock *clkDev, const whal_Stm32n6_Rcc_OscCfg *cfg) +{ + size_t rdy; + + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); + do { + whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + /** - * @brief Disable an oscillator. + * @brief Turn off an oscillator. + * + * @param clkDev RCC device instance. + * @param cfg Oscillator on/ready bit descriptor. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32n6_Rcc_DisableOsc(whal_Clock *clkDev, - const whal_Stm32n6_Rcc_OscCfg *cfg); +static inline whal_Error whal_Stm32n6_Rcc_DisableOsc( + const whal_Clock *clkDev, const whal_Stm32n6_Rcc_OscCfg *cfg) +{ + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); + return WHAL_SUCCESS; +} /** - * @brief Configure and enable PLL1. Caller must have the PLL1 source - * oscillator already enabled. Blocks until PLL1 is ready. + * @brief Configure and enable PLL1, waiting for lock. + * + * Turns PLL1 off (waits for !PLL1RDY), programs PLL1CFGR1 (SEL/DIVM/DIVN) + * and PLL1CFGR3 (PDIVEN + PDIV1/PDIV2), sets PLL1ON, polls PLL1RDY. + * + * @param clkDev RCC device instance. + * @param cfg PLL1 configuration. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32n6_Rcc_EnablePll1(whal_Clock *clkDev, - const whal_Stm32n6_Rcc_Pll1Cfg *cfg); +static inline whal_Error whal_Stm32n6_Rcc_EnablePll1( + const whal_Clock *clkDev, const whal_Stm32n6_Rcc_Pll1Cfg *cfg) +{ + size_t rdy; + + /* Disable PLL1 before reconfiguring; wait until off. */ + whal_Reg_Update(clkDev->base, WHAL_STM32N6_RCC_CR_REG, + WHAL_STM32N6_RCC_CR_PLL1ON_Msk, 0); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32N6_RCC_SR_REG, + WHAL_STM32N6_RCC_SR_PLL1RDY_Msk, + WHAL_STM32N6_RCC_SR_PLL1RDY_Pos, &rdy); + } while (rdy); + + whal_Reg_Write(clkDev->base, WHAL_STM32N6_RCC_PLL1CFGR1_REG, + whal_SetBits(WHAL_STM32N6_RCC_PLL1CFGR1_PLL1SEL_Msk, + WHAL_STM32N6_RCC_PLL1CFGR1_PLL1SEL_Pos, cfg->clkSrc) | + whal_SetBits(WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVM_Msk, + WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVM_Pos, cfg->m) | + whal_SetBits(WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVN_Msk, + WHAL_STM32N6_RCC_PLL1CFGR1_PLL1DIVN_Pos, cfg->n)); + whal_Reg_Update(clkDev->base, WHAL_STM32N6_RCC_PLL1CFGR3_REG, + WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIVEN_Msk | + WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV1_Msk | + WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV2_Msk, + WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIVEN_Msk | + whal_SetBits(WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV1_Msk, + WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV1_Pos, cfg->pdiv1) | + whal_SetBits(WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV2_Msk, + WHAL_STM32N6_RCC_PLL1CFGR3_PLL1PDIV2_Pos, cfg->pdiv2)); + + whal_Reg_Update(clkDev->base, WHAL_STM32N6_RCC_CR_REG, + WHAL_STM32N6_RCC_CR_PLL1ON_Msk, + WHAL_STM32N6_RCC_CR_PLL1ON_Msk); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32N6_RCC_SR_REG, + WHAL_STM32N6_RCC_SR_PLL1RDY_Msk, + WHAL_STM32N6_RCC_SR_PLL1RDY_Pos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + /** - * @brief Disable PLL1. + * @brief Turn PLL1 off (clears RCC_CR.PLL1ON). + * + * @param clkDev RCC device instance. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32n6_Rcc_DisablePll1(whal_Clock *clkDev); +static inline whal_Error whal_Stm32n6_Rcc_DisablePll1(const whal_Clock *clkDev) +{ + whal_Reg_Update(clkDev->base, WHAL_STM32N6_RCC_CR_REG, + WHAL_STM32N6_RCC_CR_PLL1ON_Msk, 0); + return WHAL_SUCCESS; +} /** - * @brief Switch SYSCLK to the given source. Blocks until SYSSWS confirms. + * @brief Switch the system clock (SYSSW) to the requested source. + * + * Programs CFGR1.SYSSW and polls CFGR1.SYSSWS until it reports the new source. + * + * @param clkDev RCC device instance. + * @param src System clock source. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32n6_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32n6_Rcc_SysClockSrc src); +static inline whal_Error whal_Stm32n6_Rcc_SetSysClock( + const whal_Clock *clkDev, whal_Stm32n6_Rcc_SysClockSrc src) +{ + size_t sws; + + whal_Reg_Update(clkDev->base, WHAL_STM32N6_RCC_CFGR1_REG, + WHAL_STM32N6_RCC_CFGR1_SYSSW_Msk, + whal_SetBits(WHAL_STM32N6_RCC_CFGR1_SYSSW_Msk, + WHAL_STM32N6_RCC_CFGR1_SYSSW_Pos, src)); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32N6_RCC_CFGR1_REG, + WHAL_STM32N6_RCC_CFGR1_SYSSWS_Msk, + WHAL_STM32N6_RCC_CFGR1_SYSSWS_Pos, &sws); + } while (sws != (size_t)src); + return WHAL_SUCCESS; +} + /** - * @brief Switch CPU clock to the given source. Blocks until CPUSWS confirms. + * @brief Switch the CPU clock (CPUSW) to the requested source. + * + * Programs CFGR1.CPUSW and polls CFGR1.CPUSWS until it reports the new source. + * + * @param clkDev RCC device instance. + * @param src CPU clock source. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32n6_Rcc_SetCpuClock(whal_Clock *clkDev, - whal_Stm32n6_Rcc_CpuClockSrc src); +static inline whal_Error whal_Stm32n6_Rcc_SetCpuClock( + const whal_Clock *clkDev, whal_Stm32n6_Rcc_CpuClockSrc src) +{ + size_t sws; + + whal_Reg_Update(clkDev->base, WHAL_STM32N6_RCC_CFGR1_REG, + WHAL_STM32N6_RCC_CFGR1_CPUSW_Msk, + whal_SetBits(WHAL_STM32N6_RCC_CFGR1_CPUSW_Msk, + WHAL_STM32N6_RCC_CFGR1_CPUSW_Pos, src)); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32N6_RCC_CFGR1_REG, + WHAL_STM32N6_RCC_CFGR1_CPUSWS_Msk, + WHAL_STM32N6_RCC_CFGR1_CPUSWS_Pos, &sws); + } while (sws != (size_t)src); + return WHAL_SUCCESS; +} /** - * @brief Select the ETH1 MAC-PHY interface (RCC_CCIPR2.ETH1SEL). - * Must be programmed while ETH1 is in reset and before its clocks - * are enabled. + * @brief Select the Ethernet 1 PHY interface (MII/RGMII/RMII). + * + * @param clkDev RCC device instance. + * @param mode PHY interface selection (RCC_CCIPR2.ETH1SEL). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32n6_Rcc_SetEth1If(whal_Clock *clkDev, - whal_Stm32n6_Rcc_Eth1If mode); +static inline whal_Error whal_Stm32n6_Rcc_SetEth1If( + const whal_Clock *clkDev, whal_Stm32n6_Rcc_Eth1If mode) +{ + whal_Reg_Update(clkDev->base, WHAL_STM32N6_RCC_CCIPR2_REG, + WHAL_STM32N6_RCC_CCIPR2_ETH1SEL_Msk, + whal_SetBits(WHAL_STM32N6_RCC_CCIPR2_ETH1SEL_Msk, + WHAL_STM32N6_RCC_CCIPR2_ETH1SEL_Pos, + mode)); + return WHAL_SUCCESS; +} /** - * @brief Enable a peripheral clock. + * @brief Set the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32n6_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32n6_Rcc_PeriphClk *clk); +static inline whal_Error whal_Stm32n6_Rcc_EnablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32n6_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); + return WHAL_SUCCESS; +} + /** - * @brief Disable a peripheral clock. + * @brief Clear the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32n6_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32n6_Rcc_PeriphClk *clk); +static inline whal_Error whal_Stm32n6_Rcc_DisablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32n6_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); + return WHAL_SUCCESS; +} #endif /* WHAL_STM32N6_RCC_H */ diff --git a/wolfHAL/clock/stm32wb_rcc.h b/wolfHAL/clock/stm32wb_rcc.h index d45edc6..2381bb1 100644 --- a/wolfHAL/clock/stm32wb_rcc.h +++ b/wolfHAL/clock/stm32wb_rcc.h @@ -53,6 +53,9 @@ WHAL_STM32WB_RCC_PLLCFGR_PLLQ_Msk | WHAL_STM32WB_RCC_PLLCFGR_PLLREN_Msk | \ WHAL_STM32WB_RCC_PLLCFGR_PLLR_Msk) +/* + * @brief System clock source selection (RCC_CFGR.SW). + */ typedef enum { WHAL_STM32WB_RCC_SYSCLK_SRC_MSI, WHAL_STM32WB_RCC_SYSCLK_SRC_HSI16, @@ -60,6 +63,9 @@ typedef enum { WHAL_STM32WB_RCC_SYSCLK_SRC_PLL, } whal_Stm32wb_Rcc_SysClockSrc; +/* + * @brief PLL input clock source (RCC_PLLCFGR.PLLSRC). + */ typedef enum { WHAL_STM32WB_RCC_PLLCLK_SRC_NONE, WHAL_STM32WB_RCC_PLLCLK_SRC_MSI, @@ -67,6 +73,9 @@ typedef enum { WHAL_STM32WB_RCC_PLLCLK_SRC_HSE, } whal_Stm32wb_Rcc_PllClockSrc; +/* + * @brief MSI oscillator range selection (RCC_CR.MSIRANGE). + */ typedef enum { WHAL_STM32WB_RCC_MSIRANGE_100kHz, WHAL_STM32WB_RCC_MSIRANGE_200kHz, @@ -82,12 +91,18 @@ typedef enum { WHAL_STM32WB_RCC_MSIRANGE_48MHz, } whal_Stm32wb_Rcc_MsiRange; +/* + * @brief Peripheral clock descriptor (RCC *ENR enable bit). + */ typedef struct { size_t regOffset; size_t enableMask; size_t enablePos; } whal_Stm32wb_Rcc_PeriphClk; +/* + * @brief Cfg for EnableOsc/DisableOsc — on bit + ready bit. + */ typedef struct { size_t onReg; size_t onMsk; @@ -112,6 +127,11 @@ typedef struct { .onReg = 0x090, .onMsk = (1UL << 0), \ .rdyReg = 0x090, .rdyMsk = (1UL << 1), .rdyPos = 1 +/* + * @brief PLL configuration parameters. + * VCO = (input / m) * n + * PLLR = VCO / r (SYSCLK domain) + */ typedef struct { whal_Stm32wb_Rcc_PllClockSrc clkSrc; uint8_t r; @@ -121,6 +141,14 @@ typedef struct { uint8_t m; } whal_Stm32wb_Rcc_PllCfg; +/* + * @brief Turn on an oscillator and wait for its ready bit. + * + * @param clkDev RCC device instance. + * @param cfg Oscillator on/ready bit descriptor (e.g. WHAL_STM32WB_RCC_HSE_CFG). + * + * @retval WHAL_SUCCESS Always. + */ static inline whal_Error whal_Stm32wb_Rcc_EnableOsc( const whal_Clock *clkDev, const whal_Stm32wb_Rcc_OscCfg *cfg) { @@ -134,6 +162,14 @@ static inline whal_Error whal_Stm32wb_Rcc_EnableOsc( return WHAL_SUCCESS; } +/* + * @brief Turn off an oscillator. + * + * @param clkDev RCC device instance. + * @param cfg Oscillator on/ready bit descriptor. + * + * @retval WHAL_SUCCESS Always. + */ static inline whal_Error whal_Stm32wb_Rcc_DisableOsc( const whal_Clock *clkDev, const whal_Stm32wb_Rcc_OscCfg *cfg) { @@ -141,6 +177,16 @@ static inline whal_Error whal_Stm32wb_Rcc_DisableOsc( return WHAL_SUCCESS; } +/* + * @brief Enable the MSI oscillator, wait for ready, and select its range. + * + * Sets MSION, polls MSIRDY, then writes MSIRANGE. + * + * @param clkDev RCC device instance. + * @param range MSI range selection. + * + * @retval WHAL_SUCCESS Always. + */ static inline whal_Error whal_Stm32wb_Rcc_EnableMsi( const whal_Clock *clkDev, whal_Stm32wb_Rcc_MsiRange range) { @@ -161,6 +207,16 @@ static inline whal_Error whal_Stm32wb_Rcc_EnableMsi( return WHAL_SUCCESS; } +/* + * @brief Configure and enable the PLL, waiting for lock. + * + * Programs PLLCFGR (source/M/N/P/Q/R + REN), sets PLLON, polls PLLRDY. + * + * @param clkDev RCC device instance. + * @param cfg PLL configuration. + * + * @retval WHAL_SUCCESS Always. + */ static inline whal_Error whal_Stm32wb_Rcc_EnablePll( const whal_Clock *clkDev, const whal_Stm32wb_Rcc_PllCfg *cfg) { @@ -193,6 +249,13 @@ static inline whal_Error whal_Stm32wb_Rcc_EnablePll( return WHAL_SUCCESS; } +/* + * @brief Turn the PLL off (clears RCC_CR.PLLON). + * + * @param clkDev RCC device instance. + * + * @retval WHAL_SUCCESS Always. + */ static inline whal_Error whal_Stm32wb_Rcc_DisablePll(const whal_Clock *clkDev) { whal_Reg_Update(clkDev->base, WHAL_STM32WB_RCC_CR_REG, @@ -200,6 +263,14 @@ static inline whal_Error whal_Stm32wb_Rcc_DisablePll(const whal_Clock *clkDev) return WHAL_SUCCESS; } +/* + * @brief Switch SYSCLK to the requested source and wait for the switch. + * + * @param clkDev RCC device instance. + * @param src System clock source. + * + * @retval WHAL_SUCCESS Always. + */ static inline whal_Error whal_Stm32wb_Rcc_SetSysClock( const whal_Clock *clkDev, whal_Stm32wb_Rcc_SysClockSrc src) { @@ -217,6 +288,14 @@ static inline whal_Error whal_Stm32wb_Rcc_SetSysClock( return WHAL_SUCCESS; } +/* + * @brief Set the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. + */ static inline whal_Error whal_Stm32wb_Rcc_EnablePeriphClk( const whal_Clock *clkDev, const whal_Stm32wb_Rcc_PeriphClk *clk) { @@ -225,6 +304,14 @@ static inline whal_Error whal_Stm32wb_Rcc_EnablePeriphClk( return WHAL_SUCCESS; } +/* + * @brief Clear the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. + */ static inline whal_Error whal_Stm32wb_Rcc_DisablePeriphClk( const whal_Clock *clkDev, const whal_Stm32wb_Rcc_PeriphClk *clk) { diff --git a/wolfHAL/clock/stm32wba_rcc.h b/wolfHAL/clock/stm32wba_rcc.h index 4c35604..edd2f90 100644 --- a/wolfHAL/clock/stm32wba_rcc.h +++ b/wolfHAL/clock/stm32wba_rcc.h @@ -4,6 +4,9 @@ #include #include #include +#include +#include +#include /* * @file stm32wba_rcc.h @@ -18,6 +21,50 @@ * - HPRE5 prescaler for AHB5 domain */ +#define WHAL_STM32WBA_RCC_CR_REG 0x000 +#define WHAL_STM32WBA_RCC_CR_PLL1ON_Msk (1UL << 24) +#define WHAL_STM32WBA_RCC_CR_PLL1RDY_Msk (1UL << 25) +#define WHAL_STM32WBA_RCC_CR_PLL1RDY_Pos 25 + +#define WHAL_STM32WBA_RCC_CFGR1_REG 0x01C +#define WHAL_STM32WBA_RCC_CFGR1_SW_Pos 0 +#define WHAL_STM32WBA_RCC_CFGR1_SW_Msk (3UL << WHAL_STM32WBA_RCC_CFGR1_SW_Pos) +#define WHAL_STM32WBA_RCC_CFGR1_SWS_Pos 2 +#define WHAL_STM32WBA_RCC_CFGR1_SWS_Msk (3UL << WHAL_STM32WBA_RCC_CFGR1_SWS_Pos) + +#define WHAL_STM32WBA_RCC_PLL1CFGR_REG 0x028 +#define WHAL_STM32WBA_RCC_PLL1CFGR_SRC_Pos 0 +#define WHAL_STM32WBA_RCC_PLL1CFGR_SRC_Msk (3UL << WHAL_STM32WBA_RCC_PLL1CFGR_SRC_Pos) +#define WHAL_STM32WBA_RCC_PLL1CFGR_RGE_Pos 2 +#define WHAL_STM32WBA_RCC_PLL1CFGR_RGE_Msk (3UL << WHAL_STM32WBA_RCC_PLL1CFGR_RGE_Pos) +#define WHAL_STM32WBA_RCC_PLL1CFGR_M_Pos 8 +#define WHAL_STM32WBA_RCC_PLL1CFGR_M_Msk (7UL << WHAL_STM32WBA_RCC_PLL1CFGR_M_Pos) +#define WHAL_STM32WBA_RCC_PLL1CFGR_REN_Pos 18 +#define WHAL_STM32WBA_RCC_PLL1CFGR_REN_Msk (1UL << WHAL_STM32WBA_RCC_PLL1CFGR_REN_Pos) + +#define WHAL_STM32WBA_RCC_PLL1DIVR_REG 0x034 +#define WHAL_STM32WBA_RCC_PLL1DIVR_N_Pos 0 +#define WHAL_STM32WBA_RCC_PLL1DIVR_N_Msk (0x1FFUL << WHAL_STM32WBA_RCC_PLL1DIVR_N_Pos) +#define WHAL_STM32WBA_RCC_PLL1DIVR_P_Pos 9 +#define WHAL_STM32WBA_RCC_PLL1DIVR_P_Msk (0x7FUL << WHAL_STM32WBA_RCC_PLL1DIVR_P_Pos) +#define WHAL_STM32WBA_RCC_PLL1DIVR_Q_Pos 16 +#define WHAL_STM32WBA_RCC_PLL1DIVR_Q_Msk (0x7FUL << WHAL_STM32WBA_RCC_PLL1DIVR_Q_Pos) +#define WHAL_STM32WBA_RCC_PLL1DIVR_R_Pos 24 +#define WHAL_STM32WBA_RCC_PLL1DIVR_R_Msk (0x7FUL << WHAL_STM32WBA_RCC_PLL1DIVR_R_Pos) + +#define WHAL_STM32WBA_RCC_BDCR1_REG 0x0C8 +#define WHAL_STM32WBA_RCC_BDCR1_LSI1ON_Msk (1UL << 2) +#define WHAL_STM32WBA_RCC_BDCR1_LSI1RDY_Msk (1UL << 3) +#define WHAL_STM32WBA_RCC_BDCR1_LSI1RDY_Pos 3 + +#define WHAL_STM32WBA_RCC_CFGR4_REG 0x080 +#define WHAL_STM32WBA_RCC_CFGR4_HPRE5_Pos 0 +#define WHAL_STM32WBA_RCC_CFGR4_HPRE5_Msk (7UL << WHAL_STM32WBA_RCC_CFGR4_HPRE5_Pos) + +#define WHAL_STM32WBA_RCC_CCIPR2_REG 0x0E4 +#define WHAL_STM32WBA_RCC_CCIPR2_RNGSEL_Pos 12 +#define WHAL_STM32WBA_RCC_CCIPR2_RNGSEL_Msk (3UL << WHAL_STM32WBA_RCC_CCIPR2_RNGSEL_Pos) + /* * @brief System clock source selection (RCC_CFGR1.SW). */ @@ -98,67 +145,240 @@ typedef struct { .rdyReg = 0x000, .rdyMsk = (1UL << 17), .rdyPos = 17 /* - * @brief Enable an oscillator (HSI16/HSE32). Blocks until ready. + * @brief Turn on an oscillator (HSI16/HSE32) and wait for its ready bit. + * + * @param clkDev RCC device instance. + * @param cfg Oscillator on/ready bit descriptor. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32wba_Rcc_EnableOsc(whal_Clock *clkDev, - const whal_Stm32wba_Rcc_OscCfg *cfg); +static inline whal_Error whal_Stm32wba_Rcc_EnableOsc( + const whal_Clock *clkDev, const whal_Stm32wba_Rcc_OscCfg *cfg) +{ + size_t rdy; + + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, cfg->onMsk); + do { + whal_Reg_Get(clkDev->base, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + /* - * @brief Disable an oscillator. + * @brief Turn off an oscillator (HSI16/HSE32). + * + * @param clkDev RCC device instance. + * @param cfg Oscillator on/ready bit descriptor. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32wba_Rcc_DisableOsc(whal_Clock *clkDev, - const whal_Stm32wba_Rcc_OscCfg *cfg); +static inline whal_Error whal_Stm32wba_Rcc_DisableOsc( + const whal_Clock *clkDev, const whal_Stm32wba_Rcc_OscCfg *cfg) +{ + whal_Reg_Update(clkDev->base, cfg->onReg, cfg->onMsk, 0); + return WHAL_SUCCESS; +} /* - * @brief Configure and enable PLL1. Caller must have the PLL1 source - * oscillator already enabled. Blocks until PLL1 is ready. + * @brief Configure and enable PLL1, waiting for lock. + * + * Turns PLL1 off (waits for !PLL1RDY), programs PLL1CFGR (SRC/RGE/M plus + * REN enable) and PLL1DIVR (N/P/Q/R), sets PLL1ON, polls PLL1RDY. + * + * @param clkDev RCC device instance. + * @param cfg PLL1 configuration. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32wba_Rcc_EnablePll1(whal_Clock *clkDev, - const whal_Stm32wba_Rcc_Pll1Cfg *cfg); +static inline whal_Error whal_Stm32wba_Rcc_EnablePll1( + const whal_Clock *clkDev, const whal_Stm32wba_Rcc_Pll1Cfg *cfg) +{ + size_t rdy; + + /* Disable PLL1 before reconfiguring; wait until off. */ + whal_Reg_Update(clkDev->base, WHAL_STM32WBA_RCC_CR_REG, + WHAL_STM32WBA_RCC_CR_PLL1ON_Msk, 0); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32WBA_RCC_CR_REG, + WHAL_STM32WBA_RCC_CR_PLL1RDY_Msk, + WHAL_STM32WBA_RCC_CR_PLL1RDY_Pos, &rdy); + } while (rdy); + + whal_Reg_Write(clkDev->base, WHAL_STM32WBA_RCC_PLL1CFGR_REG, + whal_SetBits(WHAL_STM32WBA_RCC_PLL1CFGR_SRC_Msk, + WHAL_STM32WBA_RCC_PLL1CFGR_SRC_Pos, cfg->clkSrc) | + whal_SetBits(WHAL_STM32WBA_RCC_PLL1CFGR_RGE_Msk, + WHAL_STM32WBA_RCC_PLL1CFGR_RGE_Pos, cfg->rge) | + whal_SetBits(WHAL_STM32WBA_RCC_PLL1CFGR_M_Msk, + WHAL_STM32WBA_RCC_PLL1CFGR_M_Pos, cfg->m) | + whal_SetBits(WHAL_STM32WBA_RCC_PLL1CFGR_REN_Msk, + WHAL_STM32WBA_RCC_PLL1CFGR_REN_Pos, 1)); + whal_Reg_Write(clkDev->base, WHAL_STM32WBA_RCC_PLL1DIVR_REG, + whal_SetBits(WHAL_STM32WBA_RCC_PLL1DIVR_N_Msk, + WHAL_STM32WBA_RCC_PLL1DIVR_N_Pos, cfg->n) | + whal_SetBits(WHAL_STM32WBA_RCC_PLL1DIVR_P_Msk, + WHAL_STM32WBA_RCC_PLL1DIVR_P_Pos, cfg->p) | + whal_SetBits(WHAL_STM32WBA_RCC_PLL1DIVR_Q_Msk, + WHAL_STM32WBA_RCC_PLL1DIVR_Q_Pos, cfg->q) | + whal_SetBits(WHAL_STM32WBA_RCC_PLL1DIVR_R_Msk, + WHAL_STM32WBA_RCC_PLL1DIVR_R_Pos, cfg->r)); + + whal_Reg_Update(clkDev->base, WHAL_STM32WBA_RCC_CR_REG, + WHAL_STM32WBA_RCC_CR_PLL1ON_Msk, + WHAL_STM32WBA_RCC_CR_PLL1ON_Msk); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32WBA_RCC_CR_REG, + WHAL_STM32WBA_RCC_CR_PLL1RDY_Msk, + WHAL_STM32WBA_RCC_CR_PLL1RDY_Pos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + /* - * @brief Disable PLL1. + * @brief Turn PLL1 off (clears RCC_CR.PLL1ON). + * + * @param clkDev RCC device instance. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32wba_Rcc_DisablePll1(whal_Clock *clkDev); +static inline whal_Error whal_Stm32wba_Rcc_DisablePll1(const whal_Clock *clkDev) +{ + whal_Reg_Update(clkDev->base, WHAL_STM32WBA_RCC_CR_REG, + WHAL_STM32WBA_RCC_CR_PLL1ON_Msk, 0); + return WHAL_SUCCESS; +} /* - * @brief Enable LSI1 oscillator (required by IWDG). Blocks until ready. + * @brief Enable LSI1 (32 kHz internal RC) and wait for ready. + * + * Sets BDCR1.LSI1ON and polls BDCR1.LSI1RDY. + * + * @param clkDev RCC device instance. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32wba_Rcc_EnableLsi(whal_Clock *clkDev); +static inline whal_Error whal_Stm32wba_Rcc_EnableLsi(const whal_Clock *clkDev) +{ + size_t rdy; + + whal_Reg_Update(clkDev->base, WHAL_STM32WBA_RCC_BDCR1_REG, + WHAL_STM32WBA_RCC_BDCR1_LSI1ON_Msk, + WHAL_STM32WBA_RCC_BDCR1_LSI1ON_Msk); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32WBA_RCC_BDCR1_REG, + WHAL_STM32WBA_RCC_BDCR1_LSI1RDY_Msk, + WHAL_STM32WBA_RCC_BDCR1_LSI1RDY_Pos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + /* - * @brief Disable LSI1. + * @brief Disable LSI1 (clears BDCR1.LSI1ON). + * + * @param clkDev RCC device instance. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32wba_Rcc_DisableLsi(whal_Clock *clkDev); +static inline whal_Error whal_Stm32wba_Rcc_DisableLsi(const whal_Clock *clkDev) +{ + whal_Reg_Update(clkDev->base, WHAL_STM32WBA_RCC_BDCR1_REG, + WHAL_STM32WBA_RCC_BDCR1_LSI1ON_Msk, 0); + return WHAL_SUCCESS; +} /* - * @brief Switch SYSCLK to the given source. Blocks until SWS confirms. + * @brief Switch SYSCLK to the requested source and wait for the switch. + * + * @param clkDev RCC device instance. + * @param src System clock source. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32wba_Rcc_SetSysClock(whal_Clock *clkDev, - whal_Stm32wba_Rcc_SysClockSrc src); +static inline whal_Error whal_Stm32wba_Rcc_SetSysClock( + const whal_Clock *clkDev, whal_Stm32wba_Rcc_SysClockSrc src) +{ + size_t sws; + + whal_Reg_Update(clkDev->base, WHAL_STM32WBA_RCC_CFGR1_REG, + WHAL_STM32WBA_RCC_CFGR1_SW_Msk, + whal_SetBits(WHAL_STM32WBA_RCC_CFGR1_SW_Msk, + WHAL_STM32WBA_RCC_CFGR1_SW_Pos, src)); + do { + whal_Reg_Get(clkDev->base, WHAL_STM32WBA_RCC_CFGR1_REG, + WHAL_STM32WBA_RCC_CFGR1_SWS_Msk, + WHAL_STM32WBA_RCC_CFGR1_SWS_Pos, &sws); + } while (sws != (size_t)src); + return WHAL_SUCCESS; +} /* * @brief Select the RNG kernel clock source (RCC_CCIPR2.RNGSEL). + * + * @param clkDev RCC device instance. + * @param src RNG kernel clock source. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32wba_Rcc_SetRngClockSrc(whal_Clock *clkDev, - whal_Stm32wba_Rcc_RngSrc src); +static inline whal_Error whal_Stm32wba_Rcc_SetRngClockSrc( + const whal_Clock *clkDev, whal_Stm32wba_Rcc_RngSrc src) +{ + whal_Reg_Update(clkDev->base, WHAL_STM32WBA_RCC_CCIPR2_REG, + WHAL_STM32WBA_RCC_CCIPR2_RNGSEL_Msk, + whal_SetBits(WHAL_STM32WBA_RCC_CCIPR2_RNGSEL_Msk, + WHAL_STM32WBA_RCC_CCIPR2_RNGSEL_Pos, + src)); + return WHAL_SUCCESS; +} /* - * @brief Set the HPRE5 prescaler for the AHB5 domain (max 32 MHz). - * 0xx: not divided - * 100: div 2 - * 101: div 4 - * 110: div 8 - * 111: div 16 + * @brief Program the AHB5 domain prescaler (RCC_CFGR4.HPRE5). + * + * @param clkDev RCC device instance. + * @param hpre5 HPRE5 encoded divider value. + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32wba_Rcc_SetHpre5(whal_Clock *clkDev, uint8_t hpre5); +static inline whal_Error whal_Stm32wba_Rcc_SetHpre5( + const whal_Clock *clkDev, uint8_t hpre5) +{ + whal_Reg_Update(clkDev->base, WHAL_STM32WBA_RCC_CFGR4_REG, + WHAL_STM32WBA_RCC_CFGR4_HPRE5_Msk, + whal_SetBits(WHAL_STM32WBA_RCC_CFGR4_HPRE5_Msk, + WHAL_STM32WBA_RCC_CFGR4_HPRE5_Pos, hpre5)); + return WHAL_SUCCESS; +} /* - * @brief Enable a peripheral clock. + * @brief Set the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32wba_Rcc_EnablePeriphClk(whal_Clock *clkDev, - const whal_Stm32wba_Rcc_PeriphClk *clk); +static inline whal_Error whal_Stm32wba_Rcc_EnablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32wba_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); + return WHAL_SUCCESS; +} + /* - * @brief Disable a peripheral clock. + * @brief Clear the enable bit for a peripheral clock gate. + * + * @param clkDev RCC device instance. + * @param clk Peripheral clock descriptor (RCC *ENR register + bit). + * + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Stm32wba_Rcc_DisablePeriphClk(whal_Clock *clkDev, - const whal_Stm32wba_Rcc_PeriphClk *clk); +static inline whal_Error whal_Stm32wba_Rcc_DisablePeriphClk( + const whal_Clock *clkDev, const whal_Stm32wba_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(clkDev->base, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); + return WHAL_SUCCESS; +} #endif /* WHAL_STM32WBA_RCC_H */ diff --git a/wolfHAL/crypto/crypto.h b/wolfHAL/crypto/crypto.h index 34e0de1..775c813 100644 --- a/wolfHAL/crypto/crypto.h +++ b/wolfHAL/crypto/crypto.h @@ -17,6 +17,9 @@ /* ---- Common enums ---- */ +/** + * @brief Direction (encrypt or decrypt) for symmetric ciphers. + */ typedef enum { WHAL_CRYPTO_ENCRYPT, WHAL_CRYPTO_DECRYPT, @@ -63,6 +66,9 @@ whal_Error whal_Crypto_Deinit(whal_Crypto *dev); typedef struct whal_AesEcb whal_AesEcb; +/** + * @brief Driver vtable for AES-ECB. + */ typedef struct { whal_Error (*Oneshot)(whal_AesEcb *dev, whal_Crypto_Dir dir, const void *key, size_t keySz, @@ -73,16 +79,46 @@ typedef struct { const void *in, void *out, size_t sz); } whal_AesEcbDriver; +/** + * @brief AES-ECB device instance. + */ struct whal_AesEcb { whal_Crypto *crypto; const whal_AesEcbDriver *driver; }; +/** + * @brief AES-ECB one-shot encrypt or decrypt. + * + * @param dev AES-ECB device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes. + * @param in Input data (multiple of 16 bytes). + * @param out Output buffer. + * @param sz Data size in bytes. + */ whal_Error whal_AesEcb_Oneshot(whal_AesEcb *dev, whal_Crypto_Dir dir, const void *key, size_t keySz, const void *in, void *out, size_t sz); +/** + * @brief Start an AES-ECB streaming session (load key). + * + * @param dev AES-ECB device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes. + */ whal_Error whal_AesEcb_Start(whal_AesEcb *dev, whal_Crypto_Dir dir, const void *key, size_t keySz); +/** + * @brief Process data through an active AES-ECB session. + * + * @param dev AES-ECB device instance. + * @param in Input data (multiple of 16 bytes). + * @param out Output buffer. + * @param sz Data size in bytes. + */ whal_Error whal_AesEcb_Process(whal_AesEcb *dev, const void *in, void *out, size_t sz); @@ -90,6 +126,9 @@ whal_Error whal_AesEcb_Process(whal_AesEcb *dev, typedef struct whal_AesCbc whal_AesCbc; +/** + * @brief Driver vtable for AES-CBC. + */ typedef struct { whal_Error (*Oneshot)(whal_AesCbc *dev, whal_Crypto_Dir dir, const void *key, size_t keySz, @@ -102,18 +141,50 @@ typedef struct { const void *in, void *out, size_t sz); } whal_AesCbcDriver; +/** + * @brief AES-CBC device instance. + */ struct whal_AesCbc { whal_Crypto *crypto; const whal_AesCbcDriver *driver; }; +/** + * @brief AES-CBC one-shot encrypt or decrypt. + * + * @param dev AES-CBC device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes. + * @param iv Initialization vector (16 bytes). + * @param in Input data (multiple of 16 bytes). + * @param out Output buffer. + * @param sz Data size in bytes. + */ whal_Error whal_AesCbc_Oneshot(whal_AesCbc *dev, whal_Crypto_Dir dir, const void *key, size_t keySz, const void *iv, const void *in, void *out, size_t sz); +/** + * @brief Start an AES-CBC streaming session (load key and IV). + * + * @param dev AES-CBC device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes. + * @param iv Initialization vector (16 bytes). + */ whal_Error whal_AesCbc_Start(whal_AesCbc *dev, whal_Crypto_Dir dir, const void *key, size_t keySz, const void *iv); +/** + * @brief Process data through an active AES-CBC session. + * + * @param dev AES-CBC device instance. + * @param in Input data (multiple of 16 bytes). + * @param out Output buffer. + * @param sz Data size in bytes. + */ whal_Error whal_AesCbc_Process(whal_AesCbc *dev, const void *in, void *out, size_t sz); @@ -121,6 +192,9 @@ whal_Error whal_AesCbc_Process(whal_AesCbc *dev, typedef struct whal_AesCtr whal_AesCtr; +/** + * @brief Driver vtable for AES-CTR. + */ typedef struct { whal_Error (*Oneshot)(whal_AesCtr *dev, whal_Crypto_Dir dir, const void *key, size_t keySz, @@ -133,18 +207,50 @@ typedef struct { const void *in, void *out, size_t sz); } whal_AesCtrDriver; +/** + * @brief AES-CTR device instance. + */ struct whal_AesCtr { whal_Crypto *crypto; const whal_AesCtrDriver *driver; }; +/** + * @brief AES-CTR one-shot encrypt or decrypt. + * + * @param dev AES-CTR device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes. + * @param iv Initial counter block (16 bytes). + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. + */ whal_Error whal_AesCtr_Oneshot(whal_AesCtr *dev, whal_Crypto_Dir dir, const void *key, size_t keySz, const void *iv, const void *in, void *out, size_t sz); +/** + * @brief Start an AES-CTR streaming session (load key and counter). + * + * @param dev AES-CTR device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes. + * @param iv Initial counter block (16 bytes). + */ whal_Error whal_AesCtr_Start(whal_AesCtr *dev, whal_Crypto_Dir dir, const void *key, size_t keySz, const void *iv); +/** + * @brief Process data through an active AES-CTR session. + * + * @param dev AES-CTR device instance. + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. + */ whal_Error whal_AesCtr_Process(whal_AesCtr *dev, const void *in, void *out, size_t sz); @@ -152,6 +258,9 @@ whal_Error whal_AesCtr_Process(whal_AesCtr *dev, typedef struct whal_AesGcm whal_AesGcm; +/** + * @brief Driver vtable for AES-GCM. + */ typedef struct { whal_Error (*Oneshot)(whal_AesGcm *dev, whal_Crypto_Dir dir, const void *key, size_t keySz, @@ -169,24 +278,72 @@ typedef struct { void *tag, size_t tagSz); } whal_AesGcmDriver; +/** + * @brief AES-GCM device instance. The @c state pointer holds driver-specific + * streaming scratch (AAD/data lengths for GHASH final phase). + */ struct whal_AesGcm { whal_Crypto *crypto; const whal_AesGcmDriver *driver; void *state; }; +/** + * @brief AES-GCM one-shot authenticated encrypt or decrypt. + * + * @param dev AES-GCM device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes. + * @param iv Initialization vector. + * @param ivSz IV size in bytes (typically 12). + * @param aad Additional authenticated data. + * @param aadSz AAD size in bytes. + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. + * @param tag Authentication tag output. + * @param tagSz Tag size in bytes (up to 16). + */ whal_Error whal_AesGcm_Oneshot(whal_AesGcm *dev, whal_Crypto_Dir dir, const void *key, size_t keySz, const void *iv, size_t ivSz, const void *aad, size_t aadSz, const void *in, void *out, size_t sz, void *tag, size_t tagSz); +/** + * @brief Start an AES-GCM streaming session (init + header phases). + * + * @param dev AES-GCM device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes. + * @param iv Initialization vector. + * @param ivSz IV size in bytes (typically 12). + * @param aad Additional authenticated data. + * @param aadSz AAD size in bytes. + */ whal_Error whal_AesGcm_Start(whal_AesGcm *dev, whal_Crypto_Dir dir, const void *key, size_t keySz, const void *iv, size_t ivSz, const void *aad, size_t aadSz); +/** + * @brief Process payload data through an active AES-GCM session. + * + * @param dev AES-GCM device instance. + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. + */ whal_Error whal_AesGcm_Process(whal_AesGcm *dev, const void *in, void *out, size_t sz); +/** + * @brief Finalize an AES-GCM session and produce the authentication tag. + * + * @param dev AES-GCM device instance. + * @param tag Authentication tag output. + * @param tagSz Tag size in bytes (up to 16). + */ whal_Error whal_AesGcm_Finalize(whal_AesGcm *dev, void *tag, size_t tagSz); @@ -194,6 +351,9 @@ whal_Error whal_AesGcm_Finalize(whal_AesGcm *dev, typedef struct whal_AesGmac whal_AesGmac; +/** + * @brief Driver vtable for AES-GMAC (authentication only, no payload). + */ typedef struct { whal_Error (*Oneshot)(whal_AesGmac *dev, const void *key, size_t keySz, @@ -202,11 +362,27 @@ typedef struct { void *tag, size_t tagSz); } whal_AesGmacDriver; +/** + * @brief AES-GMAC device instance. + */ struct whal_AesGmac { whal_Crypto *crypto; const whal_AesGmacDriver *driver; }; +/** + * @brief AES-GMAC one-shot authentication (no payload). + * + * @param dev AES-GMAC device instance. + * @param key Key buffer. + * @param keySz Key size in bytes. + * @param iv Initialization vector. + * @param ivSz IV size in bytes (typically 12). + * @param aad Authenticated data. + * @param aadSz Data size in bytes. + * @param tag Authentication tag output. + * @param tagSz Tag size in bytes (up to 16). + */ whal_Error whal_AesGmac_Oneshot(whal_AesGmac *dev, const void *key, size_t keySz, const void *iv, size_t ivSz, @@ -217,6 +393,9 @@ whal_Error whal_AesGmac_Oneshot(whal_AesGmac *dev, typedef struct whal_AesCcm whal_AesCcm; +/** + * @brief Driver vtable for AES-CCM. + */ typedef struct { whal_Error (*Oneshot)(whal_AesCcm *dev, whal_Crypto_Dir dir, const void *key, size_t keySz, @@ -235,25 +414,75 @@ typedef struct { void *tag, size_t tagSz); } whal_AesCcmDriver; +/** + * @brief AES-CCM device instance. The @c state pointer holds driver-specific + * streaming scratch (AAD/data lengths for final-phase tag). + */ struct whal_AesCcm { whal_Crypto *crypto; const whal_AesCcmDriver *driver; void *state; }; +/** + * @brief AES-CCM one-shot authenticated encrypt or decrypt. + * + * @param dev AES-CCM device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes. + * @param nonce Nonce buffer. + * @param nonceSz Nonce size in bytes (7-13). + * @param aad Additional authenticated data. + * @param aadSz AAD size in bytes. + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. + * @param tag Authentication tag output. + * @param tagSz Tag size in bytes (4, 6, 8, 10, 12, 14, or 16). + */ whal_Error whal_AesCcm_Oneshot(whal_AesCcm *dev, whal_Crypto_Dir dir, const void *key, size_t keySz, const void *nonce, size_t nonceSz, const void *aad, size_t aadSz, const void *in, void *out, size_t sz, void *tag, size_t tagSz); +/** + * @brief Start an AES-CCM streaming session (init + header phases). + * + * @param dev AES-CCM device instance. + * @param dir Encrypt or decrypt. + * @param key Key buffer. + * @param keySz Key size in bytes. + * @param nonce Nonce buffer. + * @param nonceSz Nonce size in bytes (7-13). + * @param aad Additional authenticated data. + * @param aadSz AAD size in bytes. + * @param tagSz Tag size (needed for B0 block construction). + * @param sz Total payload size (needed for B0 block construction). + */ whal_Error whal_AesCcm_Start(whal_AesCcm *dev, whal_Crypto_Dir dir, const void *key, size_t keySz, const void *nonce, size_t nonceSz, const void *aad, size_t aadSz, size_t tagSz, size_t sz); +/** + * @brief Process payload data through an active AES-CCM session. + * + * @param dev AES-CCM device instance. + * @param in Input data. + * @param out Output buffer. + * @param sz Data size in bytes. + */ whal_Error whal_AesCcm_Process(whal_AesCcm *dev, const void *in, void *out, size_t sz); +/** + * @brief Finalize an AES-CCM session and produce the authentication tag. + * + * @param dev AES-CCM device instance. + * @param tag Authentication tag output. + * @param tagSz Tag size in bytes. + */ whal_Error whal_AesCcm_Finalize(whal_AesCcm *dev, void *tag, size_t tagSz); @@ -261,6 +490,9 @@ whal_Error whal_AesCcm_Finalize(whal_AesCcm *dev, typedef struct whal_Sha1 whal_Sha1; +/** + * @brief Driver vtable for SHA-1. + */ typedef struct { whal_Error (*Oneshot)(whal_Sha1 *dev, const void *in, size_t inSz, @@ -270,22 +502,56 @@ typedef struct { whal_Error (*Finalize)(whal_Sha1 *dev, void *digest, size_t digestSz); } whal_Sha1Driver; +/** + * @brief SHA-1 device instance. + */ struct whal_Sha1 { whal_Crypto *crypto; const whal_Sha1Driver *driver; }; +/** + * @brief SHA-1 one-shot hash. + * + * @param dev SHA-1 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + * @param digest Output buffer. + * @param digestSz Output buffer size (must be >= 20). + */ whal_Error whal_Sha1_Oneshot(whal_Sha1 *dev, const void *in, size_t inSz, void *digest, size_t digestSz); +/** + * @brief Start a SHA-1 streaming session. + * + * @param dev SHA-1 device instance. + */ whal_Error whal_Sha1_Start(whal_Sha1 *dev); +/** + * @brief Process a chunk of data into an active SHA-1 session. + * + * @param dev SHA-1 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + */ whal_Error whal_Sha1_Process(whal_Sha1 *dev, const void *in, size_t inSz); +/** + * @brief Finalize a SHA-1 session and emit the digest. + * + * @param dev SHA-1 device instance. + * @param digest Output buffer. + * @param digestSz Output buffer size (must be >= 20). + */ whal_Error whal_Sha1_Finalize(whal_Sha1 *dev, void *digest, size_t digestSz); /* SHA-224 */ typedef struct whal_Sha224 whal_Sha224; +/** + * @brief Driver vtable for SHA-224. + */ typedef struct { whal_Error (*Oneshot)(whal_Sha224 *dev, const void *in, size_t inSz, @@ -295,16 +561,47 @@ typedef struct { whal_Error (*Finalize)(whal_Sha224 *dev, void *digest, size_t digestSz); } whal_Sha224Driver; +/** + * @brief SHA-224 device instance. + */ struct whal_Sha224 { whal_Crypto *crypto; const whal_Sha224Driver *driver; }; +/** + * @brief SHA-224 one-shot hash. + * + * @param dev SHA-224 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + * @param digest Output buffer. + * @param digestSz Output buffer size (must be >= 28). + */ whal_Error whal_Sha224_Oneshot(whal_Sha224 *dev, const void *in, size_t inSz, void *digest, size_t digestSz); +/** + * @brief Start a SHA-224 streaming session. + * + * @param dev SHA-224 device instance. + */ whal_Error whal_Sha224_Start(whal_Sha224 *dev); +/** + * @brief Process a chunk of data into an active SHA-224 session. + * + * @param dev SHA-224 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + */ whal_Error whal_Sha224_Process(whal_Sha224 *dev, const void *in, size_t inSz); +/** + * @brief Finalize a SHA-224 session and emit the digest. + * + * @param dev SHA-224 device instance. + * @param digest Output buffer. + * @param digestSz Output buffer size (must be >= 28). + */ whal_Error whal_Sha224_Finalize(whal_Sha224 *dev, void *digest, size_t digestSz); @@ -312,6 +609,9 @@ whal_Error whal_Sha224_Finalize(whal_Sha224 *dev, typedef struct whal_Sha256 whal_Sha256; +/** + * @brief Driver vtable for SHA-256. + */ typedef struct { whal_Error (*Oneshot)(whal_Sha256 *dev, const void *in, size_t inSz, @@ -321,16 +621,47 @@ typedef struct { whal_Error (*Finalize)(whal_Sha256 *dev, void *digest, size_t digestSz); } whal_Sha256Driver; +/** + * @brief SHA-256 device instance. + */ struct whal_Sha256 { whal_Crypto *crypto; const whal_Sha256Driver *driver; }; +/** + * @brief SHA-256 one-shot hash. + * + * @param dev SHA-256 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + * @param digest Output buffer. + * @param digestSz Output buffer size (must be >= 32). + */ whal_Error whal_Sha256_Oneshot(whal_Sha256 *dev, const void *in, size_t inSz, void *digest, size_t digestSz); +/** + * @brief Start a SHA-256 streaming session. + * + * @param dev SHA-256 device instance. + */ whal_Error whal_Sha256_Start(whal_Sha256 *dev); +/** + * @brief Process a chunk of data into an active SHA-256 session. + * + * @param dev SHA-256 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + */ whal_Error whal_Sha256_Process(whal_Sha256 *dev, const void *in, size_t inSz); +/** + * @brief Finalize a SHA-256 session and emit the digest. + * + * @param dev SHA-256 device instance. + * @param digest Output buffer. + * @param digestSz Output buffer size (must be >= 32). + */ whal_Error whal_Sha256_Finalize(whal_Sha256 *dev, void *digest, size_t digestSz); @@ -338,6 +669,9 @@ whal_Error whal_Sha256_Finalize(whal_Sha256 *dev, typedef struct whal_HmacSha1 whal_HmacSha1; +/** + * @brief Driver vtable for HMAC-SHA-1. + */ typedef struct { whal_Error (*Oneshot)(whal_HmacSha1 *dev, const void *key, size_t keySz, @@ -351,20 +685,56 @@ typedef struct { void *digest, size_t digestSz); } whal_HmacSha1Driver; +/** + * @brief HMAC-SHA-1 device instance. The @c state pointer holds driver-specific + * streaming scratch. + */ struct whal_HmacSha1 { whal_Crypto *crypto; const whal_HmacSha1Driver *driver; void *state; }; +/** + * @brief HMAC-SHA-1 one-shot MAC. + * + * @param dev HMAC-SHA-1 device instance. + * @param key Key buffer. + * @param keySz Key size in bytes. + * @param in Input data. + * @param inSz Input size in bytes. + * @param digest Output MAC buffer. + * @param digestSz Output buffer size (must be >= 20). + */ whal_Error whal_HmacSha1_Oneshot(whal_HmacSha1 *dev, const void *key, size_t keySz, const void *in, size_t inSz, void *digest, size_t digestSz); +/** + * @brief Start an HMAC-SHA-1 streaming session (load key). + * + * @param dev HMAC-SHA-1 device instance. + * @param key Key buffer. + * @param keySz Key size in bytes. + */ whal_Error whal_HmacSha1_Start(whal_HmacSha1 *dev, const void *key, size_t keySz); +/** + * @brief Process a chunk of data into an active HMAC-SHA-1 session. + * + * @param dev HMAC-SHA-1 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + */ whal_Error whal_HmacSha1_Process(whal_HmacSha1 *dev, const void *in, size_t inSz); +/** + * @brief Finalize an HMAC-SHA-1 session and emit the MAC. + * + * @param dev HMAC-SHA-1 device instance. + * @param digest Output MAC buffer. + * @param digestSz Output buffer size (must be >= 20). + */ whal_Error whal_HmacSha1_Finalize(whal_HmacSha1 *dev, void *digest, size_t digestSz); @@ -372,6 +742,9 @@ whal_Error whal_HmacSha1_Finalize(whal_HmacSha1 *dev, typedef struct whal_HmacSha224 whal_HmacSha224; +/** + * @brief Driver vtable for HMAC-SHA-224. + */ typedef struct { whal_Error (*Oneshot)(whal_HmacSha224 *dev, const void *key, size_t keySz, @@ -385,20 +758,56 @@ typedef struct { void *digest, size_t digestSz); } whal_HmacSha224Driver; +/** + * @brief HMAC-SHA-224 device instance. The @c state pointer holds + * driver-specific streaming scratch. + */ struct whal_HmacSha224 { whal_Crypto *crypto; const whal_HmacSha224Driver *driver; void *state; }; +/** + * @brief HMAC-SHA-224 one-shot MAC. + * + * @param dev HMAC-SHA-224 device instance. + * @param key Key buffer. + * @param keySz Key size in bytes. + * @param in Input data. + * @param inSz Input size in bytes. + * @param digest Output MAC buffer. + * @param digestSz Output buffer size (must be >= 28). + */ whal_Error whal_HmacSha224_Oneshot(whal_HmacSha224 *dev, const void *key, size_t keySz, const void *in, size_t inSz, void *digest, size_t digestSz); +/** + * @brief Start an HMAC-SHA-224 streaming session (load key). + * + * @param dev HMAC-SHA-224 device instance. + * @param key Key buffer. + * @param keySz Key size in bytes. + */ whal_Error whal_HmacSha224_Start(whal_HmacSha224 *dev, const void *key, size_t keySz); +/** + * @brief Process a chunk of data into an active HMAC-SHA-224 session. + * + * @param dev HMAC-SHA-224 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + */ whal_Error whal_HmacSha224_Process(whal_HmacSha224 *dev, const void *in, size_t inSz); +/** + * @brief Finalize an HMAC-SHA-224 session and emit the MAC. + * + * @param dev HMAC-SHA-224 device instance. + * @param digest Output MAC buffer. + * @param digestSz Output buffer size (must be >= 28). + */ whal_Error whal_HmacSha224_Finalize(whal_HmacSha224 *dev, void *digest, size_t digestSz); @@ -406,6 +815,9 @@ whal_Error whal_HmacSha224_Finalize(whal_HmacSha224 *dev, typedef struct whal_HmacSha256 whal_HmacSha256; +/** + * @brief Driver vtable for HMAC-SHA-256. + */ typedef struct { whal_Error (*Oneshot)(whal_HmacSha256 *dev, const void *key, size_t keySz, @@ -419,20 +831,56 @@ typedef struct { void *digest, size_t digestSz); } whal_HmacSha256Driver; +/** + * @brief HMAC-SHA-256 device instance. The @c state pointer holds + * driver-specific streaming scratch. + */ struct whal_HmacSha256 { whal_Crypto *crypto; const whal_HmacSha256Driver *driver; void *state; }; +/** + * @brief HMAC-SHA-256 one-shot MAC. + * + * @param dev HMAC-SHA-256 device instance. + * @param key Key buffer. + * @param keySz Key size in bytes. + * @param in Input data. + * @param inSz Input size in bytes. + * @param digest Output MAC buffer. + * @param digestSz Output buffer size (must be >= 32). + */ whal_Error whal_HmacSha256_Oneshot(whal_HmacSha256 *dev, const void *key, size_t keySz, const void *in, size_t inSz, void *digest, size_t digestSz); +/** + * @brief Start an HMAC-SHA-256 streaming session (load key). + * + * @param dev HMAC-SHA-256 device instance. + * @param key Key buffer. + * @param keySz Key size in bytes. + */ whal_Error whal_HmacSha256_Start(whal_HmacSha256 *dev, const void *key, size_t keySz); +/** + * @brief Process a chunk of data into an active HMAC-SHA-256 session. + * + * @param dev HMAC-SHA-256 device instance. + * @param in Input data. + * @param inSz Input size in bytes. + */ whal_Error whal_HmacSha256_Process(whal_HmacSha256 *dev, const void *in, size_t inSz); +/** + * @brief Finalize an HMAC-SHA-256 session and emit the MAC. + * + * @param dev HMAC-SHA-256 device instance. + * @param digest Output MAC buffer. + * @param digestSz Output buffer size (must be >= 32). + */ whal_Error whal_HmacSha256_Finalize(whal_HmacSha256 *dev, void *digest, size_t digestSz); diff --git a/wolfHAL/crypto/stm32n6_hash.h b/wolfHAL/crypto/stm32n6_hash.h index 4f4dc05..a328a28 100644 --- a/wolfHAL/crypto/stm32n6_hash.h +++ b/wolfHAL/crypto/stm32n6_hash.h @@ -18,6 +18,14 @@ typedef whal_Stm32wba_HmacSha1_State whal_Stm32n6_HmacSha1_State; typedef whal_Stm32wba_HmacSha224_State whal_Stm32n6_HmacSha224_State; typedef whal_Stm32wba_HmacSha256_State whal_Stm32n6_HmacSha256_State; +#define whal_Stm32n6_Hash_Dev whal_Stm32wba_Hash_Dev +#define whal_Stm32n6_Sha1_Dev whal_Stm32wba_Sha1_Dev +#define whal_Stm32n6_Sha224_Dev whal_Stm32wba_Sha224_Dev +#define whal_Stm32n6_Sha256_Dev whal_Stm32wba_Sha256_Dev +#define whal_Stm32n6_HmacSha1_Dev whal_Stm32wba_HmacSha1_Dev +#define whal_Stm32n6_HmacSha224_Dev whal_Stm32wba_HmacSha224_Dev +#define whal_Stm32n6_HmacSha256_Dev whal_Stm32wba_HmacSha256_Dev + #define whal_Stm32n6_Hash_CryptoDriver whal_Stm32wba_Hash_CryptoDriver #define whal_Stm32n6_Hash_Sha1Driver whal_Stm32wba_Hash_Sha1Driver diff --git a/wolfHAL/crypto/stm32wba_aes.h b/wolfHAL/crypto/stm32wba_aes.h index a0a78aa..3943ce2 100644 --- a/wolfHAL/crypto/stm32wba_aes.h +++ b/wolfHAL/crypto/stm32wba_aes.h @@ -17,6 +17,14 @@ typedef whal_Stm32wb_Aes_Cfg whal_Stm32wba_Aes_Cfg; typedef whal_Stm32wb_AesGcm_State whal_Stm32wba_AesGcm_State; typedef whal_Stm32wb_AesCcm_State whal_Stm32wba_AesCcm_State; +#define whal_Stm32wba_Aes_Dev whal_Stm32wb_Aes_Dev +#define whal_Stm32wba_AesEcb_Dev whal_Stm32wb_AesEcb_Dev +#define whal_Stm32wba_AesCbc_Dev whal_Stm32wb_AesCbc_Dev +#define whal_Stm32wba_AesCtr_Dev whal_Stm32wb_AesCtr_Dev +#define whal_Stm32wba_AesGcm_Dev whal_Stm32wb_AesGcm_Dev +#define whal_Stm32wba_AesGmac_Dev whal_Stm32wb_AesGmac_Dev +#define whal_Stm32wba_AesCcm_Dev whal_Stm32wb_AesCcm_Dev + #define whal_Stm32wba_Aes_CryptoDriver whal_Stm32wb_Aes_CryptoDriver #define whal_Stm32wba_Aes_EcbDriver whal_Stm32wb_Aes_EcbDriver diff --git a/wolfHAL/flash/stm32f3_flash.h b/wolfHAL/flash/stm32f3_flash.h index d76ff59..1ec35ac 100644 --- a/wolfHAL/flash/stm32f3_flash.h +++ b/wolfHAL/flash/stm32f3_flash.h @@ -14,6 +14,8 @@ typedef whal_Stm32f0_Flash_Cfg whal_Stm32f3_Flash_Cfg; +#define whal_Stm32f3_Flash_Dev whal_Stm32f0_Flash_Dev + #define WHAL_STM32F3_FLASH_LATENCY_0 WHAL_STM32F0_FLASH_LATENCY_0 #define WHAL_STM32F3_FLASH_LATENCY_1 WHAL_STM32F0_FLASH_LATENCY_1 #define WHAL_STM32F3_FLASH_LATENCY_2 2 diff --git a/wolfHAL/platform/arm/cortex_m0.h b/wolfHAL/platform/arm/cortex_m0.h index fefd652..c1f85cf 100644 --- a/wolfHAL/platform/arm/cortex_m0.h +++ b/wolfHAL/platform/arm/cortex_m0.h @@ -3,6 +3,14 @@ #include +/* + * @file cortex_m0.h + * @brief ARM Cortex-M0 core platform constants. + * + * Exposes the SysTick base address and driver pointer used by boards built + * on the Cortex-M0 core. Pulled in by chip-specific platform headers. + */ + #define WHAL_CORTEX_M0_SYSTICK_BASE 0xE000E010 #define WHAL_CORTEX_M0_SYSTICK_DRIVER &whal_SysTick_Driver diff --git a/wolfHAL/platform/arm/cortex_m0plus.h b/wolfHAL/platform/arm/cortex_m0plus.h index 784ac8b..c0ec27c 100644 --- a/wolfHAL/platform/arm/cortex_m0plus.h +++ b/wolfHAL/platform/arm/cortex_m0plus.h @@ -3,6 +3,14 @@ #include +/* + * @file cortex_m0plus.h + * @brief ARM Cortex-M0+ core platform constants. + * + * Exposes the SysTick base address and driver pointer used by boards built + * on the Cortex-M0+ core. Pulled in by chip-specific platform headers. + */ + #define WHAL_CORTEX_M0PLUS_SYSTICK_BASE 0xE000E010 #define WHAL_CORTEX_M0PLUS_SYSTICK_DRIVER &whal_SysTick_Driver diff --git a/wolfHAL/platform/arm/cortex_m3.h b/wolfHAL/platform/arm/cortex_m3.h index 020edbc..9140142 100644 --- a/wolfHAL/platform/arm/cortex_m3.h +++ b/wolfHAL/platform/arm/cortex_m3.h @@ -4,6 +4,14 @@ #include #include +/* + * @file cortex_m3.h + * @brief ARM Cortex-M3 core platform constants. + * + * Exposes SysTick and NVIC base addresses and driver pointers for boards + * built on the Cortex-M3 core. Pulled in by chip-specific platform headers. + */ + #define WHAL_CORTEX_M3_SYSTICK_BASE 0xE000E010 #define WHAL_CORTEX_M3_SYSTICK_DRIVER &whal_SysTick_Driver diff --git a/wolfHAL/platform/arm/cortex_m33.h b/wolfHAL/platform/arm/cortex_m33.h index 4f854a2..8719026 100644 --- a/wolfHAL/platform/arm/cortex_m33.h +++ b/wolfHAL/platform/arm/cortex_m33.h @@ -4,6 +4,14 @@ #include #include +/* + * @file cortex_m33.h + * @brief ARM Cortex-M33 core platform constants. + * + * Exposes SysTick and NVIC base addresses and driver pointers for boards + * built on the Cortex-M33 core. Pulled in by chip-specific platform headers. + */ + #define WHAL_CORTEX_M33_SYSTICK_BASE 0xE000E010 #define WHAL_CORTEX_M33_SYSTICK_DRIVER &whal_SysTick_Driver diff --git a/wolfHAL/platform/arm/cortex_m4.h b/wolfHAL/platform/arm/cortex_m4.h index e6b9cd0..74dfddf 100644 --- a/wolfHAL/platform/arm/cortex_m4.h +++ b/wolfHAL/platform/arm/cortex_m4.h @@ -4,6 +4,14 @@ #include #include +/* + * @file cortex_m4.h + * @brief ARM Cortex-M4 core platform constants. + * + * Exposes SysTick and NVIC base addresses and driver pointers for boards + * built on the Cortex-M4 core. Pulled in by chip-specific platform headers. + */ + #define WHAL_CORTEX_M4_SYSTICK_BASE 0xE000E010 #define WHAL_CORTEX_M4_SYSTICK_DRIVER &whal_SysTick_Driver diff --git a/wolfHAL/platform/arm/cortex_m55.h b/wolfHAL/platform/arm/cortex_m55.h index 091dd0b..a5af9d4 100644 --- a/wolfHAL/platform/arm/cortex_m55.h +++ b/wolfHAL/platform/arm/cortex_m55.h @@ -4,6 +4,14 @@ #include #include +/* + * @file cortex_m55.h + * @brief ARM Cortex-M55 core platform constants. + * + * Exposes SysTick and NVIC base addresses and driver pointers for boards + * built on the Cortex-M55 core. Pulled in by chip-specific platform headers. + */ + #define WHAL_CORTEX_M55_SYSTICK_BASE 0xE000E010 #define WHAL_CORTEX_M55_SYSTICK_DRIVER &whal_SysTick_Driver diff --git a/wolfHAL/platform/arm/cortex_m7.h b/wolfHAL/platform/arm/cortex_m7.h index c94aefc..cdf242f 100644 --- a/wolfHAL/platform/arm/cortex_m7.h +++ b/wolfHAL/platform/arm/cortex_m7.h @@ -3,6 +3,14 @@ #include +/* + * @file cortex_m7.h + * @brief ARM Cortex-M7 core platform constants. + * + * Exposes the SysTick base address and driver pointer used by boards built + * on the Cortex-M7 core. Pulled in by chip-specific platform headers. + */ + #define WHAL_CORTEX_M7_SYSTICK_BASE 0xE000E010 #define WHAL_CORTEX_M7_SYSTICK_DRIVER &whal_SysTick_Driver diff --git a/wolfHAL/platform/microchip/pic32cz.h b/wolfHAL/platform/microchip/pic32cz.h index 9ee6c6e..7d2f365 100644 --- a/wolfHAL/platform/microchip/pic32cz.h +++ b/wolfHAL/platform/microchip/pic32cz.h @@ -8,6 +8,11 @@ #include #include +/* + * @file pic32cz.h + * @brief Convenience initializers for PIC32CZ device instances. + */ + #define WHAL_PIC32CZ_FLASH_BASE 0x44002000 #define WHAL_PIC32CZ_FLASH_DRIVER &whal_Pic32cz_Flash_Driver diff --git a/wolfHAL/power/pic32cz_supc.h b/wolfHAL/power/pic32cz_supc.h index 9ba2660..95573c3 100644 --- a/wolfHAL/power/pic32cz_supc.h +++ b/wolfHAL/power/pic32cz_supc.h @@ -4,6 +4,8 @@ #include #include #include +#include +#include #include /* @@ -15,8 +17,13 @@ * driver — there is no generic whal_Power_* API or vtable. */ +#define WHAL_PIC32CZ_SUPC_VREGCTRL_REG 0x1C +#define WHAL_PIC32CZ_SUPC_VREGCTRL_AVREGEN_Pos 16 +#define WHAL_PIC32CZ_SUPC_VREGCTRL_AVREGEN_Msk (WHAL_BITMASK(3) << WHAL_PIC32CZ_SUPC_VREGCTRL_AVREGEN_Pos) + /* - * @brief Descriptor for one SUPC voltage regulator output (VREGCTRL.AVREGEN). + * @brief Descriptor for one SUPC voltage-regulator output (mask + bit position + * within VREGCTRL.AVREGEN). */ typedef struct whal_Pic32cz_Supc_Supply { size_t enableMask; @@ -24,27 +31,37 @@ typedef struct whal_Pic32cz_Supc_Supply { } whal_Pic32cz_Supc_Supply; /* - * @brief Enable a SUPC voltage regulator output. + * @brief Set a regulator's enable bit in SUPC VREGCTRL.AVREGEN. * * @param powerDev Power device instance. - * @param supply Supply descriptor identifying which regulator output. + * @param supply Descriptor for the regulator output to enable. * - * @retval WHAL_SUCCESS Output enabled. - * @retval WHAL_EINVAL Null pointer. + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Pic32cz_Supc_EnableSupply(whal_Power *powerDev, - const whal_Pic32cz_Supc_Supply *supply); +static inline whal_Error whal_Pic32cz_Supc_EnableSupply( + const whal_Power *powerDev, const whal_Pic32cz_Supc_Supply *supply) +{ + whal_Reg_Update(powerDev->base, WHAL_PIC32CZ_SUPC_VREGCTRL_REG, + supply->enableMask, + whal_SetBits(supply->enableMask, supply->enablePos, 1)); + return WHAL_SUCCESS; +} /* - * @brief Disable a SUPC voltage regulator output. + * @brief Clear a regulator's enable bit in SUPC VREGCTRL.AVREGEN. * * @param powerDev Power device instance. - * @param supply Supply descriptor identifying which regulator output. + * @param supply Descriptor for the regulator output to disable. * - * @retval WHAL_SUCCESS Output disabled. - * @retval WHAL_EINVAL Null pointer. + * @retval WHAL_SUCCESS Always. */ -whal_Error whal_Pic32cz_Supc_DisableSupply(whal_Power *powerDev, - const whal_Pic32cz_Supc_Supply *supply); +static inline whal_Error whal_Pic32cz_Supc_DisableSupply( + const whal_Power *powerDev, const whal_Pic32cz_Supc_Supply *supply) +{ + whal_Reg_Update(powerDev->base, WHAL_PIC32CZ_SUPC_VREGCTRL_REG, + supply->enableMask, + whal_SetBits(supply->enableMask, supply->enablePos, 0)); + return WHAL_SUCCESS; +} #endif /* WHAL_PIC32CZ_SUPC_H */ diff --git a/wolfHAL/power/stm32l1_pwr.h b/wolfHAL/power/stm32l1_pwr.h index 4169023..96a714b 100644 --- a/wolfHAL/power/stm32l1_pwr.h +++ b/wolfHAL/power/stm32l1_pwr.h @@ -2,7 +2,11 @@ #define WHAL_STM32L1_PWR_H #include +#include #include +#include +#include +#include #include /* @@ -22,8 +26,15 @@ * Range 3 (1.2 V): SYSCLK <= 4 MHz, PLL disabled. */ +#define WHAL_STM32L1_PWR_CR_REG 0x00 +#define WHAL_STM32L1_PWR_CR_VOS_Pos 11 +#define WHAL_STM32L1_PWR_CR_VOS_Msk (WHAL_BITMASK(2) << WHAL_STM32L1_PWR_CR_VOS_Pos) +#define WHAL_STM32L1_PWR_CSR_REG 0x04 +#define WHAL_STM32L1_PWR_CSR_VOSF_Pos 4 +#define WHAL_STM32L1_PWR_CSR_VOSF_Msk (1UL << WHAL_STM32L1_PWR_CSR_VOSF_Pos) + /* - * @brief Internal voltage regulator output ranges (PWR_CR.VOS). + * @brief Internal regulator voltage scaling range (PWR_CR.VOS). */ typedef enum { WHAL_STM32L1_PWR_VOS_RANGE_1 = 1, @@ -32,21 +43,37 @@ typedef enum { } whal_Stm32l1_Pwr_VosRange; /* - * @brief Set the voltage regulator output range. Polls PWR_CSR.VOSF - * until voltage scaling completes. The PWR APB1 clock must already - * be enabled (via whal_Stm32l1_Rcc_EnablePeriphClk with - * WHAL_STM32L152_PWR_CLOCK) before calling. + * @brief Switch the regulator to a new VOS range. + * + * Waits for any in-progress VOS transition to finish (PWR_CSR.VOSF == 0), + * writes the new range to PWR_CR.VOS, then waits for VOSF == 0 again. Must + * be called before raising the system clock past the current range's limit. * * @param powerDev Power device instance. - * @param range Desired VOS range (RANGE_1, RANGE_2, or RANGE_3). - * @param timeout Optional timeout for the VOSF poll loop. + * @param range Target VOS range. + * @param timeout Timeout instance (NULL for unbounded wait). * - * @retval WHAL_SUCCESS Voltage scaling settled at the requested range. - * @retval WHAL_EINVAL Null powerDev. - * @retval WHAL_ETIMEOUT VOSF did not clear within the configured timeout. + * @retval WHAL_SUCCESS Range switched and regulator settled. + * @retval WHAL_ETIMEOUT VOSF didn't clear within the timeout. */ -whal_Error whal_Stm32l1_Pwr_SetVosRange(whal_Power *powerDev, - whal_Stm32l1_Pwr_VosRange range, - whal_Timeout *timeout); +static inline whal_Error whal_Stm32l1_Pwr_SetVosRange( + const whal_Power *powerDev, whal_Stm32l1_Pwr_VosRange range, + whal_Timeout *timeout) +{ + whal_Error err; + + err = whal_Reg_ReadPoll(powerDev->base, WHAL_STM32L1_PWR_CSR_REG, + WHAL_STM32L1_PWR_CSR_VOSF_Msk, 0, timeout); + if (err) + return err; + + whal_Reg_Update(powerDev->base, WHAL_STM32L1_PWR_CR_REG, + WHAL_STM32L1_PWR_CR_VOS_Msk, + whal_SetBits(WHAL_STM32L1_PWR_CR_VOS_Msk, + WHAL_STM32L1_PWR_CR_VOS_Pos, range)); + + return whal_Reg_ReadPoll(powerDev->base, WHAL_STM32L1_PWR_CSR_REG, + WHAL_STM32L1_PWR_CSR_VOSF_Msk, 0, timeout); +} #endif /* WHAL_STM32L1_PWR_H */ diff --git a/wolfHAL/rng/stm32n6_rng.h b/wolfHAL/rng/stm32n6_rng.h index cf67ca3..7321fa7 100644 --- a/wolfHAL/rng/stm32n6_rng.h +++ b/wolfHAL/rng/stm32n6_rng.h @@ -14,6 +14,8 @@ typedef whal_Stm32wba_Rng_Cfg whal_Stm32n6_Rng_Cfg; +#define whal_Stm32n6_Rng_Dev whal_Stm32wba_Rng_Dev + #ifndef WHAL_CFG_STM32N6_RNG_DIRECT_API_MAPPING #define whal_Stm32n6_Rng_Driver whal_Stm32wba_Rng_Driver #define whal_Stm32n6_Rng_Init whal_Stm32wba_Rng_Init diff --git a/wolfHAL/sensor/imu/bmi270_config_data.h b/wolfHAL/sensor/imu/bmi270_config_data.h index a1a582e..be94a10 100644 --- a/wolfHAL/sensor/imu/bmi270_config_data.h +++ b/wolfHAL/sensor/imu/bmi270_config_data.h @@ -5,14 +5,23 @@ #include /* - * @brief BMI270 configuration data blob (8192 bytes). + * @file bmi270_config_data.h + * @brief Bosch BMI270 configuration data blob. * - * Extracted from the Bosch Sensortec BMI270_SensorAPI repository - * under BSD-3-Clause license. See src/sensor/imu/bmi270_config_data.c - * for the full license text and data. + * Extracted from the Bosch Sensortec BMI270_SensorAPI repository under + * BSD-3-Clause license. See src/sensor/imu/bmi270_config_data.c for the + * full license text and data. + */ + +/* + * @brief Size in bytes of the BMI270 configuration data blob. */ #define WHAL_BMI270_CONFIG_DATA_SZ 8192 +/* + * @brief BMI270 configuration data blob. Uploaded to the sensor during init + * via the INIT_DATA register. + */ extern const uint8_t whal_bmi270_config_data[WHAL_BMI270_CONFIG_DATA_SZ]; #endif /* WHAL_BMI270_CONFIG_DATA_H */ diff --git a/wolfHAL/watchdog/stm32f0_iwdg.h b/wolfHAL/watchdog/stm32f0_iwdg.h index 7cbbfb3..ebf26f9 100644 --- a/wolfHAL/watchdog/stm32f0_iwdg.h +++ b/wolfHAL/watchdog/stm32f0_iwdg.h @@ -14,6 +14,8 @@ typedef whal_Stm32wb_Iwdg_Cfg whal_Stm32f0_Iwdg_Cfg; +#define whal_Stm32f0_Iwdg_Dev whal_Stm32wb_Iwdg_Dev + #ifndef WHAL_CFG_STM32F0_IWDG_DIRECT_API_MAPPING #define whal_Stm32f0_Iwdg_Driver whal_Stm32wb_Iwdg_Driver #define whal_Stm32f0_Iwdg_Init whal_Stm32wb_Iwdg_Init diff --git a/wolfHAL/watchdog/stm32f3_iwdg.h b/wolfHAL/watchdog/stm32f3_iwdg.h index b119596..7eb1bcb 100644 --- a/wolfHAL/watchdog/stm32f3_iwdg.h +++ b/wolfHAL/watchdog/stm32f3_iwdg.h @@ -12,6 +12,8 @@ typedef whal_Stm32wb_Iwdg_Cfg whal_Stm32f3_Iwdg_Cfg; +#define whal_Stm32f3_Iwdg_Dev whal_Stm32wb_Iwdg_Dev + #ifndef WHAL_CFG_STM32F3_IWDG_DIRECT_API_MAPPING #define whal_Stm32f3_Iwdg_Driver whal_Stm32wb_Iwdg_Driver #define whal_Stm32f3_Iwdg_Init whal_Stm32wb_Iwdg_Init diff --git a/wolfHAL/watchdog/stm32f3_wwdg.h b/wolfHAL/watchdog/stm32f3_wwdg.h index 6fc0c47..0011cdb 100644 --- a/wolfHAL/watchdog/stm32f3_wwdg.h +++ b/wolfHAL/watchdog/stm32f3_wwdg.h @@ -13,6 +13,8 @@ typedef whal_Stm32f0_Wwdg_Cfg whal_Stm32f3_Wwdg_Cfg; +#define whal_Stm32f3_Wwdg_Dev whal_Stm32f0_Wwdg_Dev + #ifndef WHAL_CFG_STM32F3_WWDG_DIRECT_API_MAPPING #define whal_Stm32f3_Wwdg_Driver whal_Stm32f0_Wwdg_Driver #define whal_Stm32f3_Wwdg_Init whal_Stm32f0_Wwdg_Init diff --git a/wolfHAL/watchdog/stm32l1_iwdg.h b/wolfHAL/watchdog/stm32l1_iwdg.h index 1df097b..3c884bb 100644 --- a/wolfHAL/watchdog/stm32l1_iwdg.h +++ b/wolfHAL/watchdog/stm32l1_iwdg.h @@ -12,6 +12,8 @@ typedef whal_Stm32wb_Iwdg_Cfg whal_Stm32l1_Iwdg_Cfg; +#define whal_Stm32l1_Iwdg_Dev whal_Stm32wb_Iwdg_Dev + #ifndef WHAL_CFG_STM32L1_IWDG_DIRECT_API_MAPPING #define whal_Stm32l1_Iwdg_Driver whal_Stm32wb_Iwdg_Driver #define whal_Stm32l1_Iwdg_Init whal_Stm32wb_Iwdg_Init diff --git a/wolfHAL/watchdog/stm32l1_wwdg.h b/wolfHAL/watchdog/stm32l1_wwdg.h index c11d438..6c532cc 100644 --- a/wolfHAL/watchdog/stm32l1_wwdg.h +++ b/wolfHAL/watchdog/stm32l1_wwdg.h @@ -13,6 +13,8 @@ typedef whal_Stm32f0_Wwdg_Cfg whal_Stm32l1_Wwdg_Cfg; +#define whal_Stm32l1_Wwdg_Dev whal_Stm32f0_Wwdg_Dev + #ifndef WHAL_CFG_STM32L1_WWDG_DIRECT_API_MAPPING #define whal_Stm32l1_Wwdg_Driver whal_Stm32f0_Wwdg_Driver #define whal_Stm32l1_Wwdg_Init whal_Stm32f0_Wwdg_Init diff --git a/wolfHAL/watchdog/stm32n6_iwdg.h b/wolfHAL/watchdog/stm32n6_iwdg.h index f033a3b..f2ac54e 100644 --- a/wolfHAL/watchdog/stm32n6_iwdg.h +++ b/wolfHAL/watchdog/stm32n6_iwdg.h @@ -14,6 +14,8 @@ typedef whal_Stm32wb_Iwdg_Cfg whal_Stm32n6_Iwdg_Cfg; +#define whal_Stm32n6_Iwdg_Dev whal_Stm32wb_Iwdg_Dev + #ifndef WHAL_CFG_STM32N6_IWDG_DIRECT_API_MAPPING #define whal_Stm32n6_Iwdg_Driver whal_Stm32wb_Iwdg_Driver #define whal_Stm32n6_Iwdg_Init whal_Stm32wb_Iwdg_Init diff --git a/wolfHAL/watchdog/stm32n6_wwdg.h b/wolfHAL/watchdog/stm32n6_wwdg.h index e022931..7dd5f6a 100644 --- a/wolfHAL/watchdog/stm32n6_wwdg.h +++ b/wolfHAL/watchdog/stm32n6_wwdg.h @@ -14,6 +14,8 @@ typedef whal_Stm32wb_Wwdg_Cfg whal_Stm32n6_Wwdg_Cfg; +#define whal_Stm32n6_Wwdg_Dev whal_Stm32wb_Wwdg_Dev + #ifndef WHAL_CFG_STM32N6_WWDG_DIRECT_API_MAPPING #define whal_Stm32n6_Wwdg_Driver whal_Stm32wb_Wwdg_Driver #define whal_Stm32n6_Wwdg_Init whal_Stm32wb_Wwdg_Init diff --git a/wolfHAL/watchdog/stm32wba_iwdg.h b/wolfHAL/watchdog/stm32wba_iwdg.h index f3faa2d..6bc4273 100644 --- a/wolfHAL/watchdog/stm32wba_iwdg.h +++ b/wolfHAL/watchdog/stm32wba_iwdg.h @@ -14,6 +14,8 @@ typedef whal_Stm32wb_Iwdg_Cfg whal_Stm32wba_Iwdg_Cfg; +#define whal_Stm32wba_Iwdg_Dev whal_Stm32wb_Iwdg_Dev + #ifndef WHAL_CFG_STM32WBA_IWDG_DIRECT_API_MAPPING #define whal_Stm32wba_Iwdg_Driver whal_Stm32wb_Iwdg_Driver #define whal_Stm32wba_Iwdg_Init whal_Stm32wb_Iwdg_Init diff --git a/wolfHAL/watchdog/stm32wba_wwdg.h b/wolfHAL/watchdog/stm32wba_wwdg.h index 178adf9..29ec299 100644 --- a/wolfHAL/watchdog/stm32wba_wwdg.h +++ b/wolfHAL/watchdog/stm32wba_wwdg.h @@ -14,6 +14,8 @@ typedef whal_Stm32wb_Wwdg_Cfg whal_Stm32wba_Wwdg_Cfg; +#define whal_Stm32wba_Wwdg_Dev whal_Stm32wb_Wwdg_Dev + #ifndef WHAL_CFG_STM32WBA_WWDG_DIRECT_API_MAPPING #define whal_Stm32wba_Wwdg_Driver whal_Stm32wb_Wwdg_Driver #define whal_Stm32wba_Wwdg_Init whal_Stm32wb_Wwdg_Init