ENTR-18: Docker toolchain, real CI gate on make test, pre-commit hooks

[davidshukhin]

Summary

Implements the core of ENTR-18: Docker environment, CI gating on make test, and minimal pre-commit — plus the test-suite repairs required to make that gate real. The old CI skipped the ARM and FPGA jobs with || true/echo, and the Python test scripts always exited 0, so no test had ever actually gated anything. Getting to a genuinely green make test surfaced real bugs, several of them hardware-relevant:

DevOps (the issue's core scope)

• Dockerfile (python:3.11-slim-trixie + pinned g++-13 + CPU torch): deps-only image, repo bind-mounted, so it rebuilds only when Dockerfile/requirements.txt change. make docker-build / make docker-test.
• CI: single test job — buildx with GHA layer cache, then make test in the container. This is the required status check for branch protection (ENO-11); the name is intentionally short and stable. Separate lint job runs flake8 + clang-format.
• Pre-commit: flake8 + clang-format (both pinned to match CI), wired into make lint, one setup line in CONTRIBUTING.md. One-time clang-format pass over arm/ fpga/ test/ in its own commit.
• Out of scope per the issue: 3.10/3.12 matrix and changelog gate (left as starter tasks).

Bugs found by un-skipping the tests

• fpga/hls_compat.h never compiled under g++ — rebuilt the ap_* sim types around implicit integral conversions.
• spatial_hash.h: ap_int<2> loop indices made the 3×3 neighborhood sweep an infinite loop; linear probing stored no keys, so k-NN lookups could never find a populated bucket (always 0 neighbors).
• Counter widths: 4096-capacity buffers counted with ap_uint<12>, wrapping to 0 at exactly full — new event_cnt_t (13-bit) used for all counts.
• pwm_output.h: pwm_tick_t was 16-bit but pulse widths reach 200,000 ticks — every motor output truncated mod 65536, including the disarmed safe-minimum. Now 18-bit.
• aer_interface.h: handshake state register was a non-static uninitialized local — UB every call.
• arm/collision_predictor.h: TTC formula multiplied Lee's τ = θ/θ̇ by fov/θ, cancelling object size — TTC came out ~30× too large and urgency was permanently 0 (no looming object could ever trigger evasion). Now τ = θ/θ̇ as documented. ⚠️ Flagging for ENTR-15: this changes flight-relevant behavior; the SITL parameter sweeps should validate the thresholds against the corrected TTC scale.
• arm/Makefile: sim target compiled objects with the ARM cross-compiler but linked with native g++.
• Python test runners now sys.exit(1) on failure (previously always 0 → CI could never catch a regression); RNG seeded (unseeded data made runs flaky).

Known limitation (intentionally visible)

models/models/FPGA.pth (weight truncation, not a retrain) predicts near-constant/NaN flow regardless of input, so the two model-quality assertions in test_fpga_simulator.py are XFAIL with an explicit degeneracy probe — they re-arm automatically once the ENTR-16 d=128 retrain lands. Everything structural still gates.

Verification

• make docker-test green locally: Python 5/5, golden model clean, ARM 23/23, FPGA testbench 17/17 assertions
• make lint exit 0 in the container; pre-commit run --all-files passes
• Old workflow's convert_weights_to_fpga.py --validate-only step dropped (depends on untracked UNION.pth)

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