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[OMNIML-4886] specdec_bench cell t0_d3 — Qwen/Qwen3.5-4B / MTP / vllm#1608

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[OMNIML-4886] specdec_bench cell t0_d3 — Qwen/Qwen3.5-4B / MTP / vllm#1608
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pensieve-intern/OMNIML-4885/t0_d3

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@ChenhanYu
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Summary

  • add SPEED-bench cell t0_d3 for Qwen/Qwen3.5-4B MTP vLLM

Testing

  • not run (cluster execution only)

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copy-pr-bot Bot commented Jun 2, 2026

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coderabbitai Bot commented Jun 2, 2026

Important

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codecov Bot commented Jun 2, 2026

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 75.85%. Comparing base (5eba879) to head (e0cdb1e).
⚠️ Report is 22 commits behind head on main.

Additional details and impacted files
@@            Coverage Diff             @@
##             main    #1608      +/-   ##
==========================================
- Coverage   76.88%   75.85%   -1.03%     
==========================================
  Files         478      481       +3     
  Lines       52209    55107    +2898     
==========================================
+ Hits        40140    41802    +1662     
- Misses      12069    13305    +1236     
Flag Coverage Δ
unit 53.90% <ø> (+0.38%) ⬆️

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@ChenhanYu ChenhanYu force-pushed the pensieve-intern/OMNIML-4885/t0_d3 branch from 93ef053 to c7cb26e Compare June 3, 2026 00:49
Signed-off-by: chenhany <chenhany@nvidia.com>
@ChenhanYu ChenhanYu force-pushed the pensieve-intern/OMNIML-4885/t0_d3 branch from c7cb26e to e0cdb1e Compare June 3, 2026 01:21
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