docs(dn)-Simon Hu-03/08/2026

src/design_notebooks/2026spring/yh4970.md

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 # Simon Hu - Design Notebook (Spring 2026)
 
+## Week 7
+### Comments:
+In lab 3 exercise 3, the reset and several output is revised, so I need to do correponding changes 
+in the cpp testing file. After the revision, I verified the testbench and all tests passed.
+### Work done:
+- revised the lab 3 and verified the testbench on exercise 3.
+- terminal respond:
+simonlinux@DESKTOP-8L3L3I6:/mnt/e/NYU/processerVIP/onboarding-lab-3/build$ ./exercise3
+Randomness seeded to: 703770779
+===============================================================================    
+All tests passed (101 assertions in 1 test case)
+
+## Week 6
+### Comments:
+Read the paper Design and Constructionof RTL Toolchains at NYU
+
+Summary of the paper:
+This paper describes the design of an open-source RTL verification toolchain developed by the NYU Processor Design Team to replace traditional ad-hoc workflows that rely on commercial EDA tools. The system integrates modern software development tools—CMake for orchestration, Verilator for RTL simulation, vcpkg for dependency management, and Catch2 for testing—to create a portable and automated workflow that students can run on their own machines. The goal is to provide a robust, reproducible, and software-style development environment for hardware design and verification, supporting testing, waveform generation, and continuous integration.
+
 ## Week 5
 ### Comments:
 Read the paper NYU Processor Design Team SoC CPU Core