ram: add nangate45 cross-platform regression test

src/ram/src/ram.cpp

@@ -116,11 +116,35 @@ std::unique_ptr<Cell> RamGen::makeCellBit(const std::string& prefix,
 
   auto storage_net = makeNet(prefix, "storage");
 
+  // Resolve the clock-pin name for the storage cell by querying the
+  // Liberty data.  This avoids hard-coding technology-specific pin names
+  // (e.g. "CLK", "CK") and works with any technology node.
+  const char* clk_pin = nullptr;
+  auto sta_cell = network_->dbToSta(storage_cell_);
+  if (sta_cell) {
+    auto liberty = network_->libertyCell(sta_cell);
+    if (liberty) {
+      auto port_iter = liberty->portIterator();
+      while (port_iter->hasNext()) {
+        auto lib_port = port_iter->next();
+        if (lib_port->libertyPort() && lib_port->libertyPort()->isClock()) {
+          clk_pin = lib_port->name();
+          break;
+        }
+      }
+      delete port_iter;
+    }
+  }
+  if (!clk_pin) {
+    logger_->error(
+        RAM, 12, "No clock pin found on storage cell {}.",
+        storage_cell_->getName());
+  }
   makeCellInst(bit_cell.get(),
                prefix,
                "bit",
                storage_cell_,
-               {{storage_cell_->findMTerm("CLK") ? "CLK" : "GATE", clock},
+               {{clk_pin, clock},
                 {"D", data_input},
                 {"Q", storage_net}});
 

src/ram/test/CMakeLists.txt

@@ -2,5 +2,6 @@ or_integration_tests(
   "ram"
   TESTS
     make_8x8
+    make_7x7_nangate45
 )
 

src/ram/test/Nangate45

@@ -0,0 +1 @@
+../../../test/Nangate45

src/ram/test/make_7x7_nangate45.tcl

@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2024-2025, The OpenROAD Authors
+#
+# Test: ram/make_7x7_nangate45
+# Verifies that generate_ram works correctly with the Nangate45 technology
+# node using an intentionally odd 7-word x 1-byte (56-bit) configuration
+# to exercise the decoder logic on a non-power-of-2 word count.
+# Addresses Issue #9468.
+
+source "helpers.tcl"
+
+set_thread_count [expr [cpu_count] / 4]
+
+read_liberty Nangate45/Nangate45_typ.lib
+
+read_lef Nangate45/Nangate45_tech.lef
+read_lef Nangate45/Nangate45.lef
+
+set behavioral_file [make_result_file make_7x7_nangate45_behavioral.v]
+
+generate_ram \
+  -bytes_per_word 1 \
+  -word_count 7 \
+  -read_ports 1 \
+  -storage_cell DFF_X1 \
+  -power_pin VDD \
+  -ground_pin VSS \
+  -routing_layer {metal1 0.07} \
+  -ver_layer {metal2 0.07 0.42} \
+  -hor_layer {metal3 0.07 0.42} \
+  -filler_cells {FILLCELL_X1 FILLCELL_X2 FILLCELL_X4 FILLCELL_X8} \
+  -write_behavioral_verilog $behavioral_file
+
+set lef_file [make_result_file make_7x7_nangate45.lef]
+write_abstract_lef $lef_file
+diff_files make_7x7_nangate45.lefok $lef_file
+
+set def_file [make_result_file make_7x7_nangate45.def]
+write_def $def_file
+diff_files make_7x7_nangate45.defok $def_file
+
+diff_files make_7x7_nangate45_behavioral.vok $behavioral_file

src/ram/test/make_7x7_nangate45_behavioral.vok

@@ -0,0 +1,32 @@
+module RAM7x8 (
+  clk,
+  D,
+  Q,
+  addr_rw,
+  we
+);
+  input clk;
+  input [7:0] D;
+  output reg [7:0] Q;
+  input [2:0] addr_rw;
+  input [0:0] we;
+
+  // memory array declaration
+  reg [7:0] mem[0:6];
+
+  // write logic
+  integer i;
+  always @(posedge clk) begin
+    for (i = 0; i < 1; i = i + 1) begin
+      if (we[i]) begin
+        mem[addr_rw][i*8 +:8] <= D[i*8 +:8];
+      end
+    end
+  end
+
+  // read logic
+  always @(*) begin
+    Q = mem[addr_rw];
+  end
+
+endmodule

src/ram/test/regression_tests.tcl

@@ -1,3 +1,4 @@
 record_tests {
   make_8x8
+  make_7x7_nangate45
 }