arch/tricore: add support for tc4xx series chips and boards

Documentation/platforms/tricore/index.rst

@@ -31,8 +31,8 @@ The core Chip implementation is based on Infineon Low Level Drivers (iLLDs).
 The unified API is more friendly to developers familiar with Infineon SDK/HAL.
 We can get more code examples on Infineon's official Github: `AURIX_code_examples <https://github.com/Infineon/AURIX_code_examples>`__
 
-``TC3xx``
-  This is the implementation of NuttX on the Infineon’s AURIX™- TC3xx microcontroller family.
+``TC3xx/TC4xx``
+  This is the implementation of NuttX on the Infineon’s AURIX™- TC3xx/TC4xx microcontroller family.
 
 .. toctree::
    :maxdepth: 1

Documentation/platforms/tricore/tc4d9/boards/triboard_tc4x9_com/index.rst

@@ -0,0 +1,55 @@
+==================
+TRIBOARD_TC4X9_COM
+==================
+
+This port should work on TRIBOARD_TC4X9_COM with a proper CPU.
+The mandatory CPU features are:
+
+* System Timer (STM)
+* Asynchronous Serial Interface(ASCLIN) UART
+* IRQs are managed by Interrupt Router(INT), IR Service Request Control Registers(SRC).
+
+Toolchains
+==========
+
+Currently, only the Infineon’s AURIX™ GCC toolchain is tested.
+
+Configurations
+==============
+
+Common Configuration Notes
+--------------------------
+
+1. Each TRIBOARD_TC4X9_COM configuration is maintained in a sub-directory
+   and can be selected as follow::
+
+     tools/configure.sh triboard_tc4x9_com:<subdir>
+
+   Where ``<subdir>`` is one of the configuration sub-directories described in
+   the following paragraph.
+
+   NuttX Shell::
+
+     tools/configure.sh triboard_tc4x9_com:nsh
+
+2. These configurations use the mconf-based configuration tool.  To
+   change a configurations using that tool, you should:
+
+   a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+      see additional README.txt files in the NuttX tools repository.
+
+   b. Execute ``make menuconfig`` in nuttx/ in order to start the
+      reconfiguration process.
+
+3. By default, all configurations assume the Linux.  This is easily
+   reconfigured::
+
+     CONFIG_HOST_LINUX=y
+
+Configuration Sub-Directories
+-----------------------------
+
+ostest
+------
+
+The "standard" NuttX examples/ostest configuration.

Documentation/platforms/tricore/tc4d9/index.rst

@@ -0,0 +1,23 @@
+=============
+TriCore/TC4DA
+=============
+
+**TriCore/TC4DA** An TriCore flat address port was ported in NuttX-12.0. It
+consists of the following features:
+
+- Runs in Supervisor Mode.
+- IRQs are managed by Interrupt Router (INT), IR Service Request Control Registers (SRC).
+- Used System timer (STM) for systick.
+
+This kernel with ostest have been tested with
+
+-  Infineon's AURIX™ TC4DA Evaluation Board: TRIBOARD_TC4X9_COM
+
+Supported Boards
+================
+
+.. toctree::
+   :glob:
+   :maxdepth: 1
+
+   boards/*/*

arch/tricore/Kconfig

@@ -22,30 +22,76 @@ config TRICORE_TOOLCHAIN_GNU
 
 endchoice # Tricore Toolchain Selection
 
-config ARCH_TC3XX
+config ARCH_TC1V6
 	bool
+	select ARCH_HAVE_MPU
+	select ARCH_HAVE_IRQTRIGGER
+	select ARCH_HAVE_PERF_EVENTS
+	select ARCH_HAVE_POWEROFF
+	select ARCH_HAVE_PERF_EVENTS_USER_ACCESS
+	select ARCH_HAVE_SETJMP
+	select ARCH_HAVE_RESET
 	select ARCH_HAVE_TESTSET
+	default n
+
+config ARCH_TC1V8
+	bool
+	select ARCH_DCACHE
+	select ARCH_ICACHE
+	select ARCH_HAVE_MPU
 	select ARCH_HAVE_IRQTRIGGER
-	select ARCH_MINIMAL_VECTORTABLE
-	select ARCH_MINIMAL_VECTORTABLE_DYNAMIC
+	select ARCH_HAVE_PERF_EVENTS
+	select ARCH_HAVE_PERF_EVENTS_USER_ACCESS
+	select ARCH_HAVE_POWEROFF
+	select ARCH_HAVE_SETJMP
+	select ARCH_HAVE_RESET
+	select ARCH_HAVE_TESTSET
 	default n
 
 config ARCH_FAMILY
 	string
-	default "tc3xx"		if ARCH_TC3XX
+	default "tc1v6"		if ARCH_TC1V6
+	default "tc1v8"		if ARCH_TC1V8
 
-config ARCH_CHIP
-	string
-	default "tc397"		if ARCH_CHIP_TC397
+config ARCH_CHIP_TC3XX
+	bool
+	select ARCH_TC1V6
+	select ARCH_HAVE_ADDRENV
+	select ARCH_HAVE_I2CRESET
+	select ARCH_MINIMAL_VECTORTABLE
+	select ARCH_MINIMAL_VECTORTABLE_DYNAMIC
+	select ALARM_ARCH
+	select ONESHOT
+	select ONESHOT_COUNT
+	---help---
+		Infineon aurix tc3xx (six cores)
 
-config ARCH_CHIP_TC397
-	bool "AURIX Family TC397"
-	select ARCH_TC3XX
+config ARCH_CHIP_TC4XX
+	bool
+	select ARCH_TC1V8
+	select ARCH_HAVE_ADDRENV
+	select ARCH_HAVE_I2CRESET
+	select ARCH_MINIMAL_VECTORTABLE
+	select ARCH_MINIMAL_VECTORTABLE_DYNAMIC
 	select ALARM_ARCH
 	select ONESHOT
 	select ONESHOT_COUNT
+	select HAVE_SECURITY_CORE
 	---help---
-		AURIX TC39x family: TC397
+		Infineon aurix tc4xx (six cores and one security core)
+
+config ARCH_CHIP_TC397
+	bool "AURIX CHIP TC397"
+	select ARCH_CHIP_TC3XX
+
+config ARCH_CHIP_TC4DA
+	bool "AURIX CHIP TC4DA"
+	select ARCH_CHIP_TC4XX
+
+config ARCH_CHIP
+	string
+	default "tc397"		if ARCH_CHIP_TC397
+	default "tc4da"		if ARCH_CHIP_TC4DA
 
 config ARCH_DCACHE_ADDR
 	hex "AURIX Dcache base address"
@@ -72,11 +118,26 @@ config ARCH_MPU_CODE_NREGIONS
 	---help---
 		The code regions count
 
+config HAVE_SECURITY_CORE
+	bool
+	--help--
+		In addition to the 6 cores, tc4xx also has one more security core.
+
+config CPU_COREID
+	int "TRICORE CPU CORE ID"
+	default 0
+	range 0 6
 
-if ARCH_TC3XX
+if ARCH_CHIP_TC3XX
 source "arch/tricore/src/tc3xx/Kconfig"
 endif
-if ARCH_TC397
+if ARCH_CHIP_TC4XX
+source "arch/tricore/src/tc4xx/Kconfig"
+endif
+if ARCH_CHIP_TC397
 source "arch/tricore/src/tc397/Kconfig"
 endif
+if ARCH_CHIP_TC4DA
+source "arch/tricore/src/tc4da/Kconfig"
+endif
 endif # ARCH_TRICORE

arch/tricore/include/irq.h

@@ -44,10 +44,8 @@
 /* Include chip-specific IRQ definitions (including IRQ numbers) */
 
 #include <arch/chip/irq.h>
-
-#if defined(CONFIG_ARCH_TC3XX)
-#  include <arch/tc3xx/irq.h>
-#endif
+#include <arch/arch.h>
+#include <IfxCpu_Intrinsics.h>
 
 /****************************************************************************
  * Pre-processor Prototypes
@@ -60,6 +58,86 @@
 #define tricore_addr2csa(addr) ((uintptr_t)(((((uintptr_t)(addr)) & 0xF0000000) >> 12) \
                                             | (((uintptr_t)(addr) & 0x003FFFC0) >> 6)))
 
+/* Upper CSA */
+
+#define REG_UPCXI        0
+#define REG_PSW          1
+#define REG_A10          2
+#define REG_UA11         3
+#define REG_D8           4
+#define REG_D9           5
+#define REG_D10          6
+#define REG_D11          7
+#define REG_A12          8
+#define REG_A13          9
+#define REG_A14          10
+#define REG_A15          11
+#define REG_D12          12
+#define REG_D13          13
+#define REG_D14          14
+#define REG_D15          15
+
+/* Lower CSA */
+
+#define REG_LPCXI        0
+#define REG_LA11         1
+#define REG_A2           2
+#define REG_A3           3
+#define REG_D0           4
+#define REG_D1           5
+#define REG_D2           6
+#define REG_D3           7
+#define REG_A4           8
+#define REG_A5           9
+#define REG_A6           10
+#define REG_A7           11
+#define REG_D4           12
+#define REG_D5           13
+#define REG_D6           14
+#define REG_D7           15
+
+#define REG_RA           REG_UA11
+#define REG_SP           REG_A10
+#define REG_UPC          REG_UA11
+
+#define REG_LPC          REG_LA11
+
+#define TC_CONTEXT_REGS  (16)
+#define TC_CONTEXT_SIZE  (sizeof(void *) * TC_CONTEXT_REGS)
+
+#define XCPTCONTEXT_REGS (TC_CONTEXT_REGS * 2)
+#define XCPTCONTEXT_SIZE (sizeof(void *) * XCPTCONTEXT_REGS)
+
+#define NR_IRQS          (2048)
+
+/* PSW: Program Status Word Register */
+
+#define PSW_CDE         (1 << 7) /* Bits 7: Call Depth Count Enable */
+#define PSW_IS          (1 << 9) /* Bits 9: Interrupt Stack Control */
+#define PSW_IO          (10)     /* Bits 10-11: Access Privilege Level Control (I/O Privilege) */
+#  define PSW_IO_USER0      (0 << PSW_IO)
+#  define PSW_IO_USER1      (1 << PSW_IO)
+#  define PSW_IO_SUPERVISOR (2 << PSW_IO)
+
+/* PCXI: Previous Context Information and Pointer Register */
+
+#define PCXI_UL         (1 << 20) /* Bits 20: Upper or Lower Context Tag */
+#define PCXI_PIE        (1 << 21) /* Bits 21: Previous Interrupt Enable */
+
+/* FCX: Free CSA List Head Pointer Register */
+
+#define FCX_FCXO        (0)       /* Bits 0-15: FCX Offset Address */
+#define FCX_FCXS        (16)      /* Bits 16-19: FCX Segment Address */
+#define FCX_FCXO_MASK   (0xffff << FCX_FCXO)
+#define FCX_FCXS_MASK   (0xf    << FCX_FCXS)
+#define FCX_FREE        (FCX_FCXS_MASK | FCX_FCXO_MASK) /* Free CSA manipulation */
+
+#define TRICORE_SRCNUM_PER_GPSR  8
+#define TRICORE_SRC2IRQ(src_addr) \
+  (((uintptr_t)(src_addr) - (uintptr_t)&MODULE_SRC) / 4)
+#define TRICORE_GPSR_IRQNUM(src_cpu, dest_cpu)  \
+  TRICORE_SRC2IRQ(&SRC_GPSR00 + src_cpu * 8 + dest_cpu)
+
 /* For use with EABI and floating point, the stack must be aligned to 8-byte
  * addresses.
  */
@@ -76,6 +154,28 @@ extern "C"
 #define EXTERN extern
 #endif
 
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+struct xcptcontext
+{
+#ifdef CONFIG_ENABLE_ALL_SIGNALS
+  /* These are saved copies of the context used during
+   * signal processing.
+   */
+
+  uintptr_t *saved_regs;
+#endif
+  /* Register save area with XCPTCONTEXT_SIZE, only valid when:
+   * 1.The task isn't running or
+   * 2.The task is interrupted
+   * otherwise task is running, and regs contain the stale value.
+   */
+
+  uintptr_t *regs;
+};
+
 /****************************************************************************
  * Public Data
  ****************************************************************************/
@@ -119,7 +219,7 @@ noinstrument_function static inline_function uintptr_t up_getsp(void)
 #ifdef CONFIG_TRICORE_TOOLCHAIN_TASKING
   return (uintptr_t)__get_sp();
 #else
-  return __builtin_frame_address(0);
+  return (uintptr_t)__builtin_frame_address(0);
 #endif
 }
 
@@ -202,7 +302,7 @@ static inline_function bool up_interrupt_context(void)
 
 static inline_function uintptr_t up_getusrsp(void *regs)
 {
-  uintptr_t *csaregs = regs;
+  uintptr_t *csaregs = (uintptr_t *)regs;
 
   if (csaregs[REG_LPCXI] & PCXI_UL)
     {

arch/tricore/include/tc397/irq.h

@@ -34,6 +34,7 @@
 /****************************************************************************
  * Pre-processor Prototypes
  ****************************************************************************/
+
 #define TRICORE_UART_RX_IRQ      21
 
 /****************************************************************************