This repository was archived by the owner on Mar 7, 2026. It is now read-only.

Feature: Hazard3 example SoC on Icebreaker support#2113

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ALTracer wants to merge 174 commits intoblackmagic-debug:mainfrom

ALTracer:feature/hazard3-ice40-support

Commits on Mar 8, 2026

misc: update links github to codeberg
gojimmypi
committed
bmp-v3: Begun fleshing out the platform definitions for the pinout
dragonmux
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bmp-v3: Added pin definitions for all the most major moving pieces
dragonmux
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adiv5_swd: Fixed some issues in the copyright header
dragonmux
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bmp-v3: Started filling in interrupt setup and control macros
dragonmux
committed
common/stm32: Defined the STM32U5 as a viable BMP platform target
dragonmux
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native: Fixed the copyright headers
dragonmux
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common: Enable various facilities for the STM32U5 series
dragonmux
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bmp-v3: Roughly implemented the SWDIO drive mode switch macros
dragonmux
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bmp-v3: Added configuration for the SWO pin
dragonmux
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bmp-v3: Defined the DMA setup for the SWO and AUX UART subsystems
dragonmux
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common/aux_serial: Implemented support for sourcing data from two UARTs and switching between them automatically
dragonmux
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bmp-v3: Added a linker script for the platform
dragonmux
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common/aux_serial: Built out DMA configuration for the STM32U5 as it's quite different to the other platforms
dragonmux
committed
ch32vx: Gate the read Flash size function properly on whether DEBUG_INFO does anything to avoid unused warnings
dragonmux
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common/swo_uart: Built out DMA configuration for the STM32U5 as it's quite different to the other platforms
dragonmux
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common/swo_manchester: Handle the STM32U5 timer input multiplexing properly
dragonmux
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meson: Added the new BMPv3 platform to the build system, integrating a suitable cross file too
dragonmux
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bmp-v3: Begun implementing the platform-specific functions
dragonmux
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native: Removed a duplicated include line
dragonmux
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native: Fixed up the copyright header
dragonmux
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bmp-v3: Defined the first part of platform initialisation, bringing up USB, timing, and setting up the correct vector table address
dragonmux
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stlinkv3: Removed a duplicated include line
dragonmux
committed
native: Added some `const` to the ADC code the updated locm3 allows
dragonmux
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bmp-v3: Implemented target voltage readout using the ADCs and tpwr sense pin
dragonmux
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bmp-v3: Implemented bringup of the various core peripherals and clocking
dragonmux
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bmp-v3: Implemented the boot request logic
dragonmux
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bmp-v3: Implemented handling for the hardware version info
dragonmux
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bmp-v3: Fleshed out GPIO configuration and bringup
dragonmux
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bmp-v3: Defined clocking for the platform
dragonmux
committed
bmp-v3: Built out the bootloader for the platform
dragonmux
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common: Built a new, more suitable bootloader backend for the STM32U5
dragonmux
committed
common: Enabled the STM32U5 in the core DFU bootloader
dragonmux
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common: Cleaned up the core DFU bootloader using the buffer_utils header
dragonmux
committed
bmp-v3: Initialise the UART subsystem and configure the UART pins appropriately
dragonmux
committed
misc: Turn off a clang-analyzer-core lint that we cannot avoid due to writing firmware
dragonmux
committed
bmp-v3: Initialise the LED pins so we can see the GDB machinary state
dragonmux
committed

Commits on Mar 9, 2026

Commits on Mar 14, 2026

Commits on Mar 16, 2026

Commits on Mar 22, 2026

Commits on Mar 25, 2026

riscv_debug: Reorder editing triggers *after* the halting
ALTracer
committed

Commits on Mar 27, 2026

Commits on Mar 29, 2026

Commits on Apr 4, 2026

Commits on Apr 6, 2026

stlink: document stlink v2-1 bootloader behavior
fufixman
committed

Commits on Apr 9, 2026

adiv5_jtag: Restore lost JTAG-DP state across resets

ALTracer
authored and
ALTracer
committed
adiv5_jtag: Make _ensure_idle method public

ALTracer
authored and
ALTracer
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remote: Add JTAG ensure idle command (!JI#)

ALTracer
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ALTracer
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hosted/remote/protocol_v4: Add JTAG ensure idle command (!JI#)

ALTracer
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ALTracer
committed
stm32mp15: Read DBGMCU for CA7 via AP1
ALTracer
committed
stm32mp15: Add DRAM (512 MiB) and Boot ROM to CA7 memory map
ALTracer
committed

Commits on Apr 12, 2026

riscv32: Prepare memory access via progbuf

ALTracer
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ALTracer
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riscv32: Implement memory I/O via progbuf (4+1 slots, uncompressed)

ALTracer
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ALTracer
committed

Commits on Apr 13, 2026

riscv32: Refactor progbuf-based memory I/O to fit into 1 slot and use GPR

ALTracer
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ALTracer
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riscv32: Update riscv32_progbuf_mem_read to use both x10 & x11

ALTracer
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ALTracer
committed
riscv_debug: extract DM ProgBuf Base macro
ALTracer
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riscv_debug: Extract macros for A0/A1 core registers
ALTracer
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riscv_debug: Extract EBREAK instruction to common header
ALTracer
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riscv32: Use newly added RV_GPR_A1
ALTracer
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riscv32: Delegate to riscv_csr_read/write in riscv32_progbuf_mem_read/write for AAR
ALTracer
committed
riscv32: Restore saved GPR A0,A1 on progbuf_mem errors in the loop
ALTracer
committed
riscv32: Compose the progbuf read/write instructions via macros, drop arrays
ALTracer
committed

Commits on Apr 14, 2026

hosted/ftdi_bmp: Register generic FT2232H on Icebreaker for JTAG on MPSSE interface A

ALTracer
authored and
ALTracer
committed
jtag_devs: Register Hazard3/ice40 TAP as a RISC-V DTM

ALTracer
authored and
ALTracer
committed
riscv32: Add very basic support for Hazard3 SoC on Icebreaker SPRAM

ALTracer
authored and
ALTracer
committed