Interface struct#672
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…al/instance naming routine names
- Module: add portGroups map and registerPortGroup() API - Interface.connectIO: detect group name from uniquify function, register each port with its interface group - PairInterface: pass groupName through to super.connectIO and sub-interface connections Enables downstream synthesis/tools to identify which ports belong to the same logical interface without relying on naming heuristics.
…addInterfacePorts When asStruct=true, interface ports are registered as LogicStructure ports (prefix_in / prefix_out) instead of individual leaf ports. Backward compatible: default asStruct=false preserves existing behavior.
Clarify comment Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
This aligns central_naming with the simplified naming approach already adopted by all downstream branches (module_services, netlist, source_debug, systemc_trace, fst-writer). Changes: - Remove Namer._instanceNames cache field - Remove Namer.instanceNameOf(Module) method - Update synthesizers to use Namer.allocateName(String) directly - Remove destination tracking from _BusSubsetForStructSlice Benefit: Eliminates duplication across 5+ branches, making each branch truly orthogonal and mergeable without conflicts. Trade-off: Instance names no longer cached across synthesis passes, but all downstreams already use this simpler approach.
# Conflicts: # tool/gh_codespaces/install_dart.sh
instanceNameOf(Module) allocates a collision-free instance name on the first call and returns the cached result thereafter. The _instanceNames Map is keyed by Module.instanceNameKey so repeated synthesis passes over the same hierarchy always produce stable names. This method belongs in central_naming because it is pure naming infrastructure with no dependency on any feature branch.
instanceNameOf and _instanceNames were added here independently. central_naming is now the canonical home; remove the duplicate to keep the branch delta minimal.
- Update comment: 'allocateName' → 'instanceNameOf' - Add 'submodule instance names are stable across repeated definitions' test (the canonical 'run synthesis twice, same names' regression test) Both belong here since they directly exercise Namer.instanceNameOf, which is now defined in central_naming.
SynthSubModuleInstantiation.pickName was calling namer.allocateName() directly, bypassing the _instanceNames cache in Namer.instanceNameOf. This caused the second SynthModuleDefinition build over the same module hierarchy to see 'inner' already taken and allocate 'inner_0' instead. Fix: call namer.instanceNameOf(module) which caches on first allocation and returns the same name on subsequent synthesis passes.
Two new tests in 'shared instance and signal namespace': 1. 'instance name wins the shared namespace; signal gets the suffix' Asserts deterministic ordering: non-reserved instances are picked before non-reserved signals, so the instance keeps the bare name and the colliding signal is uniquified to inner_0. 2. 'instance-signal collision resolution is stable across repeated synthesis passes' Calls generateSynth() twice and verifies the module body is identical (timestamp stripped). Guards against name drift where the second pass would assign different suffixes.
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Description & Motivation
When we add
Interfaces toModules, we loop through them to flattenLogicStructures (hierarchically) and add individualPorts for each signal.A novel and compact way is instead to split the
Interfaceinto twoLogicStructures, one for input and one for output, and then add those two asPorts for theModule. For connectivityModules where anInterfaceor a subset of theInterfaceis consistently handed through to other subblocks, we see a dramatic decrease in complexity of wiring.Related Issue(s)
None.
Testing
This was tested on large, complex designs. Missing, however, are directed tests at corner cases to make sure this capability works in all use cases.
Backwards-compatibility
No. This adds a new way of adding interfaces to modules, but the old way is retained.
Documentation
No. Likely we need to provide an example and a description. A proposal may be to create a matrix of methods to add
Ports toModules and include this method.