Add tests for WaveActiveAllEqual

test/WaveOps/WaveActiveAllEqual.32.test

@@ -0,0 +1,372 @@
+#--- source.hlsl
+StructuredBuffer<int> In  : register(t0);
+StructuredBuffer<int2> In2  : register(t1);
+StructuredBuffer<int3> In3  : register(t2);
+StructuredBuffer<int4> In4  : register(t3);
+
+StructuredBuffer<uint> UIn  : register(t4);
+StructuredBuffer<uint2> UIn2  : register(t5);
+StructuredBuffer<uint3> UIn3  : register(t6);
+StructuredBuffer<uint4> UIn4  : register(t7);
+
+StructuredBuffer<float> FIn  : register(t8);
+StructuredBuffer<float2> FIn2  : register(t9);
+StructuredBuffer<float3> FIn3  : register(t10);
+StructuredBuffer<float4> FIn4  : register(t11);
+
+RWStructuredBuffer<int> Out : register(u12);
+RWStructuredBuffer<int> UOut : register(u13);
+RWStructuredBuffer<int> FOut : register(u14);
+
+// Expect all 4s, all elements will be the same.
+
+[numthreads(4,1,1)]
+void main(uint3 TID : SV_GroupThreadID)
+{
+    unsigned int index = 0;
+    bool Result = WaveActiveAllEqual(In[TID.x]);
+    Out[index + TID.x] = Result;
+    index += 4;
+
+    bool2 Result2 = WaveActiveAllEqual(In2[TID.x]);
+    Out[index + TID.x] = Result2.x;
+    index += 4;
+    Out[index + TID.x] = Result2.y;
+    index += 4;
+
+    bool3 Result3 = WaveActiveAllEqual(In3[TID.x]);
+    Out[index + TID.x] = Result3.x;
+    index += 4;
+    Out[index + TID.x] = Result3.y;
+    index += 4;
+    Out[index + TID.x] = Result3.z;
+    index += 4;
+
+    bool4 Result4 = WaveActiveAllEqual(In4[TID.x]);
+    Out[index + TID.x] = Result4.x;
+    index += 4;
+    Out[index + TID.x] = Result4.y;
+    index += 4;
+    Out[index + TID.x] = Result4.z;
+    index += 4;
+    Out[index + TID.x] = Result4.w;
+    index += 4;
+
+
+    // constant folding case
+    bool4 ResultCF = WaveActiveAllEqual(int4(1,1,1,1));
+    Out[index + TID.x] = ResultCF.x;
+    index += 4;
+    Out[index + TID.x] = ResultCF.y;
+    index += 4;
+    Out[index + TID.x] = ResultCF.z;
+    index += 4;
+    Out[index + TID.x] = ResultCF.w;
+    index += 4;
+
+    unsigned int uindex = 0;
+    bool UResult = WaveActiveAllEqual(UIn[TID.x]);    
+    UOut[uindex + TID.x] = UResult;
+    uindex += 4;
+
+    bool2 UResult2 = WaveActiveAllEqual(UIn2[TID.x]);
+    UOut[uindex + TID.x] = UResult2.x;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult2.y;
+    uindex += 4;    
+
+    bool3 UResult3 = WaveActiveAllEqual(UIn3[TID.x]);
+    UOut[uindex + TID.x] = UResult3.x;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult3.y;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult3.z;
+    uindex += 4; 
+
+    bool4 UResult4 = WaveActiveAllEqual(UIn4[TID.x]);
+    UOut[uindex + TID.x] = UResult4.x;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult4.y;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult4.z;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResult4.w;
+    uindex += 4;
+
+    // constant folding case
+    bool4 UResultCF = WaveActiveAllEqual(uint4(1,1,1,1));
+    UOut[uindex + TID.x] = UResultCF.x;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResultCF.y;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResultCF.z;
+    uindex += 4;
+    UOut[uindex + TID.x] = UResultCF.w;
+    uindex += 4;
+
+    unsigned int findex = 0;
+    bool FResult = WaveActiveAllEqual(FIn[TID.x]);    
+    FOut[findex + TID.x] = FResult;
+    findex += 4;
+
+    bool2 FResult2 = WaveActiveAllEqual(FIn2[TID.x]);
+    FOut[findex + TID.x] = FResult2.x;
+    findex += 4;
+    FOut[findex + TID.x] = FResult2.y;
+    findex += 4;
+
+    bool3 FResult3 = WaveActiveAllEqual(FIn3[TID.x]);
+    FOut[findex + TID.x] = FResult3.x;
+    findex += 4;
+    FOut[findex + TID.x] = FResult3.x;
+    findex += 4;
+    FOut[findex + TID.x] = FResult3.y;
+    findex += 4;
+
+    bool4 FResult4 = WaveActiveAllEqual(FIn4[TID.x]);
+    FOut[findex + TID.x] = FResult4.x;
+    findex += 4;
+    FOut[findex + TID.x] = FResult4.y;
+    findex += 4;
+    FOut[findex + TID.x] = FResult4.x;
+    findex += 4;
+    FOut[findex + TID.x] = FResult4.y;
+    findex += 4;
+
+    // constant folding case
+    bool4 FResultCF = WaveActiveAllEqual(float4(1,1,1,1));
+    FOut[findex + TID.x] = FResultCF.x;
+    findex += 4;
+    FOut[findex + TID.x] = FResultCF.y;
+    findex += 4;
+    FOut[findex + TID.x] = FResultCF.x;
+    findex += 4;
+    FOut[findex + TID.x] = FResultCF.y;
+    findex += 4;
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Int32
+    Stride: 4
+    Data: [ -1, -1, -1, -1]
+  - Name: In2
+    Format: Int32
+    Stride: 8
+    Data: [ -1, -1, -1, -1, -1, -1, -1, -1]
+  - Name: In3
+    Format: Int32
+    Stride: 12
+    Data: [ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1]
+  - Name: In4
+    Format: Int32
+    Stride: 16
+    Data: [ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1]
+  - Name: UIn
+    Format: UInt32
+    Stride: 4
+    Data: [ 1, 1, 1, 1]
+  - Name: UIn2
+    Format: UInt32
+    Stride: 8
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1]
+  - Name: UIn3
+    Format: UInt32
+    Stride: 12
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
+  - Name: UIn4
+    Format: UInt32
+    Stride: 16
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+  - Name: FIn
+    Format: Float32
+    Stride: 4
+    Data: [ 1.0, 1.0, 1.0, 1.0 ]
+  - Name: FIn2
+    Format: Float32
+    Stride: 8
+    Data: [ 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0 ]
+  - Name: FIn3
+    Format: Float32
+    Stride: 12
+    Data: [ 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0 ]
+  - Name: FIn4
+    Format: Float32
+    Stride: 16
+    Data: [ 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0 ]
+
+  - Name: Out
+    Format: Int32
+    Stride: 4
+    FillSize: 224
+  - Name: UOut
+    Format: Int32
+    Stride: 4
+    FillSize: 224 
+  - Name: FOut
+    Format: Int32
+    Stride: 4
+    FillSize: 224
+
+  - Name: ExpectedOut
+    Format: Int32
+    Stride: 4
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+  - Name: UExpectedOut
+    Format: Int32
+    Stride: 4
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+  - Name: FExpectedOut
+    Format: Int32
+    Stride: 4
+    Data: [ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 ]
+
+Results:
+  - Result: ExpectedOut
+    Rule: BufferExact
+    Actual: Out
+    Expected: ExpectedOut
+  - Result: UExpectedOut
+    Rule: BufferExact
+    Actual: UOut
+    Expected: UExpectedOut
+  - Result: FExpectedOut
+    Rule: BufferExact
+    Actual: FOut
+    Expected: FExpectedOut
+
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: In2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: In3
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: In4
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: UIn
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: UIn2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+    - Name: UIn3
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 6
+        Space: 0
+      VulkanBinding:
+        Binding: 6
+    - Name: UIn4
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 7
+        Space: 0
+      VulkanBinding:
+        Binding: 7
+    - Name: FIn
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 8
+        Space: 0
+      VulkanBinding:
+        Binding: 8
+    - Name: FIn2
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 9
+        Space: 0
+      VulkanBinding:
+        Binding: 9
+    - Name: FIn3
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 10
+        Space: 0
+      VulkanBinding:
+        Binding: 10
+    - Name: FIn4
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 11
+        Space: 0
+      VulkanBinding:
+        Binding: 11
+    - Name: Out
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 12
+        Space: 0
+      VulkanBinding:
+        Binding: 12
+    - Name: UOut
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 13
+        Space: 0
+      VulkanBinding:
+        Binding: 13
+    - Name: FOut
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 14
+        Space: 0
+      VulkanBinding:
+        Binding: 14
+...
+#--- end
+
+# Bug: https://github.com/llvm/offload-test-suite/issues/943
+# XFAIL: Intel && Vulkan
+
+# Bug: https://github.com/llvm/offload-test-suite/issues/981
+# XFAIL: Clang
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o