ot_sram_ctrl: Connect the lc_ctrl HW_DEBUG_EN signal for ifetch / execution enablement#311
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When the OTP SRAM ifetch is disabled, hardware does not check the CSR iftech but instead checks whether the pervasive `HW_DEBUG_EN` signal from the lifecycle controller is being broadcast. If so, it allows ifetch/execution from SRAM. For now, it is kept that the property-configured `ifetch` still overrides the LC HW_DEBUG_EN ifetch enablement, so that this configuration ifetch is seen as a "global" disable that can override all other ifetch enablement mechanisms. Signed-off-by: Alex Jones <alex.jones@lowrisc.org>
Connect the lifecycle controller's broadcast `LC_HW_DEBUG_EN` signal to each SRAM controller in both tops, to match the ifetch/execution enablement conditions that are specified in the RTL. Signed-off-by: Alex Jones <alex.jones@lowrisc.org>
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rivos-eblot
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Dec 8, 2025
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Done, I just opened a PR instead: lowRISC/opentitan#28900 |
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Merging as CI failures are unrelated. |
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The current SRAM controller ifetch / execution enablement logic only considers that the configured
ifetchenable property should be true, in addition to the OTPHW_CFG1.EN_SRAM_IFETCHfield and the sram_ctrl CSREXEC.ENfield. This is likely based on theEXEC.ENdocumentation which states that:While this isn't incorrect, it doesn't paint the full picture. From the RTL:
In the case that the OTP iftech is disabled, the CSR value is entirely ignored and instead the value of the pervasive lifecycle controller
hw_debug_enbroadcast signal is used to determine SRAM ifetch enablement. This PR implements this functionality, retaining the behaviour that theifetchconfig property acts a disable regardless of theHW_DEBUG_ENvalue.