Release v0.4.1

.github/workflows/test.yml

@@ -0,0 +1,27 @@
+name: Test Suite
+
+on:
+  push:
+    branches: [main, devel]
+  pull_request:
+    branches: [main]
+
+jobs:
+  test:
+    runs-on: ubuntu-latest
+    timeout-minutes: 10
+    steps:
+      - uses: actions/checkout@v4
+
+      - uses: actions/setup-python@v5
+        with:
+          python-version: "3.12"
+
+      - name: Install iverilog
+        run: sudo apt-get install -y iverilog
+
+      - name: Install dependencies
+        run: pip install -e .
+
+      - name: Run test suite (HDL + Python sim)
+        run: timeout 300 python suite.py -f -j -P -n 4

.gitignore

@@ -1,7 +1,33 @@
+# Hidden files and directories
 .gitignore
 .*/
 .*
-__pycache__
+!.github/
+
+# Debugging
 debug*
+
+# Legacy output directory
 out/
+
+# Suite ignore list
 .suite_ignores
+
+# Virtual environment (uv)
+.venv/
+
+# Python bytecode
+__pycache__/
+*.pyc
+*.pyo
+
+# Polyphony compiler output
+polyphony_out/
+
+# Python packaging
+*.egg-info/
+dist/
+build/
+
+# Testing
+.pytest_cache/

.suite_ignores

@@ -1,3 +1,4 @@
+# IO: unimplemented features
 io/connect01.py
 io/connect02.py
 io/connect03.py
@@ -8,3 +9,39 @@ io/flipped03.py
 io/flipped04.py
 io/thru01.py
 io/thru02.py
+# timed: compile error
+timed/fifo01.py
+# module: compile hangs (also in v0.4.0)
+module/module04.py
+module/module05.py
+module/module06.py
+# error tests: wrong or missing error messages
+error/callable.py
+error/field_reference.py
+error/global01.py
+error/global03.py
+error/io_conflict01.py
+error/io_conflict02.py
+error/io_pipeline_read_conflict01.py
+error/io_pipeline_write_conflict01.py
+error/io_write_conflict01.py
+error/io_write_conflict02.py
+error/io_write_conflict03.py
+error/is_not_subscriptable02.py
+error/is_not_subscriptable03.py
+error/loop_var01.py
+error/module_args01.py
+error/must_be_x_type05.py
+error/must_be_x_type06.py
+error/reserved_port_name.py
+error/return_type01.py
+error/return_type02.py
+error/sub.py
+error/seq_capacity01.py
+error/seq_capacity02.py
+error/toomany_args01.py
+error/toomany_args02.py
+# warning tests: wrong or missing warnings
+warning/pipeline_hazard01.py
+warning/port_is_not_used01.py
+warning/port_is_not_used02.py

README.md

@@ -0,0 +1,48 @@
+[![Test Suite](https://github.com/ktok07b6/polyphony/actions/workflows/test.yml/badge.svg?branch=devel)](https://github.com/ktok07b6/polyphony/actions/workflows/test.yml)
+[![PyPI](https://badge.fury.io/py/polyphony.svg)](https://badge.fury.io/py/polyphony)
+[![Python](https://img.shields.io/badge/python-%3E%3D3.12-blue)](https://github.com/ktok07b6/polyphony)
+[![License](https://img.shields.io/github/license/ktok07b6/polyphony)](https://github.com/ktok07b6/polyphony/blob/main/LICENSE)
+
+# polyphony
+
+Polyphony is a Python-based High-Level Synthesis (HLS) compiler that generates synthesizable Verilog HDL from a Python subset.
+
+## Requirements
+
+- Python >= 3.12
+- Icarus Verilog (for HDL simulation)
+
+## Installation
+
+```bash
+pip install polyphony
+```
+
+## Usage
+
+```
+polyphony [-h] [-o FILE] [-d DIR] [-c CONFIG] [-v] [-D] [-hd] [-q]
+          [-vd] [-vm] [-op PREFIX] [-t TARGETS [TARGETS ...]] [-V]
+          source
+```
+
+| Option | Description |
+|--------|-------------|
+| `-o FILE, --output FILE` | output filename (default is "polyphony_out") |
+| `-d DIR, --dir DIR` | output directory |
+| `-c CONFIG, --config CONFIG` | set configuration (JSON literal or file) |
+| `-v, --verbose` | verbose output |
+| `-D, --debug` | enable debug mode |
+| `-hd, --hdl_debug` | enable HDL debug mode |
+| `-q, --quiet` | suppress warning/error messages |
+| `-vd, --verilog_dump` | output VCD file in testbench |
+| `-vm, --verilog_monitor` | enable $monitor in testbench |
+| `-V, --version` | print the Polyphony version number |
+
+## Examples
+
+See [tests](https://github.com/ktok07b6/polyphony/tree/main/tests)
+
+## License
+
+MIT License. See [LICENSE](LICENSE) for details.

error.py

@@ -47,6 +47,8 @@ def make_compile_options(casename, casefile_path, err_options, quiet_level):
     options.debug_mode = err_options.debug_mode
     options.verilog_dump = False
     options.verilog_monitor = False
+    options.hdl_debug_mode = False
+    options.targets = []
     return options
 
 

polyphony/__init__.py

@@ -1,4 +1,8 @@
 import inspect
+from typing import TYPE_CHECKING
+if TYPE_CHECKING:
+    from typing import Any
+
 from . import version
 
 __version__ = version.__version__
@@ -71,6 +75,9 @@ def init_wrapper(self, *args, **kwargs):
     cls._is_module = True
     return cls
 
+if TYPE_CHECKING:
+    module: Any  # type: ignore[no-redef]
+
 
 '''
 A decorator to mark a testbench function.
@@ -174,38 +181,53 @@ def __call__(self, **kwargs):
 
 
 def pipelined(seq, ii=-1):
-    pass
+    return seq
 
 
 def unroll(seq, factor='full'):
+    return seq
+
+
+def append_worker(fn, *args, loop=False):
     pass
 
+
 #class Reg:
 #    pass
 
 #class Net:
 #    pass
 
 
-@module
-class Channel:
-    def __init__(self, dtype:type, capacity=4):
-        pass
+if TYPE_CHECKING:
+    class Channel:
+        def __init__(self, dtype: type, capacity: int = 4) -> None: ...
+        def put(self, v: Any) -> None: ...
+        def get(self) -> Any: ...
+        def full(self) -> bool: ...
+        def empty(self) -> bool: ...
+        def will_full(self) -> bool: ...
+        def will_empty(self) -> bool: ...
+else:
+    @module
+    class Channel:
+        def __init__(self, dtype:type, capacity=4):
+            pass
 
-    def put(self, v):
-        pass
+        def put(self, v):
+            pass
 
-    def get(self):
-        pass
+        def get(self):
+            pass
 
-    def full(self):
-        pass
+        def full(self):
+            pass
 
-    def empty(self):
-        pass
+        def empty(self):
+            pass
 
-    def will_full(self):
-        pass
+        def will_full(self):
+            pass
 
-    def will_empty(self):
-        pass
+        def will_empty(self):
+            pass

polyphony/_internal/__init__.py

@@ -1,4 +1,4 @@
-__version__:str = '0.3.6'
+__version__:str = '0.4.1'
 __python__:bool = False
 
 

polyphony/_internal/_simulator.py

@@ -0,0 +1,2 @@
+def watch(*signals, vcd=None, log=None) -> None:
+    pass

polyphony/compiler/__main__.py

@@ -890,6 +890,7 @@ def setup_options(options):
     env.quiet_level = options.quiet_level if options.quiet_level else 0
     env.enable_verilog_dump = options.verilog_dump
     env.enable_verilog_monitor = options.verilog_monitor
+    env.watch_signals = getattr(options, 'watch_signals', '')
     env.targets = options.targets
     if options.config:
         try:

polyphony/compiler/ahdl/hdlgen.py

@@ -220,6 +220,7 @@ def _build_module(self):
                     if stm.dst.is_a(AHDL_VAR) and stm.dst.sig.is_net():
                         assign = AHDL_ASSIGN(stm.dst, stm.src)
                         self.hdlmodule.add_static_assignment(assign, '')
+                self.hdlmodule.remove_sig(fsm.state_var)
                 del self.hdlmodule.fsms[fsm.name]
             else:
                 self._process_fsm(fsm)