🧠 Self-Healing Cache Controller with Fault Injection & Recovery FSM

A fault-tolerant RTL cache controller capable of detecting simulated hardware faults and autonomously recovering using a dedicated Recovery Finite State Machine (FSM).

✨ Features

• Direct-mapped cache controller
• Fault injection module
• Recovery FSM
• Autonomous cache-line invalidation
• GTKWave waveform visualization
• Modular Verilog RTL design

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🏗 Architecture

CPU → Cache Controller → Fault Detection → Recovery FSM → Self-Healing

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📂 Project Structure

self_healing_cache/
├── rtl/
│   ├── cache_controller.v
│   ├── parity_checker.v
│   ├── fault_injector.v
│   └── recovery_fsm.v
├── tb/
│   └── tb_top.v
├── sim/
│   └── run.sh
└── README.md

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▶️ Running the Simulation

chmod +x sim/run.sh
./sim/run.sh

Open waveforms:

gtkwave waves/dump.vcd

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🔍 Recovery FSM Flow

IDLE → DETECT → REPAIR → RESUME → IDLE

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📸 Waveform Output

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📈 Concepts Demonstrated

• Cache architecture
• FSM design
• Fault tolerance
• Hardware verification
• RTL simulation
• Waveform debugging

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🚀 Future Improvements

• ECC / Hamming code
• 2-way set associative cache
• LRU replacement policy
• Fault logging registers
• SystemVerilog assertions

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👨‍💻 Author

B Prince Philomon