example: FixVec — pulseengine treatment of eclipse's logic_arc_int#4
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…+WIT shape
User asked for a tangible 'how would we do this in pulseengine's world'
example, derived from real eclipse-score content. FixVec is the
candidate: small (5 ops), real Rust impl on disk, well-defined typed-
graph in eclipse's logic_arc_int__b_r__fixvec + 5 logic_arc_int_op
needs.
Adds examples/pulseengine-fixvec/ with:
- rivet.yaml — self-contained rivet project (extends common + score schemas)
- artifacts/fixvec.yaml — 7 typed rivet artifacts:
1× logic-arc-int (the interface itself)
5× logic-arc-int (the five operations, linked via belongs-to)
1× comp (the component providing the interface)
1× dd-sta (detailed design, satisfies schema's sw-unit chain)
1× sw-unit (cites the actual upstream Rust file)
- arch/fixvec.aadl — spar-flavoured AADL package with typed feature
group, 5 subprogram signatures, ARP4761 safety properties, and a
component implementation declaration. Hand-authored; a real
score-to-aadl converter would emit this shape.
- arch/fixvec.wit — the WIT binary contract spar would emit from the
AADL. The file that makes the pulseengine treatment more than
eclipse's interface-as-documentation: wit-bindgen generates a
Rust trait against this contract, the impl must satisfy it at
link time. Eclipse's equivalent step doesn't exist — a dev can
rename `fn push` and the interface need stays unchanged.
- Makefile — `make validate` (always works, uses rivet),
`make aadl` and `make wit` (skip if spar not installed)
- README — concrete answer to 'what would FixVec look like in
pulseengine's world?': side-by-side mapping table, traceability
diagram showing the three-form representation, validation
instructions, explicit 'what this is not' (no working AADL build,
no full Rust component — modelling layer only)
Validation:
examples/pulseengine-fixvec/$ rivet --schemas ../../vendor/rivet-schemas validate
Result: PASS (1 warnings) # comp realizes feat — intentional gap
Full corpus also still PASS (2786 warnings, 4/4 variants). The
example is additive; it doesn't disturb the playground's existing
corpus.
This is the small/concrete worked example. The persistency::kvs
full-stack treatment is the planned follow-up (separate repo
pulseengine/example-kvs) if this lands well.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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What
A worked example under
examples/pulseengine-fixvec/showing whateclipse-score's
logic_arc_int__b_r__fixvecinterface (with its 5operations on
InlineVec<T, CAPACITY>inbaselibs_rust) looks likewhen expressed in the pulseengine stack:
validate/aadl/wittargetsWhy
User asked for a tangible how would we do this in pulseengine's world
example, derived from real eclipse-score content. FixVec is the
smallest realistic candidate.
The central operational difference the example illustrates: eclipse
models the interface as a specification (typed need-graph,
hand-maintained alongside the Rust source). Pulseengine models the
same interface as a contract (AADL → WIT → wit-bindgen-generated
Rust trait → link-time gate). The user can change
fn pushineclipse's repo and the interface need stays unchanged; in the
pulseengine treatment the build fails.
Test plan
examples/pulseengine-fixvec/$ rivet validate→ PASS (1 warning, intentional)make validatestill PASS (2786 warnings, 4/4 variants)hand-authored example; no full Rust component — modelling layer only)
Next
If this lands, the persistency::kvs full-stack example follows in a
separate repo (
pulseengine/example-kvs) per the original scopequestion.