Workaround: Change to enable USB type A ports on rb3gen2#286
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akakum-qualcomm wants to merge 12 commits intoqualcomm-linux:qcom-6.18.yfrom
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Workaround: Change to enable USB type A ports on rb3gen2#286akakum-qualcomm wants to merge 12 commits intoqualcomm-linux:qcom-6.18.yfrom
akakum-qualcomm wants to merge 12 commits intoqualcomm-linux:qcom-6.18.yfrom
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shashim-quic
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Feb 16, 2026
When creating the regulator object, associated with a consumer device, the supply_name is string formatted into a statically sized buffer on the stack, then strdup()'ed onto the heap. Not only is the dance on the stack unnecessary, but when the device's name is long we might not fit the constructed supply_name in the fixed 64 byte buffer on the stack. One such case can be seen on the Qualcomm Rb3Gen2 board, where we find a PCIe controller, with a PCIe switch, with a USB controller, with a USB hub, consuming a regulator. In this example the dev->kobj.name itself is 62 characters long. Drop the temporary buffer on the stack and kasprintf() the string directly on the heap, both to simplify the code, and to remove the length limitation. Link:https://lore.kernel.org/linux-arm-msm/177091226767.237262.6699917364293122804.b4-ty@kernel.org/T/#t Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
…USB 3.0 xHCI Host Controller Document the Renesas UPD720201/UPD720202 USB 3.0 xHCI Host Controller, which connects over PCIe and requires specific power supplies to start up. Link: https://lore.kernel.org/all/20260206-topic-sm8650-ayaneo-pocket-s2-base-v3-0-5b79c5d61a03@linaro.org/ Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
The code was not returning dev_err_probe() but dev_err_probe() returns the error code, so simplify the code. Link: https://lore.kernel.org/all/20260206-topic-sm8650-ayaneo-pocket-s2-base-v3-0-5b79c5d61a03@linaro.org/ Suggested-by: Bartosz Golaszewski <brgl@kernel.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
The driver is pretty generic and would fit for either PCI Slots or PCI devices connected to PCI ports, so rename the driver and module as pci-pwrctrl-generic. Link: https://lore.kernel.org/all/20260206-topic-sm8650-ayaneo-pocket-s2-base-v3-0-5b79c5d61a03@linaro.org/ Suggested-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
…USB 3.0 xHCI Host Controller Enable the generic pwrctrl driver to control the power of the PCIe UPD720201/UPD720202 USB 3.0 xHCI Host Controller. Link: https://lore.kernel.org/all/20260206-topic-sm8650-ayaneo-pocket-s2-base-v3-0-5b79c5d61a03@linaro.org/ Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
Enable the generic power control driver module since it's required to power up the PCIe USB3 controller found on the Ayaneo Pocket S2 gaming console. Link: https://lore.kernel.org/all/20260206-topic-sm8650-ayaneo-pocket-s2-base-v3-0-5b79c5d61a03@linaro.org/ Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
Document the Ayaneo from the Anyun Intelligent Technology (Hong Kong) Co., Ltd company. Website: https://www.ayaneo.com/product/ayaneobrand.html Link: https://lore.kernel.org/all/20260206-topic-sm8650-ayaneo-pocket-s2-base-v3-0-5b79c5d61a03@linaro.org/ Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
Document the Qualcomm SM8650 based Ayaneo Pocket S2 gaming console. Link: https://lore.kernel.org/all/20260206-topic-sm8650-ayaneo-pocket-s2-base-v3-0-5b79c5d61a03@linaro.org/ Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
Sound DAI devices exposing same set of mixers, e.g. each DisplayPort controller, need to add dedicated prefix for these mixers to avoid conflicts and to allow ALSA to properly configure given instance. Link: https://lore.kernel.org/all/20260206-topic-sm8650-ayaneo-pocket-s2-base-v3-0-5b79c5d61a03@linaro.org/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
…gaming console Add initial Device Tree for the Ayaneo Pocket S2 gaming console based on the Qualcomm Snapdragon 8 Gen 3 platform. The design is similar to a phone without the modem, the game control is handled via a standalone controller connected to a PCIe USB controller. Display panel support will be added in a second time. Signed-off-by: KancyJoe <kancy2333@outlook.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
The QCS6490 Rb3Gen2 has a Renesas μPD720201 XHCI controller hanging off the TC9563 PCIe switch, on this a Genesys Logic GL3590 USB hub provides two USB Type-A ports and an ASIX AX88179 USB 3.0 Gigabit Ethernet interface. The Renesas chip is powered by two regulators controlled through PM7250B GPIOs 1 and 4, and the power/reset pin is pulled down by PM8350C GPIO 4. The Genesys chip power is always-on, but the reset pin is controlled through TLMM GPIO 162. Describe the Renesas chip on the PCIe bus, with supplies and reset, to allow it to be brought out of reset and discovered. Then describe the two peers of the USB hub, with its reset GPIO, to allow this to be brought out of reset. The USB Type-A connectors are not described, as they are in no regard controlled by the operating system. Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> --- Posting this as a RFC, because it doesn't work without some hacks in the PCI pwrctrl code. It depends on Neil's work for μPD720201 pwrctrl [1], on the GL3590 work by Swati and Krisha [2], and my regulator fix [3]. With these three dependencies, the hacks in drivers/pci/pwrctrl/core.c, and firmware for the μPD720201, the primary ethernet lights up. Then in pci_pwrctrl_create_device() we assume that anything in a PCI device node, with either a -supply or port/ports property, should be a platform_device. When the USB bus(es) of the μPD720201 shows up, it again registers this platform_device. It seems that of_platform_device_create() saves us and does an early exit, but by "accident". __pci_pwrctrl_power_on_device() and __pci_pwrctrl_power_off_device() on the other hand, they happily pick up the non-NULL drvdata, which is of type struct onboard_dev, to call the power_on() and power_off() methods. Link: https://lore.kernel.org/all/20260212-rb3gen2-upd-gl3590-v1-1-18fb04bb32b0@oss.qualcomm.com/ Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
Enable configs to support USB typeA ports on qcs6490 rb3gen2. These configs enable Renesas μPD720201 XHCI controller and Genesys Logic GL3590 USB hub provides two USB Type-A ports and an ASIX AX88179 USB 3.0 Gigabit Ethernet interface. Signed-off-by: Akash Kumar <akash.kumar@oss.qualcomm.com>
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arm64: dts: qcom: qcs6490-rb3gen2: Enable uPD720201 and GL3590
Date: Thu, 12 Feb 2026 14:43:46 -0600 [thread overview]
Message-ID: 20260212-rb3gen2-upd-gl3590-v1-1-18fb04bb32b0@oss.qualcomm.com (raw)
The QCS6490 Rb3Gen2 has a Renesas μPD720201 XHCI controller hanging off
the TC9563 PCIe switch, on this a Genesys Logic GL3590 USB hub provides
two USB Type-A ports and an ASIX AX88179 USB 3.0 Gigabit Ethernet
interface.
The Renesas chip is powered by two regulators controlled through PM7250B
GPIOs 1 and 4, and the power/reset pin is pulled down by PM8350C GPIO 4.
The Genesys chip power is always-on, but the reset pin is controlled
through TLMM GPIO 162.
Describe the Renesas chip on the PCIe bus, with supplies and reset, to
allow it to be brought out of reset and discovered. Then describe the
two peers of the USB hub, with its reset GPIO, to allow this to be
brought out of reset.
The USB Type-A connectors are not described, as they are in no regard
controlled by the operating system.
Signed-off-by: Bjorn Andersson bjorn.andersson@oss.qualcomm.com
Posting this as a RFC, because it doesn't work without some hacks in the
PCI pwrctrl code. It depends on Neil's work for μPD720201 pwrctrl [1],
on the GL3590 work by Swati and Krisha [2], and my regulator fix [3].
With these three dependencies, the hacks in drivers/pci/pwrctrl/core.c,
and firmware for the μPD720201, the primary ethernet lights up.
Then in pci_pwrctrl_create_device() we assume that anything in a PCI
device node, with either a -supply or port/ports property, should be a
platform_device. When the USB bus(es) of the μPD720201 shows up, it
again registers this platform_device. It seems that
of_platform_device_create() saves us and does an early exit, but by
"accident".
__pci_pwrctrl_power_on_device() and __pci_pwrctrl_power_off_device() on
the other hand, they happily pick up the non-NULL drvdata, which is of
type struct onboard_dev, to call the power_on() and power_off() methods.
It's not clear to me why the whole board resets at this point, but I
don't think we can assume that any random platform_device we find at any
level below the PCIe bus has a drvdata of type struct pci_pwrctrl...
[1] https://lore.kernel.org/all/20260206-topic-sm8650-ayaneo-pocket-s2-base-v3-0-5b79c5d61a03@linaro.org/
[2] https://lore.kernel.org/all/20260122092852.887624-1-swati.agarwal@oss.qualcomm.com/
[3] https://lore.kernel.org/linux-arm-msm/177091226767.237262.6699917364293122804.b4-ty@kernel.org/T/#t
CR Fixed: 4440584