qcom: Update qualcomm platform SOCs with SMEM, FIT multi-DTB, PSCI, USB/PHY fixes#2
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aswinm94 wants to merge 18 commits intoqualcomm-linux:qcom-nextfrom
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qcom: Update qualcomm platform SOCs with SMEM, FIT multi-DTB, PSCI, USB/PHY fixes#2aswinm94 wants to merge 18 commits intoqualcomm-linux:qcom-nextfrom
aswinm94 wants to merge 18 commits intoqualcomm-linux:qcom-nextfrom
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Do FAT read and write based on the device sector size instead of the size recorded in the FAT meta data. FAT code issues i/o in terms of the sector size. Convert that to device sector size before doing the actual i/o. Additionally, handle leading/trailing blocks when the meta data based block no and i/o size is not an exact multiple of the device sector size or vice versa. Tested on UFS device with sector size 4096 and meta data recorded sector size 512. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Add cached access functions for commonly used SMEM data to reduce redundant SMEM lookups across the boot process. This patch introduces three generic caching functions: - qcom_get_smem_device(): Cached SMEM device access - qcom_get_socinfo(): Cached socinfo structure access - qcom_get_ram_partitions(): Cached RAM partition table access The implementation includes new header files for data structures: - include/soc/qcom/socinfo.h: Added socinfo header from Linux [1] Provides socinfo structure definitions for SoC identification and hardware parameters - arch/arm/mach-snapdragon/rampart.h: Provides RAM partition table structures for memory layout information The caching mechanism initializes SMEM data on first access and returns cached pointers on subsequent calls, avoiding expensive SMEM lookups during boot. This infrastructure is designed to be reusable by other Qualcomm-specific features that require hardware information from SMEM. The functions provide a clean API for accessing: - SoC information (chip ID, version, platform details) - RAM partition layout for memory size calculations - Hardware parameters needed for device-specific configurations [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/linux/soc/qcom/socinfo.h?id=7dcc1dfaa3d1cd3aafed2beb7086ed34fdb22303 Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Implement multi DTB selection from FIT images based on hardware detection via SMEM. The implementation provides: 1. Hardware Detection: Reads SoC parameters from SMEM including chip ID, version, platform ID, OEM variant, DDR size, and storage type from IMEM. 2. Metadata DTB Processing: Parses a metadata DTB (first image in FIT) to build a "bucket list" of hardware-specific node names that match the detected hardware parameters. 3. FIT Configuration Matching: Uses standard FIT mechanisms to find the configuration with the most matching tokens in its compatible string compared to the hardware-derived bucket list. 4. DTB Loading and Overlays: Loads the base DTB and applies any DTBOs specified in the selected configuration using standard FIT overlay application. 5. EFI Integration: Loads selected dtb from qclinux_fit.img and sets fdt_addr for use by the EFI boot flow. This enables multi DTB selection across hardware variants. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Enable CONFIG_QCOM_FIT_MULTIDTB and CONFIG_OF_LIBFDT_OVERLAY by default for Qualcomm Snapdragon platforms to provide automatic DTB selection from qclinux_fit.img with overlay support. This allows U-Boot to automatically select the appropriate device tree based on hardware parameters detected from SMEM, improving boot compatibility across different hardware variants and reducing the need for board-specific DTB selection logic. Additionally, configure platform-specific IMEM sizes required for storage type detection: - QCM6490 and QCS615: 0x2B000 - QCS9100: 0x59000 The IMEM size configuration enables proper shared IMEM cookie access for boot device type detection (UFS/eMMC/NAND), which is essential for the FIT multi-DTB selection process. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
…ications of board information, DDR configuration, and hardware subset parts through the OF_LIVE interface.
This patch introduces three fixup handlers that modify the device tree
at runtime to provide platform-specific information from SMEM:
1. Board info fixup (qcom_fixup_boardinfo.c)
- Adds board-specific information like serial number to the
device tree
2. DDR info fixup (qcom_fixup_ddrinfo.c)
- Adds DDR configuration information like DDR size & regions
3. Subset parts fixup (qcom_fixup_subsetparts.c)
- Identifies & enables OS to adapt to available hardware subparts
(GPU, video, camera, display, audio, modem, WLAN, compute,
sensors, NPU, disabled CPU cores, etc.)
Supporting headers:
- qcom_fixup_handlers.h: Function prototypes and type definitions
- chipinfo_def.h: Chip identification and part definitions
Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Previously, U-Boot’s PSCI-based implementation of `efi_reset_system()` was always enabled when `CONFIG_PSCI_RESET` was set, but it did not handle additional arguments required for specialized reset modes. This caused issues where special reboot requests (e.g., bootloader, EDL) were ignored, resulting in a normal reboot. This change introduces a new configuration option, `CONFIG_EFI_PSCI_RESET_RUNTIME`, to explicitly control whether the runtime PSCI-specific EFI reset implementation is enabled. By default, the PSCI EFI reset is enabled, it can be disabled at platform defconfig allowing the kernel to handle the reset logic and pass the necessary arguments for the intended reset mode correctly. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Disable CONFIG_EFI_PSCI_RESET_RUNTIME in qcom_defconfig to let the kernel manage reset modes and handle specialized reboot requests correctly. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Add functionality to detect and handle reboot-to-bootloader requests by reading PMIC PON (Power On) registers. When the device is rebooted with the bootloader flag set, U-Boot will automatically enter fastboot mode. This implementation supports multiple PMIC generations: - Gen 4 PMICs: Uses PON_SOFT_RB_SPARE register (0x88F) - Newer PMICs: Uses SDAM-based PON_REBOOT_REASON register (0x7148) The PMIC model is automatically detected via revision ID registers to determine the correct register addresses. After detecting a fastboot reboot reason, the register is cleared and fastboot mode is entered via the "run fastboot" command. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Implemented platform-specific reserved memory registration for EFI on Qualcomm Snapdragon platforms. This adds SoC-specific memory regions to the EFI memory map. Added qcom_reserved_memory.c with predefined memory regions for QCS615 and QCM6490/SC7280 SoCs. The implementation detects the SoC type from device tree and registers appropriate memory regions via efi_add_memory_map(). Implemented efi_add_known_memory() in board.c to hook into the EFI memory initialization. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Remove GCC_USB3_PRIM_CLKREF_CLK from the USB controller node as it is not implemented in the U-Boot clock driver. Keep only the supported clocks to avoid clock warnings during boot. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615 clock driver. This clock is required for proper PHY operation and eliminates clock-related warnings during USB initialization. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Add support for QCS615 QUSB2 PHY by introducing platform-specific
initialization table and register layout. The implementation reuses
the IPQ6018 register layout and defines QCS615-specific tuning
parameters for proper USB PHY operation.
Taken from Linux commit 8adbf20e0502 ("phy: qcom-qusb2: Add support for QCS615")
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Change USB controller dr_mode from "host" to "peripheral" to enable fastboot support on the QCS6490 RB3Gen2 board. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Add support for GCC_USB3_PRIM_PHY_PIPE_CLK which is required by the USB3 PHY on SC7280/QCM6490 platforms. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Add a 100 ms delay after clearing the core soft reset bit to ensure the DWC3 controller has sufficient time to complete its reset sequence before subsequent register accesses. Without this delay, USB initialization can fail on some Qualcomm platforms, particularly when using super-speed capable PHYs like the QMP USB3-DP Combo PHY on SC7280/QCM6490. Taken from Linux commit f88359e ("usb: dwc3: core: Do core softreset when switch mode") Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Add support for the Qualcomm QMP USB3-DP Combo PHY found on
SC7280 and QCM6490 platforms. This driver currently implements
USB3 super-speed functionality of the combo PHY.
The QMP Combo PHY is a dual-mode PHY
that can operate in either USB3 mode or DisplayPort mode. This
initial implementation focuses on USB3 mode to enable Super-Speed
USB support.
Taken from Linux commit 3d25d46a255a ("pmdomain: qcom: rpmhpd: Add rpmhpd support for SM8750")
This patch is dependent on this patch: https://lore.kernel.org/u-boot/20251112164204.1557934-1-aswin.murugan@oss.qualcomm.com/
Enabled and tested the driver on Qualcomm RB3 Gen2 (QCS6490) board.
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Automatically detect super-speed USB PHY driver availability and skip the USB speed fixup if driver is available, eliminating the need for manual configuration. Previously, U-Boot unconditionally limited USB to high-speed mode on all Qualcomm platforms because most lacked super-speed PHY drivers. This change implements runtime detection that checks if a PHY driver exists for the super-speed PHY node referenced by the DWC3 controller. The fixup is automatically skipped when a compatible driver is found, allowing the hardware to operate at full capability. Platforms without super-speed PHY drivers continue to receive the fixup automatically.
Enable the QMP Combo PHY driver to allow super-speed USB operation on QCM6490 platforms. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Member
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@aswinm94 split this PR into multiple PRs adding patches per feature. That's the approach we need to follow to carefully review upstream discussions alongside a feature. The multi-dtb feature especially where the discussions are still ongoing related to how secure boot feature is expected to work. So we shouldn't merge such feature as of now as otherwise it will become an ABI. |
Author
@b49020 , sure will split this PR |
Member
The upstream DTB bundled in U-Boot image does enables kernel booting. Would that approach work until we sort out proper upstream FIT support with signatures? |
Author
@b49020 , will confirm the booting with upstream DTS |
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This PR aggregates a series of upstream‑submitted patches improving FAT handling, SMEM infra, FIT multi‑DTB boot, PSCI reset handling, USB3/PHY support, and clock updates across QCS615/QCS6490/Snapdragon platforms.
Each commit corresponds to an already‑submitted upstream patch.
Links to the upstream posts are included for reviewer reference.
Commits Summary
fs: fat: Handle FAT sector size mismatch
https://lore.kernel.org/all/20260122063442.2622684-1-balaji.selvanathan@oss.qualcomm.com/
mach: snapdragon: Add generic SMEM cache infrastructure
https://lore.kernel.org/all/20260129184817.224101-2-aswin.murugan@oss.qualcomm.com/
mach: snapdragon: Add FIT multi‑DTB selection support
https://lore.kernel.org/all/20260129184817.224101-3-aswin.murugan@oss.qualcomm.com/
configs: snapdragon: Enable FIT multi‑DTB & configuration support
https://lore.kernel.org/all/20260129184817.224101-4-aswin.murugan@oss.qualcomm.com/
dts: Add device‑tree fixup handler infrastructure
https://lore.kernel.org/all/20260113115404.1448759-1-aswin.murugan@oss.qualcomm.com/
firmware: psci: Refactor EFI runtime PSCI reset handling
https://lore.kernel.org/all/20260114111624.2321852-2-aswin.murugan@oss.qualcomm.com/
qcom_defconfig: Disable CONFIG_EFI_PSCI_RESET_RUNTIME
https://lore.kernel.org/all/20260114111624.2321852-3-aswin.murugan@oss.qualcomm.com/
mach: snapdragon: Add fastboot reboot‑reason support
https://lore.kernel.org/all/20260108065533.1143179-1-aswin.murugan@oss.qualcomm.com/
arm: snapdragon: Add EFI reserved memory regions for QCS platforms
https://lore.kernel.org/all/20260107091406.2428132-1-balaji.selvanathan@oss.qualcomm.com/
dts: qcs615‑ride: Remove unsupported USB clock reference
https://lore.kernel.org/all/20251114063804.3835132-2-balaji.selvanathan@oss.qualcomm.com/
clk: qcom: qcs615: Add GCC_AHB2PHY_WEST_CLK support
https://lore.kernel.org/all/20260120042551.650113-3-balaji.selvanathan@oss.qualcomm.com/
phy: qcom: qusb2: Add QCS615 QUSB2 PHY support
https://lore.kernel.org/all/20260120042551.650113-4-balaji.selvanathan@oss.qualcomm.com/
dts: qcs6490-rb3gen2: Switch USB controller to peripheral mode
https://lore.kernel.org/all/20251114064042.3835312-1-balaji.selvanathan@oss.qualcomm.com/
clk: qcom: sc7280: Add USB3 PHY pipe clock
https://lore.kernel.org/all/20251203110735.1959862-2-balaji.selvanathan@oss.qualcomm.com/
usb: dwc3: Add delay after core soft reset
https://lore.kernel.org/all/20251203110735.1959862-3-balaji.selvanathan@oss.qualcomm.com/
phy: qcom: Add QMP USB3/DP Combo PHY driver
https://lore.kernel.org/all/20251203110735.1959862-4-balaji.selvanathan@oss.qualcomm.com/
mach: snapdragon: Auto‑detect USB SSPHY driver
https://lore.kernel.org/all/20251203110735.1959862-5-balaji.selvanathan@oss.qualcomm.com/
configs: qcm6490: Enable super‑speed USB support
https://lore.kernel.org/all/20251203110735.1959862-6-balaji.selvanathan@oss.qualcomm.com/