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Let's split this patch-set again per SoC wise and keep only the patch-set needed in the PR. |
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@b49020 , To prevent merge conflicts, the current branch was derived from the previous PR branch, which is why this PR displays all the commits from that earlier branch. |
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@aswinm94 let's rather just put one patch-set in a PR and try to resolve merge conflicts while merging. This way it's not possible to merge in a non-sequential order. |
Remove GCC_USB3_PRIM_CLKREF_CLK from the USB controller node as it is not implemented in the U-Boot clock driver. Keep only the supported clocks to avoid clock warnings during boot. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615 clock driver. This clock is required for proper PHY operation and eliminates clock-related warnings during USB initialization. Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Add support for QCS615 QUSB2 PHY by introducing platform-specific
initialization table and register layout. The implementation reuses
the IPQ6018 register layout and defines QCS615-specific tuning
parameters for proper USB PHY operation.
Taken from Linux commit 8adbf20e0502 ("phy: qcom-qusb2: Add support for QCS615")
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
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This PR introduces comprehensive USB functionality improvements on Qualcomm platform QCS615.
QCS615: Enables USB High‑Speed by correcting clock configurations and adding QUSB2 PHY support.
upstream link: https://lore.kernel.org/all/20251114063804.3835132-1-balaji.selvanathan@oss.qualcomm.com/
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