A conceptual model for real-time, intra-frame hardware scaling to eliminate gaming micro-stutters and minimize input latency.
An open-source architectural concept for dynamic hardware frequency scaling, prioritizing zero-hitch performance and ultra-low input latency during real-time rendering pipelines.
Traditional Dynamic Voltage and Frequency Scaling (DVFS) algorithms look backward—using the execution time of past frames to guess the power requirements of the current frame. This leaves systems vulnerable to sudden workload spikes, resulting in dropped frames and micro-stuts.
This model shifts the paradigm to Intra-Frame Micro-Tracking. It treates every single frame as an isolated, self-correcting deadline by tracking the velocity of completion in real-time.
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Real-Time Sampling: The GPU/CPU execution pipeline is sampled at micro-intervals (e.g., every 0.5ms) to compare the percentage of workload completed against the remaining time before the monitor's vertical refresh deadline.
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Preemptive Deficit Correction: If the completion percentage falls even a fraction behind the ideal timeline, the algorithm aggressively ramps up clock speeds and power to crush the bottleneck early.
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Graceful Coasting: Once a safe completion margin is secured, the hardware dynamically ramps down to a stable, mid-tier idle speed ("Decent Idle State") to save power and reduce thermal accumulation without incurring wake-up latency (
C-statelag) for the next frame.
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Zero-Hitch Frame Pacing: Eliminates micro-stutters caused by sudden asset loading or particle spikes by adapting mid-frame.
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Ultra-Low Input Latency: Front-loads heavy execution blocks to ensure the frame is ready as early as safely possible.
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Thermal Control via Coasting: Avoids the excessive heat of running at 100% flat out by allowing the silicon to cool down during verified safety margins at the end of a frame cycle.
Credits : Sighthough , Google Gemini 3.5 flash ai MIT licence included in the directory