PolarFire SoC M-Mode, QSPI and L2-LIM support by dgarske · Pull Request #667 · wolfSSL/wolfBoot

dgarske · 2026-01-13T20:45:38Z

Adds support for running wolfBoot in Machine Mode (M-mode) on the PolarFire SoC MPFS250T, booting from eNVM and loading a signed application from SC QSPI flash into on-chip LIM (Loosely Integrated Memory). No HSS (Hart Software Services) or DDR is required. It also extends the existing PolarFire HAL with multi-hart support, L2 cache configuration, per-hart UART, and refactors shared code (SDHCI, SCB mailbox, linker/test-app) for both S-mode and M-mode builds.

Copilot

Pull request overview

This PR adds Machine Mode (M-mode) support for PolarFire SoC MPFS250T, enabling wolfBoot to run directly from eNVM without requiring HSS (Hart Software Services) or DDR. The implementation boots from eNVM, executes from L2 Scratchpad SRAM, and loads signed applications from SC QSPI flash into on-chip LIM.

Changes:

Added M-mode boot path with multi-hart support, L2 cache configuration, and per-hart UART
Extended HAL with SC QSPI flash driver and UART-based QSPI programmer
Refactored shared code (SDHCI, SCB mailbox, linker scripts) for both S-mode and M-mode builds

Reviewed changes

Copilot reviewed 19 out of 19 changed files in this pull request and generated 7 comments.

Show a summary per file

File	Description
test-app/vector_riscv.S	Simplified to use mret for M-mode payload
test-app/startup_riscv.c	Updated to use M-mode CSRs (mtvec, mcause)
test-app/app_mpfs250.c	Removed duplicate UART/HAL init to avoid clearing TX FIFO
test-app/RISCV64-mpfs250.ld	Added dummy _main_hart_hls symbol
src/vector_riscv.S	Refactored to use MODE_PREFIX macro for CSR access
src/update_disk.c	Fixed unused variable warning with conditional compilation
src/sdhci.c	Moved power init into card init, added udelay helper, refined debug flags
src/boot_riscv_start.S	Added comprehensive M-mode boot sequence with eNVM-to-L2 copy
src/boot_riscv.c	Added M-mode to S-mode transition support and direct M-mode jump
hal/riscv.h	Extended with CLINT, L2 cache, and additional MSTATUS definitions
hal/mpfs250.h	Added L2 cache, UART mapping, HLS structures, and M-mode peripherals
hal/mpfs250.c	Refactored with L2 init, multi-hart support, and UART QSPI programmer
hal/mpfs250-m.ld	New M-mode linker script for eNVM + L2 SRAM layout
docs/Targets.md	Added M-mode documentation and updated S-mode references
config/examples/polarfire_mpfs250_m_qspi.config	New M-mode configuration file
config/examples/polarfire_mpfs250.config	Updated DTS comment and debug flag name
arch.mk	Added M-mode vs S-mode build logic with appropriate flags
.github/workflows/test-configs.yml	Added CI tests for M-mode configs
.gdbinit	Updated for RISC-V debugging

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src/boot_riscv.c

hal/mpfs250.c

src/sdhci.c

.gdbinit

hal/mpfs250.c

Copilot

Pull request overview

Copilot reviewed 20 out of 20 changed files in this pull request and generated 8 comments.

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tools/scripts/mpfs_qspi_prog.py

src/update_disk.c

src/sdhci.c

src/boot_riscv_start.S

src/boot_riscv.c

hal/riscv.h

hal/mpfs250.c

.gdbinit

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Pull request overview

Copilot reviewed 21 out of 21 changed files in this pull request and generated 13 comments.

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test-app/vector_riscv.S

test-app/startup_riscv.c

src/boot_riscv_start.S

docs/Targets.md

src/sdhci.c

hal/mpfs250.c

Copilot

Pull request overview

Copilot reviewed 24 out of 24 changed files in this pull request and generated 13 comments.

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src/boot_riscv_start.S

hal/mpfs250.c

config/examples/polarfire_mpfs250_m_qspi.config

src/boot_riscv.c

test-app/startup_riscv.c

tools/scripts/mpfs_qspi_prog.py

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Copilot reviewed 27 out of 28 changed files in this pull request and generated 9 comments.

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src/boot_riscv_start.S

hal/mpfs250-m.ld

hal/riscv.h

.github/workflows/test-configs.yml

.github/workflows/test-build-riscv.yml

src/boot_riscv_start.S

hal/mpfs250.c

Adds support for running wolfBoot in **Machine Mode (M-mode)** on the PolarFire SoC MPFS250T, booting from eNVM and loading a signed application from **SC QSPI flash** into on-chip LIM (Loosely Integrated Memory). No HSS (Hart Software Services) or DDR is required. It also extends the existing PolarFire HAL with multi-hart support, L2 cache configuration, per-hart UART, and refactors shared code (SDHCI, SCB mailbox, linker/test-app) for both S-mode and M-mode builds.

Copilot

Pull request overview

Copilot reviewed 26 out of 27 changed files in this pull request and generated 3 comments.

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hal/mpfs250.c

src/sdhci.c

hal/riscv.h

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Copilot reviewed 27 out of 28 changed files in this pull request and generated 4 comments.

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Copilot · 2026-03-06T18:28:16Z

src/boot_riscv_start.S

+    /* Set up per-hart stack: base + (hartid+1)*STACK_SIZE_PER_HART */
+    csrr  a0, mhartid
+    la    t0, _secondary_hart_stack_base
+    li    t1, STACK_SIZE_PER_HART
+    addi  a1, a0, 1
+    mul   t2, a1, t1


The secondary-hart stack calculation uses (hartid + 1) * STACK_SIZE_PER_HART. With _secondary_hart_stack_base sized for only 4 secondary stacks, hart 4 computes an SP that can land above the secondary region and overlap the main stack. Use hartid * STACK_SIZE_PER_HART (for harts 1–4) or expand the reserved region/base to match the (hartid+1) indexing scheme.

Suggested change

/* Set up per-hart stack: base + (hartid+1)*STACK_SIZE_PER_HART */

csrr a0, mhartid

la t0, _secondary_hart_stack_base

li t1, STACK_SIZE_PER_HART

addi a1, a0, 1

mul t2, a1, t1

/* Set up per-hart stack: base + hartid*STACK_SIZE_PER_HART */

csrr a0, mhartid

la t0, _secondary_hart_stack_base

li t1, STACK_SIZE_PER_HART

mul t2, a0, t1

Copilot · 2026-03-06T18:28:17Z

hal/mpfs250.c

+    timeout = 10000;
+    while ((SCBCTRL_REG(SERVICES_CR_OFFSET) & SERVICES_CR_REQ_MASK) && timeout > 0) {
+        timeout--;
    }
-
-    if (mpfs_scb_wait_clear(SERVICES_SR_OFFSET, SERVICES_SR_BUSY_MASK,
-            timeout) < 0) {
+    if (timeout == 0) {
+        wolfBoot_printf("SCB mailbox request timeout\n");
        return -3;
    }

-    status = (SCBCTRL_REG(SERVICES_SR_OFFSET) >> SERVICES_SR_STATUS_SHIFT)
-        & 0xFFFF;
-    if (status != 0) {
-        return -4;
+    /* Wait for busy bit to clear (command completed) */
+    timeout = 10000;
+    while (mpfs_scb_mailbox_busy() && timeout > 0) {
+        timeout--;
    }


These SCB mailbox wait loops decrement a small fixed counter without any delay, so timeouts will elapse extremely quickly on a fast core and can fail even when the SCB would complete normally. Consider using a time-based timeout (e.g., hal_get_timer_us) or at least include a bounded delay per iteration, and/or reuse the existing mpfs_scb_wait_clear() with a meaningful timeout value.

Copilot · 2026-03-06T18:28:17Z

hal/mpfs250.h

+    volatile uint32_t shared_mem_marker; /* 0x08: Init marker */
+    volatile uint32_t shared_mem_status; /* 0x0C: Status */
+    volatile uint64_t* shared_mem;       /* 0x10: Shared memory pointer */
+    volatile uint64_t reserved[2];       /* 0x18: Reserved/padding */


HLS_DATA is annotated as 64 bytes, but the fields shown total 40 bytes on RV64 (16 bytes of u32s + 8-byte pointer + 16 bytes reserved). This is easy to get wrong given the assembly allocates/clears 64 bytes for HLS. Either adjust the struct padding to actually be 64 bytes (e.g., increase the reserved space) or correct the size/comments and ensure all users agree on the layout.

Suggested change

volatile uint64_t reserved[2]; /* 0x18: Reserved/padding */

volatile uint64_t reserved[5]; /* 0x18: Reserved/padding to 64 bytes total */

Copilot · 2026-03-06T18:28:17Z

docs/Targets.md

+| Configuration | Config File | Boot Mode | Storage | Memory | HSS |
+|---------------|-------------|-----------|---------|--------|-----|
+| **SDCard** | `polarfire_mpfs250.config` | S-mode (U54 via HSS) | SD Card | DDR | Yes |
+| **eMMC** | `polarfire_mpfs250.config` + `DISK_EMMC=1` | S-mode (U54 via HSS) | eMMC | DDR | Yes |
+| **QSPI (S-mode)** | `polarfire_mpfs250_qspi.config` | S-mode (U54 via HSS) | MSS or SC QSPI | DDR | Yes |
+| **QSPI + L2-LIM** | `polarfire_mpfs250_hss_l2lim.config` | S-mode (U54 via HSS) | SC QSPI | L2-LIM (no DDR) | Yes |
+| **M-Mode (no HSS)** | `polarfire_mpfs250_m_qspi.config` | M-mode (E51, no HSS) | SC QSPI | L2 Scratchpad | No |


These markdown tables start each row with ||, which typically renders as an extra empty column (or breaks table formatting depending on the renderer). Use a single leading | for proper GitHub-flavored markdown tables.

dgarske self-assigned this Jan 21, 2026

dgarske force-pushed the polarfire_soc_m branch from eba460a to c9486a9 Compare February 13, 2026 23:59

dgarske changed the title ~~PolarFire SoC M-Mode Support with DDR Initialization~~ PolarFire SoC M-Mode Support with SC QSPI Flash Feb 20, 2026

dgarske force-pushed the polarfire_soc_m branch from c9486a9 to acfd97b Compare February 20, 2026 00:06

dgarske marked this pull request as ready for review February 20, 2026 00:06

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dgarske changed the title ~~PolarFire SoC M-Mode Support with SC QSPI Flash~~ PolarFire SoC M-Mode, QSPI and L2-LIM support Mar 6, 2026

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Documentation improvements. Peer review fixes

bc95fc5

dgarske assigned danielinux and unassigned dgarske Mar 6, 2026

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dgarske assigned dgarske and unassigned danielinux Mar 6, 2026

Fix CI build errors

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	volatile uint64_t reserved[2]; /* 0x18: Reserved/padding */
	volatile uint64_t reserved[5]; /* 0x18: Reserved/padding to 64 bytes total */

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dgarske commented Jan 13, 2026 •

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