Microprocessor Architecture

project 1: Cache Design, Memory Hierarchy Design (C++)

• Designed a flexible cache and memory hierarchy simulator to simulate different cache sizes, associations, hierarchies.
• Developed caches with LRU (least-recently-used) replacement policy and WBWA (write-back + write-allocate) policy.
• Implemented victim cache between L1 and L2 cache to decrease L1 cache miss rate.

project 2: Branch Prediction (C++)

project 3: Dynamic Instruction Scheduling (C++)

Note: Project 4, 5, 6, 7 is based on an OOO(out-of-order) superscalar microarchitecture

project 4: ILP Limit Study (C++)

project 5: Register File and Renaming (C++)

• Implemented AMT(Architectural Map Table), RMT(Rename Map Table), Active List, Free List, PRF(Physical Register File) to rename register and read register value.
• Implemented GBM(Global Branch Mask), Branch Checkpoints to resolve and recover branch.