Submission of 8 Digital Verilog IPs - Bellana Venkata Chaitanya My digital ips submission

[chaitubellana-droid]

Respected Mr. Sumanto Kar SIR and Ms. Shanthi Priya K Mam,

I am submitting a single Pull Request containing 8 separate digital IP cores, each cleanly packaged into its own individual commit with structured project files and complete Markdown documentation as requested.

Included IPs:

1. 8-bit Arithmetic Logic Unit (Alu20_8)
2. 8-bit Sequential Signed Booth Multiplier (BoothMultiplier19_17)
3. 16-bit Sequential CORDIC Core (Cordic19_33)
4. 16-bit Hierarchical Leading Zero Counter (LeadingzeroCnt16_5)
5. 8-bit Ladner-Fischer Parallel Prefix Adder (LFadder17_9)
6. 8-bit Combinational Non-Restoring Divider (Non-Res-Divider16_17)
7. Synchronous SPI Master/Multi-Slave Controller Subsystem (SPIprotocol20_25)
8. 7:3 Thermometer-to-Binary Wallace Tree Encoder (wallaceEncoder7_3)

Please review my submission. Thank you!