Submission of 8 Digital Verilog IPs - Bellana Venkata Chaitanya My digital ips submission

Alu20_8/README.md

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+# 8-bit Arithmetic Logic Unit (ALU) IP
+
+## 1. Description
+This IP core implements an 8-bit Arithmetic Logic Unit (ALU) designed in Verilog HDL. The module is entirely combinational and performs a wide array of mathematical, logical, shifting, and comparison operations based on a 4-bit selection input (`ALU_Sel`). It is structured to serve as a foundational execution unit within a digital processor or processor-subcircuit architecture.
+
+---
+
+## 2. Block Diagram
+The architectural block diagram below illustrates the inputs, outputs, and internal control flow of the ALU module:
+![8-bit ALU Block Diagram](alu_block_diagram.png)

Alu20_8/Verilog Files/alu_8bit.v

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+module alu_8bit (
+    input  [7:0] A, B,      
+    input  [3:0]       ALU_Sel,  
+    output reg [7:0] ALU_Out
+);
+
+    always @(*) begin
+        case(ALU_Sel)
+
+            4'b0000: ALU_Out = A + B;        // Addition
+            4'b0001: ALU_Out = A - B;        // Subtraction
+            4'b0010: ALU_Out = A * B;        // Multiplication
+            4'b0011: ALU_Out = A / B;        // Division
+            4'b0100: ALU_Out = A << 1;       // Logical shift left
+            4'b0101: ALU_Out = A >> 1;       // Logical shift right
+            4'b0110: ALU_Out = ~A;           // Logical NOT (Unary)
+            4'b0111: ALU_Out = A & B;        // Logical AND
+            4'b1000: ALU_Out = A | B;        // Logical OR
+            4'b1001: ALU_Out = A ^ B;        // Logical XOR
+            4'b1010: ALU_Out = ~(A ^ B);     // Logical XNOR
+            4'b1011: ALU_Out = ~(A & B);     // Logical NAND
+            4'b1100: ALU_Out = ~(A | B);     // Logical NOR
+            4'b1101: ALU_Out = (A < B) ? 1'b1 : 1'b0;  // Less than
+            4'b1110: ALU_Out = (A == B) ? 1'b1 : 1'b0; // Equality
+            4'b1111: ALU_Out = (A > B) ? 1'b1 : 1'b0;  // Greater than (Last Case)
+
+            default: ALU_Out = {8{1'b0}};
+        endcase
+    end
+
+endmodule

Alu20_8/eSim Test Circuit Project Files/alu_subcircuit-cache.lib

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+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_4
+#
+DEF adc_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_8
+#
+DEF adc_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# alu_8bit
+#
+DEF alu_8bit U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "alu_8bit" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 -200 0 1 0 N
+X A7 1 2150 1900 200 R 50 50 1 1 I
+X A6 2 2150 1800 200 R 50 50 1 1 I
+X A5 3 2150 1700 200 R 50 50 1 1 I
+X A4 4 2150 1600 200 R 50 50 1 1 I
+X A3 5 2150 1500 200 R 50 50 1 1 I
+X A2 6 2150 1400 200 R 50 50 1 1 I
+X A1 7 2150 1300 200 R 50 50 1 1 I
+X A0 8 2150 1200 200 R 50 50 1 1 I
+X B7 9 2150 1100 200 R 50 50 1 1 I
+X B6 10 2150 1000 200 R 50 50 1 1 I
+X ALU_Sel0 20 2150 0 200 R 50 50 1 1 I
+X B5 11 2150 900 200 R 50 50 1 1 I
+X ALU_Out7 21 3550 1900 200 L 50 50 1 1 O
+X B4 12 2150 800 200 R 50 50 1 1 I
+X ALU_Out6 22 3550 1800 200 L 50 50 1 1 O
+X B3 13 2150 700 200 R 50 50 1 1 I
+X ALU_Out5 23 3550 1700 200 L 50 50 1 1 O
+X B2 14 2150 600 200 R 50 50 1 1 I
+X ALU_Out4 24 3550 1600 200 L 50 50 1 1 O
+X B1 15 2150 500 200 R 50 50 1 1 I
+X ALU_Out3 25 3550 1500 200 L 50 50 1 1 O
+X B0 16 2150 400 200 R 50 50 1 1 I
+X ALU_Out2 26 3550 1400 200 L 50 50 1 1 O
+X ALU_Sel3 17 2150 300 200 R 50 50 1 1 I
+X ALU_Out1 27 3550 1300 200 L 50 50 1 1 O
+X ALU_Sel2 18 2150 200 200 R 50 50 1 1 I
+X ALU_Out0 28 3550 1200 200 L 50 50 1 1 O
+X ALU_Sel1 19 2150 100 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_8
+#
+DEF dac_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library

Alu20_8/eSim Test Circuit Project Files/alu_subcircuit.cir

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+* C:\FOSSEE\eSim\library\SubcircuitLibrary\alu_subcircuit\alu_subcircuit.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/23/26 14:07:33
+
+* Sheet Name: /
+
+a1 [pin_a7 pin_a6 pin_a5 pin_a4 pin_a3 pin_a2 pin_a1 pin_a0] [pin_b7 pin_b6 pin_b5 pin_b4 pin_b3 pin_b2 pin_b1 pin_b0] [pin_sel3 pin_sel2 pin_sel1 pin_sel0] [pin_out7 pin_out6 pin_out5 pin_out4 pin_out3 pin_out2 pin_out1 pin_out0] u1
+a2 [net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_] [pin_a7 pin_a6 pin_a5 pin_a4 pin_a3 pin_a2 pin_a1 pin_a0] u3
+a3 [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_] [pin_b7 pin_b6 pin_b5 pin_b4 pin_b3 pin_b2 pin_b1 pin_b0] u4
+a4 [net-_u2-pad17_ net-_u2-pad18_ net-_u2-pad19_ net-_u2-pad20_] [pin_sel3 pin_sel2 pin_sel1 pin_sel0] u5
+a5 [pin_out7 pin_out6 pin_out5 pin_out4 pin_out3 pin_out2 pin_out1 pin_out0] [net-_u2-pad21_ net-_u2-pad22_ net-_u2-pad23_ net-_u2-pad24_ net-_u2-pad25_ net-_u2-pad26_ net-_u6-pad15_ net-_u6-pad16_] u6
+
+U2  net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ net-_u2-pad17_ net-_u2-pad18_ net-_u2-pad19_ net-_u2-pad20_ net-_u2-pad21_ net-_u2-pad22_ net-_u2-pad23_ net-_u2-pad24_ net-_u2-pad25_ net-_u2-pad26_ PORT
+U7  net-_u6-pad15_ net-_u6-pad16_ PORT
+
+.model u1 alu_8bit(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+.model u6 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+
+.tran 10n 10u
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end

Alu20_8/eSim Test Circuit Project Files/alu_subcircuit.cir.out

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+* c:\fossee\esim\library\subcircuitlibrary\alu_subcircuit\alu_subcircuit.cir
+
+a1 [pin_a7 pin_a6 pin_a5 pin_a4 pin_a3 pin_a2 pin_a1 pin_a0] [pin_b7 pin_b6 pin_b5 pin_b4 pin_b3 pin_b2 pin_b1 pin_b0] [pin_sel3 pin_sel2 pin_sel1 pin_sel0] [pin_out7 pin_out6 pin_out5 pin_out4 pin_out3 pin_out2 pin_out1 pin_out0] u1
+a2 [net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_] [pin_a7 pin_a6 pin_a5 pin_a4 pin_a3 pin_a2 pin_a1 pin_a0] u3
+a3 [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_] [pin_b7 pin_b6 pin_b5 pin_b4 pin_b3 pin_b2 pin_b1 pin_b0] u4
+a4 [net-_u2-pad17_ net-_u2-pad18_ net-_u2-pad19_ net-_u2-pad20_] [pin_sel3 pin_sel2 pin_sel1 pin_sel0] u5
+a5 [pin_out7 pin_out6 pin_out5 pin_out4 pin_out3 pin_out2 pin_out1 pin_out0] [net-_u2-pad21_ net-_u2-pad22_ net-_u2-pad23_ net-_u2-pad24_ net-_u2-pad25_ net-_u2-pad26_ net-_u6-pad15_ net-_u6-pad16_] u6
+* u2  net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ net-_u2-pad17_ net-_u2-pad18_ net-_u2-pad19_ net-_u2-pad20_ net-_u2-pad21_ net-_u2-pad22_ net-_u2-pad23_ net-_u2-pad24_ net-_u2-pad25_ net-_u2-pad26_ port
+* u7  net-_u6-pad15_ net-_u6-pad16_ port
+
+.tran 10n 10u
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end

Alu20_8/eSim Test Circuit Project Files/alu_subcircuit.pro

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+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts