Support for NXP T1040 RDB

Makefile

@@ -264,6 +264,9 @@ endif
 ifeq ($(TARGET),nxp_t1024)
     MAIN_TARGET:=factory_wstage1.bin
 endif
+ifeq ($(TARGET),nxp_t1040)
+    MAIN_TARGET:=factory_wstage1.bin
+endif
 
 ifeq ($(TARGET),sama5d3)
     MAIN_TARGET:=wolfboot.bin test-app/image_v1_signed.bin

arch.mk

@@ -991,6 +991,27 @@ ifeq ($(TARGET),nxp_t1024)
   OPTIMIZATION_LEVEL=0 # using default -Os causes issues with alignment
 endif
 
+ifeq ($(TARGET),nxp_t1040)
+  # Power PC big endian (e5500, same core as T1024)
+  ARCH_FLAGS=-mhard-float -mcpu=e5500
+  CFLAGS+=$(ARCH_FLAGS)
+  BIG_ENDIAN=1
+  CFLAGS+=-DMMU -DWOLFBOOT_FDT -DWOLFBOOT_DUALBOOT
+  CFLAGS+=-pipe # use pipes instead of temp files
+  CFLAGS+=-feliminate-unused-debug-types
+  LDFLAGS+=$(ARCH_FLAGS)
+  LDFLAGS+=-Wl,--hash-style=both # generate both sysv and gnu symbol hash table
+  LDFLAGS+=-Wl,--as-needed # remove weak functions not used
+  OBJS+=src/boot_ppc_mp.o # support for spin table
+  OBJS+=src/fdt.o
+  OBJS+=src/pci.o
+  CFLAGS+=-DWOLFBOOT_USE_PCI
+  UPDATE_OBJS:=src/update_ram.o
+
+  SPI_TARGET=nxp
+  OPTIMIZATION_LEVEL=0 # using default -Os causes issues with alignment
+endif
+
 ifeq ($(TARGET),nxp_t2080)
   # Power PC big endian
   ARCH_FLAGS=-mhard-float -mcpu=e6500

config/examples/nxp-t1040.config

@@ -0,0 +1,67 @@
+# NXP QorIQ T1040 (4 core)
+
+ARCH=PPC
+TARGET=nxp_t1040
+SIGN?=ECC384
+HASH?=SHA384
+IMAGE_HEADER_SIZE?=512
+DEBUG?=0
+DEBUG_UART?=1
+VTOR?=1
+CORTEX_M0?=0
+NO_ASM?=0
+EXT_FLASH?=0
+SPI_FLASH?=0
+NO_XIP?=0
+UART_FLASH?=0
+ALLOW_DOWNGRADE?=0
+NVM_FLASH_WRITEONCE?=0
+WOLFBOOT_VERSION?=0
+NO_MPU?=0
+SPMATH?=0
+SPMATHALL?=1
+RAM_CODE?=0
+DUALBANK_SWAP?=0
+WOLFTPM?=0
+ELF?=1
+DEBUG_ELF=0
+
+# NOR Base Address (128MB NOR at 0xE8000000 - 0xEFFFFFFF)
+ARCH_FLASH_OFFSET?=0xE8000000
+
+# Flash Sector Size (128KB)
+WOLFBOOT_SECTOR_SIZE=0x20000
+
+# wolfBoot start address (same as T1024 - NOR top is 0xEFFFFFFF)
+WOLFBOOT_ORIGIN=0xEFF40000
+# wolfBoot partition size (custom)
+BOOTLOADER_PARTITION_SIZE=0xC0000
+
+# Application Partition Size (15MB)
+WOLFBOOT_PARTITION_SIZE?=0xF00000
+# Location in Flash for Application Partition
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xEE000000
+# Load Partition to RAM Address
+WOLFBOOT_LOAD_ADDRESS?=0x70000000
+
+# Location in Flash for Update Partition
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xEEF00000
+
+# Location of temporary sector used during updates
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xE80F0000
+
+# Stage 1 loader settings (16KB)
+WOLFBOOT_STAGE1_SIZE=0x4000
+# Location in Flash for stage 1 loader (XIP from boot ROM)
+WOLFBOOT_STAGE1_FLASH_ADDR=0xEFFFC000
+# Address in RAM to load wolfBoot (end of DDR at 2GB-1MB for 32-bit addressing)
+WOLFBOOT_STAGE1_LOAD_ADDR=0x7FF00000
+
+# DTS (Device Tree)
+WOLFBOOT_DTS_BOOT_ADDRESS?=0xE8800000
+WOLFBOOT_DTS_UPDATE_ADDRESS?=0xE8820000
+# DTS Load to RAM Address
+WOLFBOOT_LOAD_DTS_ADDRESS?=0x7F100000
+
+# Load to RAM before hash and verify
+CFLAGS_EXTRA+=-DWOLFBOOT_USE_RAMBOOT

docs/Targets.md

@@ -3260,6 +3260,91 @@ If getting errors with keystore then you can reset things using `make distclean`
 Flash factory_custom.bin to NOR base 0xEC00_0000
 
 
+## NXP QorIQ T1040 PPC
+
+The NXP QorIQ T1040 is a four core 64-bit PPC e5500 based processor at 1400MHz. Each core has 256KB L2 cache.
+
+Board: T1040D4RDB
+Board rev: 0x01
+CPLD ver: 0x04
+
+T1040E, Version: 1.1, (0x8528_0011)
+e5500, Version: 2.1, (0x8024_1021)
+
+Reset Configuration Word (RCW):
+00000000: 0c18000e 0e000000 00000000 00000000
+00000010: 66000002 40000002 ec027000 01000000
+00000020: 00000000 00000000 00000000 00030810
+00000030: 00000000 0342580f 00000000 00000000
+
+Flash is NOR on IFC CS0 (0x0_E800_0000) 128MB (Micron JS28F00AM29EWHA, 16-bit, AMD CFI).
+
+Default NOR Flash Memory Layout (128MB) (128KB block, 1K page)
+
+| Description       | Address    | Size                 |
+| ----------------- | ---------- | -------------------- |
+| RCW               | 0xE8000000 | 0x00020000 (128 KB)  |
+| Free              | 0xE8020000 | 0x000D0000 (832 KB)  |
+| Swap Sector       | 0xE80F0000 | 0x00010000 ( 64 KB)  |
+| Free              | 0xE8100000 | 0x00700000 (  7 MB)  |
+| FDT (Primary)     | 0xE8800000 | 0x00020000 (128 KB)  |
+| FDT (Update)      | 0xE8820000 | 0x00020000 (128 KB)  |
+| Free              | 0xE8840000 | 0x057C0000 ( 87 MB)  |
+| Application (OS)  | 0xEE000000 | 0x00F00000 ( 15 MB)  |
+| Update (OS)       | 0xEEF00000 | 0x00F00000 ( 15 MB)  |
+| QUICC             | 0xEFE00000 | 0x00100000 (  1 MB)  |
+| DPAA (FMAN)       | 0xEFF00000 | 0x00020000 (128 KB)  |
+| wolfBoot          | 0xEFF40000 | 0x000BC000 (752 KB)  |
+| wolfBoot Stage 1  | 0xEFFFC000 | 0x00004000 ( 16 KB)  |
+
+QE: uploading microcode 'Microcode for T1040 r1.0' version 0.0.1
+
+DDR4 8GB
+
+### Building wolfBoot for NXP T1040 PPC
+
+By default wolfBoot will use `powerpc-linux-gnu-` cross-compiler prefix. These tools can be installed with the Debian package `gcc-powerpc-linux-gnu` (`sudo apt install gcc-powerpc-linux-gnu`).
+
+The `make` creates a `factory_stage1.bin` image that can be programmed at `0xE8000000`
+
+```
+cp ./config/examples/nxp-t1040.config .config
+make clean
+make keytools
+make
+```
+
+Or each `make` component can be manually built using:
+
+```
+make stage1
+make wolfboot.elf
+make test-app/image_v1_signed.bin
+```
+
+If getting errors with keystore then you can reset things using `make distclean`.
+
+### Signing Custom application
+
+```
+./tools/keytools/sign --ecc384 --sha384 custom.elf wolfboot_signing_private_key.der 1
+```
+
+### Assembly of custom firmware image
+
+```
+./tools/bin-assemble/bin-assemble factory_custom.bin \
+    0xE8000000 RCW.bin \
+    0xE8020000 custom.dtb \
+    0xEE000000 custom_v1_signed.bin \
+    0xEFE00000 iram_Type_A_T1040_r1.0.bin \
+    0xEFF00000 fsl_fman_ucode_t1040.bin \
+    0xEFF40000 wolfboot.bin \
+    0xEFFFC000 stage1/loader_stage1.bin
+```
+
+Flash factory_custom.bin to NOR base 0xE800_0000
+
 
 ## NXP QorIQ T2080 PPC
 

hal/nxp_ppc.h

@@ -94,12 +94,69 @@
     #endif
 
     #define FLASH_BASE_ADDR      0xEC000000UL
-    #define FLASH_BASE_PHYS_HIGH 0xFULL
+    #ifndef BUILD_LOADER_STAGE1
+    #define FLASH_BASE_PHYS_HIGH 0xFULL /* 36-bit: 0xF_EC000000 */
+    #else
+    #define FLASH_BASE_PHYS_HIGH 0x0ULL /* 32-bit stage1 */
+    #endif
     #define FLASH_LAW_SIZE       LAW_SIZE_64MB
     #define FLASH_TLB_PAGESZ     BOOKE_PAGESZ_64M
 
     #define USE_LONG_JUMP
 
+#elif defined(TARGET_nxp_t1040)
+    /* NXP T1040 */
+    #define CORE_E5500
+    #define CPU_NUMCORES 4
+    #define CORES_PER_CLUSTER 1
+    #define LAW_MAX_ENTRIES 16
+
+    #define CCSRBAR_DEF (0xFE000000) /* T1040RM 4.4.1 default base */
+    #define CCSRBAR_SIZE BOOKE_PAGESZ_16M
+
+    #define ENABLE_L1_CACHE
+    #define ENABLE_INTERRUPTS
+
+    /* T1040 has a 256KB CPC (CoreNet Platform Cache), not PSRAM.
+     * Use L1 locked dcache (16KB) as initial stack, same as T2080.
+     * CPC SRAM is configured but not used for stack to avoid
+     * cold power cycle reliability issues via CoreNet. */
+    #define L1_CACHE_ADDR (0xFDFC0000UL)
+
+    #define L2SRAM_ADDR   (0xFDFE0000UL) /* CPC as SRAM (256KB) */
+    #define L2SRAM_SIZE   (256UL * 1024UL)
+
+    #define INITIAL_SRAM_ADDR     L2SRAM_ADDR
+    #define INITIAL_SRAM_LAW_SZ   LAW_SIZE_256KB
+    #define INITIAL_SRAM_LAW_TRGT LAW_TRGT_DDR_1 /* CPC target per T1040RM */
+    #define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_256K
+
+    #ifdef BUILD_LOADER_STAGE1
+        #define ENABLE_L2_CACHE
+    #else
+        /* relocate to 64-bit 0xF_ */
+        #define CCSRBAR_PHYS_HIGH 0xFULL
+        #define CCSRBAR_PHYS (CCSRBAR_PHYS_HIGH + CCSRBAR_DEF)
+    #endif
+
+    #define ENABLE_DDR
+    #ifndef DDR_SIZE
+    #define DDR_SIZE (8192ULL * 1024ULL * 1024ULL) /* 8GB */
+    #endif
+
+    /* 128MB NOR: 0xE8000000 - 0xEFFFFFFF */
+    #define FLASH_BASE_ADDR      0xE8000000UL
+    #ifndef BUILD_LOADER_STAGE1
+    #define FLASH_BASE_PHYS_HIGH 0xFULL /* 36-bit: 0xF_E8000000 */
+    #else
+    #define FLASH_BASE_PHYS_HIGH 0x0ULL /* 32-bit stage1 */
+    #endif
+    #define FLASH_LAW_SIZE       LAW_SIZE_128MB
+    /* e5500 BookE has no 128M page size (64M->256M), use 256M TLB */
+    #define FLASH_TLB_PAGESZ     BOOKE_PAGESZ_256M
+
+    #define USE_LONG_JUMP
+
 #elif defined(TARGET_nxp_t2080)
     /* NXP T2080 */
     #define CORE_E6500
@@ -176,7 +233,7 @@
 
     #define USE_LONG_JUMP
 #else
-    #error Please define TARGET (nxp_t2080, nxp_t1024, or nxp_p1021)
+    #error Please define TARGET (nxp_t2080, nxp_t1040, nxp_t1024, or nxp_p1021)
 #endif